August 2000 PRELIMINARY ML6516244* 16-Bit Buffer/Line Driver with 3-State Outputs GENERAL DESCRIPTION FEATURES The ML6516244 is a BiCMOS, 16-bit buffer/line driver with 3-state outputs. This device was specifically designed for high speed bus applications. Its 16 channels support propagation delay of 2.5ns maximum, and fast output enable and disable times of 7.0ns or less to minimize datapath delay. ■ Low propagation delays — 2.5ns maximum for 3.3V 2.25ns maximum for 5.0V ■ Fast output enable/disable times of 5.0ns maximum ■ FastBus Charge current to minimize the bus settling time during active capacitive loading ■ 3.0 to 3.6V and 4.5 to 5.5V VCC supply operation; LV-TTL compatible input and output levels with 3-state capability ■ Industry standard pinout compatible to FCT, ALV, LCX, LVT, and other low voltage logic families ■ ESD protection exceeds 2000V ■ Full output swing for increased noise margin ■ Undershoot and overshoot protection to 400mV typically ■ Low ground bounce design This device is designed to minimize undershoot, overshoot, and ground bounce to decrease noise delays. These transceivers implement a unique digital and analog implementation to eliminate the delays and noise inherent in traditional digital designs. The device offers a new method for quickly charging up a bus load capacitor to minimize bus settling times, or FastBus™ Charge. FastBus Charge is a transition current, (specified as IDYNAMIC) that injects between 60 to 200mA (depending on output load) of current during the rise time and fall time. This current is used to reduce the amount of time it takes to charge up a heavily-capacitive loaded bus, effectively reducing the bus settling times, and improving data/clock margins in tight timing budgets. Micro Linear’s solution is intended for applications for critical bus timing designs that include minimizing device propagation delay, bus settling time, and time delays due to noise. Applications include; high speed memory arrays, bus or backplane isolation, bus to bus bridging, and sub2.5ns propagation delay schemes. * This part is End of Life as of August 1, 2000. The ML6516244 follows the pinout and functionality of the industry standard 3.3V-logic families. BLOCK DIAGRAM VCC OE A0 B0 A1 B1 A2 B2 A3 B3 GND 1 of 4 1 ML6516244 PIN CONFIGURATION ML6516244 48-Pin SSOP (R48) 48-Pin TSSOP (T48) 1OE 1 48 2OE 1B0 2 47 1A0 1B1 3 46 1A1 GND 4 45 GND 1B2 5 44 1A2 1B3 6 43 1A3 VCC 7 42 VCC 2B0 8 41 2A0 2B1 9 40 2A1 GND 10 39 GND 2B2 11 38 2A2 2B3 12 37 2A3 3B0 13 36 3A0 3B1 14 1 15 35 20 34 3A1 19 33 18 32 3A2 3B3 2 16 3 17 VCC 4 18 17 31 VCC 4B0 5 19 16 30 4A0 4B1 6 20 15 29 4A1 GND 7 21 14 28 GND 4B2 8 22 13 27 4A2 4B3 9 23 12 26 4A3 4OE 10 24 11 25 3OE GND 3B2 TOP VIEW FUNCTION TABLE (Each 4-bit section) INPUTS OUTPUTS OE 1Ai, 2Ai, 3Ai, 4Ai 1Bi, 2Bi, 3Bi, 4Bi L L H H L X H L Z L = Logic Low, H = Logic High, X = Don’t Care, Z = High Impedance 2 GND 3A3 ML6516244 PIN DESCRIPTION PIN NAME FUNCTION PIN NAME FUNCTION 1 1OE Output Enable 25 3OE Output Enable 2 1B0 Data Output 26 4A3 Data Input 3 1B1 Data Output 27 4A2 Data Input 4 GND Signal Ground 28 GND Signal Ground 5 1B2 Data Output 29 4A1 Data Input 6 1B3 Data Output 30 4A0 Data Input 7 VCC 3.3V or 5.0V Supply 31 VCC 3.3V or 5.0V Supply 8 2B0 Data Output 32 3A3 Data Input 9 2B1 Data Output 33 3A2 Data Input 10 GND Signal Ground 34 GND Signal Ground 11 2B2 Data Output 35 3A1 Data Input 12 2B3 Data Output 36 3A0 Data Input 13 3B0 Data Output 37 2A3 Data Input 14 3B1 Data Output 38 2A2 Data Input 15 GND Signal Ground 39 GND Signal Ground 16 3B2 Data Output 40 2A1 Data Input 17 3B3 Data Output 41 2A0 Data Input 18 VCC 3.3V or 5.0V Supply 42 VCC 3.3V or 5.0V Supply 19 4B0 Data Output 43 1A3 Data Input 20 4B1 Data Output 44 1A2 Data Input 21 GND Signal Ground 45 GND Signal Ground 22 4B2 Data Output 46 1A1 Data Input 23 4B3 Data Output 47 1A0 Data Input 24 4OE Output Enable 48 2OE Output Enable 3 ML6516244 ABSOLUTE MAXIMUM RATINGS Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. Storage Temperature Range...................... –65°C to 150°C Junction Temperature ............................................. 150°C Lead Temperature (Soldering, 10sec) ...................... 150°C Thermal Impedance (qJA) ..................................... 76°C/W VCC ............................................................................. 7V DC Input Voltage .............................. –0.3V to VCC + 0.3V AC Input Voltage (PW < 20ns) ................................. –3.0V DC Output Voltage ................................... –0.3V to 7VDC Output Current, Source or Sink ............................. 180mA OPERATING CONDITIONS Temperature Range ........................................ 0°C to 70°C VIN Operating Range ................................... 3.0V to 5.5V ELECTRICAL CHARACTERISTICS – 3.3V OPERATION Unless otherwise specified, VIN = 3.3V, TA = Operating Temperature Range (Note 1). SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS 1.8 2.1 2.5 ns AC ELECTRICAL CHARACTERISTICS (CLOAD = 50pF) tPHL, tPLH Propagation Delay Ai to Bi tOE Output Enable Time OE to Ai 7.0 ns tOD Output Disable Time OE to Ai 7.0 ns TOS Output-to-Output Skew 500 ps CIN Input Capacitance 5 pF DC ELECTRICAL CHARACTERISTICS (CLOAD = 50pF, RLOAD = Open) VIH Input High Voltage Logic high VIL Input Low Voltage Logic low 0.8 V IIH Input High Current Per pin, VIN = 3V 300 mA IIL Input Low Current Per pin, VIN = 0V 300 mA IHI-Z Three-State Output Current VCC = 3.6V, 0 < VIN < VCC 5 mA VIC Input Clamp Voltage VCC = 3.6V, IIN = 18mA –0.2 V IDYNAMIC Dynamic Transition Current (FastBus Charge) V –0.7 Low to high transitions 80 mA High to low transitions 80 mA VOH Output High Voltage VCC = 3.6V, IOH = –2mA VOL Output LowVoltage VCC = 3.6V, IOL = 2mA ICC Quiescent Power Supply Current VCC = 3.6V, f = 0Hz, inputs = VCC or 0V Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions. 4 2.0 2.4 V 0.6 V 3 mA ML6516244 ELECTRICAL CHARACTERISTICS – 5V OPERATION Unless otherwise specified, VIN = 5V, TA = Operating Temperature Range (Note 1). SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS 1.6 1.9 2.25 ns AC ELECTRICAL CHARACTERISTICS (CLOAD = 50pF) tPHL, tPLH Propagation Delay Ai to Bi tOE Output Enable Time OE to Ai 7.0 ns tOD Output Disable Time OE to Ai/Bi 7.0 ns TOS Output-to-Output Skew 500 ps CIN Input Capacitance 5 pF DC ELECTRICAL CHARACTERISTICS (CLOAD = 50pF, RLOAD = Open) VIH Input High Voltage Logic high VIL Input Low Voltage Logic low 0.8 V IIH Input High Current Per pin, VIN = 4.5V 300 mA IIL Input Low Current Per pin, VIN = 0V 300 mA IHI-Z Three-State Output Current VCC = 5.5V, 0 < VIN < VCC 5 mA VIC Input Clamp Voltage VCC = 5.5V, IIN = 18mA –0.7 –0.2 V Low to high transitions 120 mA High to low transitions 120 mA IDYNAMIC Dynamic Transition Current (FastBus Charge) VOH Output High Voltage VCC = 5.5V, IOH = –2mA VOL Output Low Voltage VCC = 5.5V, IOL = 2mA ICC Quiescent Power Supply Current VCC = 5.5V, f = 0Hz, inputs = VCC or 0V 3.6 V 4.5 V 1.2 V 3 mA Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions. 5 ML6516244 PERFORMANCE DATA 3.3V OPERATION 3.50 90 3.00 80 150pF 100pF 70 tPHL 2.50 2.00 ICC (mA) Tpd (ns) 60 tPLH 1.50 75pF 50 40 30 1.00 50pF 20 0.50 0.00 30pF 10 30 75 50 100 0 150 10 20 30 LOAD (pF) 50 60 70 80 90 100 FREQUENCY (MHz) Figure 2. ICC vs. Frequency (10 to 100 MHz) over Load, VCC = VIN = 3.3V Figure 3. Ground Bounce: ML6516244, VCC = VIN = 3.0V VIN: tRISE = tFALL = 2ns Figure 4. IDYNAMIC Current (FastBus Charge): ML6516244, VCC = VIN = 3.3V, 50pF load, 40mA/DIV, VIN: tRISE = tFALL = 2ns 250 0 200 -30 150 -60 IOH (mA) IOL (mA) Figure 1. Propagation Delay over Load Capacitance: 30 to 150pF, VCC = VIN = 3.3V, 20MHz 100 50 0 -90 -130 0 0.4 0.8 1.2 1.6 2.0 VOL (V) Figure 5a. Typical VOL vs. IOL for One Buffer Output 6 40 -160 1.5 2.0 2.5 3.0 3.5 VOH (V) Figure 5b. Typical VOH vs. IOH for One Buffer Output ML6516244 PERFORMANCE DATA 5.0V OPERATION 3.00 100 100pF 150pF 2.50 80 75pF tPHL ICC (mA) Tpd (ns) 2.00 1.50 tPLH 60 50pF 40 1.00 30pF 20 0.50 0.00 30 50 75 100 150 0 0 20 LOAD (pF) 40 60 80 100 FREQUENCY (MHz) Figure 6. Propagation Delay over Load Capacitance: 30 to 150pF, VCC = VIN = 5.0V, 20MHz Figure 7. ICC vs. Frequency (10 to 100 MHz) over Load, VCC = VIN = 5.0V Figure 8. IDYNAMIC Current (FastBus Charge): ML6516244, VCC = VIN = 5.0V, 50pF load, 100mA/DIV, VIN: tRISE = tFALL = 2ns 7 ML6516244 FUNCTIONAL DESCRIPTION 1OE 1A0 1B0 1A1 1B1 1A2 1B2 1A3 1B3 2OE 2A0 2B0 2A1 2B1 2A2 2B2 2A3 2B3 3OE 3A0 3B0 3A1 3B1 3A2 3B2 3A3 3B3 4OE 4A0 4B0 4A1 4B1 4A2 4B2 4A3 4B3 Figure 9. Logic Diagram 1A0 1A1 1A2 1A3 2A0 2A1 2A2 2A3 3A0 3A1 3A2 4A0 4A1 4A2 4A3 2OE 3OE 1OE 4OE 1B0 1B1 1B2 1B3 2B0 2B1 2B2 2B3 3B0 3B1 3B2 Figure 10. Logic Symbol 8 3A3 3B3 4B0 4B1 4B2 4B3 ML6516244 ARCHITECTURAL DESCRIPTION One path sources current to the load capacitance where the signal is asserted, and the other path sinks current from the output when the signal is negated. The ML6516244 is a 16-bit buffer/line driver with 3-state outputs designed for 3.0V to 3.6V and 4.5V to 5.5V VCC operation. This device is designed for Quad-Nibble, Dual-Byte or single 16-bit word memory interleaving operations. Each bank has an independently controlled 3state output enable pin with output enable/disable access times of less than 7.0ns. Each bank is configured to have four independent buffer/line drivers. The assertion path is the Darlington pair consisting of transistors Q1 and Q2. The effect of transistor Q1 is to increase the current gain through the stage from input to output, to increase the input resistance and to reduce input capacitance. During an input low-to-high transition, the output transistor Q2 sources large amount of current to quickly charge up a highly capacitive load which in effect reduces the bus settling time. This current is specified as IDYNAMIC. Until now, these buffer/line drivers were typically implemented in CMOS logic and made to be TTL compatible by sizing the input devices appropriately. In order to buffer large capacitances with CMOS logic, it is necessary to cascade an even number of inverters, each successive inverter larger than the preceding, eventually leading to an inverter that will drive the required load capacitance at the required frequency. Each inverter stage represents an additional delay in the gating process because in order for a single gate to switch, the input must slew more than half of the supply voltage. The best of these 16-bit CMOS buffers has managed to drive 50pF load capacitance with a delay of 3.6ns. The negation path is also the Darlington pair consisting of transistor Q3 and transistor Q4. With M1 connecting to the input of the Darlington pair, Transistor Q4 then sinks a large amount of current during the input transition from high-to-low. Inverter X2 is a helpful buffer that not only drives the output toward the upper rail but also pulls the output to the lower rail. Micro Linear has produced a 16-bit buffer/line driver with a delay less than 2.5ns by using a unique circuit architecture that does not require cascade logic gates. There are a number of MOSFETs not shown in Figure 11. These MOSFETs are used to 3-state the buffers. For instance, R1 and R2 were implemented as resistive transmission gates to ensure that disabled buffers do not load the lines of which they are connected. The basic architecture of the ML6516244 is shown in Figure 11. In this circuit, there are two paths to the output. VCC R1 Q1 Q2 X1 X2 IN OUT R2 M1 Q3 Q4 Figure 11. One Buffer Cell of the ML6516244 9 ML6516244 CIRCUITS AND WAVE FORMS VCC = 3V 1.5V ML6516244 DUT INPUT 0V 3V tPLH VIN VOUT 50pF IOUT 1.5V OUTPUT 0V tRISE AND tFALL INPUT = 2ns Figure 12. Test Circuits for All Outputs ENABLE Figure 13. Propagation Delay DISABLE VCC = 3V CONTROL INPUT tPHL INPUT 1.5V 1.5V tOE tOD 3V OUTPUT1 OUTPUT LOW 1.5V VOL + 0.3V VOL tOE VOH VOH – 0.3V OUTPUT HIGH OUTPUTi i = 1 to 16 1.5V 0V tOD Figure 14. Enable and Disable Times 10 tOS Figure 15. Output Skew ML6516244 PHYSICAL DIMENSIONS inches (millimeters) Package: R48 48-Pin SSOP 0.620 - 0.630 (15.75 - 16.00) 48 0.291 - 0.301 0.402 - 0.410 (7.39 - 7.65) (10.21 - 10.41) PIN 1 ID 1 0.015 - 0.025 (0.38 - 0.64) (4 PLACES) 0.025 BSC (0.63 BSC) 0.094 - 0.110 (2.39 - 2.79) 0º - 8º 0.088 - 0.092 (2.24 - 2.34) 0.006 - 0.014 (0.15 - 0.36) SEATING PLANE 0.024 - 0.040 (0.61 - 1.02) 0.008 - 0.016 (0.20 - 0.41) 0.005 - 0.010 (0.13 - 0.26) Package: T48 48-Pin TSSOP 0.487 - 0.497 (12.37 - 12.63) 0.236 - 0.244 (6.00 - 6.20) 0.319 BSC (8.1 BSC) PIN 1 ID 0.020 BSC (0.50 BSC) 0.047 MAX (1.20 MAX) 0º - 8º 0.031 - 0.039 (0.80 - 1.00) 0.007 - 0.011 (0.17 - 0.27) SEATING PLANE 0.002 - 0.006 (0.05 - 0.15) 0.020 - 0.028 (0.50 - 0.70) 0.004 - 0.008 (0.10 - 0.20) 11 ML6516244 ORDERING INFORMATION PART NUMBER TEMPERATURE RANGE PACKAGE ML6516244CR (OBS) 0°C to 70°C 48-Pin SSOP (R48) ML6516244CT (EOL) 0°C to 70°C 48-Pin TSSOP (T48) Micro Linear Corporation 2092 Concourse Drive San Jose, CA 95131 Tel: (408) 433-5200 Fax: (408) 432-0295 www.microlinear.com © Micro Linear 2000. is a registered trademark of Micro Linear Corporation. All other trademarks are the property of their respective owners. Products described herein may be covered by one or more of the following U.S. patents: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; 5,652,479; 5,661,427; 5,663,874; 5,672,959; 5,689,167; 5,714,897; 5,717,798; 5,742,151; 5,747,977; 5,754,012; 5,757,174; 5,767,653; 5,777,514; 5,793,168; 5,798,635; 5,804,950; 5,808,455; 5,811,999; 5,818,207; 5,818,669; 5,825,165; 5,825,223; 5,838,723; 5.844,378; 5,844,941. Japan: 2,598,946; 2,619,299; 2,704,176; 2,821,714. Other patents are pending. 12 DS6516244-01