May 1997 ML6698* 100BASE-TX Physical Layer with 5-Bit Interface GENERAL DESCRIPTION FEATURES The ML6698 is a high-speed physical layer transceiver that provides a 5-bit (or symbol) interface to unshielded twisted pair cable media. The ML6698 is well suited for adapter card applications using the DEC 21143, the Macronix MX98713, or equivalent Media Access Controllers (MACs). The ML6698 may be used in other 100BASE-TX applications requiring the 5-bit interface as well as FDDI-over-copper applications. ■ 5-bit (or symbol) parallel interface Compliant to IEEE 802.3u 100BASE-TX standard Compliant to ANSI X3T12 TP-PMD (FDDI) standard Single-jack 10BASE-T/100BASE-TX solution when used with external 10Mbps PHY 125MHz receive clock recovery/generation Baseline wander correction Adaptive equalization and MLT-3 encoding/decoding Supports full-duplex operation ■ ■ ■ ■ ■ The ML6698 integrates 125MHz clock recovery/ generation, receive adaptive equalization, baseline wander correction and MLT-3/10BASE-T transmitter. ■ ■ *Some Packages Are End Of Life As Of August 1, 2000 BLOCK DIAGRAM (PLCC Pin Configuration) TXC CLOCK SYTHESIZER 40 10BTTXINN 44 10BTTXINP 41 TPOUTP 2 3 4 5 6 TSM4 TSM3 TSM2 SERIALIZER NRZ TO NRZI AND NRZI TO MLT-3 ENCODER 13 15 31 NRZI TO NRZ DECODER RSM4 TPINP EQUALIZER BLW CORRECTION MLT-3 DECODER LOOPBACK MUX RSM3 DESERIALIZER TPINN CMREF RGMSET SDO RSM2 38 37 39 30 24 RSM1 RSM0 CONTROL LOGIC 25 42 PWRDN 11 RXC LPBK 9 33 TSM0 SEL100/10 8 RTSET 34 TSM1 CLOCK AND DATA RECOVERY 16 100BASE-TX/10BASE-T TWISTED PAIR DRIVER TPOUTN 7 1 ML6698 PIN CONFIGURATION TSM0 TSM1 TSM2 TSM3 TSM4 AGND1 TXC AVCC1 LPBK 10BTTXINP 10BTTXINN ML6698 44-Pin PLCC (Q44) 6 5 4 3 2 1 44 43 42 41 40 CMREF RSM4 8 38 TPINP RSM3 9 37 TPINN DGND1 10 36 AVCC2 RSM2 11 35 AGND2 DVCC1 12 34 TPOUTP RSM1 13 33 TPOUTN DGND2 14 32 AGND3 RSM0 15 31 RTSET RXC 16 30 RGMSET DGND3 17 29 NC 26 27 28 AVCC3 25 NC 24 NC 23 SEL100/10 22 SDO 21 DGND5 20 DVCC5 19 DGND4C 18 DGND4B 39 DGND4A 7 DVCC2 PWRDN TSM3 TSM4 AGND1 TXC AVCC1 LPBK 10BTTXINP 10BTTXINN 43 42 41 40 39 38 37 36 35 34 TPINN DGND1 4 30 AVCC2 RSM2 5 29 AGND2 DVCC1 6 28 TPOUTP RSM1 7 27 TPOUTN DGND2 8 26 AGND3 RSM0 9 25 RTSET 10 24 RGMSET 23 NC 13 DGND4A 11 12 DVCC2 DGND3 14 15 16 17 18 19 20 21 22 AVCC3 31 NC 3 NC RSM3 SDO TPINP SEL100/10 32 DGND5 CMREF 2 DVCC5 33 RSM4 DGND4B 1 DGND4C PWRDN RXC 2 TSM2 44 TSM1 TSM0 ML6698 44-Pin TQFP (H44-10) ML6698 PIN DESCRIPTION (Pin numbers for TQFP package in parentheses) PIN NAME DESCRIPTION 1 (39) AGND1 Analog ground. 2-6 (40-44) TSM<4:0> Transmit data TTL inputs. TSM<4:0> inputs accept TX data symbols. Data appearing at TSM<4:0> are clocked into the ML6698 on the rising edge of TXC. 7 (1) PWRDN Device power down input. A low signal powers down all ciruits of the ML6698, and dissipates less than 20mA. 8,9, (2, 3, 11,13, 5, 7, 9) 15 RSM<4:0> Receive data TTL outputs. RSM<4:0> outputs may be sampled synchronously with RXC’s rising edge. 10 (4) DGND1 Digital ground. 12 (6) DVCC1 Digital +5V power supply. 14 (8) DGND2 Digital ground. 16 (10) RXC Recovered receive symbol clock TTL output. This 25MHz clock is phase-aligned with the internal 125MHz bit clock recovered from the signal received at TPINP/N when data is present. Receive data at RSM<4:0> change on the falling edges and should be sampled on the rising edges of this clock. RXC is phase aligned to TXC when 100BASE-TX signal is not present at TPINP/N 17 (11) DGND3 Digital ground. 18 (12) DVCC2 Digital +5V power supply. 19 (13) DGND4A Digital ground. 20 (14) DGND4B Digital ground. 21 (15) DGND4C Digital ground. 22 (16) DVCC5 Digital +5V power supply. 23 (17) DGND5 Digital ground. 24 (18) SD0 Signal detect TTL output. A high output level indicates 100BASE-TX activity at TPINP/N with an amplitude exceeding the preset threshold. The signal detect function is always active independent of the configuration of the SEL100/10 pin. 25 (19) SEL100/10 Speed select TTL input. Driving this pin low disables 100BASE-TX transmit and receive functions, and enables the 10BASE-T transmit path from 10BTTXINP/N to TPOUTP/N. A high signal on SEL100/10 disables the 10BTTXINP/N inputs and enables 100BASE-TX operation. 28 (22) AVCC3 Analog positive power supply. 30 (24) RGMSET Equalizer bias resistor input. An external 9.53ký, 1% resistor connected between RGMSET and AGND3 sets internal time constants controlling the receive equalizer transfer function. 31 (25) RTSET Transmit level bias resistor input. An external 2.49ký, 1% resistor connected between RTSET and AGND3 sets a precision constant bias current for the twisted pair transmit level. 32 (26) AGND3 Analog ground. 33,34 (27,28) TPOUTN/P Transmit twisted pair outputs. This differential current output pair drives MLT-3 waveforms into the network coupling transformer in 100BASE-TX mode, and 10BASE-T or FLP waveforms in 10BASE-T mode. 35 (29) AGND2 Analog ground. 36 (30) AVCC2 Analog +5V power supply. TPINN/P Receive twisted pair inputs. This differential input pair receives 100BASE-TX signals from the network. 37,38 (31, 32) 3 ML6698 PIN DESCRIPTION PIN 39 (33) (Continued) NAME DESCRIPTION CMREF Receiver common-mode reference output. This pin provides a common-mode bias point for the twisted-pair media line receiver. A typical value for CMREF is (VCC–1.26)V. 40,41 (34,35) 10BTTXINN/P 10BASE-T transmit waveform inputs. The ML6698 presents a linear copy of the input at 10BTTXINN/P to the TPOUTN/P outputs when the ML6698 functions in 10BASE-T mode. Signals presented to these pins must be centered at VCC/2 with a single ended amplitude of ± 0.25V. 42 (36) LPBK Loopback TTL input pin. Tying this pin to ground places the part in loopback mode; data at RSM<4:0> are serialized, MLT-3 encoded, equalized then sent to the receive PLL for clock recovery and sent to the RSM<4:0> outputs. Floating this pin or tying it to VCC places the part in its normal mode of operation. 43 (37) AVCC1 Analog +5V power supply. 44 (38) TXC Transmit clock TTL input. This 25MHz clock is the frequency reference for the internal transmit PLL clock multiplier. This pin should be driven by an external 25MHz clock at TTL or CMOS levels. 4 ML6698 ABSOLUTE MAXIMUM RATINGS Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. VCC Supply Voltage Range ................... GND –0.3V to 6V Input Voltage Range Digital Inputs ....................... GND –0.3V to VCC + 0.3V TPINP, TPINN, 10BTTXINP, 10BTTXINN ..................... GND –0.3V to VCC + 0.3V Output Current TPOUTP, TPOUTN .............................................. 60mA All other outputs .................................................. 10mA Junction Temperature ............................................. 150°C Storage Temperature .............................. .. –65°C to 150°C Lead Temperature (Soldering, 10 sec) ..................... 260°C OPERATING CONDITIONS VCC Supply Voltage ............................................ 5V ± 5% All VCC supply pins must be within 0.1V of each other. All GND pins must be within 0.1V of each other. TA, Ambient temperature ................................ 0°C to 70°C RGMSET ..................................................... 9.53ký ± 1% RTSET .......................................................... 2.49ký ± 1% Receive transformer insertion loss ........................ <–0.5dB DC ELECTRICAL CHARACTERISTICS Over full range of operating conditions unless otherwise specified (Note 1) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS 0.8 V TTL Inputs (TSM<4:0>, TXC, SEL100/10, PWRDN, LPBK) VIL Input Low Voltage IIL = –400µA VIH Input High Voltage IIH = 100µA 2.0 V IIL Input Low Current VIN = 0.4V –200 µA IIH Input High Current VIN = 2.7V 100 µA 0.4 V TTL Outputs (RSM<4:0>, RXC, SDO) VOL Output Low Voltage IOL = 4mA VOH Output High Voltage IOH = –4mA VICM TPINP/N Input Common-Mode Voltage 100ý Termination across TPINP/N VID TPINP-TPINN Differential Input Voltage Range –3.0 RIDR TPINP-TPINN Differential Input Resistance 10.0k IICM TPINP/N Common-Mode Input Current IRGM RGMSET Input Current RGMSET = 9.53ký 130 µA IRT RTSET Input Current RTSET = 2.49ký 500 µA ITD100 TPOUTP/N 100BASE-TX Mode Differential Output Current Note 2, 3 ITD10 TPOUTP/N 10BASE-T Mode Differential Output Current ITOFF TPOUTP/N Off-State Output RL = 200, 1% ITXI TPOUTP/N Differential Output Current Imbalance RL = 200, 1% 2.4 V Receiver VCC – 1.26 V 3.0 V ý +10 µA Transmitter ±19 ±55 0 ±60 ±21 mA ±65 mA 1.5 mA 500 µA 5 ML6698 DC ELECTRICAL CHARACTERISTICS SYMBOL PARAMETER (Continued) CONDITIONS MIN TYP MAX UNITS Transmitter (Continued) XERR TPOUTP/N Differential Output Current Error VOUT = VCC; Note 3 –5.0 +5.0 % XCMP100 TPOUTP/N 100BASE-X Output Current Compliance Error VOUT = VCC ± 2.2V; referred to IOUT at VCC –2.0 +2.0 % VOCM10 TPOUTP/N 10BASE-T Output Voltage Compliance Range ITD10 remains within specified values VCC – 2.7 VCC + 2.7 V VICM10 10BTTXNN/P Input Common-Mode Voltage Range VCC/2 – 0.3 VCC/2 + 0.3 V 195 260 mA 155 175 mA 20 mA MAX UNITS Power Supply Current ICC100 Supply Current, 100BASE-TX Operation, Transmitting ICC10 Supply Current, 10BASE-T Mode ICCOFF Supply Current Power Down Mode Current into all VCC pins, VCC = 5.25V (Note 2) PWRDN AC ELECTRICAL CHARACTERISTICS Over full range of operating conditions unless otherwise specified SYMBOL PARAMETER CONDITIONS MIN TYP tTR/F TPOUTP-TPOUTN Differential Rise/Fall Time Notes 5, 6; for any legal code sequence 3.0 5.0 ns tTM TPOUTP-TPOUTN Differential Rise/Fall Time Mismatch Notes 5, 6; for any legal code sequence –0.5 0.5 ns tTDC TPOUTP-TPOUTN Differential Output Duty Cycle Distortion Notes 4, 6 –0.5 0.5 ns tTJT TPOUTP-TPOUTN Differential Output Peak-to-Peak Jitter Note 6 1400 ps XOST TPOUTP-TPOUTN Differential Output Voltage Overshoot Notes 6, 7 5 % tTXP Transmit Bit Delay Note 8 10.5 Bit Times tRXDC Receive Bit Delay Note 9 15.5 Bit Times 6 300 ML6698 AC ELECTRICAL CHARACTERISTICS SYMBOL PARAMETER (Continued) CONDITIONS MIN TYP MAX UNITS +100 ppm MII (Media-Independent Interface) XBTOL TX Output Clock Frequency Tolerance tTPWH TXC pulse width HIGH 14 ns tTPWL TXC pulse width LOW 14 ns tRPWH RXC pulse width HIGH 14 ns tRPWL RXC pulse width LOW 14 ns tTPS Setup time, TSM<4:0> Data Valid to TXC Rising Edge (1.4V point) 12 ns tTPH Hold Time, TSM<4:0> Data Valid After TXC Rising Edge (1.4V point) 3 ns tRCS Time that RSM<4:0> Data are Valid Before RXC Rising Edge (1.4V point) 10 ns tRCH Time that RSM<4:0> Data are Valid After RXC Rising Edge (1.4V point) 10 ns tRPCR RXC 10% – 90% Rise Time 6 ns tRPCF RXC 90%-10% Fall Time 6 ns Note 1. Note 2. Note 3. Note 4. Note 5. Note 6. Note 7. Note 8. Note 9. 25MHz frequency –100 Limits are guaranteed by 100% testing, sampling, or correlation with worst case test conditions. Measured using the test circuit shown in Fig. 1, under the following conditions: RLP = 200ý, RLS = 49.9ý, RTSET = 2.49ký. All resistors are 1% tolerance. Output current amplitude is IOUT = 40 3 1.25V/RTSET. Measured relative to ideal negative and positive signal 50% points, using the four successive MLT-3 transitions for the 01010101 bit sequence. Time difference between 10% and 90% levels of the transition from the baseline voltage (nominally zero) to either the positive or negative peak signal voltage. The times specified here correlate to the transition times defined in the ANSI X3T9.5 TP-PMD Rev 2.0 working draft, section 9.1.6, which include the effects of the external network coupling transformer and EMI/RFI emissions filter. Differential test load is shown in fig. 1 (see note 3). Defined as the percentage excursion of the differential signal transition beyond its final adjusted value during the symbol interval following the transition. The adjusted value is obtained by doing a straight line best-fit to an output waveform containing 14 bit-times of no transition preceded by a transition from zero to either a positive or negative signal peak; the adjusted value is the point at which the straight line fit meets the rising or falling signal edge. Symbol /J/ at TSM <4:0> sampled by TXC to first bit of /J/ at MDI. First bit of /J/ at MDI to first rising edge of RXC after the last part of the /J/ appears at RSM <4:0>. VCC TPOUTP RLP 200Ω 2:1 1 RLP 200Ω TPOUTN 2 RLS 49.9Ω RLS 49.9Ω Figure 1. Test Circuit 7 ML6698 tTPWL tTPWH TXC TSM<4:0> tTPS tTPH Figure 2. tTPWH tTPWL tRPCF RXC RSM<4:0> tRCS tRCM Figure 3. 8 tRPCR ML6698 FUNCTIONAL DESCRIPTION TRANSMIT SECTION 100BASE-TX Operation The transmitter accepts scrambled 5-bit symbols clocked in at 25MHz and outputs MLT-3 signals onto the twisted-pair media at 100Mbps. The on-chip transmit PLL converts a 25MHz TTL-level clock at TXC to an internal 125MHz bit clock. TXC from the ML6698 clocks scrambled transmit symbols from the MAC into the ML6698's TSM<4:0> input pins. Symbols from the TSM<4:0> inputs are converted from parallel to serial form at the 125MHz clock rate. The serial transmit data is converted to MLT-3 3-level code and driven differentialy out of the TPOUTP and TPOUTN pins at nominal ± 2V levels with the proper loads. The transmitter is designed to drive a center-tapped transformer with a 2:1 winding ratio, so a differential 400 ohm load is used on the transformer primary to properly terminate the 100 ohm cable and termination on the secondary. The transformer’s center tap must be tied to VCC. A 2:1 transformer allows using a ±20mA output current in 100BASE-TX mode. Using a 1:1 transformer would have required twice the output current and increased the on-chip power dissipation. An external 2.49kW, 1% resistor at the RTSET pin creates the correct output levels at TPOUP/N. 10BASE-T In 10BASE-T mode, the transmitter acts as a linear buffer with a gain of 10. 10BASE-T inputs (Manchester data and normal link pulses) at 10BTTXINP/N appear as full-swing signals at TPOUTP/N in this mode. Inputs to the 10BTTXINP/N pins should have a nominal ±0.25V differential amplitude and a common-mode voltage of VCC/2, and should also be waveshaped or filtered to meet the 10BASE-T harmonic content requirements. The ML6698 does not provide any 10BASE-T transmit filtering. ML6698 SCHEMATIC Figure 2 shows a general design where the 5-bit and other control signals interface to the controller. TXC is connected to a 25MHz, 100ppm clock oscillator. Inductors L1 and L2 are for the purpose of improving return loss. Capacitor C7 is recommended. It decouples some noise at the inputs of the ML6698 and improves the Bit Error Rate (BER) performance of the board. It is recommended having a 0.1µF capacitor on every VCC pin as indicated by C3, 4, 9-12. Also, it is recommended to split the AVCC and DVCC, AGND and DGND. It is recommended that AGND and DGND planes are large enough for low inductance. If splitting the two grounds and keeping the ground planes large enough is not possible due to board space, you could join them into one larger ground plane. DIFFERENCES BETWEEN THE ML6694 AND ML6698 Both parts are pin to pin compatible and perform the same functions. The only differences are: 1. SDO: The ML6694 has SDO (Signal Detect Output) active in 100BASE-TX mode only, while the ML6698 has it active in both 10BASE-T and 100BASE-TX modes. 2. SEL10/100 or SEL100/10: The ML6694 has the 100BASE-TX mode active low and the 10BASE-T mode active high (SEL10/100). The ML6698 has the opposite polarity where the 100BASE-TX mode is active high and the 10BASE-T mode is active low (SEL100/10). RECEIVE SECTION The receiver converts 3-level MLT-3 signals from the twisted-pair media to 5-bit scrambled symbols at RSM<4:0> with extracted clock at RXC. The adaptive equalizer compensates for the distortion of up to 140m of cable and attenuates cable-induced jitter, corrects for DC baseline wander, and converts the MLT-3 signal to 2-level NRZ. The receive PLL extracts clock from the equalized signal, providing additional jitter attenuation, and clocks the signal through the serial to parallel converter. The resulting 5-bit symbols appear at RSM<4:0>. The extracted clock appears at RXC. Resistor RGMSET sets internal time constants controlling the adaptive equalizer’s transfer function. RGMSET must be set to 9.53k (1%). LOOPBACK Tying LPBK pin low places the part in loopback mode. Data at TXD<4:0> are serialized, MLT-3 encoded, equalized, then sent to receive PLL for clock recovery and sent to the RXD<4:0> outputs. In this mode, data at TXD<4:0> has to be valid 5-bit symbol data. 9 ML6698 4 U2 2 3 AVCC FB1 + INPUT FROM A 10BASE-T PHY 1 INPUT FROM A CONTROLLER, OTHERWISE FLOAT NC DVCC C3 C9 C10 + C6 C4 C11 C5 C12 FB2 OUTPUTS TO A 10BASE-T PHY 1:1 10BTTXINN 8 RSM4 TPINP 38 9 RSM3 TPINN 37 10 DGND1 AVCC2 36 R10 8 L1 R8 AVCC TPOUTN 33 14 DGND2 R9 AGND3 32 15 RSM0 R16 R18 20 21 22 23 R19 R21 R22 R20 24 25 26 NC NC 29 NC SEL100/10 SDO DGND5 DVCC5 DGND4C DGND4B DGND4A 18 19 DVCC 27 R17 L2 RGMSET 30 17 DGND3 RJ45 SHIELD GROUNDED R15 2:1 U5 RTSET 31 16 RXC 6 RXTP– 7 R11 TPOUTP 34 13 RSM1 5 C7 AGND2 35 ML6698 U1 12 DVCC1 DVCC2 3 RXTP+ 4 C1 CMREF 39 11 RSM2 1 TXTP+ 2 TXTP– R23 40 AVCC3 CONTROLLER INTERFACE 7 PWRDN 41 10BTTXINP LPBK AGND1 44 43 42 AVCC1 1 TXC 2 TSM4 3 TSM3 4 TSM2 TSM1 5 TSM0 6 R2 R1 C8 C2 28 AVCC R1 2.49kW 1%, 1/8W Surface Mount C7 10pF Cap R2 9.53kW 1%, 1/8W Surface Mount C2 Board Layer Cap (2kV rated) R8, R9, R23 200W 1%, 1/8W Surface Mount U1 ML6698 44-PLCC Surface Mount U2 Clock Oscillator, 25MHz 4-Pin Surface Mount R10, R11 100W 1%, 1/8W Surface Mount U5 R15-R20 49.9W 5%, 1/8W Surface Mount R21-R22 75W 5%, 1/8W Surface Mount Bel Transformer Module S558-1287-02, XFMRS Inc. XF6692TX, or Valor ST6129 (not pin compatible) FB1, FB2 Fair-Rite SM Bead P/N 2775019447 L1, L2 130nH Inductors rated at 50MHz C1, C3, 0.1µF Ceramic Chip Cap C4, C8-C12 C5, C6 10µF Tantalum Cap Figure 2. ML6698 Typical Applications Circuit 10 ML6698 PHYSICAL DIMENSIONS inches (millimeters) Package: Q44 44-Pin PLCC 0.685 - 0.695 (17.40 - 17.65) 0.042 - 0.056 (1.07 - 1.42) 0.650 - 0.656 (16.51 - 16.66) 0.025 - 0.045 (0.63 - 1.14) (RADIUS) 1 PIN 1 ID 0.042 - 0.048 (1.07 - 1.22) 12 34 0.650 - 0.656 0.685 - 0.695 (16.51 - 16.66) (17.40 - 17.65) 0.500 BSC (12.70 BSC) 0.590 - 0.630 (14.99 - 16.00) 23 0.009 - 0.011 (0.23 - 0.28) 0.050 BSC (1.27 BSC) 0.165 - 0.180 (4.06 - 4.57) 0.026 - 0.032 (0.66 - 0.81) 0.013 - 0.021 (0.33 - 0.53) 0.100 - 0.112 (2.54 - 2.84) 0.148 - 0.156 (3.76 - 3.96) SEATING PLANE Package: H44-10 44-Pin (10 x 10 x 1mm) TQFP 0.472 BSC (12.00 BSC) 0º - 8º 0.394 BSC (10.00 BSC) 0.003 - 0.008 (0.09 - 0.20) 34 1 PIN 1 ID 0.394 BSC (10.00 BSC) 0.472 BSC (12.00 BSC) 0.018 - 0.030 (0.45 - 0.75) 23 12 0.032 BSC (0.80 BSC) 0.012 - 0.018 (0.29 - 0.45) 0.048 MAX (1.20 MAX) SEATING PLANE 0.037 - 0.041 (0.95 - 1.05) 11 ML6698 ORDERING INFORMATION PART NUMBER TEMPERATURE RANGE PACKAGE ML6698CQ (End Of Life) 0°C to 70°C 44-PIN PLCC (Q44) ML6698CH 0°C to 70°C 44-PIN TQFP (H44-10) © Micro Linear 1997 is a registered trademark of Micro Linear Corporation Products described in this document may be covered by one or more of the following patents, U.S.: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; Japan: 2598946; 2619299. Other patents are pending. Micro Linear reserves the right to make changes to any product herein to improve reliability, function or design. Micro Linear does not assume any liability arising out of the application or use of any product described herein, neither does it convey any license under its patent right nor the rights of others. The circuits contained in this data sheet are offered as possible applications only. Micro Linear makes no warranties or representations as to whether the illustrated circuits infringe any intellectual property rights of others, and will accept no responsibility or liability for use of any application herein. The customer is urged to consult with appropriate legal counsel before deciding on a particular application. 12 2092 Concourse Drive San Jose, CA 95131 Tel: 408/433-5200 Fax: 408/432-0295 Ds6698-01