July 1997 PRELIMINARY ML6697 100BASE-TX Physical Layer with MII GENERAL DESCRIPTION FEATURES The ML6697 implements the complete physical layer of the Fast Ethernet 100BASE-TX standard. The ML6697 offers a single-chip per-port solution for MII-based repeater applications. The ML6697 interfaces to the controller through the Media Independent Interface (MII). n Single-chip 100BASE-TX physical layer The ML6697 functionality includes 4B/5B encoding/ decoding, Stream Cipher scrambling/descrambling, 125MHz clock recovery/generation, receive adaptive equalization, baseline wander correction, and MLT-3 transmitter. n Compliant MII (Media Indendent Interface) n Compliant to IEEE 802.3u 100BASE-TX standard n Supports MII-based repeater applications n 4B/5B encoder/decoder n Stream Cipher scrambler/descrambler n 125MHz clock recovery/generation n Baseline wander correction n Adaptive equalization and MLT-3 encoding/decoding BLOCK DIAGRAM (PLCC Package) 8 18 19 17 10 12 14 16 21 23 TXEN NRZ TO NRZI ENCODER SCRAMBLER SERIALIZER FLP/100BASE-TX TWISTED PAIR DRIVER TPOUTN RTSET MLT-3 ENCODER 40 39 37 TXER CRS CLOCK AND DATA RECOVERY EQUALIZER TPINP NRZI TO NRZ DECODER BLW CORRECTION TPINN DESERIALIZER MLT-3 DECODER RXEN RXCLK RXD3 PCS RECEIVE STATE MACHINE LOOPBACK MUX RXD2 RXD1 RXD0 CMREF RGMSET LINK100 5B/4B DECODER 45 44 46 36 43 DESCRAMBLER MII MANAGEMENT REGISTERS AND CONTROL LOGIC RXDV RXER 24 25 29 30 31 32 PHYAD4 7 TXD0 TPOUTP 4B/5B ENCODER PHYAD3 6 TXD1 PCS TRANSMIT STATE MACHINE PHYAD2 5 TXD2 PHYAD1 4 TXD3 PHYAD0 3 CLOCK SYNTHESIZER TXCLK MDIO 9 TXCLKIN MDC 1 33 1 ML6697 PIN CONFIGURATION TXEN TXD0 TXD1 TXD2 TXD3 AGND1 TXCLKIN AVCC1 NC NC NC NC NC ML6697 52-Pin PLCC (Q52) 7 6 5 4 3 2 1 52 51 50 49 48 47 TXER 8 46 CMREF TXCLK 9 45 TPINP RXD3 10 44 TPINN DGND1 11 43 LINK100 RXD2 12 42 AVCC2 DVCC1 13 41 AGND2 CRS 18 36 RGMSET RXEN 19 35 AVCC3B 20 21 34 AVCC3A 2 22 23 24 25 26 RXER RXDV DGND3 27 28 29 30 31 32 33 PHYAD4 RTSET PHYAD3 37 PHYAD2 17 PHYAD1 AGND3 RXCLK PHYAD0 TPOUTN 38 DVCC5 39 16 DGND5 15 RXD0 DGND4 TPOUTP MDIO 40 MDC 14 DVCC2 RXD1 DGND2 ML6697 PIN CONFIGURATION (Continued) TXER TXEN TXD0 TXD1 TXD2 TXD3 AGND1A AGND1B TXCLKIN AVCC1 NC NC NC NC NC NC ML6697 64-Pin TQFP (H64-10) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 TXCLK 1 48 NC RXD3 2 47 CMREF DGND1A 3 46 TPINP DGND1B 4 45 TPINN RXD2 5 44 LINK100 DVCC1A 6 43 AVCC2 DVCC1B 7 42 AGND2A RXD1 8 41 AGND2B DGND2A 9 40 TPOUTP DGND2B 10 39 TPOUTN RXD0 11 38 AGND3A AGND3B 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PHYAD4 AVCC3A 18 PHYAD3 33 17 PHYAD2 16 PHYAD1 DGND3B PHYAD0 AVCC3B DGND5B 34 DVCC5B 15 DGND5A DGND3A DVCC5A RGMSET DGND4B 35 DGND4A 14 MDIO RXEN RXER RTSET MDC 13 36 DVCC2 CRS RXCLK RXDV 12 37 3 ML6697 PIN DESCRIPTION (Pin numbers for TQFP package in parentheses) PIN NAME DESCRIPTION 1 (56) TXCLKIN Transmit clock TTL input. This 25MHz clock is the frequency reference for the internal transmit PLL clock multiplier. This pin should be driven by an external 25MHz clock at TTL or CMOS levels. 2 (58, 57) AGND1 Analog ground. 3, 4 5, 6 (59,60, 61,62) TXD<3:0> Transmit data TTL inputs. TXD<3:0> inputs accept TX data from the MII. Data appearing at TXD<3:0> are clocked into the ML6697 on the rising edge of TXCLK. 7 (63) TXEN Transmit enable TTL input. Driving this input high indicates to the ML6697 that transmit data are present at TXD<3:0>. TXEN edges should be synchronous with TXCLK. 8 (64) TXER Transmit error TTL input. Driving this pin high with TXEN also high causes the part to continuously transmit scrambled H symbols. When TXEN is low, TXER has no effect. 9 (1) TXCLK Transmit clock TTL output. This 25MHz clock is phase-aligned with the internal 125MHz TX bit clock. Data appearing at TXD<3:0> are clocked into the ML6697 on the rising edge of this clock. 10, 12, (2, 5, 14, 16 8, 11) RXD<3:0> Receive data TTL outputs. RXD<3:0> outputs are valid on RXCLK’s rising edge. 11 (3, 4) DGND1 Digital ground. 13 (6, 7) DVCC1 Digital +5V power supply. 15 (9, 10) DGND2 Digital ground. 17 (12) RXCLK Recovered receive clock TTL output. This 25MHz clock is phase-aligned with the internal 125MHz bit clock recovered from the signal received at TPINP/N. Receive data at RXD<3:0> changes on the falling edges and should be sampled on the rising edges of this clock. RXCLK is phase aligned to TXCLKIN when the 100BASE-TX signal is not present at TPINP/N. 18 (13) CRS Carrier Sense TTL output. CRS goes high in the presence of non-idle signals at TPINP/ N. CRS goes low when receive is idle. 19 (14) RXEN Receive enable TTL input. When this input is high, all the MII TTL outputs are enabled. When this input is low, all the MII TTL outputs are in high impedance mode. This input does not affect MDIO, TXCLK and CRS. 20 (15, 16) DGND3 Digital ground. 21 (17) RXDV Receive data valid TTL output. This output goes high when the ML6697 is receiving a data packet. RXDV should be sampled synchronously with RXCLK’s rising edge. 22 (18) DVCC2 Digital +5V power supply. 23 (19) RXER Receive error TTL output. This output goes high to indicate error or invalid symbols within a packet, or corrupted idle between packets. RXER should be sampled synchronously with RXCLK’s rising edge. 24 (20) MDC MII Management Interface clock TTL input. A clock at this pin clocks serial data into or out of the ML6697’s MII management registers through the MDIO pin. The maximum clock frequency at MDC is 2.5MHz. 4 ML6697 PIN DESCRIPTION (Continued) PIN NAME DESCRIPTION (21) MDIO MII Management Interface data TTL input/output. Serial data are written to and read from the ML6697’s management registers through this I/O pin. Input data is sampled on the rising edge of MDC. Data output should be sampled synchronously with MDC's rising edge. 26 (22, 23) DGND4 Digital ground. 27 (24, 25) DVCC5 Digital +5V power supply. 28 (26, 27) DGND5 Digital ground. 29 (28) PHYAD0 MII Serial Management Interface address bit 0. 30 (29) PHYAD1 MII Serial Management Interface address bit 1. 31 (30) PHYAD2 MII Serial Management Interface address bit 2. 32 (31) PHYAD3 MII Serial Management Interface address bit 3. 33 (32) PHYAD4 MII Serial Management Interface address bit 4. 34 (33) AVCC3A Analog +5V power supply. 35 (34) AVCC3B Analog +5V power supply. 36 (35) RGMSET Equalizer bias resistor input. An external 9.53kW, 1% resistor connected between RGMSET and AGND3 sets internal time constants controlling the receive equalizer transfer function. 37 (36) RTSET Transmit level bias resistor input. An external 2.49kW, 1% resistor connected between RTSET and AGND3 sets a precision constant bias current for the twisted pair transmit level. 38 (37, 38) AGND3 Analog ground. 39, 40 (39, 40) TPOUTN/P Transmit twisted pair outputs. This differential current output pair drives MLT-3 waveforms into the network coupling transformer. 41 AGND2 Analog ground. 25 (41, 42) 42 (43) AVCC2 Analog +5V power supply. 43 (44) LINK100 100BASE-TX link activity open-drain output. LINK100 pulls low when there is 100BASE-TX activity at TPINP/N in 100BASE-TX or auto-negotiation modes. This output is capable of driving an LED directly. 44, 45 (45, 46) TPINN/P Receive twisted pair inputs. This differential input pair receives 100BASE-TX signals from the network. 46 (47) CMREF Receiver common-mode reference output. This pin provides a common-mode bias point for the twisted-pair media line receiver, typically (VCC – 1.26)V. 52 (55) AVCC1 Analog +5V power supply. 5 ML6697 ABSOLUTE MAXIMUM RATINGS Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. VCC Supply Voltage Range .................. GND –0.3V to 6V Input Voltage Range Digital Inputs ...................... GND –0.3V to VCC +0.3V TPINP, TPINN, .................... GND –0.3V to VCC +0.3V Output Current TPOUTP, TPOUTN ............................................. 60mA All other outputs ................................................. 10mA Junction Temperature ............................................. 150°C Storage Temperature ..............................–65°C to +150°C Lead Temperature (Soldering, 10 sec) .................... 260°C Thermal Resistance (qJA) PLCC ............................................................... 40°C/W TQFP ............................................................... 52°C/W OPERATING CONDITIONS VCC Supply Voltage ........................................... 5V ± 5% All VCC supply pins must be within 0.1V of each other. All GND pins must be within 0.1V of each other. TA, Ambient temperature .............................. 0°C to 70°C RGMSET .................................................... 9.53kW ± 1% RTSET ........................................................ 2.49kW ± 1% Receive transformer insertion loss ...................... <–0.5dB DC ELECTRICAL CHARACTERISTICS Over full range of operating conditions unless otherwise specified (Note 1). SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS RECEIVER VICM TPINP/N Input Common-Mode Voltage (CMREF) VID TPINP-TPINN Differential Input Voltage Range –3.0 RIDR TPINP-TPINN Differential Input Resistance 10.0k IICM TPINP/N Common-Mode Input Current IRGM RGMSET Input Current RGMSET = 9.53kW 130 µA IRT RTSET Input Current RTSET = 2.49kW 500 µA VCC – 1.26 V 3.0 V W +10 µA LED OUTPUT (LINK100) IOLS Output Low Current 5 mA IOHS Output Off Current 10 µA ±19 ±21 mA 0 1.5 mA 500 µA TRANSMITTER ITD TPOUTP/N Differential Output Current Note 2, 3 ITOFF TPOUTP/N Off-State Output RL = 200, 1% ITXI TPOUTP/N Differential Output Current Imbalance RL = 200, 1% XERR TPOUTP/N Differential Output Current Error VOUT = VCC; Note 3 –5.0 +5.0 % XCMP TPOUTP/N Current Compliance Error VOUT = VCC ± 2.2V; referred to IOUT at VCC –2.0 +2.0 % 6 ML6697 DC ELECTRICAL CHARACTERISTICS (Continued) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS 200 300 mA 0.8 V POWER SUPPLY CURRENT ICC Supply Current, Transmitting Current into all VCC pins TTL INPUTS (TXD<3:0>, TXCLKIN, MDC, MDIO, TXEN, TXER, RXEN) VIL Input Low Voltage IIL = –400µA VIH Input High Voltage IIH = 100µA 2.0 V IIL Input Low Current VIN = 0.4V –200 µA IIH Input High Current VIN = 2.7V 100 µA 0.4 V MII TTL OUTPUTS (RXD<3:0>, RXCLK, RXDV, RXER, CRS, MDIO, TXCLK) VOLT Output Low Voltage IOL = 4mA VOHT Output High Voltage IOH = –4mA 2.4 V CMOS INPUTS (PHYAD<4:0>) VILC Input Low Voltage VIHC Input High Voltage 0.2 x VCC 0.8 x VCC V V Note 1. Limits are guaranteed by 100% testing, sampling, or correlation with worst case test conditions. 7 ML6697 AC ELECTRICAL CHARACTERISTICS Over full range of operating conditions unless otherwise specified (Note 1). SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS TRANSMITTER (Note 3) tTR/F TPOUTP-TPOUTN Differential Rise/Fall Time Notes 5, 6; for any legal code sequence 3.0 5.0 ns tTM TPOUTP-TPOUTN Differential Rise/Fall Time Mismatch Notes 5, 6; for any legal code sequence –0.5 0.5 ns tTDC TPOUTP-TPOUTN Differential Output Duty Cycle Distortion Notes 4, 6 –0.5 0.5 ns tTJT TPOUTP-TPOUTN Differential Output Peak-to-Peak Jitter Note 6 1400 ps XOST TPOUTP-TPOUTN Differential Output Voltage Overshoot Notes 6, 7 5 % tCLK TXCLKIN – TXCLK Delay 11 ns tTXP Transmit Bit Delay Note 8 10.5 bit times tRXDC Receive Bit Delay (CRS) Note 9 15.5 bit times tRXDR Receive Bit Delay (RXDV) Note 10 25.5 bit times +100 ppm 300 6 8 RECEIVER MII (Media-Independent Interface) XBTOL TX Output Clock Frequency Tolerance tTPWH TXCLKIN pulse width HIGH 14 ns tTPWL TXCLKIN pulse width LOW 14 ns tRPWH RXCLK pulse width HIGH 14 18 ns tRPWL RXCLK pulse width LOW 14 22 ns tTPS Setup time, TXD<3:0> Data Valid to TXCLK Rising Edge (1.4V point) 15 ns tTPH Hold Time, TXD<3:0> Data Valid After TXCLK Rising Edge (1.4V point) 0 ns tRCS Time that RXD<3:0> Data are Valid Before RXCLK Rising Edge (1.4V point) 10 20 ns tRCH Time that RXD<3:0> Data are Valid After RXCLK Rising Edge (1.4V point) 10 19 ns tRPCR RXCLK 10% – 90% Rise Time 6 ns tRPCF RXCLK 90%-10% Fall Time 6 ns tREND RXEN high to RXD<3:0>, RXDV, RXER, RXCLK Driving 2 10 ns tRENZ RXEN low to RXD<3:0>, RXDV, RXER, RXCLK High Impedence 2 10 ns 8 25MHz frequency –100 ML6697 AC ELECTRICAL CHARACTERISTICS (Continued) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS MDC-MDIO (MII Management Interface) tSPWS Write Setup Time, MDIO Data Valid to MDC Rising Edge 1.4V Point 10 ns tSPWH Write Hold Time, MDIO Data Valid After MDC Rising Edge 1.4V Point 10 ns tSPRS Read Setup Time, MDIO Data Valid to MDC Rising Edge 1.4V Point 100 ns tSPRH Read Hold Time, MDIO Data Valid After MDC Rising Edge 1.4V Point 0 ns tCPER Period of MDC 400 ns tCPW Pulsewidth of MDC 160 ns Note 1. Note 2. Note 3. Note 4. Note 5. Note 6. Note 7. Note 8. Note 9. Note 10. Positive or negative pulses Limits are guaranteed by 100% testing, sampling, or correlation with worst case test conditions. Measured using the test circuit shown in fig. 1, under the following conditions: RLP = 200W, RLS = 49.9W, RTSET = 2.49kW. All resistors are 1% tolerance. Output current amplitude is IOUT = 40 ´ 1.25V/RTSET. Measured relative to ideal negative and positive signal 50% points, using the four successive MLT-3 transitions for the 01010101 bit sequence. Time difference between 10% and 90% levels of the transition from the baseline voltage (nominally zero) to either the positive or negative peak signal voltage. The times specified here correlate to the transition times defined in the ANSI X3T9.5 TP-PMD Rev 2.0 working draft, section 9.1.6, which include the effects of the external network coupling transformer and EMI/RFI emissions filter. Differential test load is shown in fig. 1 (see note 2). Defined as the percentage excursion of the differential signal transition beyond its final adjusted value during the symbol interval following the transition. The adjusted value is obtained by doing a straight line best-fit to an output waveform containing 14 bit-times of no transition preceded by a transition from zero to either a positive or negative signal peak; the adjusted value is the point at which the straight line fit meets the rising or falling signal edge. From first rising edge of TXCLK after TXEN goes high, to first bit of J at the MDI. From first bit of J at the MDI, to CRS. From first bit of J at the MDI, to first rising edge of RXCLK after RXDV goes high. VCC TPOUTP 2:1 RLP 200Ω 1 RLP 200Ω 2 RLS 49.9Ω TPOUTN RLS 49.9Ω Figure 1. 9 ML6697 TXCLKIN tTPWH tTPWL TXCLK TXD<3:0> TXER TXEN tTPS tTPH Figure 2. MII Transmit Timing tRPCR tRPCF RXCLK RXD<3:0> RXER RXDV tRCS tRCH Figure 3. MII Receive Timing MDC MDIO tSPWS tSPWH Figure 4. MII Management Interface Write Timing tCPER MDC tSPRS tSPRH tCPW tCPW MDIO Figure 5. MII Management Interface Read Timing 10 ML6697 FUNCTIONAL DESCRIPTION TRANSMIT SECTION RECEIVE SECTION The transmitter includes everything necessary to accept 4-bit data nibbles clocked in at 25MHz at the MII and output scrambled, 5-bit encoded MLT-3 signals into twisted pair at 100Mbps. The on-chip transmit PLL converts a 25MHz TTL-level clock at TXCLKIN to an internal 125MHz bit clock. TXCLK from the ML6697 clocks transmit data from the MAC into the ML6697’s TXD<3:0> input pins upon assertion of TXEN. Data from the TXD<3:0> inputs are 5-bit encoded, scrambled, and converted from parallel to serial form at the 125MHz clock rate. The serial transmit data is converted to MLT-3 3-level code and driven differentially out of the TPOUTP and TPOUTN pins at nominal ±2V levels with the proper loads. The transmitter is designed to drive a center-tapped transformer with a 2:1 winding ratio, so a differential 400W load is used on the transformer primary to properly terminate the 100W cable and termination on the secondary. The transformer’s center tap must be tied to VCC. A 2:1 transformer allows using a ±20mA output current. Using a 1:1 transformer would have required twice the output current and increased the on-chip power dissipation. An external 2.49kW, 1% resistor at the RTSET pin creates the correct output levels at TPOUTP/N. The receiver includes all necessary functions for converting 3-level MLT-3 signals from the twisted-pair media to 4-bit data nibbles at RXD<3:0> with extracted clock at RXCLK. The adaptive equalizer compensates for cable distortion and attenuation, corrects for DC baseline wander, and converts the MLT-3 signal to 2-level NRZ. The receive PLL extracts clock from the equalized signal, providing additional jitter attenuation, and clocks the signal through the serial to parallel converter. The resulting 5-bit nibbles are descrambled, aligned and decoded, and appear at RXD<3:0>. The ML6692 asserts RXDV when it’s ready to present properly decoded receive data at RXD<3:0>. The extracted clock appears at RXCLK. Resistor RGMSET sets internal time constants controlling the adaptive equalizer’s transfer function. RGMSET must be set to 9.53kW (1%). Driving TXER high when TXEN is high causes the H symbol (00100) to appear in scrambled MLT-3 form at TPOUTP/N. The media access controller asserts TXER synchronously with TXCLK rising edge, and the H symbol appears at least once in place of a valid symbol in the current packet. With no data at TXD<3:0> scrambled idle appears at TPOUTP/N. The receiver will assert RXER high if it detects code errors in the receive data packet, or if the idle symbols between packets are corrupted. CRS goes high whenever there is non-idle receive activity in the network. ML6697 PHY MANAGEMENT FUNCTIONS The ML6697 has management functions controlled by the register locations given in Tables 1 and 2. There are two 16-bit MII Management registers, with several unused locations. Register 0 (Table 1) is the basic control register (read/write). Register 1 (Table 2) is the basic status register (read-only). The ML6697 powers on with all management register bits set to their default values. See IEEE 802.3u section 22.2.4 for a discussion of MII management functions and status/control register definitions. 11 ML6697 MII MANAGEMENT INTERFACE REGISTERS TABLE 1: CONTROL REGISTER BIT(s) NAME DESCRIPTION R/W DEFAULT R/W, SC 0 0.15 Reset 1 = reset all register bits to defaults 0 = normal operation 0.14 Loopback 1 = PMD loopback mode 0 = normal operation R/W 0 0.13 Manual Speed Select 1 = 100Mb/s 0 = 10Mb/s RO 1 0.11 Power down 1 = power down 0 = normal operation R/W 0 RO 0 R/W DEFAULT 0.12, 0.10-0.0 Not Used TABLE 2: STATUS REGISTER BIT(s) NAME DESCRIPTION 1.14 100BASE-TX full duplex 1 = full duplex 100BASE-TX capability 0 = No full duplex 100BASE-TX capability RO 0 1.13 100BASE-TX half duplex 1 = half duplex 100BASE-TX capability 0 = no half duplex 100BASE-TX capability RO 1 1.2 Link status 1 = 100BASE-TX line is up 0 = 100BASE-TX link is down RO/LL latch low after link fail until read 1.0 Extended capability 1 = extended register capabilities 0 = basic register set only RO 0 RO 0 1.15, 1.12-1.3, 1.1 NOTE: KEY: 12 Not used All unnamed or unused register locations will return a 0 value when accessed. LL = latch low until read, R/W = read/write, RO = read only, SC = self-clearing. MII INTERFACE RXEN MDIO MDC RXD3 RXD2 RXD1 RXD0 RXDV RXCLK RXER TXER 20 DGND3 19 RXEN TXD1 17 RXCLK 16 RXD0 15 DGND2 14 RXD1 13 DVCC1 12 RXD2 18 CRS TXCLK R3 21 22 23 24 25 26 27 28 29 30 AVCC3A 34 AVCC3B 35 RGMSET 36 RTSET 37 AGND3 38 TPOUTN 39 TPOUTP 40 AGND2 41 AVCC2 42 LINK100 43 TPINN 44 11 DGND1 TXD2 TXEN 48 47 10 RXD3 RXDV ML6697 U1 49 D1 TPINP 45 DGND4 9 TXCLK DVCC2 TXD0 52 51 50 31 32 PHYAD3 TXD3 1 DVCC5 CMREF 46 2 3 4 TXD2 NC NC NC NC NC 33 PHYAD4 CRS 5 DGND5 8 TXER TXEN 6 TXD0 7 TXD1 RXER TXD3 MDC AGND1 MDIO 3 TXCLKIN 2 AVCC1 4 NC PHYAD0 U2 NC PHYAD1 NC 1 NC PHYAD2 NC NC R2 R1 C1 1 14 L2 5 10 C9 L1 13 12 11 U6 2 3 4 C8 R9 R8 R11 C7 R10 C3 DVCC 6 9 7 8 D6 U5 2:1 1:1 C10 R21 C6 + D5 R14 C14 R13 C13 D2 C11 R18 R15 C4 R19 R22 R16 FB2 FB1 RXTP– RXTP+ TXTP– TXTP+ C5 R24 C2 R20 R17 R25 D3 RJ45 SHIELD GROUNDED 8 7 6 5 4 3 2 1 C12 + AVCC ML6697 Figure 6. Applications Circuit 13 ML6697 ML6697 SCHEMATIC Figure 6 shows a general ML6697 design. The inductors L1 and L2 are for the purpose of improving return loss. Capacitor C7 is recommended. It decouples some noise at the inputs of the ML6697, and improves the Bit Error Rate (BER) performance of the board. We recommend having a 0.1µF Cap on every VCC pin as indicated by C3, 4, 9-12. Also, we recommend splitting the VCC, AVCC, AGND and DGND. It is recommended that AGND and DGND planes are large enough for low inductance. If splitting the two grounds and keeping the ground planes large enough is not possible due to board space, you could join them into one larger ground plane. ML6697 PARTS LIST COMPONENT DESCRIPTION COMPONENT DESCRIPTION U1 ML6697 52-Pin PLCC surface mount R10, R11 50W 1% 1/8W surface mount U2 Can Crystal Oscillator, 25MHz 4-pin surface mount R13, R14 100kW 10% 1/8W surface mount R15–R20 49.9W 5% 1/8W surface mount U5 Transformer Module R21, R22 75W 5% 1/8W surface mount U6 HEX Inverter 74HC04 Fair-Rite SM Bead P/N 2775019447 C1,C3, C4, C8-12 0.1µF Ceramic Chip Cap FB1, FB2 L1, L2 130nH inductors rated at 50MHz C5, C6 10mF Tantalum Cap. R1 2.49kW 1% 1/8W surface mount C7 10pF Cap R2 9.53kW 1% 1/8W surface mount C2 Board layer Cap (2V rated) R3, R24, R25 750W 5% 1/8W surface mount C13, C14 22nF Cap R8, R9 200W 1% 1/8W surface mount D1-D3 LED Diodes D5-D6 Diodes Phillips PMLL 4148 14 ML6697 PHYSICAL DIMENSIONS inches (millimeters) Package: Q52 52-Pin PLCC 0.785 - 0.795 (19.94 - 20.19) 0.042 - 0.056 (1.07 - 1.42) 0.750 - 0.754 (19.05 - 19.15) 0.025 - 0.045 (0.63 - 1.14) (RADIUS) 1 PIN 1 ID 0.042 - 0.048 (1.07 - 1.22) 14 40 0.750 - 0.754 0.785 - 0.795 (19.05 - 19.15) (19.94 - 20.19) 0.600 BSC (15.24 BSC) 0.690 - 0.730 (17.53 - 18.54) 27 0.009 - 0.011 (0.23 - 0.28) 0.050 BSC (1.27 BSC) 0.026 - 0.032 (0.66 - 0.81) 0.013 - 0.021 (0.33 - 0.53) 0.165 - 0.180 (4.06 - 4.57) 0.148 - 0.156 (3.76 - 3.96) 0.100 - 0.110 (2.54 - 2.79) SEATING PLANE 15 ML6697 PHYSICAL DIMENSIONS inches (millimeters) Package: H64-10 64-Pin (10 x 10 x 1mm) TQFP 0.472 BSC (12.00 BSC) 0º - 8º 0.394 BSC (10.00 BSC) 0.003 - 0.008 (0.09 - 0.20) 49 1 PIN 1 ID 0.394 BSC (10.00 BSC) 0.472 BSC (12.00 BSC) 33 0.018 - 0.030 (0.45 - 0.75) 17 0.020 BSC (0.50 BSC) 0.007 - 0.011 (0.17 - 0.27) 0.048 MAX (1.20 MAX) SEATING PLANE 0.037 - 0.041 (0.95 - 1.05) ORDERING INFORMATION PART NUMBER ML6697CQ ML6697CH TEMPERATURE RANGE 0°C to 70°C 0°C to 70°C PACKAGE 52-Pin PLCC (Q52) 64-Pin TQFP (H64-10) Micro Linear makes no representations or warranties with respect to the accuracy, utility, or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. No license, express or implied, by estoppel or otherwise, to any patents or other intellectual property rights is granted by this document. The circuits contained in this document are offered as possible applications only. Particular uses or applications may invalidate some of the specifications and/or product descriptions contained herein. The customer is urged to perform its own engineering review before deciding on a particular application. Micro Linear assumes no liability whatsoever, and disclaims any express or implied warranty, relating to sale and/or use of Micro Linear products including liability or warranties relating to merchantability, fitness for a particular purpose, or infringement of any intellectual property right. Micro Linear products are not designed for use in medical, life saving, or life sustaining applications. is a registered trademark of Micro Linear Corporation. All other trademarks are the © Micro Linear 2000. property of their respective owners. Products described herein may be covered by one or more of the following U.S. patents: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; 5,652,479; 5,661,427; 5,663,874; 5,672,959; 5,689,167; 5,714,897; 5,717,798; 5,742,151; 5,747,977; 5,754,012; 5,757,174; 5,767,653; 5,777,514; 5,793,168; 5,798,635; 5,804,950; 5,808,455; 5,811,999; 5,818,207; 5,818,669; 5,825,165; 5,825,223; 5,838,723; 5.844,378; 5,844,941. Japan: 2,598,946; 2,619,299; 2,704,176; 2,821,714. Other patents are pending. 2092 Concourse Drive San Jose, CA 95131 Tel: 408/433-5200 Fax: 408/432-0295 16 DS6697-01