MICRONAS VPC3211A

ADVANCE INFORMATION
MICRONAS
Edition Jan. 19, 1999
6251-472-1AI
VPC323xD,
VPC324xD
Comb Filter Video
Processor
MICRONAS
VPC 323xD, VPC 324xD
ADVANCE INFORMATION
Contents
Page
Section
Title
5
5
6
7
1.
1.1.
1.2.
1.3.
Introduction
System Architecture
Video Processor Family
VPC Applications
8
8
8
8
8
8
8
8
9
9
10
10
10
11
11
11
11
12
13
13
13
13
13
13
14
14
14
14
15
15
15
15
16
16
16
17
17
17
17
17
18
18
2.
2.1.
2.1.1.
2.1.2.
2.1.3.
2.1.4.
2.1.5.
2.1.6.
2.2.
2.3.
2.3.1.
2.3.2.
2.3.3.
2.3.4.
2.3.5.
2.3.6.
2.3.7.
2.3.8.
2.3.9.
2.3.10.
2.4.
2.4.1.
2.4.2.
2.4.3.
2.4.4.
2.4.4.1.
2.4.4.2.
2.4.4.3.
2.4.5.
2.4.6.
2.5.
2.5.1.
2.5.2.
2.5.3.
2.5.4.
2.6.
2.7.
2.8.
2.9.
2.9.1.
2.9.2.
2.9.3.
Functional Description
Analog Video Front-End
Input Selector
Clamping
Automatic Gain Control
Analog-to-Digital Converters
Digitally Controlled Clock Oscillator
Analog Video Output
Adaptive Comb Filter
Color Decoder
IF-Compensation
Demodulator
Chrominance Filter
Frequency Demodulator
Burst Detection / Saturation Control
Color Killer Operation
Automatic standard recognition
PAL Compensation/1-H Comb Filter
Luminance Notch Filter
Skew Filtering
Component Interface Processor CIP
Component Analogue Front End
Matrix
Component YCrCb Control
Softmixer
Static Switch Mode
Static Mixer Mode
Dynamic Mixer Mode
4:4:4 to 4:2:2 Downsampling
Fast Blank and Signal Monitoring
Horizontal Scaler
Horizontal Lowpass-filter
Horizontal Prescaler
Horizontal Scaling Engine
Horizontal Peaking-filter
Vertical Scaler
Contrast and Brightness
Blackline Detector
Control and Data Output Signals
Line-Locked Clock Generation
Sync Signals
DIGIT3000 Output Format
2
Micronas
ADVANCE INFORMATION
VPC 323xD, VPC 324xD
Contents, continued
Page
Section
Title
18
18
18
20
20
20
20
20
22
24
24
25
25
28
28
28
28
28
29
2.9.4.
2.9.5.
2.9.6.
2.9.7.
2.9.8.
2.9.9.
2.10.
2.10.1.
2.11.
2.12.
2.12.1.
2.12.2.
2.12.3.
2.12.4.
2.12.5.
2.12.6.
2.12.7.
2.12.8.
2.12.9.
Line-Locked 4:2:2 Output Format
Line-Locked 4:1:1 Output Format
ITU-R 656 Output Format
Output Code Levels
Output Ports
Test Pattern Generator
PAL+ Support
Output Signals for PAL+/Color+ Support
Video Sync Processing
Picture in Picture (PIP) Processing and Control
Configurations
PIP Display Modes
Predefined Inset Picture Size
Acquisition and Display Window
Frame and Background Color
Vertical Shift of the Main Picture
Free Running Display Mode
Frame and Field Display Mode
External Field Memory
30
30
30
49
49
3.
3.1.
3.2.
3.2.1.
3.2.2.
Serial Interface
I2C-Bus Interface
Control and Status Registers
Calculation of Vertical and East-West Deflection Coefficients
Scaler Adjustment
51
51
51
54
57
58
59
59
59
60
61
61
61
61
62
63
63
64
64
66
67
4.
4.1.
4.2.
4.3.
4.4.
4.5.
4.6.
4.6.1.
4.6.2.
4.6.3.
4.6.4.
4.6.4.1.
4.6.4.2.
4.6.4.3.
4.6.4.4.
4.6.4.5.
4.6.4.6.
4.6.4.7.
4.6.4.8.
4.6.4.9.
4.6.4.10.
Specifications
Outline Dimensions
Pin Connections and Short Descriptions
Pin Descriptions (pin numbers for PQFP80 package)
Pin Configuration
Pin Circuits
Electrical Characteristics
Absolute Maximum Ratings
Recommended Operating Conditions
Recommended Crystal Characteristics
Characteristics
Characteristics, 5 MHz Clock Output
Characteristics, 20 MHz Clock Input/Output, External Clock Input (XTAL1)
Characteristics, Reset Input, Test Input, VGAV Input, YCOEQ Input
Characteristics, Power-up Sequence
Characteristics, FPDAT Input/Output
Characteristics, I2C Bus Interface
Characteristics, Analog Video and Component Inputs
Characteristics, Analog Front-End and ADCs
Characteristics, Analog FB Input
Characteristics, Output Pin Specification
Micronas
3
VPC 323xD, VPC 324xD
ADVANCE INFORMATION
Contents, continued
Page
Section
Title
69
70
4.6.4.11.
4.6.4.12.
Characteristics, Input Pin Specification
Characteristics, Clock Output Specification
71
72
73
73
73
75
75
75
76
5.
5.1.
5.2.
5.2.1.
5.2.2.
5.2.3.
5.2.3.1.
5.2.3.2.
5.2.3.3.
Application Circuit
Application Note: VGA mode with VPC 3215C
Application Note: PIP Mode Programming
Procedure to Program a PIP Mode
I2C Registers Programming for PIP Control
Examples
Select Predefined Mode 2
Select a Strobe Effect in Expert Mode
Select Predefined Mode 6 for Tuner Scanning
78
6.
Data Sheet History
4
Micronas
VPC 323xD, VPC 324xD
ADVANCE INFORMATION
Comb Filter Video Processor
1. Introduction
– display and deflection control (VPC 324xD)
The VPC 323xD/324xD is a high-quality, single-chip
video front-end, which is targeted for 4:3 and 16:9, 50/
60 and 100/120 Hz TV sets. It can be combined with
other members of the DIGIT3000 IC family (such as
DDP 33x0A/B, TPU 3040) and/or it can be used with
3rd-party products.
– peaking, contrast, brightness, color saturation and
tint for RGB/ YCrCb and CVBS/S-VHS
– high-quality soft mixer controlled by Fast Blank
1
- , or
– PIP processing for four picture sizes ( 1--4-, --91-, ----16
normal size) with 8 bit resolution
The main features of the VPC 323xD/324xD are
1
--of
36
– high-performance adaptive 4H comb filter Y/C separator with adjustable vertical peaking
– 15 predefined PIP display configurations and expert
mode (fully programmable)
– multi-standard color decoder PAL/NTSC/SECAM
including all substandards
– control interface for external field memory
– four CVBS, one S-VHS input, one CVBS output
– one 20.25 MHz crystal, few external components
– two RGB/YCrCb component inputs, one Fast Blank
(FB) input
– 80-pin PQFP package
– integrated high-quality A/D converters and associated clamp and AGC circuits
1.1. System Architecture
– I2C-Bus Interface
– multi-standard sync processing
Fig.1–1 shows the block diagram of the video processor
– linear horizontal scaling (0.25 ... 4), as well as
non-linear horizontal scaling ‘panorama vision’
– PAL+ preprocessing (VPC 323xD)
– line-locked clock, data and sync, or 656-output interface (VPC 323xD)
CIN
VIN1
Analog
Front-end
Adaptive
Comb
Filter
VIN2
Color
Decoder
Y
NTSC
PAL
SECAM
Cr
Cb
VIN3
VIN4
NTSC
PAL
AGC
2×ADC
VOUT
Saturation
Tint
Mixer
Y
2D Scaler
PIP
Output
Formatter
Cr
Panorama
Mode
ITU-R 656
ITU-R 601
Cb
Contrast
Brightness
Memory
Control
Peaking
FB
RGB/
YCrCb
Processing Y
Analog
Component U/B
Cr
Matrix
Front-End
Contrast
V/R
Saturation Cb
Brightness
4 x ADC
FB
FB
Tint
I2C Bus
Clock
Gen.
CrCb
OUT
YCOE
Y/G
RGB/
YCrCb
Y OUT
Sync
+
Clock
Generation
FIFO
CNTL
LL Clock
H Sync
V Sync
AVO
20.25 MHz I2C Bus
Fig. 1–1: .Block diagram of the VPC 323xD
Micronas
5
VPC 323xD, VPC 324xD
ADVANCE INFORMATION
1.2. Video Processor Family
The VPC video processor family supports 15/32-kHz
systems and is available with different comb filter
options. The 50-Hz/single-scan versions (e. g.
VPC 324xD) provide controlling for the display and the
vertical/east-west deflection of DDP 3300A. The
100-Hz/double-scan versions (e. g. VPC 323xD) have
a line-locked clock output interface and the PAL+ preprocessing option. Table 1–1 gives an overview of the
VPC video processor family.
Table 1–1: VPC Processor Family for 100 Hz, Double Scan and Line Locked Clock Application
Features
Typ
VPC 3230D
Adaptive
Combfilter (PAL/
NTSC)
Panorama
Vision
Analog
Component
Inputs
Vertical Scaler
(PIP)
4H
✓
2
✓
ITU-R 601,
ITU-R 656
✓
2
✓
ITU-R 601,
ITU-R 656
✓
✓
ITU-R 601,
ITU-R 656
✓
✓
ITU-R 601,
ITU-R 656
VPC 3231D
VPC 3232D
4H
VPC 3233D
Digital Output
Interface
VPC 3215C
4H
✓
ITU-R 601
VPC 3210A
2H
✓
ITU-R 601
✓
ITU-R 601
VPC 3211A
Table 1–2: VPC Processor Family for 50 Hz Single Scan Applications
Features
Typ
VPC 3240D
Adaptive
Combfilter (PAL/
NTSC)
Panorama
Vision
Analog
Component
Inputs
Vertical Scaler
(PIP)
4H
✓
2
✓
DIGIT 3000
✓
2
✓
DIGIT 3000
✓
✓
DIGIT 3000
✓
✓
DIGIT 3000
VPC 3241D
VPC 3242D
4H
VPC 3243D
VPC 3205C
4H
✓
DIGIT 3000
VPC 3200A
2H
✓
DIGIT 3000
✓
DIGIT 3000
VPC 3201A
6
Digital Output
Interface
Micronas
VPC 323xD, VPC 324xD
ADVANCE INFORMATION
1.3. VPC Applications
Fig. 1–2 depicts several VPC applications. Since the
VPC functions as a video front-end, it must be complemented with additional functionality to form a complete
TV set.
The DDP 33x0 contains the video back-end with video
postprocessing (contrast, peaking, DTI,...), H/V-deflection, RGB insertion (SCART, Text, PIP,...) and tube
control (cutoff, white drive, beam current limiter). It
generates a beam scan velocity modulation output
from the digital YCrCb and RGB signals. Note that this
signal is not generated from the external analog RGB
inputs.
The component interface of the VPC 32xxD provides a
high-quality analog RGB interface with character insertion capability. It also allows appropriate processing of
external sources, such as MPEG2 set-top boxes in
transparent (4:2:2) quality. Furthermore, it transforms
RGB/Fast Blank signals to the common digital video
bus and makes those signals available for 100-Hz upconversion or double-scan processing. In some European countries (Italy), this feature is mandatory.
The IP indicates memory based image processing,
such as scan rate conversion, vertical processing
(Zoom), or PAL+ reconstruction. The VPC supports
memory based applications through line-locked clocks,
syncs and data. Additionally, the VPC323xD provides
a 656-output interface and FIFO control signals.
Examples:
– Europe: 15 kHz/50 Hz → 32 kHz/100 Hz interlaced
– US: 15 kHz/60 Hz → 32 kHz/60 Hz non-interlaced
a) YCrCb/RGBFB
CVBS
VPC
32xxD
YCrCb/RGBFB
CVBS
RGB
VPC
32xxD
YCrCb
CVBS
VPC
32xxD
VPC
32xxD
b)
c) YCrCb/RGBFB
CVBS
FIFO
DDP
3300A
RGB
H/V
Defl.
IP
DDP
3310B
RGB
H/V
Defl.
IP
DDP
3310B
RGB
H/V
Defl.
Fig. 1–2: VPC 32xxD applications
a) 15 kHz application Europe
b) double scan application (US, Japan) with YCrCb inputs
c) 100 Hz application (Europe) with RGBFB inputs
Micronas
7
VPC 323xD, VPC 324xD
ADVANCE INFORMATION
2. Functional Description
2.1.3. Automatic Gain Control
2.1. Analog Video Front-End
A digitally working automatic gain control adjusts the
magnitude of the selected baseband by +6/–4.5 dB in
64 logarithmic steps to the optimal range of the ADC.
The gain of the video input stage including the ADC is
213 steps/V with the AGC set to 0 dB.
This block provides the analog interfaces to all video
inputs and mainly carries out analog-to-digital conversion for the following digital video processing. A block
diagram is given in Fig. 2–1.
Most of the functional blocks in the front-end are digitally controlled (clamping, AGC, and clock-DCO). The
control loops are closed by the Fast Processor (‘FP’)
embedded in the decoder.
2.1.1. Input Selector
Up to five analog inputs can be connected. Four inputs
are for composite video or S-VHS luma signal. These
inputs are clamped to the sync back porch and are amplified by a variable gain amplifier. One input is for connection of S-VHS carrier-chrominance signal. This input is
internally biased and has a fixed gain amplifier. A second
S-VHS chroma signal can be connected video-input
VIN1.
2.1.4. Analog-to-Digital Converters
Two ADCs are provided to digitize the input signals.
Each converter runs with 20.25 MHz and has 8 bit resolution. An integrated bandgap circuit generates the
required reference voltages for the converters. The two
ADCs are of a 2-stage subranging type.
2.1.5. Digitally Controlled Clock Oscillator
The clock generation is also a part of the analog front
end. The crystal oscillator is controlled digitally by the
control processor; the clock frequency can be adjusted
within ±150 ppm.
2.1.6. Analog Video Output
2.1.2. Clamping
The composite video input signals are AC coupled to
the IC. The clamping voltage is stored on the coupling
capacitors and is generated by digitally controlled current sources. The clamping level is the back porch of
the video signal. S-VHS chroma is also AC coupled.
The input pin is internally biased to the center of the
ADC input range.
Analog Video
Output
CVBS/Y
CVBS/Y
CVBS/Y/C
C
AGC
+6/–4.5 dB
VIN4
clamp
VIN3
VIN2
VIN1
input
mux
CVBS/Y
The input signal of the Luma ADC is available at the
analog video output pin. The signal at this pin must be
buffered by a source follower. The output voltage is
2 V, thus the signal can be used to drive a 75 Ω line.
The magnitude is adjusted with an AGC in 8 steps
together with the main AGC.
CIN
ADC
digital CVBS or Luma
ADC
digital Chroma
gain
bias
system clocks
reference
generation
frequency
DVCO
±150
ppm
20.25 MHz
Fig. 2–1: Analog front-end
8
Micronas
VPC 323xD, VPC 324xD
ADVANCE INFORMATION
2.2. Adaptive Comb Filter
The 4H adaptive comb filter is used for high-quality
luminance/chrominance separation for PAL or NTSC
composite video signals. The comb filter improves the
luminance resolution (bandwidth) and reduces interferences like cross-luminance and cross-color. The adaptive algorithm eliminates most of the mentioned errors
without introducing new artifacts or noise.
A block diagram of the comb filter is shown in Fig. 2–2.
The filter uses four line delays to process the information of three video lines. To have a fixed phase relationship of the color subcarrier in the three channels, the
system clock (20.25 MHz) is fractionally locked to the
color subcarrier. This allows the processing of all color
standards and substandards using a single crystal frequency.
The CVBS signal in the three channels is filtered at the
subcarrier frequency by a set of bandpass/notch filters. The output of the three channels is used by the
adaption logic to select the weighting that is used to
reconstruct the luminance/chrominance signal from
the 4 bandpass/notch filter signals. By using soft mixing of the 4 signals switching artifacts of the adaption
algorithm are completely suppressed.
The comb filter uses the middle line as reference,
therefore, the comb filter delay is two lines. If the comb
filter is switched off, the delay lines are used to pass
the luma/chroma signals from the A/D converters to
the luma/chroma outputs. Thus, the processing delay
is always two lines.
In order to obtain the best-suited picture quality, the
user has the possibility to influence the behaviour of
the adaption algorithm going from moderate combing
to strong combing. Therefore, the following three parameters may be adjusted:
– VDG ( vertical difference gain )
– DDR ( diagonal dot reducer )
VDG typically determines the comb filter behaviour on
vertical edges. As VDG increases, the comb strength,
e. g. the amount of hanging dots, decreases.
After selecting the combfilter performance in horizontal
and vertical direction, the diagonal picture performance may further be optimized by adjusting DDR. As
DDR increases, the dot crawl on diagonal colored
edges is reduced.
To enhance the vertical resolution of the picture, the
VPC provides a vertical peaking circuitry. The filter
gain is adjustable between 0 – +6 dB and a coring filter
suppresses small amplitudes to reduce noise artifacts.
In relation to the comb filter, this vertical peaking
widely contributes to an optimal two-dimensional resolution homogeneity.
2.3. Color Decoder
In this block, the standard luma/chroma separation and
multi-standard color demodulation is carried out. The
color demodulation uses an asynchronous clock, thus
allowing a unified architecture for all color standards.
A block diagram of the color decoder is shown in Fig.
2–4. The luma as well as the chroma processing, is
shown here. The color decoder also provides several
special modes, e.g. wide band chroma format which is
intended for S-VHS wide bandwidth chroma. Also, filter
settings are available for processing a PAL+ helper signal.
If the adaptive comb filter is used for luma chroma
separation, the color decoder uses the S-VHS mode
processing. The output of the color decoder is YCrCb
in a 4:2:2 format.
Bandpass
Filter
CVBS Input
Chroma Input
2H Delay Line
Bandpass/
Notch Filter
2H Delay Line
Bandpass
Filter
Luma / Chroma Mixers
Adaption Logic
– HDG ( horizontal difference gain )
HDG typically defines the comb strength on horizontal
edges. It determines the amount of the remaining
cross-luminance and the sharpness on edges respectively. As HDG increases, the comb strength, e. g.
cross luminance reduction and sharpness, increases.
Luma Output
Chroma Output
Fig. 2–2: Block diagram of the adaptive comb filter (PAL mode)
Micronas
9
VPC 323xD, VPC 324xD
ADVANCE INFORMATION
2.3.1. IF-Compensation
2.3.2. Demodulator
With off-air or mistuned reception, any attenuation at
higher frequencies or asymmetry around the color
subcarrier is compensated. Four different settings of
the IF-compensation are possible (see Fig. 2–3):
– 10 dB/MHz
The entire signal (which might still contain luma) is
quadrature-mixed to the baseband. The mixing frequency is equal to the subcarrier for PAL and NTSC,
thus achieving the chroma demodulation. For SECAM,
the mixing frequency is 4.286 MHz giving the quadrature baseband components of the FM modulated
chroma. After the mixer, a lowpass filter selects the
chroma components; a downsampling stage converts
the color difference signals to a multiplexed half rate
data stream.
The last setting gives a very large boost to high frequencies. It is provided for SECAM signals that are
decoded using a SAW filter specified originally for the
PAL standard.
The subcarrier frequency in the demodulator is generated by direct digital synthesis; therefore, substandards such as PAL 3.58 or NTSC 4.43 can also be
demodulated.
– flat (no compensation)
– 6 dB/octave
– 12 dB/octave
2.3.3. Chrominance Filter
dB
The demodulation is followed by a lowpass filter for the
color difference signals for PAL/NTSC. SECAM requires a modified lowpass function with bell-filter characteristic. At the output of the lowpass filter, all luma
information is eliminated.
The lowpass filters are calculated in time multiplex for
the two color signals. Three bandwidth settings (narrow, normal, broad) are available for each standard
(see Fig. 2–5). For PAL/NTSC, a wide band chroma filter can be selected. This filter is intended for high
bandwidth chroma signals, e.g. a nonstandard wide
bandwidth S-VHS signal.
MHz
Fig. 2–3: Frequency response of chroma IF-compensation
Notch
Filter
MUX
Luma / CVBS
1 H Delay
Luma
Chroma
CrossSwitch
MUX
ACC
Chroma
IF Compensation
MIXER
DC-Reject
Lowpass Filter
Phase/Freq
Demodulator
ColorPLL/ColorACC
Fig. 2–4: Color decoder
10
Micronas
VPC 323xD, VPC 324xD
ADVANCE INFORMATION
color killer operation; they are used for automatic standard detection as well.
dB
2.3.6. Color Killer Operation
PAL/NTSC
MHz
dB
The color killer uses the burst-phase/burst-frequency
measurement to identify a PAL/NTSC or SECAM color
signal. For PAL/NTSC, the color is switched off (killed)
as long as the color subcarrier PLL is not locked. For
SECAM, the killer is controlled by the toggle of the
burst frequency. The burst amplitude measurement is
used to switch-off the color if the burst amplitude is
below a programmable threshold. Thus, color will be
killed for very noisy signals. The color amplitude killer
has a programmable hysteresis.
2.3.7. Automatic standard recognition
SECAM
MHz
Fig. 2–5: Frequency response of chroma filters
The burst-frequency measurement is also used for
automatic standard recognition (together with the status of horizontal and vertical locking) thus allowing a
completely independent search of the line and color
standard of the input signal. The following standards
can be distinguished:
2.3.4. Frequency Demodulator
PAL B,G,H,I; NTSC M; SECAM; NTSC 44; PAL M;
PAL N; PAL 60
The frequency demodulator for demodulating the SECAM signal is implemented as a CORDIC-structure. It
calculates the phase and magnitude of the quadrature
components by coordinate rotation.
For a preselection of allowed standards, the recognition can be enabled/disabled via I2C bus for each standard separately.
The phase output of the CORDIC processor is differentiated to obtain the demodulated frequency. After
the deemphasis filter, the Dr and Db signals are scaled
to standard CrCb amplitudes and fed to the crossover-switch.
2.3.5. Burst Detection / Saturation Control
In the PAL/NTSC-system the burst is the reference for
the color signal. The phase and magnitude outputs of
the CORDIC are gated with the color key and used for
controlling the phase-lock-loop (APC) of the demodulator and the automatic color control (ACC) in PAL/NTSC.
The ACC has a control range of +30 ... –6 dB.
If at least one standard is enabled, the VPC32xxD
checks regularly the horizontal and vertical locking of
the input signal and the state of the color killer. If an
error exists for several adjacent fields a new standard
search is started. Depending on the measured line
number and burst frequency the current standard is
selected.
For error handling the recognition algorithm delivers
the following status information:
– search active (busy)
– search terminated, but failed
– found standard is disabled
– vertical standard invalid
Color saturation can be selected once for all color
standards. In PAL/NTSC it is used as reference for the
ACC. In SECAM the necessary gains are calculated
automatically.
For SECAM decoding, the frequency of the burst is
measured. Thus, the current chroma carrier frequency
can be identified and is used to control the SECAM
processing. The burst measurements also control the
Micronas
11
VPC 323xD, VPC 324xD
ADVANCE INFORMATION
2.3.8. PAL Compensation/1-H Comb Filter
The color decoder uses one fully integrated delay line.
Only active video is stored.
CVBS
Y
Notch
filter
8
– NTSC:
1-H comb filter or color compensation
– PAL:
color compensation
Y
8
Chroma
Process.
The delay line application depends on the color standard:
Luma
Cr C b
a) conventional
chroma
8
Chroma
Process.
Cr C b
b) S-VHS
CVBS
Y
Notch
filter
8
– SECAM: crossover-switch
In the NTSC compensated mode, Fig. 2–6 c), the color
signal is averaged for two adjacent lines. Thus,
cross-color distortion and chroma noise is reduced. In
the NTSC 1-H comb filter mode, Fig. 2–6 d), the delay
line is in the composite signal path, thus allowing
reduction of cross-color components, as well as
cross-luminance. The loss of vertical resolution in the
luminance channel is compensated by adding the vertical detail signal with removed color information. If the
4H adaptive comb filter is used, the 1-H NTSC comb
filter has to be deselected.
Chroma
Process.
Cr C b
1H
Delay
c) compensated
8
Y
Notch
filter
CVBS
1H
Delay
Cr C b
Chroma
Process.
d) comb filter
Fig. 2–6: NTSC color decoding options
CVBS
8
Y
Notch
filter
Chroma
Process.
1H
Delay
Cr C b
a) conventional
Luma
Y
8
Chroma
8
Chroma
Process.
Cr C b
1H
Delay
b) S-VHS
Fig. 2–7: PAL color decoding options
CVBS
8
Y
Notch
filter
Chroma
Process.
1H
Delay
MUX
Cr C b
Fig. 2–8: SECAM color decoding
12
Micronas
VPC 323xD, VPC 324xD
ADVANCE INFORMATION
2.3.9. Luminance Notch Filter
2.4. Component Interface Processor CIP
If a composite video signal is applied, the color information is suppressed by a programmable notch filter.
The position of the filter center frequency depends on
the subcarrier frequency for PAL/NTSC. For SECAM,
the notch is directly controlled by the chroma carrier
frequency. This considerably reduces the cross-luminance. The frequency responses for all three systems
are shown in Fig. 2–9.
This block (see Fig. 2–10) contains all the necessary
circuitry dedicated to external analogue components
(YCrCb_cip) such as RGB or YCrCb signals from DVD
players, or other RGB sources with Fast Blank for real
time insertion on the main picture (YCrCb_main).
10
2.4.1. Component Analogue Front End
VPC 32xxD provides two analogue RGB/YCrCb input
ports, one with Fast Blank capability and one without.
dB
0
It is strongly recommended to use analogue 5 MHz
anti-alias low-pass filters on each input, including FB.
While all signals need to be capacitively coupled by
220 nF clamping capacitors, the Fast Blank input
requires DC coupling.
–10
–20
–30
–40
0
2
4
6
8
10
MHz
PAL/NTSC notch filter
10
The selected signal channel is further converted into a
digital form by 3 high quality ADCs running at
20.25 MHz with a resolution of 8 bits. The FB input is
digitized with a resolution of 6 bits.
Note: The VPC32xxD system synchronization always
occurs through the main CVBS/Y ADC input. In any
component mode, this input must therefore be handled
accordingly.
dB
0
–10
2.4.2. Matrix
–20
The RGB signals are converted to the YCrCb format by
a matrix operation:
–30
–40
0
2
4
6
8
10
MHz
SECAM notch filter
Y = 0.299R + 0.587G + 0.114B
(R−Y)= 0.701R − 0.587G − 0.114B
(B−Y)=−0.299R − 0.587G + 0.886B
Fig. 2–9: Frequency responses of the luma
notch filter for PAL, NTSC, SECAM
In case of YCrCb input the matrix is bypassed.
2.3.10. Skew Filtering
2.4.3. Component YCrCb Control
The system clock is free-running and not locked to the
TV line frequency. Therefore, the ADC sampling pattern is not orthogonal. The decoded YCrCb signals are
converted to an orthogonal sampling raster by the
skew filters, which are part of the scaler block.
To guarantee optimum mixing results, various I2C programmable parameters are provided:
The skew filters are controlled by a skew parameter
and allow the application of a group delay to the input
signals without introducing waveform or frequency
response distortion.
– 0 ≤ contrast ≤63/32
– −128 ≤ brightness ≤ 127
– 0 ≤ saturation Cr ≤ 63/32
– 0 ≤ saturation Cb ≤ 63/32
– −20 ≤ tint ≤ 20 degrees
The amount of phase shift of this filter is controlled by
the horizontal PLL1. The accuracy of the filters is 1/32
clocks for luminance and 1/4 clocks for chroma. Thus
the 4:2:2 YCrCb data is in an orthogonal pixel format
even in the case of nonstandard input signals such as
VCR.
Micronas
13
VPC 323xD, VPC 324xD
ADVANCE INFORMATION
Table 2–1 gives the picture settings achieving exact
level matching between the YCrCb_cip and
YCrCb_main channel.
The factor k is clamped to 0 or 64, hence selecting
YCrCb_main or the component input YCrCb_cip. (see
Table 2–2)
Table 2–1: Standard picture settings
2.4.4.2. Static Mixer Mode
input
format
contrast
brightness
satCr
satCb
RGB
27
68
29
23
YCrCb
27
68
40
40
The signal YCrCb_main and the component signal
YCrCb_cip may also be statically mixed. In this environment, k is manually controlled via I2C registers
FBGAIN and FBOFFS according to the following
expression:
k = FBGAIN*(31−FBOFFS) + 32
Note: R, G, B, Cr, Cb, = 0.7 Vpp, Y(+ sync) 1 Vpp
2.4.4. Softmixer
All the necessary limitation and rounding operation are
built-in to fit the range: 0 ≤ k ≤ 64.
After an automatic delay matching, the component signals and the upsampled main video signal are gathered onto a unique YCrCb channel by means of a versatile 4:4:4 softmixer (see also Fig. 2–10).
In the static mixer mode as well as in the previously
mentioned static switch mode (see Table 2–2), the
softmixer operates independently of the analogue Fast
Blank input.
The softmixer circuit consists of a Fast Blank (FB) processing block supplying a mixing factor k (0...64) to a
high quality signal mixer achieving the output function:
2.4.4.3. Dynamic Mixer Mode
YCrCb_mix=( k*YCrCb_main+ (64-k)*YCrCb_cip )/64
In the dynamic mixer mode, the mixer is controlled by
the Fast Blank signal. The VPC32xxD provides a linear
mixing coefficient
The softmixer supports several basic modes that are
selected via I2C bus (see Table 2–2).
k=kl = FBGAIN*(FB−FBOFFS) + 32
(FB is the digitized Fast Blank), and a non-linear mixing coefficient knl=F(kl), which results from a further
non-linear processing of kl.
2.4.4.1. Static Switch Mode
In its simplest and most common application the softmixer is used as a static switch between YCrCb_main
and YCrCb_cip. This is for instance the adequate way
to handle a DVD component signal.
While the linear mixing coefficient is used to insert a
fullscreen video signal, the non-linear coefficient is
well-suited to insert Fast Blank related signals like text.
The non-linear mixing reduces disturbing effects like
over/undershoots at critical Fast Blank edges.
mixer
YCrCb_main
VIDEO
Y/C processing
YCrCb_mix
YCrCb_cip
RGB/YCrCb
Component
Processing
Fig. 2–10: Block diagram of the component mixer
14
Micronas
VPC 323xD, VPC 324xD
ADVANCE INFORMATION
Table 2–2: CIP softmixer modes
I2C
SELLIN
RGB
DLY
analog fast
blank input
FBCLP
FB
MODE
CIP
mode
0
x
reading I2C
register <27>
<27>FBLSTAT
0
1
1
0
0
<27>FBLRISE
0
1
0
0
0
<27>FBLFALL
0
0
0
1
0
<27>FBLHIGH
0
1
1
1
0
Force
YCrCb
main
0
11
Force
RGB/
YCrCb
0
0
x
x0
Static
Mixer
0
0
1
01
An additional monitoring bit is also provided for the
RGB/YCrCb signal; it indicates whether the ADCs
inputs are clipped or not. In case of clipping conditions
(1Vpp RGB input for example) the ADC range can be
extended by 3db by using the XAR bit.
FB
Linear
0
0
0
01
– CLIPD: set by RGB/YCrCb input clip, reset by register read
FB nonLinear
1
1
0
01
2.5. Horizontal Scaler
Fig. 2–11: Fast Blank Monitor
2.4.5. 4:4:4 to 4:2:2 Downsampling
After the mixer, the 4:4:4 YCrCb_mix data stream is
downsampled to the 4:2:2 format. For this sake, a
chroma lowpass filter is provided to eliminate high-frequency components above 5-6 Mhz which may typically be present on inserted high resolution RGB/
YCrCb sources.
In case of main video processing (loopthrough) only, it
is recommended to bypass this filter by using the I2C
bit CIPCFBY.
The 4:2:2 YCrCb signal from the mixer output is processed by the horizontal scaler. It contains a lowpassfilter, a prescaler, a scaling engine and a peaking filter.
The scaler block allows a linear or nonlinear horizontal
scaling of the input signal in the range of 1/32 to 4.
Nonlinear scaling, also called “panorama vision”, provides a geometrical distortion of the input picture. It is
used to fit a picture with 4:3 format on a 16:9 screen by
stretching the picture geometry at the borders. Also,
the inverse effect - called water glass - can be produced by the scaler. A summary of scaler modes is
given in Table 2–3.
2.5.1. Horizontal Lowpass-filter
2.4.6. Fast Blank and Signal Monitoring
The analogue Fast Blank state is monitored by means
of four I2C readable bits. These bits may be used by
the TV controller for SCART signal ident:
The luma filter block applies anti-aliasing lowpass filters. The cutoff frequencies are selectable and have to
be adapted to the horizontal scaling ratio.
– FBHIGH: set by FB high, reset by register read at
FB low
– FBSTAT: FB status at register read
– FBRISE: set by FB rising edge, reset by register
read
– FBFALL: set by FB falling edge, reset by register
read
Micronas
15
VPC 323xD, VPC 324xD
ADVANCE INFORMATION
dB
Table 2–3: Scaler modes
10
0
Mode
-10
-20
Scale
Factor
Compression
4:3 → 16:9
0.75
linear
4:3 source displayed on
a 16:9 tube,
with side panels
Panorama
4:3 →16:9
nonlinear
compr
4:3 source displayed on
a 16:9 tube,
Borders distorted
Zoom
4:3 → 4:3
1.33
linear
Letterbox source (PAL+)
displayed on a 4:3 tube,
vertical overscan with
cropping of side panels
Water glass
16:9 → 4:3
nonlinear
zoom
Letterbox source (PAL+)
displayed on a 4:3 tube,
vertical overscan, borders distorted, no cropping
20.25 →
13.5 MHz
0.66
sample rate conversion
to line-locked clock
-30
-40
-50
2
4
6
8
Description
10
MHz
dB
10
0
-10
-20
-30
-40
-50
1
2
3
4
5
MHz
Fig. 2–12: YCrCb downsampling lowpass-filter
2.5.2. Horizontal Prescaler
To achieve a horizontal compression ratio between
1/4 and 1/32 (e. g. for double window or PIP operation)
a linear downsampler resamples the input signal by 1
(no presampling), 2, 4 and 8.
2.5.4. Horizontal Peaking-filter
The horizontal scaler block offers an extra peaking filter for sharpness control. The center frequency of the
peaking filter automatically adopts to the horizontal
scaling ratio. Three center frequencies are selectable
(see Fig. 2–13: )
– center at sampling rate / 2
– center at sampling rate / 4
– center at sampling rate / 6
2.5.3. Horizontal Scaling Engine
The scaler contains a programmable decimation filter,
a 1-H FIFO memory, and a programmable interpolation filter. The scaler input filter is also used for pixel
skew correction, see 2.3.10. The decimator/interpolator structure allows optimal use of the FIFO memory. It
allows a linear or nonlinear horizontal scaling of the
input video signal in the range of 0.25 to 4. The controlling of the scaler is done by the internal Fast Processor.
16
The filter gain is adjustable between 0 – +10 dB and a
coring filter suppresses small amplitudes to reduce
noise artifacts.
Micronas
VPC 323xD, VPC 324xD
ADVANCE INFORMATION
amplitude, the external controller reads this register,
calculates the vertical scaling coefficient and transfers
the new settings, e.g. vertical sawtooth parameters,
horizontal scaling coefficient etc., to the VPC.
dB
20
15
10
5
0
-5
-10
2
4
6
8
10
Letterbox signals containing logos on the left or right
side of the black areas are processed as black lines,
while subtitles, inserted in the black areas, are processed as non-black lines. Therefore the subtitles are
visible on the screen. To suppress the subtitles, the
vertical zoom coefficient is calculated by selecting the
larger number of black lines only. Dark video scenes
with a low contrast level compared to the letterbox area
are indicated by the BLKPIC bit.
MHz
Fig. 2–13: Peaking characteristics
2.6. Vertical Scaler
For PIP operation, the vertical scaler compresses the
incoming 4:2:2 YCrCb active video signal in vertical
direction. It supports a vertical compression ratio of
1(= no compression), 2, 3, 4 and 6.
In case of a vertical compression of 2, 4 and 6, the filter performs the PAL compensation automatically and
the standard PAL delay line should be bypassed (see
2.3.8.).
2.7. Contrast and Brightness
The VPC32xxD provides a selectable contrast and
brightness adjustment for the luma samples. The control ranges are:
– 0 ≤contrast ≤63/32
– −128 ≤ brightness ≤ 127
Note: for ITU-R luma output code levels (16 ... 240),
contrast has to be set to 48 and brightness has to be
set to 16!
2.8. Blackline Detector
In case of a letterbox format input video, e.g. Cinemascope, PAL+ etc., black areas at the upper and lower
part of the picture are visible. It is suitable to remove or
reduce these areas by a vertical zoom and/or shift
operation.
The VPC 32xx supports this feature by a letterbox
detector. The circuitry detects black video lines by
measuring the signal amplitude during active video.
For every field the number of black lines at the upper
and lower part of the picture are measured, compared
to the previous measurement and the minima are
stored in the I2C-register BLKLIN. To adjust the picture
Micronas
2.9. Control and Data Output Signals
The VPC 32xx supports two output modes: In
DIGIT3000 mode, the output interfaces run at the main
system clock, in line-locked mode, the VPC generates
an asynchronous line-locked clock that is used for the
output interfaces. The VPC delivers either a YCrCb
4:2:2 or a YCrCb 4:1:1 data stream, each with separate
sync information. In case of YCrCb 4:2:2 format, the
VPC32xxD also provides an interface with embedded
syncs according to ITU-R656.
2.9.1. Line-Locked Clock Generation
An on-chip rate multiplier is used to synthesize any
desired output clock frequency of 13.5/16/18 MHz. A
double clock frequency output is available to support
100 Hz systems. The synthesizer is controlled by the
embedded RISC controller, which also controls all
front-end loops (clamp, AGC, PLL1, etc.). This allows
the generation of a line-locked output clock regardless
of the system clock (20.25 MHz) which is used for
comb filter operation and color decoding. The control
of scaling and output clock frequency is kept independent to allow aspect ratio conversion combined with
sample rate conversion. The line-locked clock circuity
generates control signals, e.g. horizontal/vertical sync,
active video output, it is also the interface from the
internal (20.25 MHz) clock to the external line-locked
clock system.
If a line-locked clock is not required, i.e. in the
DIGIT3000 mode, the system runs at the 20.25 MHz
main clock. The horizontal timing reference in this
mode is provided by the front-sync signal. In this case,
the line-locked clock block and all interfaces run from
the 20.25 MHz main clock. The synchronization signals from the line-locked clock block are still available,
but for every line the internal counters are reset with
the main-sync signal. A double clock signal is not available in DIGIT3000 mode.
17
VPC 323xD, VPC 324xD
ADVANCE INFORMATION
2.9.2. Sync Signals
2.9.5. Line-Locked 4:1:1 Output Format
The front end will provide a number of sync/control signals which are output with the output clock. The sync
signals are generated in the line-locked clock block.
The orthogonal 4:1:1 output format is compatible to the
industry standard. The YCrCb samples are skew-corrected and interpolated to an orthogonal sampling raster (see Table 2–5).
– Href:
horizontal sync
– AVO:
active video out (programmable)
– HC:
horizontal clamp (programmable)
– Vref:
vertical sync
– INTLC:
interlace
Table 2–5: 4:1:1 Orthogonal output format
Luma
Chroma
Y1
Y2
Y3
Y4
C3 , C7
Cb17
Cb15
Cb13
Cb11
All horizontal signals are not qualified with field information, i.e. the signals are present on all lines. The
horizontal timing is shown in Fig. 2–16. Details of the
horizontal/vertical timing are given in Fig. 2–20.
C2 , C6
Cb16
Cb14
Cb12
Cb10
C1 , C5
Cr17
Cr15
Cr13
Cr11
C0 , C4
Cr16
Cr14
Cr12
Cr10
Note: In the ITU-R656 compliant output format, the
sync information is embedded in the data stream.
note: C*xY
(x = pixel number and y = bit number)
2.9.6. ITU-R 656 Output Format
2.9.3. DIGIT3000 Output Format
The picture bus format between all DIGIT3000 ICs is
4:2:2 YCrCb with 20.25 MHz samples/s. Only active
video is transferred, synchronized by the system main
sync signal (MSY) which indicates the start of valid
data for each scan line and which initializes the color
multiplex. The video data is orthogonally sampled
YCrCb, the output format is given in Table 2–4. The
number of active samples per line is 1080 for all standards (525 and 625).
The output can be switched to 4:1:1 mode with the output format according to Table 2–5.
Via the MSY line, serial data is transferred which contains information about the main picture such as current line number, odd/even field etc.). It is generated by
the deflection circuitry and represents the orthogonal
timebase for the entire system.
Table 2–4: Orthogonal 4:2:2 output format
Luma
Y1
Y2
Y3
Y4
Chroma
Cb1
Cr1
Cb3
Cr3
2.9.4. Line-Locked 4:2:2 Output Format
This interface uses a YCrCb 4:2:2 data stream at a
line-locked clock of 13.5 MHz. Luminance and chrominance information is multiplexed to 27 MHz in the following order:
Cb1, Y1, Cr1, Y2, ...
Timing reference codes are inserted into the data
stream at the beginning and the end of each video line:
– a ‘Start of active video’-Header (SAV) is inserted
before the first active video sample
– a ‘End of active video’-code (EAV) is inserted after
the last active video sample.
The incoming videostream is limited to a range of
1...254 since the data words 0 and 255 are used for
identification of the reference headers. Both headers
contain information about the field type and field blanking. The data words occurring during the horizontal
blanking interval between EAV and SAV are filled with
0x10 for luminance and 0x80 for chrominance information. Table 2–6 shows the format of the SAV and EAV
header.
For activation of this output format, the following selections must be assured:
– 13.5 MHz line locked clock
– double-clock mode enabled
In line-locked mode, the VPC 32xx will produce the
industry standard pixel stream for YCrCb data. The difference to DIGIT3000 native mode is only the number
of active samples, which of course, depends on the
chosen scaling factor. Thus, Table 2–4 is valid for both
4:2:2 modes.
18
– ITU-R656-mode enabled
– binary offset for Cr/Cb data
Note that the following changes and extensions to the
ITU-R656 standard have been included to support horizontal and vertical scaling:
Micronas
VPC 323xD, VPC 324xD
ADVANCE INFORMATION
– Both the length and the number of active video lines
varies with the selected window parameters. For
compliance with the ITU-R656 recommendation, a
size of 720 samples per line must be selected for
each window.
Table 2–6: Coding of the SAV/EAV-header
Bit No.
Word
– During blanked video lines SAV/EAV headers are
suppressed in pairs. To assure vertical sync detection the V-flag in the EAV header of the last active
video line is set to 1. Additionally, during field blanking all SAV/EAV headers (with the V-flag set to 1)
are inserted.
MSB
LSB
7
6
5
4
3
2
1
0
First
1
1
1
1
1
1
1
1
Second
0
0
0
0
0
0
0
0
Third
0
0
0
0
0
0
0
0
Fourth
T
F
V
H
P3
P2
P1
P0
F = 0 during field 1,
F = 1 during field 2
V = 0 during active lines V = 1 during vertical field blanking
H = 0 in SAV,
H = 1 in EAV
T = 1 (video task only)
The bits P0, P1, P2, and P3 are Hamming-coded protection bits.
dependent on window size
CB Y CR Y ...
constant during
horizontal blanking
Y=10hex; CR=CB=80hex
SAV
EAV
EAV
SAV
1728 samples
Digital
Video
Output
CB Y CR Y ...
SAV: ”start of active video” header
EAV: ”end of active video” header
AVO
Fig. 2–14: Output of video data with embedded reference headers (@27 MHz)
Y DATA
80h
10h
SAV1
SAV2
SAV3
SAV4
CB1
Y1
CR1
Y2
CBn-1
Yn-1
CRn-1
Yn
EAV1
EAV2
EAV3
EAV4
80h
10h
AVO
LLC1
LLC2
Fig. 2–15: Detailed data output (double-clock on)
Micronas
19
VPC 323xD, VPC 324xD
ADVANCE INFORMATION
Table 2–7: Output signals corresponding to the different formats
Format
dblclk
enable656
HSync
VSync
AVO
Y-Data
C-Data
16 bit
YCrCb422
0
0
PAL/NTSC
PAL/NTSC
marks active
pixels
4:2:2
4:2:2
8 bit
YCrCb422
1
0
PAL/NTSC
PAL/NTSC
marks active
pixels
4:2:2
tristated
ITU-R 656
1
1
not used
not used
not used
ITU-R 656
tristated
The multiplex of luminance and chrominance information and the embedding of 656-headers can be
enabled independently. An overview of the resulting
output formats and the corresponding signals is given
in Table 2–7.
2.10. PAL+ Support
For PAL+, the VPC 323xD provides basic helper preprocessing:
– A/D conversion (shared with the existing ADCs)
– mixing with subcarrier frequency
2.9.7. Output Code Levels
Output Code Levels correspond to ITU-R code levels:
Y = 16...240
Black Level = 16
CrCb = 128±112
An overview over the output code levels is given in
Table 2–8.
2.9.8. Output Ports
All data and sync pins operate at TTL compliant levels
and can be tristated via I2C registers.
Additionally, the data outputs can be tristated via the
YCOE output enable pin immediately. This function
allows the digital insertion of a 2nd digital video source
(e. g. MPEG aso.).
To minimize crosstalk data and clock pins automatically adopt the output driver strength depending on
their specific external load (max. 50pF). Sync and Fifo
control pins have to be adjusted manually via an I2C
register.
2.9.9. Test Pattern Generator
The YCrCb outputs can be switched to a test mode
where YCrCb data are generated digitally in the
VPC32xx. Test patterns include luma/chroma ramps,
flat field and a pseudo color bar.
20
– lowpass filter 2.5 MHz
– gain control by chroma ACC
– delay compensation to composite video path
– output at the luma output port
Helper signals are processed like the main video luma
signals, i.e. they are subject to scaling, sample rate
conversion and orthogonalization if activated. The
adaptive comb filter processing is switched off for the
helper lines.
It is expected that further helper processing (e.g. nonlinear expansion, matched filter) is performed outside
the VPC.
2.10.1. Output Signals for PAL+/Color+ Support
For a PAL+/Color+ signal, the 625 line PAL image contains a 16/9 core picture of 431 lines which is in standard PAL format. The upper and lower 72 lines contain
the PAL+ helper signal, and line 23 contains signalling
information for the PAL+ transmission.
For PAL+ mode, the Y signal of the core picture, which
is during lines 60–274 and 372–586, is replaced by the
orthogonal composite video input signal. In order to fit
the signal to the 8-bit port width, the ADC signal amplitudes are used. During the helper window, which is in
lines 24–59, 275–310, 336–371, 587–622, the demodulated helper is signal processed by the horizontal scaler
and the output circuitry. It is available at the luma output
port. The processing in the helper reference lines 23
and 623 is different for the wide screen signaling part
and the black reference and helper burst signals. The
code levels are given in detail in Table 2–8, the output
signal for the helper reference line is shown in Fig. 2–17.
Micronas
VPC 323xD, VPC 324xD
ADVANCE INFORMATION
Table 2–8: Output signal code levels for a PAL/PAL+ signal
Output Signal
Luma Outputs Y[7:0]
Output Format
Standard YCrCb
(100% Chroma)
binary
CVBS, CrCb
Black/Zero
Level
16
binary
Chroma Outputs C[7:0]
Amplitude
224
64
149 (luma)
Output Format
Amplitude
offset binary
128±112
signed
±112
offset binary
128±112
signed
±112
Demodulated
Helper
signed
0
±109
–
–
Helper WSS
binary
68
149 (WSS:106)
–
–
Helper black level,
Ref. Burst
offset binary
128
19 (128–109)
–
–
horizontal pixel counter
0
line length (programmable)
horizontal sync (HS)
1
31
horizontal clamp (HC)
start / stop programmable
newline (internal signal)
start of video output (programmable)
active video out (AVO)
start / stop programmable
vertical sync (VS), field 1
field 1
16
vertical sync (VS), field 2
field 2
line length/2
Fig. 2–16: Horizontal timing for line-locked mode
255
255
black level
WSS SIgnal
174
Helper Burst
(demodulated)
128
68
19
0
binary format
signed format
Fig. 2–17: PAL+ helper reference line output signal
Micronas
21
VPC 323xD, VPC 324xD
ADVANCE INFORMATION
2.11. Video Sync Processing
For vertical sync separation, the sliced video signal is
integrated. The FP uses the integrator value to derive
vertical sync and field information.
Fig. 2–18 shows a block diagram of the front-end sync
processing. To extract the sync information from the
video signal, a linear phase lowpass filter eliminates all
noise and video contents above 1 MHz. The sync is
separated by a slicer; the sync phase is measured. A
variable window can be selected to improve the noise
immunity of the slicer. The phase comparator measures the falling edge of sync, as well as the integrated
sync pulse.
The information extracted by the video sync processing is multiplexed onto the hardware front sync signal
(FSY) and is distributed to the rest of the video processing system. The format of the front sync signal is
given in Fig. 2–19.
The data for the vertical deflection, the sawtooth, and
the East-West correction signal is calculated by the
VPC 32xx. The data is buffered in a FIFO and transferred to the back-end IC DDP 3300A by a single wire
interface.
The sync phase error is filtered by a phase-locked loop
that is computed by the FP. All timing in the front-end is
derived from a counter that is part of this PLL, and it
thus counts synchronously to the video signal.
Frequency and phase characteristics of the analog
video signal are derived from PLL1. The results are fed
to the scaler unit for data interpolation and orthogonalization and to the clock synthesizer for line-locked
clock generation. Horizontal and vertical syncs are
latched with the line-locked clock.
A separate hardware block measures the signal back
porch and also allows gathering the maximum/minimum of the video signal. This information is processed
by the FP and used for gain control and clamping.
PLL1
lowpass
1 MHz
&
syncslicer
horizontal
sync
separation
phase
comparator
&
lowpass
counter
front
sync
generator
frontend
timing
clock
synthesizer
syncs
front sync
skew
vblank
field
video
input
clock
H/V syncs
clamp &
signal
meas.
clamping, colorkey, FIFO_write
vertical
sync
separation
Sawtooth
Parabola
Calculation
FIFO
vertical
E/W
sawtooth
vertical
serial
data
Fig. 2–18: Sync separation block diagram
F1
input
analog
video
FSY
skew
LSB
F0 reserved
(not in scale)
F0
skew not
MSB used
F
V
V: vertical sync
0 = off
Parity
1 = on
F: field #
0 = field 1
1 = field 2
F1
Fig. 2–19: Front sync format
22
Micronas
VPC 323xD, VPC 324xD
ADVANCE INFORMATION
field 1
CCIR
623
624
625
1
2
3
4
5
6
7
8
23
24
335
336
Front-Sync (FSY)
Vertical Sync (VS)
Interlace (INTLC)
> 1clk
field 2
CCIR
310
311
312
313
314
315
316
317
318
319
320
Vertical Sync (VS)
Interlace (INTLC)
>1 clk
Active Video Output (AVO)
helper ref line 23, 623 (internal signal) signal matches output video
The following signals are identical for field1 / field2
helper lines 23–59, 275–310, 336–371, 587–623 (internal signal), signal matches output video
Fig. 2–20: Vertical timing of VPC 32xxD shown in reference to input video.
Video output signals are delayed by 3-h for comb filter version (VPC 32xxD).
Micronas
23
VPC 323xD, VPC 324xD
ADVANCE INFORMATION
live. These configurations are suitable for features
such as turner scan, still picture, still in picture and
simple scan rate conversion.
2.12. Picture in Picture (PIP) Processing and
Control
2.12.1. Configurations
Fig. 2–22 shows an enhanced configuration with two
VPC 32xxD’s. In this case, one live and several still
pictures are inserted into the main live video signal.
The VPCpip processes the inset picture and writes the
original or decimated picture into the field memory.
The VPCmain delivers the main picture, combines it
with the inset picture(s) from the field memory and
stores the combined video signal into a second field
memory for the SRC.
To support PIP and/or scan rate conversion (SRC)
applications, the VPC32xxD provides several control
signals for an external field memory IC.
Fig. 2–21 demonstrates two applications with a single
VPC 32xxD. In these cases the VPCsingle writes the
main picture or one of several inset picture(s) into the
field memory. Only one of these pictures is displayed
YCrCb/RGB
CVBS
YCrCb
VPC
32XXD
(single)
YCrCb/RGB
LLC1,
RSTWR,
WE, IE
VPC
32XXD
CVBS
YCrCb
field
memory
(single)
RGB
DDP
3310B
H/V
Def.
LLC2,
FIFORRD,
FIFORD
YCrCb
YCrCb
field
memory
LLC1,
RSTWR,
WE, IE
LLC1,
RSTWR,
RE
Fig. 2–21: Typical configurations with single VPC 32xxD
YCrCb/RGB
CVBS
VPC
32XXD
(pip)
(for PIP)
YCrCb/RGB
CVBS
VPC
32XXD
YCrCb
LLC1,
RSTWR,
WE, IE
field
memory
YCrCb
(for PIP)
LLC1,
RSTWR,
RE, OE
YCrCb
(main)
(for main picture)
field
memory
LLC1,
RSTWR,
WE, IE
(for SRC)
YCrCb
LLC2,
FIFORRD,
FIFORD
DDP
3310B
RGB
H/V
Def.
Fig. 2–22: Enhanced configuration with two VPC 32xxD
24
Micronas
VPC 323xD, VPC 324xD
ADVANCE INFORMATION
In addition an expert mode is available for advanced
PIP applications. In this case the inset picture size, as
well as the PIP window arrangements are fully programmable.
A summary of VPC modes is given in Table 2–9.
Table 2–9: VPC 32xxD modes for PIP applications
Working
mode
pip
Function
Examples for the PIP mode programming are given in
5.2.
- decimate the video signal for the
inset pictures
- write the inset pictures into the field
memory
- write the frame and background
into the field memory
main
2.12.3. Predefined Inset Picture Size
The predefined PIP display modes are based on four
fixed inset picture sizes (see Table 2–10). The corresponding picture resizing is achieved by the integrated
horizontal and vertical scaler of VPC 32xxD, which
must be programmed accordingly (see Table 2–11).
- deliver the video signal for the
main picture
- read the inset pictures from the
field memory and insert them into
the main picture
- write the resulting video signal
into the field memory for the scan
rate conversion (SRC)
single
The inset pictures are displayed with or without a
frame controlled by I2C. The fixed frame width is 4 pixels and 4 lines..
Table 2–10: Inset picture size (without frame) in the
predefined PIP modes
- decimate the video signal for the
main or the inset picture(s)
- write the inset pictures into the field
memory
- write the frame and background
into the field memory
- write the main picture part outside
the inset pictures into the field
memory
- read the field memory (optional)
size
horizontal
[pixel/line]
vertical
[line/field]
4:3 screen
16:9 screen
625
line
525
line
13.5
MHz
16
MHz
13.5
MHz
16
MHz
1/2
332
392
248
292
132
110
1/3
220
260
164
196
88
74
2.12.2. PIP Display Modes
1/4
164
196
124
148
66
55
To minimize the programming effort, 15 predefined PIP
modes are already implemented, including double windows, single and multi-PIP (Fig. 2–23 and 2–24).
1/6
112
132
84
96
44
37
Table 2–11: Scaler Settings for predefined PIP modes at 13.5 MHz
PIP size
scinc1
FP h’43
fflim
FP h’42
sc-pip
FP h’41
sc_bri2)
FP h’52
newlin1)
I2C h’22
avstrt1)
I2C h’28
avstop
I2C h’29
full
h’600
h’2d0
h’00
h’010
h’86
h’86
h’356
1/2
h’600
h’168
h’11
h’110
h’194
h’86
h’356
1/3
h’480
h’f0
h’16
h’210
h’194
h’86
h’356
1/4
h’600
h’b4
h’1a
h’210
h’194
h’86
h’356
1/6
h’480
h’78
h’1f
h’310
h’194
h’86
h’356
dou. win
h’acd
h’190
h’00
h’010
h’86
h’86
h’356
Notes:
Micronas
1) must be > 47, if FIFOTYPE=0 or 1
2) BR=16 in register sc_bri
3) MSB of SC_MODE updates all scaler register
25
VPC 323xD, VPC 324xD
ADVANCE INFORMATION
P1
Mode 0
P2
Mode 1
P1
P2
P3
P4
PIP
Mode 2, 3, 4, 5
Mode 6
P1
P2
P3
P4
P1
P2
P3
Mode 7
Mode 9
Mode 8
P1
P2
P1
P2
P3
P3
P4
P4
P5
P6
P4
P6
P7
P8
P9
Mode 10 (4:3)
Fig. 2–23: Predefined PIP Modes
26
Micronas
VPC 323xD, VPC 324xD
ADVANCE INFORMATION
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
Mode 10 (16:9)
P1
P2
P3
Mode 11 (4:3)
P1
P2
P3
P9
P10
P8
P4
P4
Mode 12
Mode 11 (16:9)
P1
P1
P2
P2
Mode 13
P3
Mode 14
Fig. 2–24: Predefined PIP Modes (continued)
Micronas
27
VPC 323xD, VPC 324xD
ADVANCE INFORMATION
2.12.4. Acquisition and Display Window
2.12.5. Frame and Background Color
The acquisition window defines the picture area of the
input active video to be displayed as a inset picture on
the screen.
Two programmable frame colors COLFR1 and
COLFR2 are available to high-light a particular inset
picture.
The display window defines the display position of the
inset picture(s) on the screen.
Instead of displaying the main picture it is possible to
fill the background with a programmable color COLBGD (set SHOWBGD=1 in the register PIPMODE),
e. g. for multi PIP displays on the full screen (see mode
6 and 10).
The acquisition and display windows are controlled by
I2C parameters HSTR, VSTR, NPIX and NLIN (see
Fig. 2–25 and 2–26). They indicate the coordinate of
the upper-left corner and the horizontal and vertical
size of the active video area. In VPCpip or VPCsingle
mode, these four parameters define the acquisition
window in the decimated pixel grid, while in VPCmain
mode they define the display window.
COLFR1, COLFR2 and COLBGD are 16 bits wide
each. Therefore 65536 colors are programmable.
2.12.6. Vertical Shift of the Main Picture
The VPCmain mode supports vertical up-shifting of the
main picture (e. g. letterbox format) to enable bottom
insets (see mode 11). The vertical shift is programmable by VOFFSET.
HSTR
VSTR
NLIN
2.12.7. Free Running Display Mode
Acquisition
Window
In this mode a free running sync raster is generated to
guarantee a stable display in critical cases like tuner
scan. Therefore the LLC should be disabled (see
Table 2–12).
NPIX
2.12.8. Frame and Field Display Mode
Active Video
Fig. 2–25: Definition of the acquisition window
HSTR
In frame display mode, every field is written into the
field memory. In the field display mode every second
field is written into the field memory. This configuration
is suitable for multi picture insets and freeze mode,
since it avoids motion artifacts. On the other hand, the
frame display mode guarantees maximum vertical and
temporal resolution for animated insets.
In the predefined mode the setting of frame/field mode
is done automatically to achieve the best performance.
NLIN
VSTR
Display
Window
NPIX
Active Video
Fig. 2–26: Definition of the display window
28
Micronas
VPC 323xD, VPC 324xD
ADVANCE INFORMATION
Table 2–12: Settings for Free-Running Mode
Control bit
Function
VPCsingle
VPCpip
write
PIP
write main
pic.
VPCmain
predef.
all other
mode 6, 10 modes
bit[11] of LLC_CLKC
(FP h’6a)
enable/disable
LLC PLL
1
0
0
1
0
bit[15] of AVO START
(I2C h’28)
enable/disable freerunning sync mode
1
0
0
1
0
2.12.9. External Field Memory
The requirements of the external field memory are:
– FIFO type access with reset
As serial write and serial read clock (SWCK and
SRCK, respectively) of the field memory the line
locked clocks LLC1 and/or LLC2 are used.
– write mask function: The increasing of the write
address pointer and the over writing of the data
should be controlled separately.
– output disable function: tri-statetable outputs
For PIP applications, VPC 32xxD supports 4:1:1 or
4:2:2 chrominance format. Table 2–13 shows the typical memory size for a 13.5 and 16 MHz system clock
application.
Table 2–13: Word length and minimum size of the field
memory
Chrominance
format
Word
length
[bit]
Memory size
[word]
[bit]
4:1:1
12
245376
2944512
4:2:2
16
245376
3926016
The following 5 signals are generated by VPC 32xxD
to control the external field memory:
RSTWR (reset write/read) resets the internal write/
read address pointer to zero.
WE (write enable) is used to enable or disable incrementing of the internal write address pointer.
IE (input enable) is used to enable writing data from
the field memory input pins into the memory core, or to
disable writing and thereby preserving the previous
content of the memory (write mask function).
RE (read enable) is used to enable or disable incrementing the internal read address pointer.
OE (output enable) is used to enable or disable data
output to the output pins.
Micronas
29
VPC 323xD, VPC 324xD
ADVANCE INFORMATION
The registers of the VPC have 8 or 16-bit data size;
16-bit registers are accessed by reading/writing two
8-bit data words.
3. Serial Interface
3.1. I2C-Bus Interface
Communication between the VPC and the external
controller is done via I2C-bus. The VPC has an I2C-bus
slave interface and uses I2C clock synchronization to
slow down the interface if required. The I2C-bus interface uses one level of subaddress: one I2C-bus
address is used to address the IC and a subaddress
selects one of the internal registers. For multi
VPC32xxD applications the following three I2C-bus
chip addresses are selectable via I2CSEL pin:
A6
A5
A4
A3
A2
A1
A0 R/W I2CSEL
1
0
0
0
1
1
1
1/0
VSUP
1
0
0
0
1
1
0
1/0
VRT
1
0
0
0
1
0
0
1/0
GND
Figure 3–1 shows I2C-bus protocols for read and write
operations of the interface; the read operation requires
an extra start condition and repetition of the chip
address with read command set.
3.2. Control and Status Registers
Table 3–1 gives definitions of the VPC control and status registers. The number of bits indicated for each
register in the table is the number of bits implemented
in hardware, i.e. a 9-bit register must always be
accessed using two data bytes but the 7 MSB will be
‘don’t care’ on write operations and ‘0’ on read operations. Write registers that can be read back are indicated in Table 3–1.
Functions implemented by software in the on-chip control microprocessor (FP) are explained in Table 3–1.
S
1000 111
W Ack
FPWR
Ack
send FP-addressbyte high
Ack
send FP-addressbyte low
Ack P
S
1000 111
W Ack
FPDAT
Ack
send databyte high
Ack
send databyte low
Ack P
S
1000 111
W Ack
FPRD
Ack
send FP-addressbyte high
Ack
send FP-addressbyte low
Ack P
S
1000 111
W Ack
FPDAT
Ack S
1000 111
S
1000 111
W Ack
0111 1100
Ack 1 or 2 byte Data
S
1000 111
W Ack
0111 1100
Ack S
1000 111
R Ack
receive databyte high
receive databyte low
S
Ack
Nak P
I2C write access
subaddress 7c
I2C read access
subaddress 7c
R Ack high byte Data Ack
1
0
SCL
I2C read access
to FP
P
low byte Data
SDA
I2C write access
to FP
P
W
R
Ack
Nak
S
P
Nak P
=
=
=
=
=
=
0
1
0
1
Start
Stop
Fig. 3–1: I2C-bus protocols
30
Micronas
ADVANCE INFORMATION
VPC 323xD, VPC 324xD
A hardware reset initializes all control registers to 0.
The automatic chip initialization loads a selected set of
registers with the default values given in Table 3–1.
The register modes given in Table 3–1 are
– w:
write only register
– w/r:
write/read data register
– r:
read data from VPC
– v:
register is latched with vertical sync
The mnemonics used in the Intermetall VPC demo
software are given in the last column.
Micronas
31
VPC 323xD, VPC 324xD
ADVANCE INFORMATION
Table 3–1: Control and status registers
I2C Subaddress
Number
of bits
Mode
Function
Default
Name
FP Interface
h’35
8
r
FP status
bit [0]
bit [1]
bit [2]
write request
read request
busy
–
FPSTA
h’36
16
w
bit[8:0]
bit[11:9]
9-bit FP read address
reserved, set to zero
–
FPRD
h’37
16
w
bit[8:0]
bit[11:9]
9-bit FP write address
reserved, set to zero
–
FPWR
h’38
16
w/r
bit[11:0]
FP data register, reading/writing to this
register will autoincrement the FP read/
write address. Only 16 bit of data are
transferred per I2C telegram.
–
FPDAT
–
BLKLIN
Black Line Detector
h’12
16
w/r
read only register, do not write to this register! After reading,
LOWLIN and UPLIN are reset to 127 to start a new measurement.
bit[6:0]
number of lower black lines
bit[7]
always 0
bit[14:8]
number of upper black lines
bit[15]
0/1
normal/black picture
LOWLIN
UPLIN
BLKPIC
Pin Circuits
h’1F
h’20
32
16
8
w/r
w/r
SYNC PIN CONTROL:
bit[2:0] 0..7
reserved (set to 0)
bit[3]
0/1
pushpull/tristate for AVO Pin
bit[4]
0/1
pushpull/tristate for other video SYNC Pins
bit[5]
0
reserved (set to zero)
CLOCK/FIFO PIN CONTROL:
bit[6]
0/1
pushpull/tristate for LLC1
bit[7]
0/1
pushpull/tristate for LLC2
bit[8]
0
reserved (set ot 0)
bit[9]
0/1
pushpull/tristate for FIFO control pins
LUMA/CHROMA DATA PIN (LB[7:0], CB[7:0]) CONTROL:
bit[10]
0/1
tristate/pushpull for Chroma Data pins
bit[11]
0/1
tristate/pushpull for Luma Data pins
bit[15:12]
reserved (set to 0)
SYNC GENERATOR CONTROL:
bit[1:0] 00
AVO and active Y/C data at same time
01
AVO precedes Y/C data one clock cycle
10
AVO precedes Y/C data two clock cycles
11
AVO precedes Y/C data three clock cycles
bit[2]
0/1
positive/negative polarity for HS signal
bit[3]
0/1
positive/negative polarity for HC signal
bit[4]
0/1
positive/negative polarity for AVO signal
bit[5]
0/1
positive/negative polarity for VS signal
bit[6]
0/1
positive/negative polarity for HELP signal
bit[7]
0/1
positive/negative polarity for INTLC signal
TRPAD
0
0
0
0
0
0
0
0
AVODIS
SNCDIS
LLC1DIS
LLC2DIS
FFSNCDIS
0
0
0
0
CDIS
YDIS
SYNCMODE
0
AVOPRE
0
0
0
0
0
0
HSINV
HCINV
AVOINV
VSINV
HELPINV
INTLCINV
Micronas
VPC 323xD, VPC 324xD
ADVANCE INFORMATION
I2C Subaddress
Number
of bits
Mode
Function
h’23
16
w/r
OUTPUT STRENGTH:
bit[3:0] 0..15
output pin strength
(0 = strong, 15 = weak)
bit[9:4]
address of output pin
32
FIFO control pins FFIE, FFOE, FFWR,
FFRE and FFRSTWR
33
SYNC pins AVO, HS, HC, INTERLACE, VS
bit[10]
0/1
read/write output strength
bit[15:11]
reserved (set to 0)
h’30
8
w/r
Default
V-SYNC DELAY CONTROL:
bit[7:0]
VS delay (8 LLC clock cycles per LSB)
Name
0
OUTSTR
PADSTR
0
PADADD
0
0
PADWR
0
VSDEL
VSDEL
656 Interface
h’24
8
w/r
656 OUTPUT INTERFACE
bit [0]
1
disable hor. & vert. blanking of invalid
data in 656 mode
bit [1]
0
use vertical window as VFLAG
1
use vsync as VFLAG
bit [2]
enable suppression of 656-headers
during invalid video lines
bit [3]
enable ITU-656 output format
bit [4]
0/1
LLC1/LLC2 used as reference clock
bit [5]
0/1
output mode: DIGIT 3000 / LLC
OUT656
0 DBLNK
0 VSMODE
0 HSUP
0 656enable
0 DBLCLK
1 OMODE
Sync Generator
h’21
16
w/r
LINE LENGTH:
bit[10:0]
bit[15:11]
h’26
16
w/r
HC START:
bit[10:0]
bit[15:11]
h’27
16
w/r
bit[10:0]
bit[15:11]
Micronas
LINE LENGTH register
In LLC mode, this register defines the
cycle of the sync counter which generates
the SYNC pulses.
In LLC mode, the synccounter counts from
0 to LINE LENGTH, so this register has to
be set to “number of pixels per line –1”.
In DIGIT3000 mode, LINE LENGTH has to
be set to 1295 for correct adjustment of
vertical signals.
reserved (set to 0)
HC START defines the beginning of the
HC signal in respect to the value of the
sync counter.
reserved (set to 0)
HC STOP defines the end of the HC signal
in respect to the value of the sync counter.
reserved (set to 0)
1295
LINLEN
50
HCSTRT
800
HCSTOP
33
VPC 323xD, VPC 324xD
I2C Subaddress
Number
of bits
Mode
Function
h’28
16
w/r
AVO START:
bit[10:0]
h’29
16
w/r
Default
bit[11]
bit[12]
0/1
bit[13]
0/1
bit[14]
bit[15]
0/1
0/1
AVO STOP:
bit[10:0]
bit[15:11]
bit[11]
0/1
bit[13:12]
00
01
10
11
bit[14]
0/1
bit[15]
0/1
h’22
16
w/r
NEWLINE:
bit[10:0]
bit[15:11]
34
ADVANCE INFORMATION
AVO START defines the beginning of the
AVO signal in respect to the value of the
sync counter.
reserved (set to 0)
dis/enable suppression of AVO during VBI
and invalid video lines
vertical standard for flywheel
(312/262 lines) used if FLW is set
disable interlace for flywheel
enable vertical free run mode (flywheel)
AVO STOP defines the end of the AVO
signal in respect to the value of the
sync counter.
reserved for test picture generation
(set to 0 in normal operation)
disable/enable test pattern generator
luma output mode:
Y = ramp (240 ... 17)
Y = 16
Y = 90
Y = 240
chroma output: 422/411 mode
chroma output: pseudo color bar/zero
if LMODE = 0
NEWLINE defines the readout start of the
next line in respect to the value of the sync
counter. The value of this register must be
greater than 31 for correct operation and
should be identical to AVOSTART (recommended). In case of 1H-bypass mode for
scaler block, NEWLINE has no function.
reserved (set to 0)
60
Name
AVSTRT
0
AVOGATE
0
FLWSTD
0
DIS_INTL
FLW
0
AVSTOP
0
0
COLBAREN
0
0
M411
CMODE
50
NEWLIN
LMODE
Micronas
VPC 323xD, VPC 324xD
ADVANCE INFORMATION
I2C Subaddress
Number
of bits
Mode
Function
Default
Name
0
VPCMODE
PIP Control
h’84
16
w/r
VPC MODE:
bit[0]
0/1
bit[1]
0/1
bit[2]
0/1
bit[3]
0/1
bit[4]
0/1
bit[5]
0/1
ENA_PIP
SINGVPC
MAINVPC
F16TO9
F16MHZ
W525
dis-/enable field memory control for PIP
double/single VPC application
select VPCpip/VPCmain mode
4:3/16:9 screen
13.5/16 MHz output pixel rate
vertical PIP window size is based on
a 625/525 line video
bit[7:6]
field memory type
00
TI TMS4C2972/3
01
PHILIPS SAA 4955TJ
10
reserved
11
other (OKI MSM5412222, ...)
bit[11:8] are evaluated, only if bit[7:6]=11
bit[8]
0/1
delay the video output for 0/1 LLC1 clock
bit[9]
0/1
pos/neg polarity for WE and RE signals
bit[10]
0/1
pos/neg polarity for IE and OE signals
bit[11]
0/1
pos/neg polarity for RSTWR signal
bit[15:12]
reserved (set to 0)
FIFOTYPE
VIDEODEL
WEREINV
IEOEINV
RSTWRINV
This register is updated when the PIPOPER register is written.
h’85
16
w/r
PIP MODE:
bit[3:0]
bit[4]
0/1
the number of the PIP mode to be selected
write one/both input field(s) of a frame into
the field buffer in case TWOFB=0,
only used in the expert mode, for VPCpip
or VPCsingle
bit[5]
0/1
use one/two field buffer(s), only used
in the expert mode
bit[13:6] are used, only for VPCmain
bit[6]
0/1
show video/the background color in the
main picture, only used in the expert mode
bit[7]
0/1
dis-/enable the vertical up-shifting
of the main picture
bit[13:8] 0/1
number of lines for vertical up-shift
bif[15:14]
reserved (set to 0)
0
PIPMODE
MODSEL
FRAMOD
TWOFB
SHOWBGD
VSHIFT
VOFFSET
This register is updated when the PIPOPER register is written.
Micronas
35
VPC 323xD, VPC 324xD
ADVANCE INFORMATION
I2C Subaddress
Number
of bits
Mode
Function
Default
Name
h’83
8
w/r
PIP OPERATION:
For VPCpip or VPCsingle:
bit[1:0]
the number of the inset picture to be
accessed in the x-direction
bit[3:2]
the number of the inset picture to be
accessed in the y-direction
bit[6:4] 000
start to write the inset picture with a frame
001
stop writing
010
fill the frame with the color COLFR1
011
fill the frame with the color COLFR2
100
fill the inset picture with a frame using
the color COLBGD
101
fill the inset picture w/o a frame using
the color COLBGD
110
start to write the inset picture w/o a frame
111
write the main picture
(only for VPCsingle)
0
PIPOPER
For VPCmain:
bit[3:0]
bit[6:4] 000
001
rest
bit[7]
h’80
16
w/r
0/1
NSPX
NSPY
WRPIC
WRSTOP
WRFRCOL1
WRFRCOL2
WRBGD
WRBGDNF
WRPICNF
WRMAIN
reserved set to 0
start to display PIP
stop to display PIP
reserved set to 0
DISSTARD
DISSTOP
NEWCMD
processed/new command flag, normally
write 1. After the new PIP setting takes
effect, this bit is set to 0 to indicate
operation complete.
BACKGROUND COLOR:
bit[[4:0]
bit b7 to b3 of the chrominanc
component CR
bit[9:5]
bit b7 to b3 of the chrominanc
component CB
bit[15:10]
bit b7 to b2 of the luminance component Y
(all other bits of YCBCR are set to 0)
0
COLBGD
h’3e0
COLFR1
h’501f
COLFR2
This register is updated when the PIPOPER register is written.
h’81
16
w/r
FRAME COLOR 1:
Only used for PCpip or VPCsingle:
bit[[4:0]
bit b7 to b3 of the chrominanc
component CR
bit[9:5]
bit b7 to b3 of the chrominanc
component CB
bit[15:10]
bit b7 to b2 of the luminance component Y
(all other bits of YCBCR are set to 0)
This register is updated when the PIPOPER register is written.
h’82
16
w/r
FRAME COLOR 2:
only used for VPCpip or VPCsingle:
bit[[4:0]
bit b7 to b3 of the chrominanc
component CR
bit[9:5]
bit b7 to b3 of the chrominanc
component CB
bit[15:10]
bit b7 to b2 of the luminance component Y
(all other bits of YCBCR are set to 0)
This register is updated when the PIPOPER register is written.
36
Micronas
VPC 323xD, VPC 324xD
ADVANCE INFORMATION
I2C Subaddress
Number
of bits
Mode
Function
Default
Name
h’86
16
w/r
LINE OFFSET:
Only used for VPCpip or for the expert mode of VPCsingle:
bit[8:0]
line offset of the upper-left corner of the
inset picture with NSPX=0 and NSPY=0
in the display window
bit[9]
0/1
use the internal default/external setting
via bit[8:0]
bit[15:10]
reserved (set to 0)
0
LINOFFS
0
PIXOFFS
This register is updated when the PIPOPER register is written.
h’89
16
w/r
PIXEL OFFSET:
Only used for VPCpip or for the expert mode of VPCsingle:
bit[7:0]
quarter of the pixel offset of the upper-left
corner of the inset picture with NSPX=0
and NSPY=0 in the display window
bit[8]
0/1
use the internal default/external setting
via bit[7:0]
bit[15:9]
reserved (set to 0)
This register is updated when the PIPOPER register is written.
h’87
16
w/r
VERTICAL START:
For VPCpip and VPCsingle:
bit[8:0]
vertical start of the active video segment
to be used as a inset picture
For the VPCmain:
vertical start of the inset picture(s)
in the main picture
bit[9]
0/1
use the internal default/external setting
via bit[8:0]
bit[15:10]
reserved (set to 0)
0
VSTR
h’8a
16
w/r
0
HORIZONTAL START:
For VPCpip and VPCsingle:
bit[7:0]
horizontal start of the active video segment
to be used as a inset picture
For VPCmain:
horizontal start of the inset picture(s)
in the main picture
In both cases HSTR is given by the
number of 4-pixel-groups.
bit[8]
0/1
use the internal default/external setting
via bit[7:0]
bit[15:9]
reserved (set to 0)
HSTR
h’88
16
w/r
NUMBER OF LINES:
Only used in the expert modes:
bit[8:0]
For VPCpip and VPCsingle:
number of lines of the active video
segment to be used as a inset picture
For VPCmain:
number of lines of the inset picture(s)
bit[15:9]
0
NLIN
reserved (set to 0)
This register is updated when the PIPOPER register is written.
Micronas
37
VPC 323xD, VPC 324xD
ADVANCE INFORMATION
I2C Subaddress
Number
of bits
Mode
Function
Default
Name
h’8b
8
w/r
NUMBER OF PIXEL PER LINE:
Only used in the expert modes:
bit[7:0]
For VPCpip and VPCsingle:
quarter of the number of pixels per line
in the active video segment to be used
as a inset picture
For VPCmain:
quarter of the number of pixels per line
of the inset picture(s)
0
NPIX
0
NPFB
This register is updated when the PIPOPER register is written.
h’8c
16
w/r
NUMBER OF PIXEL PER LINE IN THE FIELD BUFFER(S):
bit[7:0]
bit[8]
bit[15:9]
0/1
quarter of the number of allocated pixels
per line in the field buffer(s)
use the internal default/external setting
via bit[7:0]
(must be set in the expert mode, optional
in the predefined modes)
reserved (set to 0)
This register is updated when the PIPOPER register is written.
h’8dh’8f
reserved, don’t write
CIP Control
h’90
h’91
h’92
h’94
h’95
38
16
8
16
8
8
w/r
w/r
w/r
w/r
w/r
SATURATION OF THE RGB/YCrCb COMPONENT INPUT:
bit[5:0]
saturation Cb( 0..63 )
bit[11:6]
saturation Cr( 0..63 )
bit[15:12]
reserved (set to 0)
18
23
CIPSAT
SATCb
SATCr
TINT CONTROL OF THE RGB/YUV COMPONENT INPUT:
bit[5:0]
tint ( −20..+20 in degrees )
bit[7:6]
reserved (set to 0)
0
CIPTNT
BRIGHTNESS OF THE RGB/YUV COMPONENT INPUT:
bit[7:0]
brightness ( −128..+127 )
CONTRAST OF THE RGB/YUV COMPONENT INPUT:
bit[13:8]
contrast ( 0..63 )
bit[15:14]
reserved (set to 0)
SOFTMIXER CONTROL:
bit[0]
0/1
rgb/main video delay (0:normal 1:dynamic)
bit[1]
0/1
linear (0)/nonlinear(1) mixer select
bit[7:4]
fastblank gain (−7 .. +7)
bit[3:2]
reserved (set to 0)
SOFTMIXER CONTROL:
bit[5:0]
fastblank offset correction (0..63 )
( fb −> fb−FBOFFS )
bit[7:6]
fastblank mode:
x0
force rgb to cip out (equ. fb=0)
01
normal mode (fb active)
11
force main yuv to cip out (equ. fb=64)
68
CIPBRCT
CIPBR
28
CIPCT
0
0
−1
CIPMIX1
RGBDLY
SELLIN
FBGAIN
32
CIPMIX2
FBOFFS
11
FBMODE
Micronas
VPC 323xD, VPC 324xD
ADVANCE INFORMATION
I2C Subaddress
Number
of bits
Mode
Function
h’96
8
w/r
ADC RANGE :
bit[0]
reserved (set to 0)
bit[1]
0/1
0/+3dB extended ADC range
INPUT PORT SELECT :
bit[2]
0/1
1/2 input port select
SOFTMIXER CONTROL:
bit[5]
0/1
clamp fb to a programable value (0:normal
1: fb=31−FBOFFS )
bit[6]
0/1
bypass chroma 444−>422 decimation filter
RGB/YUV SELECT:
bit[7]
0/1
rgb/yuv input select
bit[4:3]
reserved (set to 0)
h’97
8
r
FB MONITOR:
bit[0]
0/1
bit[1]
0/1
bit[2]
0/1
bit[3]
0/1
Default
set by fb high, reset by reg. read and fb low
set by fb falling edge, reset by reg. read
set by fb rising edge, reset by reg. read
fb status at register read
CLIP DETECTOR:
bit[4]
0/1
rgb/yuv input clip detect, reset by read
Name
CIPCNTL
0
XAR
0
RGBSEL
0
FBCLP
1
CIPCFBY
0
YUV
−
−
−
−
CIPMON
FBHIGH
FBFALL
FBRISE
FBSTAT
−
CLIPD
Hardware ID
h’9f
Micronas
16
r
Hardware version number
bit[7:0] 0/255
hardware id 1=A, 2=B aso.
bit[11:8] 0/3
product code
0
VPC32x0D
1
VPC32x1D
2
VPC32x2D
3
VPC32x3D
bit[15:12] 0/15
product code
3
VPC323xD 100Hz version
4
VPC324xD 50Hz version
read
only
39
VPC 323xD, VPC 324xD
ADVANCE INFORMATION
Table 3–2: Control Registers of the Fast Processor
– default values are initialized at reset
– * indicates: register is initialized according to the current standard when SDT register is changed.
FP Subaddress
Function
Default
Name
Standard Selection
h’20
Standard select:
bit[2:0]
standard
0
PAL B,G,H,I
1
NTSC M
2
SECAM
3
NTSC44
4
PAL M
5
PAL N
6
PAL 60
7
NTSC COMB
SDT
0
(50 Hz)
(60 Hz)
(50 Hz)
(60 Hz)
(60 Hz)
(50 Hz)
(60 Hz)
(60 Hz)
4.433618
3.579545
4.286
4.433618
3.575611
3.582056
4.433618
3.579545
PAL
NTSC
SECAM
NTSC44
PALM
PALN
PAL60
NTSCC
bit[3]
0/1
MOD standard modifier
PAL modified to simple PAL
NTSC modified to compensated NTSC
SECAM modified to monochrome 625
NTSCC modified to monochrome 525
0
SDTMOD
bit[4]
0/1
PAL+ mode off/on
0
PALPLUS
bit[5]
0/1
4-H COMB mode
0
COMB
bit[6]
0/1
S-VHS mode:
The S-VHS/COMB bits allow the following modes:
composite input signal
comb filter active
S-VHS input signal
CVBS mode (composite input signal, no luma notch)
0
SVHS
0
SDTOPT
0
ASR_ENABLE
00
01
10
11
Option bits allow to suppress parts of the initialization; this can be
used for color standard search:
h’148
bit[7]
bit[8]
bit[9]
bit[10]
no hpll setup
no vertical setup
no acc setup
4-H comb filter setup only
bit[11]
status bit, normally write 0. After the FP has switched to a
new standard, this bit is set to 1 to indicate operation
complete. Standard is automatically initialized when the
insel register is written.
Enable automatic standard recognition
bit[0]
0/1 PAL B,G,H,I
(50 Hz)
bit[1]
0/1 NTSC M
(60 Hz)
bit[2]
0/1 SECAM
(50 Hz)
bit[3]
0/1 NTSC44
(60 Hz)
bit[4]
0/1 PAL M
(60 Hz)
bit[5]
0/1 PAL N
(50 Hz)
bit[6]
0/1 PAL 60
(60 Hz)
4.433618
3.579545
4.286
4.433618
3.575611
3.582056
4.433618
0: disable recognition; 1: enable recognition
40
Micronas
ADVANCE INFORMATION
VPC 323xD, VPC 324xD
FP Subaddress
Function
h’14e
Status of automatic standard recognition
bit[0]
1
error of the vertical standard (neither 50 nor 60 Hz)
bit[1]
1
detected standard is disabled
bit[2]
1
search active
bit[3]
1
search terminated, but failed
bit[3:0]
h’21
Default
writing to this register will also initialize the standard
bit[1:0]
luma selector
VIN3
VIN2
VIN1
VIN4
chroma selector
VIN1/CIN
IF compensation
off
6 dB/Okt
12 dB/Okt
10 dB/MHz only for SECAM
chroma bandwidth selector
narrow
normal
broad
wide
adaptive/fixed SECAM notch filter
enable luma lowpass filter
hpll speed
no change
terrestrial
vcr
mixed
status bit, write 0, this bit is set to 1 to indicate
operation complete.
00
01
10
11
bit[2]
0/1
bit[4:3]
00
01
10
11
bit[6:5]
00
01
10
11
0/1
0/1
00
01
10
11
bit[11]
0
ASR_STATUS
VWINERR
DISABLED
BUSY
FAILED
0000 all ok
0001 search not started, because vwin error detected
(no input or SECAM L)
0010 search not started, because detected vert. standard
not enabled
x1x0 search started and still active
1x00 search failed (found standard not correct)
1x10 search failed, (detected color standard not enabled)
Input select:
bit[7]
bit[8]
bit[10:9]
Name
INSEL
0
VIS
1
CIS
0
IFC
2
CBW
0
0
3
FNTCH
LOWP
HPLLMD
h’22
picture start position: This register sets the start point of active video
and can be used e.g. for panning. The setting is updated when ‘sdt’
register is updated or when the scaler mode register ‘scmode’ is written.
0
SFIF
h’23
luma/chroma delay adjust. The setting is updated when ‘sdt’ register
is updated.
bit[5:0]
reserved, set to zero
bit[11:6]
luma delay in clocks, allowed range is +1 ... –7
0
LDLY
h’29
helper delay register (PAL+ mode only)
bit[11:0]
delay adjust for helper lines adjustable from
–96...96, 1 step corresponds to 1/32 clock
0
HLP_DLY
Micronas
41
VPC 323xD, VPC 324xD
ADVANCE INFORMATION
FP Subaddress
Function
Default
h’2f
VGA mode select, pull-in range is limited to 2%
bit[1:0] 0
31.5 kHz
1
35.2 kHz
2/3 37.9 kHz
is set to 0 by FP if VGA = 0
bit[10]
0/1 disable/enable VGA mode
bit[11]
status bit, write 0, this bit is set to 1 to indicate
operation complete.
Name
VGA_C
0
VGAMODE
0
VGA
Comb Filter
h’28
h’55
comb filter control register
bit[1:0] notch filter select
00
flat frequency characteristic
01
min. peaked
10
med. peaked
11
max. peaked
bit[3:2] diagonal dot reduction
00
min. reduction ... 11
max. reduction
bit[4:5] horizontal difference gain
00
min. gain
... 11
max. gain
bit[7:6] vertical difference gain
00
max. gain
... 11
min. gain
bit[11:8] vertical peaking gain
0
no vertical peaking... 15 max. vertical peaking
comb filter test register
bit[1:0] reserved, set ot 0
bit[2]
0/1 disable/enable vertical peaking DC rejection filter
bit[3]
0/1 disable/enable vertical peaking coring
bit[11:4] reserved, set to 0
h’e7
3
COMB_UC
NOSEL
1
DDR
2
HDG
3
VDG
0
VPK
CMB_TST
0
0
DCR
COR
Color Processing
h’30
Saturation control
bit[11:0] 0...4095 (2070 corresponds to 100% saturation)
h’17a
ACC PAL+ Helper gain adjust, gain is referenced to PAL burst,
allowed values from 256..1023
a value of zero allows manual adjust of Helper amplitude via ACCh
h’17d
ACC multiplier value for PAL+ Helper Signal
b[10:0] eeemmmmmmmm m * 2–e
h’39
amplitude killer level (0:killer disabled)
h’3a
2070
ACC_SAT
787
HLPGAIN
1280
ACCH
25
KILVL
amplitude killer hysteresis
5
KILHY
h’16c
automatic helper disable for nonstandard signals
bit[11:0] 0
automatic function disabled
bit[1:0] 01
enable
bit[11:2] 1..50 number of fields to switch on helper signal
0
HLPDIS
h’dc
NTSC tint angle, ±512 = ±π/4
0
TINT
42
Micronas
VPC 323xD, VPC 324xD
ADVANCE INFORMATION
FP Subaddress
Function
Default
Name
DVCO
h’f8
crystal oscillator center frequency adjust, –2048 ... 2047
h’f9
crystal oscillator center frequency adjustment value for line-lock
mode, true adjust value is DVCO – ADJUST.
For factory crystal alignment, using standard video signal: disable
autolock mode, set DVCO = 0, set lock mode, read crystal offset from
ADJUST register and use negative value for initial center frequency
adjustment via DVCO.
h’f7
crystal oscillator line-locked mode, lock command/status
write: 100
enable lock
0
disable lock
read: 0
unlocked
>2047
locked
h’b5
crystal oscillator line-locked mode, autolock feature. If autolock is
enabled, crystal oscillator locking is started automatically.
bit[11:0]
threshold, 0:autolock off
–720
read only
0
400
DVCO
ADJUST
XLCK
AUTOLCK
FP Status Register
h’12
general purpose control bits
bit[2:0]
reserved, do not change
bit[3]
vertical standard force
bit[8:4]
reserved, do not change
bit[9]
disable flywheel interlace
bit[11:10]
reserved, do not change
to enable vertical free run mode set vfrc to 1 and dflw to 0
0
VFRC
1
DFLW
–
ASR
h’13
standard recognition status
bit[0]
1
vertical lock
bit[1]
1
horizontally locked
bit[2]
1
no signal detected
bit[3]
1
color amplitude killer active
bit[4]
1
disable amplitude killer
bit[5]
1
color ident killer active
bit[6]
1
disable ident killer
bit[7]
1
interlace detected
bit[8]
1
no vertical sync detection
bit[9]
1
spurious vertical sync detection
bit[12:10]
reserved
h’14
input noise level, available only for VPC 323xC
read only
NOISE
h’cb
number of lines per field, P/S: 312, N: 262
read only
NLPF
h’15
vertical field counter, incremented per field
read only
VCNT
h’74
measured sync amplitude value, nominal: 768 (PAL), 732 (NTSC)
read only
SAMPL
h’31
measured burst amplitude
read only
BAMPL
h’f0
firmware version number
bit[7:0]
internal revision number
bit[11:8]
firmware release
hardware id see I2C register h’9f
read only
–
Micronas
43
VPC 323xD, VPC 324xD
FP Subaddress
ADVANCE INFORMATION
Function
Default
Name
Scaler Control Register
h’40
scaler mode register
bit[1:0] scaler mode
0
linear scaling mode
1
nonlinear scaling mode, ’panorama’
2
nonlinear scaling mode, ’waterglass’
3
reserved
bit[2]
reserved, set to 0
bit[3]
color mode select
0/1 4:2:2 mode / 4:1:1 mode
bit[4]
scaler bypass
bit[5]
reserved, set to 0
bit[6]
luma output format
0
ITU-R luma output format (16–240)
1
CVBS output format
bit[7]
chroma output format
0/1 ITU-R (offset binary) / signed
bit[10:8] reserved, set to 0
bit[11]
0
scaler update command, when the registers are
updated the bit is set to 1
0
pip control register
bit[1:0] horizontal downsampling
0
no downsampling
1
downsampling by 2
2
downsampling by 4
3
downsampling by 8
bit[3:2] vertical compression for PIP
0
compression by 2
1
compression by 3
2
compression by 4
3
compression by 6
bit[4]
vertical filter enable
bit[5]
interlace offset for vertical filter (NTSC mode only)
0
start in line 283 of 2nd field (ITUR 656 spec)
1
start in line 282 of 2nd field (NTSC spec)
this register is updated when the scaler mode register is written
0
h’42
active video length for 1H-FIFO
bit[11:0] length in pixels
D3000 mode (1296/h)1080
LLC mode (864/h)720
this register is updated when the scaler mode register is written
1080
FFLIM
h’43
scaler1 coefficient: This scaler compresses the signal.
For compression by a factor c, the value c*1024 is required.
bit[11:0]
allowed values from 1024... 4095
This register is updated when the scaler mode register is written.
1024
SCINC1
h’44
scaler2 coefficient: This scaler expands the signal.
For expansion by a factor c, the value 1/c*1024 is required.
bit[11:0]
allowed values from 256..1024
This register is updated when the scaler mode register is written.
1024
SCINC2
h’45
scaler1/2 nonlinear scaling coefficient
This register is updated when the scaler mode register is written.
0
h’41
44
SCMODE
PANO
S411
BYE
YOF
COF
SCPIP
DOWNSAMP
PIPSIZE
PIPE
INTERLACE_OFF
SCINC
Micronas
VPC 323xD, VPC 324xD
ADVANCE INFORMATION
FP Subaddress
Function
h’47 –
h’4b
scaler1 window controls, see table
5 12-bit registers for control of the nonlinear scaling
This register is updated when the scaler mode register is written.
0
SCW1_0 – 4
h’4c –
h’50
scaler2 window controls, see table
5 12-bit registers for control of the nonlinear scaling
This register is updated when the scaler mode register is written.
0
SCW2_0 – 4
h’52
brightness register
bit[7:0] luma brightness −128...127
ITU-R output format: 16
CVBS output format: −4
bit[9:8] horizontal lowpass filter for Y/C
0
bypass
1
filter 1
2
filter 2
3
filter 3
bit[10]
horizontal lowpass filter for highresolution chroma
0/1 bypass/filter enabled
this register is updated when the scaler mode register is written
16
16
contrast register
bit[5:0] luma contrast 0..63
ITU-R output format: 48
bit[7:6] horizontal peaking filter
0
broad
1
med
2
narrow
bit[10:8] peaking gain
0
no peaking... 7 max. peaking
bit[10]
peaking filter coring enable
0/1 bypass/coring enabled
this register is updated when the scaler mode register is written
h’53
Default
Name
SCBRI
BR
0
LPF2
0
CBW2
48
48
SCCT
CT
0
PFS
0
PK
0
PKCOR
LLC Control Register
h’65
vertical freeze start
freeze llc pll for llc_start < line number < llc_stop
bit[11:0]
allowed values from –156...+156
–10
h’66
vertical freeze stop
freeze llc pll for llc_start < line number < llc_stop
bit[11:0]
allowed values from –156...+156
4
h’69
h’6a
20 bit llc clock center frequency
12.27 MHz −79437
13.5 MHz 174763
14.75 MHz 194181
16 MHz
–135927
18 MHz
174763
Micronas
=
=
=
=
=
h’FEC9B2
h’02AAAB
h’02F685
h’FDED08
h’02AAAB
42 = h’02A
2731 = h’AAB
LLC_START
LLC_STOP
LLC_CLOCKH
LLC_CLOCKL
45
VPC 323xD, VPC 324xD
FP Subaddress
Function
h’61
pll frequency limiter, 8%
12.27 MHz 30
13.5 MHz 54
14.75 MHz 62
16 MHz
48
18 MHz
54
h’6d
llc clock generator control word
bit[5:0] hardware register shadow
llc_clkc = 5→12.27 MHz
llc_clkc = 5→13.5 MHz
llc_clkc = 35→14.75 MHz
llc_clkc = 3→16 MHz
llc_clkc = 3→18 MHz
bit[10:6] reserved
bit[11]
0/1 enable/disable llc pll
46
ADVANCE INFORMATION
Default
Name
54
2053
LLC_DFLIMIT
LLC_CLKC
Micronas
VPC 323xD, VPC 324xD
ADVANCE INFORMATION
Table 3–3: Control Registers of the Fast Processor that are used for the control of DDP 3300A
– this function is only available in the 50 Hz version (VPC 324xD)
– default values are initialized at reset
– * indicates: register is initialized according to the current standard when SDT register is changed
FP Subaddress
Function
Default
Name
FP Display Control Register
h’130
White Drive Red
(0...1023)
700
WDR 1)
h’131
White Drive Green
(0...1023)
700
WDG 1)
h’132
White Drive Blue
(0...1023)
700
WDB 1)
h’139
Internal Brightness, Picture (0 ..511), the center value is 256, the range
allows for both increase and reduction of brightness.
256
IBR
h’13c
Internal Brightness, measurement (0...511), the center value is 256,
the brightness for measurement can be set to measure at higher cutoff
current. The measurement brightness is independent of the drive values.
256
IBRM
h’13a
Analog Brightness for external RGB (0...511), the center value is 256,
the range allows for both increase and reduction of brightness.
256
ABR
h’13b
Analog Contrast for external RGB (0...511)
350
ACT
1)
The white drive values will become active only after writing the blue value WDB, latching of new values is indicated by setting the MSB of WDB.
FP Display Control Register, BCL
h’144
BCL threshold current, 0...2047 (max ADC output ~1152)
1000
BCLTHR
h’142
BCL time constant 0...15 →13 ... 1700 msec
15
BCLTM
h’143
BCL loop gain. 0..15
0
BCLG
h’145
BCL minimum contrast 0 ...1023
307
BCLMIN
h’105
Test register for BCL/EHT comp. function, register value:
0
normal operation
1
stop ADC offset compensation
x>1 use x in place of input from Measurement ADC
0
BCLTST
FP Display Control Register, Deflection
h’103
interlace offset, –2048 ...2047
This value is added to the SAWTOOTH output during one field.
0
INTLC
h’102
discharge sample count for deflection retrace,
SAWTOOTH DAC output impedance is reduced for DSCC lines after
vertical retrace.
7
DSCC
h’11f
vertical discharge value,
SAWTOOTH output value during discharge operation, typically same
as A0 init value for sawtooth.
–1365
DSCV
h’10b
EHT (electronic high tension) compensation coefficient, 0...511
0
EHT
h’10a
EHT time constant. 0 ..15 → 3.2 ...410 msec
15
EHTTM
Micronas
47
VPC 323xD, VPC 324xD
ADVANCE INFORMATION
Control registers, continued
FP Subaddress
Function
Default
Name
FP Display Control Register, Vertical Sawtooth
h’110
DC offset of SAWTOOTH output
This offset is independent of EHT compensation.
0
OFS
h’11b
accu0 init value
–1365
A0
h’11c
accu1 init value
900
A1
h’11d
accu2 init value
0
A2
h’11e
accu3 init value
0
A3
FP Display Control Register, East-West Parabola
h’12b
accu0 init value
–1121
A0
h’12c
accu1 init value
219
A1
h’12d
accu2 init value
479
A2
h’12e
accu3 init value
–1416
A3
h’12f
accu4 init value
1052
A4
48
Micronas
VPC 323xD, VPC 324xD
ADVANCE INFORMATION
3.2.1. Calculation of Vertical and East-West
Deflection Coefficients
3.2.2. Scaler Adjustment
In Table 3–4 the formula for the calculation of the
deflection initialization parameters from the polynominal coefficients a,b,c,d,e is given for the vertical and
East-West deflection. Let the polynomial be
P ÷ a + b(x – 0.5) + c(x – 0.5)2 + d(x – 0.5)3 + e(x – 0.5)4
The initialization values for the accumulators a0..a3 for
vertical deflection and a0..a4 for East-West deflection
are 12-bit values. The coefficients that should be used
to calculate the initialization values for different field
frequencies are given below, the values must be
scaled by 128, i.e. the value for a0 of the 50 Hz vertical
deflection is
a0 = (a · 128 – b · 1365.3 + c · 682.7 – d · 682.7) ÷ 128
In case of linear scaling, most of the scaler registers
need not be set. Only the scaler mode, active video
length, and the fixed scaler increments (scinc1/scinc2)
must be written.
The adjustment of the scaler for nonlinear scaling
modes should use the parameters given in table 3–5.
An example for ‘panorama vision’ mode with 13.5 MHz
line-locked clock is depicted in Fig. 3–2. The figure
shows the scaling of the input signal and the variation
of the scaling factor during the active video line. The
scaling factor starts below 1, i.e. for the borders the
video data is expanded by scaler 2. The scaling factor
becomes one and compression scaling is done by
scaler 1. When the picture center is reached, the scaling factor is held constant. At the second border the
scaler increment is inverted and the scaling factor
changes back symmetrically. The picture indicates the
function of the scaler increments and the scaler window parameters. The correct adjustment requires that
pixel counts for the respective windows are always in
number of output samples of scaler 1 or 2.
Table 3–4: Tables for the Calculation of Initialization values for Vertical Sawtooth and East-West Parabola
Vertical Deflection 50 Hz
a
a0
b
128
a1
c
East-West Deflection 50 Hz
d
–1365.3
+682.7
–682.7
a0
899.6
–904.3
+1363.4
a1
296.4
–898.4
a2
585.9
a3
a2
a3
a0
a1
a2
128
b
c
d
e
–341.3
1365.3
–85.3
341.3
111.9
–899.6
84.8
–454.5
586.8
–111.1
898.3
72.1
–1171.7
East-West Deflection 60 Hz
–1365.3
+682.7
–682.7
1083.5
–1090.2
+1645.5
429.9
–1305.8
a
a0
a1
128
b
c
d
e
–341.3
1365.3
–85.3
341.3
134.6
–1083.5
102.2
–548.4
849.3
–161.2
1305.5
125.6
–2046.6
1023.5
a3
a4
Micronas
c
756.5
d
a2
a3
128
b
a4
Vertical Deflection 60 Hz
a
a
1584.8
49
VPC 323xD, VPC 324xD
border
ADVANCE INFORMATION
border
center
input signal
video signal
output signal
scinc
compression
ratio
1
scinc1
scinc2
expansion
(scaler2)
compression
(scaler1)
scaler window 0
cutpoints
compression
(scaler1)
1
2
expansion
(scaler2)
3
4
Fig. 3–2: Scaler operation for ‘panorama’ mode at 13.5 MHz
Table 3–5: Set-up values for nonlinear scaler modes
Mode
DIGIT3000 (20.25 MHz)
‘waterglass’
border 35%
Register
center 3/4
center 5/6
LLC (13.5 MHz)
‘panorama’
border 30%
‘waterglass’
border 35%
‘panorama’
border 30%
center 4/3 center 6/5
center 3/4 center 5/6
center 4/3 center 6/5
scinc1
1643
1427
1024
1024
2464
2125
1024
1024
scinc2
1024
1024
376
611
1024
1024
573
914
scinc
90
56
85
56
202
124
190
126
fflim
945
985
921
983
719
719
681
715
scw1 – 0
110
115
83
94
104
111
29
13
scw1 – 1
156
166
147
153
104
111
115
117
scw1 – 2
317
327
314
339
256
249
226
241
scw1 – 3
363
378
378
398
256
249
312
345
scw1 – 4
473
493
461
492
360
360
341
358
scw2 – 0
110
115
122
118
104
111
38
14
scw2 – 1
156
166
186
177
104
111
124
118
scw2 – 2
384
374
354
363
256
249
236
242
scw2 – 3
430
425
418
422
256
249
322
346
scw2 – 4
540
540
540
540
360
360
360
360
50
Micronas
VPC 323xD, VPC 324xD
ADVANCE INFORMATION
4. Specifications
4.1. Outline Dimensions
23 x 0.8 = 18.4
0.8
0.17 ±0.03
64
41
14
17.2
8
1.8
10.3
9.8
5
16
80
0.8
8
1.8
1
15 x 0.8 = 12.0
40
65
25
24
1.28
23.2
2.70
3 ±0.2
20
0.1
SPGS0025-1/1E
Fig. 4–1: 80-Pin Plastic Quad Flat Package
(PQFP80)
Weight approximately 1.61 g
Dimensions in mm
4.2. Pin Connections and Short Descriptions
NC = not connected
LV = if not used, leave vacant
X = obligatory; connect as described in circuit diagram
SUPPLYA=4.75...5.25V, SUPPLYD=3.15...3.45V
Pin No.
Pin Name
Type
Connection
(if not used)
Short Description
1
B1/CB1IN
IN
VREF
Blue1/Cb1 Analog Component Input
2
G1/Y1IN
IN
VREF
Green1/Y1 Analog Component Input
3
R1/CR1IN
IN
VREF
Red1/Cr1 Analog Component Input
4
B2/CB2IN
IN
VREF
Blue2/Cb2 Analog Component Input
5
G2/Y2IN
IN
VREF
Green2/Y2 Analog Component Input
6
R2/CR2IN
IN
VREF
Red2/Cr2 Analog Component Input
7
ASGF
X
Analog Shield GNDF
9
VSUPCAP
SUPPLYD
X
Supply Voltage, Digital Decoupling Circuitry
10
VSUPD
SUPPLYD
X
Supply Voltage, Digital Circuitry
11
GNDD
SUPPLYD
X
Ground, Digital Circuitry
12
GNDCAP
SUPPLYD
X
Ground, Digital Decoupling Circuitry
13
SCL
IN/OUT
X
I2C Bus Clock
14
SDA
IN/OUT
X
I2C Bus Data
PQFP
80-pin
Micronas
51
VPC 323xD, VPC 324xD
Pin No.
ADVANCE INFORMATION
Pin Name
Type
Connection
(if not used)
Short Description
15
RESQ
IN
X
Reset Input, Active Low
16
TEST
IN
GNDD
Test Pin, connect to GNDD
17
VGAV
IN
GNDD
VGAV Input
18
YCOEQ
IN
VSUPD
Y/C Output Enable Input, Active Low
19
FFIE
OUT
LV
FIFO Input Enable
20
FFWE
OUT
LV
FIFO Write Enable
21
FFRSTW
OUT
LV
FIFO Reset Write/Read
22
FFRE
OUT
LV
FIFO Read Enable
23
FFOE
OUT
LV
FIFO Output Enable
24
CLK20
IN/OUT
LV
Main Clock Output 20.25 MHz
25
GNDPA
SUPPLYD
X
Ground, Pad Decoupling Circuitry
26
VSUPPA
SUPPLYD
X
Supply Voltage, Pad Decoupling Circuitry
27
LLC2
OUT
LV
Double Clock Output
28
LLC1
IN/OUT
LV
Clock Output
29
VSUPLLC
SUPPLYD
X
Supply Voltage, LLC Circuitry
30
GNDLLC
SUPPLYD
X
Ground, LLC Circuitry
31
Y7
OUT
GNDY
Picture Bus Luma (MSB)
32
Y6
OUT
GNDY
Picture Bus Luma
33
Y5
OUT
GNDY
Picture Bus Luma
34
Y4
OUT
GNDY
Picture Bus Luma
35
GNDY
SUPPLYD
X
Ground, Luma Output Circuitry
36
VSUPY
SUPPLYD
X
Supply Voltage, Luma Output Circuitry
37
Y3
OUT
GNDY
Picture Bus Luma
38
Y2
OUT
GNDY
Picture Bus Luma
39
Y1
OUT
GNDY
Picture Bus Luma
40
Y0
OUT
GNDY
Picture Bus Luma (LSB)
41
C7
OUT
GNDC
Picture Bus Chroma (MSB)
42
C6
OUT
GNDC
Picture Bus Chroma
43
C5
OUT
GNDC
Picture Bus Chroma
44
C4
OUT
GNDC
Picture Bus Chroma
45
VSUPC
SUPPLYD
X
Supply Voltage, Chroma Output Circuitry
PQFP
80-pin
52
Micronas
VPC 323xD, VPC 324xD
ADVANCE INFORMATION
Pin No.
Pin Name
Type
Connection
(if not used)
Short Description
46
GNDC
SUPPLYD
X
Ground, Chroma Output Circuitry
47
C3
OUT
GNDC
Picture Bus Chroma
48
C2
OUT
GNDC
Picture Bus Chroma
49
C1
OUT
GNDC
Picture Bus Chroma
50
C0
OUT
GNDC
Picture Bus Chroma (LSB)
51
GNDSY
SUPPLYD
X
Ground, Sync Pad Circuitry
52
VSUPSY
SUPPLYD
X
Supply Voltage, Sync Pad Circuitry
53
INTLC
OUT
LV
Interlace Output
54
AVO
OUT
LV
Active Video Output
55
FSY/HC
OUT
LV
Front Sync/ Horizontal Clamp Pulse
56
MSY/HS
IN/OUT
LV
Main Sync/Horizontal Sync Pulse
57
VS
OUT
LV
Vertical Sync Pulse
58
FPDAT
IN/OUT
LV
Front-End/Back-End Data
59
VSTBY
SUPPLYA
X
Standby Supply Voltage
60
CLK5
OUT
LV
CCU 5 MHz Clock Output
62
XTAL1
IN
X
Analog Crystal Input
63
XTAL2
OUT
X
Analog Crystal Output
64
ASGF
X
Analog Shield GNDF
65
GNDF
SUPPLYA
X
Ground, Analog Front-End
66
VRT
OUTPUT
X
Reference Voltage Top, Analog
67
I2CSEL
IN
X
I2C Bus Address Select
68
ISGND
SUPPLYA
X
Signal Ground for Analog Input, connect to
GNDF
69
VSUPF
SUPPLYA
X
Supply Voltage, Analog Front-End
70
VOUT
OUT
LV
Analog Video Output
71
CIN
IN
LV*
Chroma / Analog Video 5 Input
72
VIN1
IN
VRT*
Video 1 Analog Input
73
VIN2
IN
VRT
Video 2 Analog Input
74
VIN3
IN
VRT
Video 3 Analog Input
75
VIN4
IN
VRT
Video 4 Analog Input
76
VSUPAI
SUPPLYA
X
Supply Voltage, Analog Component Inputs
Front-End
PQFP
80-pin
Micronas
53
VPC 323xD, VPC 324xD
Pin No.
ADVANCE INFORMATION
Pin Name
Type
Connection
(if not used)
Short Description
77
GNDAI
SUPPLYA
X
Ground, Analog Component Inputs Front-End
78
VREF
OUTPUT
X
Reference Voltage Top, Analog Component
Inputs Front-End
79
FB1IN
IN
VREF
Fast Blank Input
80
AISGND
SUPPLYA
X
Signal Ground for Analog Component Inputs,
connect to GNDAI
8, 61
NC
–
LV OR GNDD
Not connected
PQFP
80-pin
*) chroma selector must be set to 1 (CIN chroma select)
4.3. Pin Descriptions
(pin numbers for PQFP80 package)
Pins 1-3 – Analog Component Inputs RGB1/YCrCb1
(Fig. 4–11)
These are analog component inputs with fast blank
control. A RGB or YCrCb signal is converted using the
component AD converter. The input signals must be
AC-coupled.
Pins 4-6 – Analog Component Inputs RGB2/YCrCb2
(Fig. 4–11)
These are analog component inputs without fastblank
control. A RGB or YCrCb signal is converted using the
component AD converter. The input signals must be
AC-coupled.
Pin 7, 64 – Ground, Analog Shield Front-End GNDF
Pin 9 – Supply Voltage, Decoupling Circuitry VSUPCAP
This pin is connected with 220 nF/1.5 nF/390 pF to
GNDCAP.
Pin 17 – VGAV-Input (Fig. 4–3)
This pin is connected to the vertical sync signal of a VGA
signal.
Pin 18 – YC Output Enable Input YCOEQ (Fig. 4–3)
A low level on this pin enables the luma and chroma
outputs.
Pin 19 – FIFO Input Enable FFIE (Fig. 4–4)
This pin is connected to the IE pin of the external field
memory.
Pin 20 – FIFO Write Enable FFWE (Fig. 4–4)
This pin is connected to the WE pin of the external field
memory.
Pin 21 – FIFO Reset Write/Read FFRSTW (Fig. 4–4)
This pin is connected to the RSTW pin of the external
field memory.
Pin 22 – FIFO Read Enable FFRE (Fig. 4–4)
This pin is connected to the RE pin of the external field
memory.
Pin 10 – Supply Voltage, Digital Circuitry VSUPD
Pin 11 – Ground, Digital Circuitry GNDD
Pin 23 – FIFO Output Enable FFOE (Fig. 4–4)
This pin is connected to the OE pin of the external field
memory.
Pin 12 – Ground, Decoupling Circuitry GNDCAP
Pin 13– I2C Bus Clock SCL (Fig. 4–3)
This pin connects to the I2C bus clock line.
Pin 14– I2C Bus Data SDA (Fig. 4–12)
This pin connects to the I2C bus data line.
Pin 24 – Main Clock Output CLK20 (Fig. 4–4)
This is the 20.25 MHz main clock output.
Pin 25 – Ground, Analog Pad Circuitry GNDPA
Pin 26 – Supply Voltage, Analog Pad Circuitry VSUPPA
This pin is connected with 47 nF/1.5 nF to GNDPA
Pin 15 – Reset Input RESQ (Fig. 4–3)
A low level on this pin resets the VPC 32xx.
Pin 27 – Double Output Clock, LLC2 (Fig. 4–4)
Pin 16 – Test Input TEST (Fig. 4–3)
This pin enables factory test modes. For normal operation, it must be connected to ground.
Pin 28 – Output Clock, LLC1 (Fig. 4–4)
This is the clock reference for the luma, chroma, and
status outputs.
54
Micronas
VPC 323xD, VPC 324xD
ADVANCE INFORMATION
Pin 29 – Supply Voltage, LLC Circuitry VSUPLLC
This pin is connected with 68 nF to GNDLLC
cessor. The information for the deflection drives and for
the white drive control, i. e. the beam current limiter, is
transmitted by this pin.
Pin 30 – Ground, LLC Circuitry GNDLLC
Pins 31 to 34,37 to 40 – Luma Outputs Y7 – Y0 (Fig.
4–4)
These output pins carry the digital luminance data. The
outputs are clocked with the LLC1 clock. In ITUR656
mode the Y/C data is multiplexed and clocked with
LLC2 clock.
Pin 35– Ground, Luma Output Circuitry GNDY
This pin is connected with 68 nF to GNDY
Pin 36 – Supply Voltage, Luma Output Circuitry VSUPY
Pins 41 to 44,47 to 50 – Chroma Outputs C7–C0 (Fig.
4–4) These outputs carry the digital CrCb chrominance
data. The outputs are clocked with the LL1 clock. The
CrCb data is sampled at half the clock rate and multiplexed. The CrCb multiplex is reset for each TV line. In
ITUR656 mode, the chroma outputs are tri-stated.
Pin 59 – Standby Supply Voltage VSTDBY
In standby mode, only the clock oscillator is active,
GNDF should be ground reference. Please activate
RESQ before powering-up other supplies
Pin 60 – CCU 5 MHz Clock Output CLK5 (Fig. 4–10)
This pin provides a clock frequency for the TV microcontroller, e.g. a CCU 3000 controller. It is also used by
the DDP 3300A display controller as a standby clock.
Pins 62and 63 – XTAL1 Crystal Input and XTAL2 Crystal Output (Fig. 4–7)
These pins are connected to an 20.25 MHz crystal
oscillator which is digitally tuned by integrated shunt
capacitances. The CLK20 and CLK5 clock signals are
derived from this oscillator. An external clock can be
fed into XTAL1. In this case, clock frequency adjustment must be switched off.
Pin 65 – Ground, Analog Front-End GNDF
Pin 45 – Supply Voltage, Chroma Output Circuitry
VSUPC
This pin is connected with 68 nF to GNDC
Pin 46 – Ground, Chroma Output Circuitry GNDC
Pin 66 – Reference Voltage Top VRT (Fig. 4–8)
Via this pin, the reference voltage for the A/D converters
is decoupled. The pin is connected with 10 µF/47 nF to
the Signal Ground Pin.
Pin 51 – Ground, Sync Pad Circuitry GNDSY
Pin 67 – I2C Bus address select I2CSEL
This pin determines the I2C bus address of the IC.
Pin 52 – Supply Voltage, Sync Pad Circuitry VSUPSY
This pin is connected with 47 nF/1.5 nF to GNDSY
Table 4–1: VPC32xxD I2C address select
Pin 53 – Interlace Output, INTLC (Fig. 4–4)
This pin supplies the interlace information, 0 indicates
first field, 1 indicates second field.
Pin 54 – Active Video Output, AVO (Fig. 4–4)
This pin indicates the active video output data. The
signal is clocked with the LLC1 clock.
Pin 55 – Front Sync/Horizontal Clamp Pulse, FSY/HC
(Fig. 4–4)
This signal can be used to clamp an external video signal, that is synchronous to the input signal. The timing
is programmable. In DIGIT3000 mode, this pin supplies the front sync information.
Pin 56 – Main Sync/Horizontal Sync Pulse MSY/HS
(Fig. 4–4)
This pin supplies the horizontal sync pulse information
in line-locked mode. In DIGIT3000 mode, this pin is the
main sync input.
Pin 57 – Vertical Sync Pulse, VS (Fig. 4–4)
This pin supplies the vertical sync signal.
Pin 58 – Front-End/Back-End Data FPDAT (Fig. 4–5)
This pin interfaces to the DDP 3300A back-end pro-
Micronas
I2CSEL
I2C Add.
GNDF
88/89 hex
VRT
8C/8D hex
VSUPF
8E/8F hex
Pin 68 – Signal GND for Analog Input ISGND (Fig. 4–
10) This is the high quality ground reference for the
video input signals.
Pin 69 – Supply Voltage, Analog Front-End VSUPF
(Fig. 4–8)
This pin is connected with 220 nF/1.5 nF/390 pF to
GNDF
Pin 70 – Analog Video Output, VOUT (Fig. 4–6)
The analog video signal that is selected for the main
(luma, CVBS) ADC is output at this pin. An emitter follower is required at this pin.
Pin 71 – Chroma Input CIN (Fig. 4–9)
This pin is connected to the S-VHS chroma signal. A
resistive divider is used to bias the input signal to the
middle of the converter input range. CIN can only be
55
VPC 323xD, VPC 324xD
ADVANCE INFORMATION
connected to the chroma (Video 2) A/D converter. The
signal must be AC-coupled.
Pins 72-75 – Video Input 1–4 (Fig. 4–11)
These are the analog video inputs. A CVBS or S-VHS
luma signal is converted using the luma (Video 1) AD
converter. The VIN1 input can also be switched to the
chroma (Video 2) ADC. The input signal must be
AC-coupled.
Pin 76 – Supply Voltage, Analog Component Inputs
Front-End VSUPAI
This pin is connected with 220 nF/1.5 nF/390 pF to
GNDAI
Pin 77 – Ground, Analog Component Inputs Front-End
GNDAI
Pin 78 – Reference Voltage Top VREF (Fig. 4–8)
Via this pin, the reference voltage for the analog component A/D converters is decoupled. The pin is connected
with 10 µF/47 nF to the Analog Component Signal
Ground Pin.
Pin 79 – Fast Blank Input FB1IN (Fig. 4–10)
This pin is connected to the analog fast blank signal. It
controls the insertion of the RGB1/YCrCb1 signals. The
input signal must be DC-coupled.
Pin 80 – Signal GND for Analog Component Inputs
AISGND (Fig. 4–10)
This is the high quality ground reference for the component input signals.
56
Micronas
VPC 323xD, VPC 324xD
ADVANCE INFORMATION
4.4. Pin Configuration
INTLC
AVO
VSUPSY
GNDSY
FSY/HC
C0
MSY/HS
C1
VS
C2
FPDAT
C3
VSTBY
GNDC
CLK5
VSUPC
NC
C4
XTAL1
C5
XTAL2
C6
ASGF
C7
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
65
40
Y0
VRT
66
39
Y1
I2CSEL
67
38
Y2
ISGND
68
37
Y3
VSUPF
69
36
VSUPY
VOUT
70
35
GNDY
CIN
71
34
Y4
VIN1
72
33
Y5
VIN2
73
32
Y6
VIN3
74
31
Y7
VIN4
75
30
GNDLLC
VSUPAI
76
29
VSUPLLC
GNDAI
77
28
LLC1
VREF
78
27
LLC2
FB1IN
79
26
VSUPPA
AISGND
80
25
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
GNDF
VPC323XD
1
2
3
4
5
6
7
8
9
GNDPA
CLK20
B1/CB1IN
G1/Y1IN
FFOE
R1/CR1IN
FFRE
B2/CB2IN
FFRSTW
G2/Y2IN
FFWE
R2/CR2IN
FFIE
ASGF
YCOEQ
NC
VGAV
VSUPCAP
TEST
VSUPD
GNDD
GNDCAP
RESQ
SDA
SCL
Fig. 4–2: 80-pin PQFP package
Micronas
57
VPC 323xD, VPC 324xD
ADVANCE INFORMATION
4.5. Pin Circuits
VSUPF
–
+
VSUPD
P
VRT
ADC Reference
Vref
ISGND
GNDD
Fig. 4–8: Pins VRT, ISGND and VREF, AISGND
Fig. 4–3: Input pins RESQ, TEST, VGAV, YCOEQ
VSUPF
V SUPP
V SUPD
To ADC
P
P
GNDF
N
N
Fig. 4–9: Chroma input CIN
GND P
Fig. 4–4: Output pins C0–C7, Y0–Y7, FSY, MSY,
HC, AVO, VS, INTLC, HS, LLC1, LLC2, CLK20,
FFWE, FFIE, FFIE, FFRD, RSTWR
VSTBY
P
N
GNDF
VSUPD
P
P
N
N
Fig. 4–10: Output pin CLK5
VSUPF
GNDD
To ADC
Fig. 4–5: Input/Output pin FPDAT
GNDF
Vin’s
VSUPF
–
+
P
Fig. 4–11: Input pins VIN1–VIN4, RGB/YCrCb1/2,
FB1IN
VOUT
VREF
N
GNDF
GNDD
Fig. 4–6: Output pin VOUT
Fig. 4–12: Pins SDA, SCL
VSTBY
P
P
0.5M
N
N
f ECLK
GNDF
Fig. 4–7: Input/Output Pins XTAL1, XTAL2
58
Micronas
VPC 323xD, VPC 324xD
ADVANCE INFORMATION
4.6. Electrical Characteristics
4.6.1. Absolute Maximum Ratings
Symbol
Parameter
Pin No.
Min.
Max.
Unit
TA
Ambient Operating Temperature
–
0
65
°C
TS
Storage Temperature
–
–40
125
°C
VSUPA/D
Supply Voltage, all Supply Inputs
–0.3
6
V
VI
Input Voltage, all Inputs
–0.3
VSUPA+0.3
V
VO
Output Voltage, all Outputs
–0.3
VSUPD+0.3
V
Stresses beyond those listed in the “Absolute Maximum Ratings” may cause permanent damage to the device. This
is a stress rating only. Functional operation of the device at these or any other conditions beyond those indicated in
the “Recommended Operating Conditions/Characteristics” of this specification is not implied. Exposure to absolute
maximum ratings conditions for extended periods may affect device reliability.
4.6.2. Recommended Operating Conditions
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
TA
Ambient Operating Temperature
–
0
–
65
°C
VSUP
Supply Voltages, all analog Supply
Pins
4.75
5.0
5.25
V
VSUPD
Supply Voltages, all digital Supply
Pins
3.15
3.3
3.45
V
fXTAL
Clock Frequency
–
20.25
–
MHz
Micronas
XTAL1/2
59
VPC 323xD, VPC 324xD
ADVANCE INFORMATION
4.6.3. Recommended Crystal Characteristics
Symbol
Parameter
Min.
Typ.
Max.
Unit
TA
Operating Ambient Temperature
0
–
65
°C
fP
Parallel Resonance Frequency
with Load Capacitance CL = 13 pF
–
20.250000
–
MHz
∆fP/fP
Accuracy of Adjustment
–
–
±20
ppm
∆fP/fP
Frequency Temperature Drift
–
–
±30
ppm
RR
Series Resistance
–
–
25
Ω
C0
Shunt Capacitance
3
–
7
pF
C1
Motional Capacitance
20
–
30
fF
–
3.3
–
pF
Load Capacitance Recommendation
CLext
External Load Capacitance 1) from
pins to Ground
(pin names: Xtal1 Xtal2)
DCO Characteristics 2,3)
CICLoadmin
Effective Load Capacitance @ min.
DCO–Position, Code 0,
package: 68PLCC
3
4.3
5.5
pF
CICLoadrng
Effective Load Capacitance Range,
DCO Codes from 0..255
11
12.7
15
pF
1)
Remarks on defining the External Load Capacitance:
External capacitors at each crystal pin to ground are required. They are necessary to tune the effective load capacitance of the
PCBs to the required load capacitance CL of the crystal. The higher the capacitors, the lower the clock frequency results. The
nominal free running frequency should match fp MHz. Due to different layouts of customer PCBs the matching capacitor size
should be determined in the application. The suggested value is a figure based on experience with various PCB layouts.
Tuning condition: Code DVCO Register=–720
2)
Remarks on Pulling Range of DCO:
The pulling range of the DCO is a function of the used crystal and effective load capacitance of the IC (CICLoad +CLoadBoard).
The resulting frequency fL with an effective load capacitance of CLeff = CICLoad + CLoadBoard is:
1 + 0.5 * [ C1 / (C0 + CL) ]
fL = fP * _______________________
1 + 0.5 * [ C1 / (C0 + CLeff) ]
3)
Remarks on DCO codes
The DCO hardware register has 8 bits, the fp control register uses a range of –2048...2047
60
Micronas
VPC 323xD, VPC 324xD
ADVANCE INFORMATION
4.6.4. Characteristics
at TA = 0 to 65 °C, VSUPF = 4.75 to 5.25 V, VSUPD = 3.15 to 3.45V f = 20.25 MHz for min./max. values
at TC = 60 °C, VSUPF = 5 V, VSUPD = 3.3 V f = 20.25 MHz for typical values
Symbol
Parameter
PTOT
Total Power Dissipation
IVSUPA
Current Consumption
IVSUPD
Pin Name
Min.
Typ.
Max.
Unit
–
tbd
1.4
W
VSUPF
–
tbd
160
mA
Current Consumption
VSUPD
–
tbd
190
mA
IVSTDBY
Current Consumption
VSTDBY
–
1
–
mA
IL
Input / Output Leakage Current
All I/O Pins
–1
–
1
µA
4.6.4.1. Characteristics, 5 MHz Clock Output
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
VOL
Output Low Voltage
CLK5
–
–
0.4
V
IOL = 0.4 mA
VOH
Output High Voltage
4.0
–
V–
STDBY
V
–IOL = 0.9 mA
tOT
Output Transition Time
–
50
–
ns
CLOAD = 30 pF
4.6.4.2. Characteristics, 20 MHz Clock Input/Output, External Clock Input (XTAL1)
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
VDCAV
DC Average
CLK20
VSUPD/2
– 0.3
VSUPD/2
VSUPD/2
+ 0.3
V
CLOAD = 30 pF
VPP
VOUT Peak to Peak
VSUPD/2
– 0.3
VSUPD/2
VSUPD/2
+ 0.3
V
CLOAD = 30 pF
tOT
Output Transition Time
–
–
18
ns
CLOAD = 30 pF
VIT
Input Trigger Level
2.1
2.5
2.9
V
only for test purposes
VI
Clock Input Voltage
1.3
–
–
VPP
capacitive coupling used,
XTAL2 open
XTAL1
4.6.4.3. Characteristics, Reset Input, Test Input, VGAV Input, YCOEQ Input
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
VIL
Input Low Voltage
–
–
0.8
V
VIH
Input High Voltage
RESQ
TEST
VGAV
YCOEQ
2.0
–
–
V
Micronas
Test Conditions
61
VPC 323xD, VPC 324xD
ADVANCE INFORMATION
4.6.4.4. Characteristics, Power-up Sequence
Symbol
Parameter
tVdel
tVrmpl
Pin Name
Min.
Typ.
Max.
Unit
Ramp Up Difference of Supplies
tbd
–
tbd
ms
Transition Time of Supplies
−
–
50
ms
Test Conditions
tVrmp
0.9 * VSUPAI
VSUPF
time / ms
tVdel
0.9 * VSUPD
VSTBY
time / ms
max. 1ms
(maximum guaranteed start-up time)
LLC
time / ms
RESQ
min. 1ms
0.8 * VSUPD
time / ms
max. 0.05ms
SDA/SCL
I2C-cycles invalid
time / ms
Fig. 4–13: Power-Up sequence
62
Micronas
VPC 323xD, VPC 324xD
ADVANCE INFORMATION
4.6.4.5. Characteristics, FPDAT Input/Output
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
VOL
Output Low Voltage
FPDAT
–
–
0.5
V
IOL = 4.0 mA
tOH
Output Hold Time
6
–
–
ns
tODL
Output Delay Time
–
–
35
ns
VIL
Input Low Voltage
–
–
0.8
V
VIH
Input High Voltage
1.5
–
–
V
tIS
Input Setup Time
7
–
–
ns
tIH
Input Hold Time
5
–
–
ns
CL
Load capacitance
–
40
pF
CL = 40 pF
4.6.4.6. Characteristics, I2C Bus Interface
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
VIL
Input Low Voltage
SDA, SCL
–
–
1.0
V
VIH
Input High Voltage
2.0
–
–
V
VOL
Output Low Voltage
–
–
0.4
0.6
V
V
VIH
Input Capacitance
–
–
5
pF
tF
Signal Fall Time
–
–
300
ns
CL = 400 pF
tR
Signal Rise Time
–
–
300
ns
CL = 400 pF
fSCL
Clock Frequency
0
–
400
kHz
tLOW
Low Period of SCL
1.3
–
–
µs
tHIGH
High Period of SCL
0.6
–
–
µs
tSU Data
Data Set Up Time to SCL high
100
–
–
ns
tHD Data
DATA Hold Time to SCL low
0
–
0.9
µs
Micronas
SCL
SDA
Test Conditions
Il = 3 mA
Il = 6 mA
63
VPC 323xD, VPC 324xD
ADVANCE INFORMATION
4.6.4.7. Characteristics, Analog Video and Component Inputs
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
VVIN
Analog Input Voltage
VIN1, VIN2
VIN3, VIN4
CIN
R1/CR1IN
G1/Y1IN
B1/CB1IN
R2/CR2IN
G2/Y2IN
B2/CB2IN
0
–
3.5
V
CCP
Input Coupling Capacitor
Video Inputs
VIN1, VIN2
VIN3, VIN4
–
680
–
nF
CCP
Input Coupling Capacitor
Chroma Input
CIN
–
1
–
nF
CCP
Input Coupling Capacitor
Component Input
R1/CR1IN
G1/Y1IN
B1/CB1IN
R2/CR2IN
G2/Y2IN
B2/CB2IN
–
220
–
nF
Test Conditions
4.6.4.8. Characteristics, Analog Front-End and ADCs
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
VVRT
Reference Voltage Top
VRT
VREF
2.4
2.5
2.6
V
10 µF/10 nF, 1 GΩ Probe
RVIN
Input Resistance
1
MΩ
Code Clamp–DAC=0
CVIN
Input Capacitance
VIN1
VIN2
VIN3
VIN4
VVIN
Full Scale Input Voltage
1.8
VVIN
Full Scale Input Voltage
VIN1
VIN2
VIN3
VIN4
0.5
AGC
AGC step width
DNLAGC
AGC Differential Non-Linearity
VVINCL
Input Clamping Level, CVBS
QCL
Clamping DAC Resolution
ICL–LSB
Input Clamping Current per step
DNLICL
Clamping DAC Differential NonLinearity
Luma – Path
64
4.5
pF
2.0
2.2
VPP
min. AGC Gain
0.6
0.7
VPP
max. AGC Gain
dB
6-Bit Resolution= 64 Steps
fsig=1MHz,
– 2 dBr of max. AGC–Gain
0.166
±0.5
VIN1
VIN2
VIN3
VIN4
1.0
–16
0.7
1.0
LSB
V
Binary Level = 64 LSB
min. AGC Gain
15
steps
1.3
µA
5 Bit – I–DAC, bipolar
VVIN=1.5 V
±0.5
LSB
Micronas
VPC 323xD, VPC 324xD
ADVANCE INFORMATION
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
RCIN
Input Resistance
SVHS Chroma
CIN
VIN1
1.4
2.0
2.6
kΩ
VCIN
Full Scale Input Voltage,
Chroma
1.08
1.2
1.32
VPP
VCINDC
Input Bias Level,
SVHS Chroma
–
1.5
–
V
Test Conditions
Chroma – Path
Binary Code for Open
Chroma Input
128
Component – Path
RVIN
Input Resistance
CVIN
Input Capacitance
VVIN
Full Scale Input Voltage
VVIN
Full Scale Input Voltage
VVINCL
Input Clamping Level RGB, Y
VVINCL
R1/CR1IN
G1/Y1IN
B1/CB1IN
R2/CR2IN
G2/Y2IN
B2/CB2IN
1
MΩ
4.5
pF
Code Clamp–DAC=0
0.85
1.0
1.1
VPP
min. Gain (XAR=-0)
1.2
1.4
1.6
VPP
max. Gain (XAR=-1)
1.06
V
Binary Level = 16 LSB
XAR=-0
Input Clamping Level Cr, Cb
1.5
V
Binary Level = 128 LSB
XAR=-0
Gain Match
2.0
tbd
%
Full Scale at 1 MHz, XAR=-0
31
steps
1.11
µA
6 Bit – I–DAC, bipolar
VVIN=1.5 V
±0.5
LSB
QCL
Clamping DAC Resolution
–32
ICL–LSB
Input Clamping Current per step
0.59
DNLICL
Clamping DAC Differential NonLinearity
0.85
Dynamic Characteristics for all Video-Paths (Luma + Chroma) and Component-Paths
BW
Bandwidth
XTALK
Crosstalk, any Two Video Inputs
THD
Total Harmonic Distortion
SINAD
Signal to Noise and Distortion
Ratio
INL
Integral Non-Linearity
DNL
VIN1
VIN2
VIN3
VIN4
R1/CR1IN
G1/Y1IN
B1/CB1IN
R2/CR2IN
G2/Y2IN
B2/CB2IN
8
10
MHz
–2 dBr input signal level
–56
−tbd
dB
1 MHz, –2 dBr signal level
−50
−tbd
dB
1 MHz, 5 harmonics,
–2 dBr signal level
dB
1 MHz, all outputs,
–2 dBr signal level
±1tbd
LSB
Code Density,
DC-ramp
Differential Non-Linearity
±0.8
LSB
DG
Differential Gain
±3
%
DP
Differential Phase
1.5
deg
Micronas
tbd
45
–12 dBr, 4.4 MHz signal on
DC-ramp
65
VPC 323xD, VPC 324xD
Symbol
Parameter
ADVANCE INFORMATION
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
Out:
VOUT
In:
VIN1
VIN2
VIN3
VIN4
1.7
2.0
2.3
VPP
VIN = 1 VPP, AGC= 0 dB
dB
3 Bit Resolution=7 Steps
3 MSB’s of main AGC
Analog Video Output
VOUT
Output Voltage
AGCVOUT
AGC step width, VOUT
DNLAGC
AGC Differential Non-Linearity
VOUTDC
DC-level
BW
VOUT Bandwidth
THD
VOUT Total Harmonic Distortion
CLVOUT
Load Capacitance
ILVOUT
Output Current
1.333
±0.5
8
VOUT
LSB
1
V
clamped to Back porch
10
MHz
Input: –2 dBr of main ADC
range, CL≤10 pF
–40
dB
Input: –2 dBr of main ADC
range, CL≤10 pF
1 MHz, 5 Harmonics
–
–
10
pF
–
–
±0.1
mA
Typ.
Max.
Unit
Test Conditions
MΩ
Code Clamp–DAC=0
4.6.4.9. Characteristics, Analog FB Input
Symbol
Parameter
Pin Name
Min.
RFBIN
Input Resistance
FB1IN
1
VFBIN
Full Scale Input Voltage
0.85
1.0
1.1
VPP
Threshold for FB-Monitor
0.5
0.65
0.8
VPP
BW
Bandwidth
8
10
THD
Total Harmonic Distortion
SINAD
Signal to Noise and Distortion
Ratio
INL
Integral Non-Linearity
0.3
DNL
Differential Non-Linearity
0.2
66
−50
tbd
MHz
–2 dBr input signal level
dB
1 MHz, 5 harmonics,
–2 dBr signal level
dB
1 MHz, all outputs,
–2 dBr signal level
±1
LSB
Code Density,
DC-ramp
±0.8
LSB
tbd
37
Micronas
VPC 323xD, VPC 324xD
ADVANCE INFORMATION
4.6.4.10. Characteristics, Output Pin Specification
Output Specification for SYNC, CONTROL, and DATA Pins:
Y[7:0], C[7:0], AVO, HS, HC, INTLC, VS, FSY, FFIE, FFWE, FFOE, FFRD, FFRSTWR
Symbol
Parameter
VOL
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
Output Low Voltage
–
–
0.4
V
Cload =50pF
VOH
Output High Voltage
2.4
–
–
V
Cload =50pF
tOH
Output Hold Time
20
–
–
ns
LLC1=13.5MHz
tOD
Output Delay Time
–
–
52
ns
LLC1=13.5MHz
tOH
Output Hold Time
10
–
–
ns
LLC2=27.0MHz
tOD
Output Delay Time
–
–
26
ns
LLC2=27.0MHz
CL
Load Capacitance
–
–
50
pF
CLK20
20.25 MHz
in case of DIGIT3000 mode
2.0 V
tR, tF ≤ 5 ns
0.8 V
LLC1
13.5 MHz
in case of LLC Mode
VOH
Output
Data valid
Data valid
VOL
tOH
tOD
Fig. 4–14: Sync, control, and data outputs
Micronas
67
VPC 323xD, VPC 324xD
ADVANCE INFORMATION
write address point
disable
disable
N
N+1
N+2
N+3
N+4
N+5
disable
N+6
N+7
N+8
N+9
N+10
N+11
N+10
N+11
SWCK
FFWE
FFIE
D0-D11
N+1
N+2
N+7
N+8
Fig. 4–15: Field memory write cycle timing
read address point
disable
disable
N
N+1
N+2
N+3
N+4
N+5
disable
N+6
N+7
N+8
N+9
SRCK
FFRE
FFOE
D0-D11
Hi-z
N+1
N+2
Hi-z
N+7
N+8
Hi-z
Fig. 4–16: Field memory read cycle timing
68
Micronas
VPC 323xD, VPC 324xD
ADVANCE INFORMATION
4.6.4.11. Characteristics, Input Pin Specification
Input Specification for SYNC, CONTROL, and DATA Pin: MSY (DIGIT3000 mode only)
Symbol
Parameter
VIL
Pin Name
Min.
Typ.
Max.
Unit
Input Low Voltage
–
–
0.8
V
VIH
Input High Voltage
1.5
–
–
V
tIS
Input Setup Time
7
–
–
ns
tIH
Input Hold Time
5
–
–
ns
Test Conditions
CLK20
20.25 MHz
in case of DIGIT3000 Mode
VIH
Input
Data valid
tIS
tIH
VIL
2.0 V
tR, tF ≤ 5ns
0.8 V
LLC1
13.5 MHz
in case of LLC Mode
VIH
Input
Data valid
tIS
tIH
VIL
Fig. 4–17: Sync, control, and data inputs
Micronas
69
VPC 323xD, VPC 324xD
ADVANCE INFORMATION
4.6.4.12. Characteristics, Clock Output Specification
Line-Locked Clock Pins: LLC1, LLC2
Symbol
Parameter
CL
Load capacitance
Pin Name
Min.
Typ.
Max.
Unit
–
–
50
pF
Test Conditions
13.5 MHz Line Locked Clock
1/T13
LLC1 Clock Frequency
12.5
–
14.5
MHz
tWL13
LLC1 Clock Low Time
22
–
–
ns
CL = 30 pF
tWH13
LLC1 Clock High Time
25
–
–
ns
CL = 30 pF
1/T27
LLC2 Clock Frequency
25
–
29
MHz
tWL27
LLC2 Clock Low Time
5
–
–
ns
CL = 30 pF
tWH27
LLC2 Clock High Time
10
–
–
ns
CL = 30 pF
17.2
MHz
19.4
MHz
16 MHz Line Locked Clock
1/T13
LLC1 Clock Frequency
14.8
–
18 MHz Line Locked Clock
1/T13
LLC1 Clock Frequency
16.6
–
common timings – all modes
tSK
Clock Skew
0
–
4
ns
tR, tF
Clock Rise/Fall TimeClock
–
–
5
ns
LLC1=13.5MHz, CL = 30 pF
tR, tF
Clock Rise/Fall TimeClock
–
–
10
ns
LLC2=27.0MHz, CL = 30 pF
VIL
Input Low Voltage
–
–
0.8
V
VIH
Input High Voltage
2.0
–
–
V
VOL
Output Low Voltage
–
–
0.4
V
IL = 2 mA
VOH
Output High Voltage
2.4
–
–
V
IH = –2 mA
T13
tWH13
tWL13
VIH
LLC1
(13.5 MHz ±7%)
VIL
tF
tR
tSK
tSK
tWL27
tWH27
T27
VIH
LLC2
(27 MHz ±7%)
VIL
tR
tF
Fig. 4–18: Line-locked clock output pins
70
Micronas
VPC 323xD, VPC 324xD
ADVANCE INFORMATION
VPC 32xxD
5. Application Circuit
Micronas
71
VPC 323xD, VPC 324xD
ADVANCE INFORMATION
5.1. Application Note: VGA mode with VPC 3215C
In 100 Hz TV applications it can be desirable to display
a VGA-signal on the TV. In this case a VGA-graphic
card delivers the H, V and RGB signals. These signals
can be feed "directly" to the backend signal processing. The VPC can generate a stable line locked clock
for the 100 Hz system in relation to the VGA sync signals.
While the V-sync is connected to the VGAV pin directly,
the H-sync has to be pulse-shaped and amplitude
adjusted until it is connected to one of the video input
pins of the VPC. The recommended circuitry to filter
the H sync is given in the figure below.
+5V analog
100 Ω
47pF
1kΩ
680 nF
Video Input VPC
270 Ω
540 Ω
H 31kHz
BC848B
1N4148
2kΩ
1N4148
GND analog
GND analog
Fig. 5–1: Application circuit for horizontal VGA-input
72
Micronas
VPC 323xD, VPC 324xD
ADVANCE INFORMATION
5.2. Application Note: PIP Mode Programming
5.2.1. Procedure to Program a PIP Mode
For the VPCpip or VPCsingle:
For the VPCpip or VPCsingle:
12. write the register PIPOPER to start filling a inset
picture with live video.
1. set the scaler according to the PIP size to be used
(see Table 2–11).
2. write the registers VPCMODE and PIPMODE
according to the mode to be set.
3. in expert mode write the registers NLIN, NPIX and
NPFB.
4. write the registers COLBGD, COLFR1, COLFR2,
HSTR and VSTR, if a different value as the default
one is used.
5. write the registers LINOFFS and PIXOFFS, if a different value as the default one or more than 4 inset
pictures in the X or Y direction are used.
6. write the register PIPOPER to fill the frame and
background of an inset picture. This step is repeated
for all inset pictures in a multi PIP application.
For the VPCmain:
7. set the scaler to get a full size video
(see Table 2–11).
8. write the registers VPCMODE and PIPMODE
according to the mode to be set.
9. in expert mode write the registers NLIN, NPIX and
NPFB.
13. Only for tuner scanning: write the register
PIPOPER to stop filling a inset picture with live
video and changing the channel.
14. repeat steps 12 and 13 for all inset pictures in a
multi PIP application.
15. Only for VPCsingle: write the register PIPOPER to
start filling the main picture part outside the inset
picture(s) with live video.
For the VPCmain:
16. write the registers HSTR and VSTR, if the PIP
position should be changed.
17. write the register PIPOPER, to quit the PIP mode.
In an application with a single VPC, step 7 - 11 and
16 - 17 are dropped. Additionally, the free running
mode should be set in the cases shown in Table 2–12.
5.2.2. I2C Registers Programming for PIP Control
To program a PIP mode, the register VPCMODE, PIPMODE and PIPOPER should be written always, all
other registers are used only in the expert mode or if
the default values are modified (see Table 5–1).
10. write the registers COLBGD, HSTR and VSTR, if a
different value as the default one is used.
11. write the register PIPOPER to start displaying PIP.
Table 5–1: I2C register programing for PIP control
I2C register
update
VPCMODE, PIPMODE,
PIPOPER
should be written always
COLBGD, COLFR1,
COLFR2, HSTR, VSTR
should be written only, if the default values have to be modified
LINOFFS, PIXOFFS
VPCpip
VPCmain
VPCsingle
only used in expert
mode, when more than 4
inset pictures in the X or
Y direction are used.
not used.
only used if a different
value as the default one
or more than 4 inset pictures in the X or Y direction are used
NLIN, NPIX, NPFB
Micronas
should be written, only in the expert mode. (In the predefined modes the default
values are used.)
73
VPC 323xD, VPC 324xD
ADVANCE INFORMATION
Table 5–2: Limits of the I2C register settings for programming a PIP mode
I2C register
VPCmain
VPCpip and VPCsingle
NPFB
NPFB ≥ NPIXmain + X, (X=2 for TI and X=0 for rest field memories) and
NPFB x NLINmain ≤ total field memory size
NPIX
0 < NPIX ≤ NPFB - X and
0 < NPIX ≤ NPELfp
0 < NPIX ≤ NPELsp
NLIN
NPFB x NLIN ≤ total field memory size and 0
≤ NLIN < NROWfp
0 ≤ NLIN < NROWsp
HSTR
0 ≤ HSTR < NPELfp - NPIXmain
0 ≤ HSTR < NPELsp - NPIXPIP
VSTR
0 ≤ VSTR < NLINfp - NLINmain
0 ≤ VSTR < NLINsp - NLINPIP
PIXOFFS
not used
0 ≤ PIXOFFS < NPIXmain - (number of pixels
of inset pictures to the right of PIXOFFS)
LINOFFS
not used
0 ≤ LINOFFS < NLINmain - (number of lines of
inset pictures below LINOFFS)
Notes:
- NPIXmain and NLINmain: correspond to VPCmain
- NPIXPIP and NLINPIP: correspond to VPCsingle and VPCpip
- NROWfp and NPELfp: number of lines per field and number of pixels per line of a full picture
(e.g. NROWfp=288, NPELfp= 720 for PAL at 13.5 MHz)
- NROWsp and NPELsp: number of lines per field and number of pixels per line of a inset picture
The limits of the I2C register settings are given in Table
5–2. No range check and value limitation are carried
out in the field memory controller. An illegal setting of
these parameters leads to a error behavior of the PIP
function.
The PIP display is controlled by the commands written
into the register PIPOPER. For the VPCmain, the PIP
display is turned on or off by the commends DISSTART and DISSTOP. For the VPCpip and VPCsingle, 8
commands are available:
– WRFRCOL1, WRFRCOL2: to fill the frame of a
inset picture with the color COLFR1 or COLFR2,
– WRBGD, WRBGDNF: to fill a inset picture with the
background color COLBGD,
– WRPIC, WRPICNF, WRSTOP: to start and stop to
write a inset picture with the active video,
– WRMAIN: to start write the main picture part outside
the inset picture(s) with the active video (only for
VPCsingle).
While WRPIC, WRSTOP, WRFRCOL1, WRFRCOL2
and WRBGD control a display with a frame (see Fig.
5–2), WRPICNF and WRBGDNF control a display
without a frame (see Fig. 5–3). The number of the inset
picture addressed by the current commend is given by
bits NSPX and NSPY in the register PIPOPER.
maximal 4x4 inset pictures are used, no new setting of
these registers is needed. The default setting
LINOFFS=0 and PIXOFFS=0 takes effect. If more than
4x4 inset pictures are involved in a PIP application,
these inset pictures should be grouped, so that the
inset pictures in each group can be addressed by bits
NSPX and NSPY. For writing each group, the registers
LINOFFS and PIXOFFS should be set correctly (see
Fig.5–4).
(LINOFFS, PIXOFFS)
00
01
NSPX
10
11
00
01
NSPY
10
11
display window
Fig. 5–2: 4x4 inset pictures with frame
In the display window, the coordinate of the upper-left
corner of the inset picture with NSPX=0 and NSPY=0
is defined by the registers LINOFFS and PIXOFFS. If
74
Micronas
VPC 323xD, VPC 324xD
ADVANCE INFORMATION
5.2.3.2. Select a Strobe Effect in Expert Mode
(LINOFFS, PIXOFFS)
00
01
NSPX
10
11
P1
00
P2
01
P3
NSPY
10
P4
display window
Fig. 5–3: 4x4 inset pictures without frame
5.2.3. Examples
5.2.3.1. Select Predefined Mode 2
Scaler settings for VPCpip:
SCINC1 = h’600
FFLIM = h’168
NEWLIN = h’194
AVSTRT = h’86
AVSTOP = h’356
SC_PIP = h’11
SC_BRI = h’110
SC_CT = h’30
SC_MODE = h’00 (for S411=0)
PIP controller settings to start PIP display:
For the VPCpip:
VPCMODE = h’01
PIPMODE = h’02
PIPOPER = h’c0 (write the background)
wait until NEWCMD = 0
PIPOPER = h’a0 (write the frame)
wait until NEWCMD = 0
PIPOPER = h’80 (start writing PIP)
After that the PIP position can be changed via HSTR
and VSTR registers. e.g. HSTR = h’03
For the VPCmain:
VPCMODE = h’05
PIPMODE = h’02
PIPOPER = h’80 (start display PIP)
PIP controller settings to stop PIP display:
For the VPCmain:
PIPOPER = h’90 (stop display PIP)
Micronas
LINOFFS
P5
11
P6
Fig. 5–4: Example of the expert mode
Scaler settings for VPCpip:
SCINC1 = h’480
FFLIM = h’78
NEWLIN = h’194
AVSTRT = h’86
AVSTOP = h’356
SC_PIP = h’1f
SC_BRI = h’310
SC_CT = h’30
SC_MODE = h’00 (for S411=0)
PIP controller settings to show a strobe effect:
For the VPCpip:
VPCMODE = h’01
PIPMODE = h’0f
VSTR = h’202
HSTR = h’101
NPIX = h’1c
NLIN = h’2c
NPFB = h’132
PIPOPER = h’c0 (write the background of P1)
wait until NEWCMD = 0
PIPOPER = h’a0 (write the frame of P1)
wait until NEWCMD = 0
PIPOPER = h’80 (start writing PIP of P1)
wait until NEWCMD = 0
PIPOPER = h’c4 (write the background of P2)
wait until NEWCMD = 0
PIPOPER = h’a4 (write the frame of P2)
wait until NEWCMD = 0
PIPOPER = h’84 (start writing PIP of P2)
wait until NEWCMD = 0
PIPOPER = h’c8 (write the background of P3)
wait until NEWCMD = 0
PIPOPER = h’a8 (write the frame of P3)
wait until NEWCMD = 0
PIPOPER = h’88 (start writing PIP of P3)
75
VPC 323xD, VPC 324xD
ADVANCE INFORMATION
wait until NEWCMD = 0
PIPMODE = h’06
PIPOPER = h’cc (write the background of P4)
wait until NEWCMD = 0
PIPOPER = h’ac (write the frame of P4)
wait until NEWCMD = 0
PIPOPER = h’8c (start writing PIP of P4)
wait until NEWCMD = 0
PIPOPER = h’c0 (write the background of P1)
wait until NEWCMD = 0
PIPOPER = h’a0 (write the frame of P1)
wait until NEWCMD = 0
LINOFFS = h’2b8
PIPOPER = h’c0 (write the background of P5)
wait until NEWCMD = 0
PIPOPER = h’a0 (write the frame of P5)
wait until NEWCMD = 0
PIPOPER = h’80 (start writing PIP of P5)
wait until NEWCMD = 0
PIPOPER = h’c4 (write the background of P6)
wait until NEWCMD = 0
PIPOPER = h’a4 (write the frame of P6)
wait until NEWCMD = 0
PIPOPER = h’84 (start writing PIP of P6)
For the VPCmain:
VPCMODE = h’05
PIPMODE = h’0f
VSTR = h’201
HSTR = h’193
NPIX = h’1e
NLIN = h’116
NPFB = h’132
PIPOPER = h’80 (start display PIP)
PIP controller settings to stop PIP display:
For the VPCmain:
PIPOPER = h’90 (stop display PIP)
5.2.3.3. Select Predefined Mode 6 for Tuner Scanning
Scaler settings for VPCpip:
SCINC1 = h’600
FFLIM = h’168
NEWLIN = h’194
AVSTRT = h’86
AVSTOP = h’356
SC_PIP = h’11
SC_BRI = h’110
SC_CT = h’30
SC_MODE = h’00 (for S411=0)
PIPOPER = h’c1 (write the background of P2)
wait until NEWCMD = 0
PIPOPER = h’a1 (write the frame of P2)
wait until NEWCMD = 0
PIPOPER = h’c4 (write the background of P3)
wait until NEWCMD = 0
PIPOPER = h’a4 (write the frame of P3)
wait until NEWCMD = 0
PIPOPER = h’c5 (write the background of P4)
wait until NEWCMD = 0
PIPOPER = h’a5 (write the frame of P4)
wait until NEWCMD = 0
For the VPCmain:
VPCMODE = h’05
PIPMODE = h’46
PIPOPER = h’80 (start display multi PIP)
For the VPCpip:
tune a channel
PIPOPER = h’80 (start writing PIP of P1)
wait until NEWCMD = 0
PIPOPER = h’90 (stop writing PIP of P1)
wait until NEWCMD = 0
tune an other channel
PIPOPER = h’81 (start writing PIP of P2)
wait until NEWCMD = 0
PIPOPER = h’91 (stop writing PIP of P2)
wait until NEWCMD = 0
tune an other channel
PIPOPER = h’84 (start writing PIP of P3)
wait until NEWCMD = 0
PIPOPER = h’94 (stop writing PIP of P3)
wait until NEWCMD = 0
tune an other channel
PIPOPER = h’85 (start writing PIP of P4)
wait until NEWCMD = 0
PIPOPER = h’95 (stop writing PIP of P4)
wait until NEWCMD = 0
The tuning and writing of the four inset pictures are
repeated.
PIP controller settings to stop tuner scanning:
PIP controller settings for tuner scanning:
For the VPCmain:
PIPOPER = h’90 (stop display PIP)
For the VPCpip:
VPCMODE = h’01
76
Micronas
ADVANCE INFORMATION
Micronas
VPC 323xD, VPC 324xD
77
VPC 323xD, VPC 324xD
ADVANCE INFORMATION
6. Data Sheet History
1. Advance Information: “VPC 323xD, VPC 324xD
Comb Filter Video Processor, Jan. 19, 1999,
6251-472-1AI. First release of the advance information.
Micronas GmbH
Hans-Bunte-Strasse 19
D-79108 Freiburg (Germany)
P.O. Box 840
D-79008 Freiburg (Germany)
Tel. +49-761-517-0
Fax +49-761-517-2174
E-mail: [email protected]
Internet: www.micronas.com
Printed in Germany
Order No. 6251-472-1AI
78
All information and data contained in this data sheet are without any
commitment, are not to be considered as an offer for conclusion of a
contract, nor shall they be construed as to create any liability. Any new
issue of this data sheet invalidates previous issues. Product availability
and delivery are exclusively subject to our respective order confirmation
form; the same applies to orders based on development samples delivered. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may
result from its use.
Further, Micronas GmbH reserves the right to revise this publication and
to make changes to its content, at any time, without obligation to notify
any person or entity of such revisions or changes.
No part of this publication may be reproduced, photocopied, stored on a
retrieval system, or transmitted without the express written consent of
Micronas GmbH.
Micronas