CXD2436Q Timing Generator for LCD Panels For the availability of this product, please contact the sales office. Description The CXD2436Q is a timing signal generator for the VGA LCD panel LCX012 driver. This chip has a built-in serial interface circuit which allows the mode to be switched with respect to various VGA signals through direct control from an external microcomputer, etc. Features • Generates the LCX012 drive pulse. • Supports three-panel projectors. • Built-in serial interface circuit • Supports various VGA signals. (non-interlaced mode) • • • • • Built-in 2-line pair drive circuits Supports NTSC and PAL systems. Supports up/down and/or right/left inversion. Supports line inversion and field inversion. Generates timing signal of external sample-andhold circuit. Applications LCD projectors, etc. 100 pin QFP (Plastic) Absolute Maximum Ratings (Ta=25 °C) • Supply voltage VDD VSS–0.5 to +7.0 • Input voltage VI VSS–0.5 to VDD+0.5 • Output voltage VO VSS–0.5 to VDD+0.5 • Operating temperature Topr –20 to +75 • Storage temperature Tstg –55 to +150 Recommended Operating Conditions • Supply voltage VDD +4.5 to +5.5 • Supply voltage VCC –20 to +75 V V V °C °C V °C Structure Silicon gate CMOS IC Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. —1— E95810-TE CXD2436Q Block Diagram EXT-CKI 30 CKI 34 22 NC 90 VSS 79 VSS 65 VSS 54 VSS 52 VSS 51 VSS 49 VSS 48 VSS 47 VSS 46 VSS 45 VSS 42 VSS 40 VSS 29 VSS 15 VSS 4 VSS 78 VDD 53 VDD 28 VDD VDD 3 DIRECT CLEAR 32 PWM 31 PEO 8 XCLR 9 PLNT MASTER CLOCK 10 CKO 18 33 36 HPOL 6 VPOL 7 CSYNC 5 HD2IN VD2IN 16 38 RPD FPD 39 TC 68 HDN XHDN HDO XHDO 35 PLL PHASE COMPARATOR H-SYNC DETECTOR H-SKEW DETECTOR 17 PLL COUNTER HD1IN 1 VD1IN 2 69 73 TST1 TST2 TST3 TST4 TST5 TST6 TST7 TST8 TST9 TST10 14 VCK VST1 VDO 92 59 93 60 72 61 SLDWN SLMNB 11 74 20 21 23 24 25 41 V-SYNC SEPARATOR 43 V-RESET PULSE GENERATOR 44 26 SERIAL INTERFACE 27 37 55 56 V-RESET PULSE GENERATOR 57 50 58 V-POSITION COUNTER H-POSITION COUNTER 62 63 19 64 66 DWN PRG XCLP1 XCLP2 HST HCK1 HCK2 CLR ENB INT PCG SH1 SH2 SH3 SH4 SH5 SH6 SH7 VGAV SLSY SLCKI 71 75 V-TIMING PULSE H-TIMING PULSE GENERATOR GENERATOR 67 SCK SI CS PO0 PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 & 76 77 PULSE ELIMINATOR 84 12 85 82 86 83 SLRGT RGT XRGT 87 88 89 91 94 95 FIELD & LINE CONTROLLER AUX-VD COUNTER 96 97 80 98 81 99 70 100 13 —2— FRP XFRP FLD SLFR CXD2436Q Pin Description Pin No. 1 2 3 4 5 Symbol HD1IN VD1IN VDD VSS CSYNC I/O Description I I — — I Hsync input (VGA) Vsync input (VGA) Power supply GND Composite sync input (NTSC/PAL) HD, CSYNC polarity identification input (High: positive polarity, Low: negative polarity) VD, CSYNC polarity identification input (High: positive polarity, Low: negative polarity) External clear (all clear when Low) PAL/NTSC switching (High: NTSC, Low: PAL) VGA (NTSC/PAL) switching (High: VGA, Low: NTSC/PAL) Up/down inversion discrimination signal input (High: Down, Low: Up) Right/left inversion discrimination signal input (High: Normal, Low: Reverse) 1H/1F inversion switching (High: 1H, Low: 1F) Test pin (Not connected or High.) GND HD2 input (for NTSC/PAL separate-sync) VD2 input (for NTSC/PAL separate-sync) SYNC input switching (High: CSYNC, Low: HD2IN and VD2IN) Switches mode (High: Nothing, Low: 400 480 line conversion) Test pin (Not connected or High.) Test pin (Connect to GND.) N.C. Test pin (Not connected or High.) Test pin (Not connected or High.) Test pin (Not connected or High.) Test pin (Not connected.) Test pin (Connect to GND.) Power supply GND External clock input Loop filter integrator output Loop filter integrator input Oscillation cell output (NTSC/PAL) Oscillation cell input (NTSC/PAL) Phase comparator output (NTSC/PAL) Clock input selection (High: CKI, Low: EXT-CKI) (NTSC/PAL mode only) Test pin (Not connected or High.) Phase comparator output (NTSC/PAL) 6 HPOL I 7 VPOL I 8 9 10 XCLR PLNT VGAV I I I 11 SLDWN I 12 SLRGT I 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 SLFR TST1 VSS HD2IN VD2IN SLSY SLMNB TST2 TST3 N.C. TST4 TST5 TST6 TST7 TST8 VDD I I — I I I I I I — — — — — — — — I I/O I I/O I O 36 SLCKI I 37 38 TST9 FPD I O VSS EXT-CKI PEO PWM CKO CKI RPD —3— Input pin for open status — — — — — H H H H H H H H H — — — H H H H — — — — — — — — — — — — — — H H — CXD2436Q Pin No. 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 Symbol TC VSS SCK VSS SI CS VSS VSS VSS VSS VSS TST10 VSS VSS VDD VSS PO0 PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 VSS PO10 PO11 HDN XHDN FLD DWM VDO HDO XHDO PRG XCLP1 XCLP2 VDD VSS FRP XFRP RGT I/O I/O — I — I I — — — — — I — — — — O O O O O O O O O O — O O O O O O O O O O O O — — O O O Description FPD pin pulse width adjustment GND Serial interface clock input GND Serial interface data input Serial interface chip select GND GND GND GND GND Test pin (Not connected or High.) GND GND Power supply GND Serial I/O data output Serial I/O data output Serial I/O data output Serial I/O data output Serial I/O data output Serial I/O data output Serial I/O data output Serial I/O data output Serial I/O data output Serial I/O data output GND Serial I/O data output Serial I/O data output Phase comparator output (positive polarity) Phase comparator output (negative polarity) Field discrimination signal output Up/down inversion discrimination signal output VD pulse output (positive polarity) HD pulse output (positive polarity) HD pulse output (negative polarity) Precharge signal pulse (positive polarity) Pedestal clamp pulse 1 Pedestal clamp pulse 2 Power supply GND AC drive inversion timing output AC drive inversion timing output Right/left inversion discrimination signal output —4— Input pin for open status — — H — L H — — — — — H — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — CXD2436Q Pin No. 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Symbol XRGT HST HCK1 HCK2 CLR ENB INT VSS PCG VCK VST1 SH1 SH2 SH3 SH4 SH5 SH6 SH7 I/O O O O O O O O O O O O O O O O O O O Electrical Characteristics 1. DC characteristics Item Symbol Supply voltage VDD VIH1 Input voltage 1 VIL1 VIH2 Input voltage 2 VIL2 VT+ –VT+ VOH Output voltage 1 VOL VOH Output voltage 2 VOL VOH Output voltage 3 VOL VOH Output voltage 4 VOL Input leak IIL current IIH Output leak ILZ current Current IDD consumption Input pin for open status — — — — — — — — — — — — — — — — — — Description Right/left inversion discrimination signal output H start pulse output (positive polarity) H clock pulse 1 output H clock pulse 2 output CLR pin output ENB pin output INT pin output GND PCG pin output (positive polarity) V clock pulse output V start pulse output Sample-and-hold pulse 1 (positive polarity) Sample-and-hold pulse 2 (positive polarity) Sample-and-hold pulse 3 (positive polarity) Sample-and-hold pulse 4 (positive polarity) Sample-and-hold pulse 5 (positive polarity) Sample-and-hold pulse 6 (positive polarity) Sample-and-hold pulse 7 (positive polarity) Conditions CMOS input cell CMOS Schmitt trigger input cell IOH=–2 mA IOL=4 mA IOH=–4 mA IOL=8 mA IOH=–6 mA IOL=12 mA IOH=–3 mA IOL=3 mA Pull-up resistor connected Pull-down resistor connected High impedance status fclk=31 MHz VDD=5.0 V Min. 4.5 0.7 VDD Typ. 5.0 0.8 VDD 0.6 VDD–0.8 (Temperature = 25 °C, VSS = 0 V) Max. Unit Applicable pins 5.5 V Input pins other than V 0.3 VDD those noted below HDnIN, VDnIN, CSYNC, 0.2 VDD V CKI, PWM, TC, PEO, CKO, SI, SCK, CS Output pins other than V 0.4 those noted below VDD–0.8 0.4 VDD–0.8 0.4 VDD/2 VDD/2 –40 –100 –240 40 100 240 –40 40 55 V VCK V HCKn, SHn, HST V CKO, PEO µA ∗1 SI µA RPD, FPD mA At no load ∗1 Input pins with pull-up resistors HPOL, VPOL, XCLR, PLNT, VGAV, SLDWN, SLRGT, SLFR, TST1, SLSY, TST2, TST3, SLCKI, TST9, SCK, CS —5— CXD2436Q 2. AC characteristics (VDD=5.0 V±0.5 V, VSS=0 V) Item Applicable pins Clock input cycle Cross-point time difference Output rise delay Output fall delay Output rise delay Output fall delay HCK1, SH1 delay time difference HCK2, SH1 delay time difference HCK1 duty HCK2 duty EXT-CKI, CKI HCK1, 2 HCKn, SHn HCKn, SHn Other than HCKn and SHn Other than HCKn and SHn Symbol Conditions Min. Typ. 25 –10 Max. Unit 10 20 20 ns ns ns ns ∆t tpr tpf CL=30 pF CL=30 pF CL=30 pF tpr CL=30 pF 30 ns tpf CL=30 pF 30 ns HCK1, SH1 dt1 CL=30 pF 10 ns HCK2, SH1 dt2 CL=30 pF 10 ns HCK1 HCK2 tH/tH+tL tH/tH+tL CL=30 pF CL=30 pF 52 52 % % 48 48 50 50 VDD EXT-CKI/CKI 0V VDD 90% Output 0V tpr VDD Output 10% 0V tpf VDD HCK1 50% 50% 0V VDD HCK2 50% 50% 0V ∆t ∆t —6— CXD2436Q EXT-CKI /CKI HCK1 50% 50% 50% HCK2 t2 t1 tH SH1 tL 50% 50% dt1 dt2 (SLRGT=H, SHP0/SHP1/SHP2/SHP3=L) 3. Serial interface block AC characteristics SCK SI (DATA) CS tw1 50% tw1 ts1 50% 50% th1 ts0 50% 50% 50% 50% 50% th0 (VDD=5.0 V±0.5 V, VSS=0 V, Topr=–20 to +75 °C Symbol Item Min. ts1 th1 tw1 ts0 th0 th1 SI setup time with respect to rise of SCK SI hold time with respect to rise of SCK SCK pulse width CS setup time with respect to rise of SCK CS hold time with respect to rise of SCK SCK high-level hold time with respect to rise of CS 200 ns 200 ns 200 ns 200 ns 200 ns 200 ns —7— Max. 2tw1 2tw1 th1 CXD2436Q LCD Panel Structure The structure of LCD panels (LCX012AL) driven by this IC is shown below. The dot arrangement is a square arrangement, and the shaded region within the diagram is not displayed. Gate SW1 VSR3 VSR4 VSR5 Sig6 Sig5 Sig4 Sig3 Sig2 Sig1 Sig6 Sig5 Sig4 Sig3 Sig2 Sig1 Sig6 Sig5 Sig4 Sig3 Sig2 AAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA Photo-shielding area Display area VSR 484 VSR 485 VSR 486 VSR 487 VSR 488 1 VSR 483 486 484 VSR6 Gate SW109 1 VSR2 Sig1 VSR1 Gate SW2 5 644 5 654 • The effective pixels are horizontal: 644 pixels and vertical: 484 pixels. • The horizontal pixel start position is from Sig6 of the first-stage scanner. (Sig1 to Sig5 of the first-stage scanner are the photo-shielding area and are not displayed.) • The vertical pixel start position is from the third-stage scanner. • These relationships are the same even during up/down and/or right/left inversion. (The entire area within the panel is inverted.) —8— CXD2436Q Description of Operation • Sync input pins The CXD2436Q has three types of sync input pins. Pin No. 1 2 5 16 17 Symbol HD1IN VD1IN CSYNC HD2IN VD2IN SLSY setting Application — SYNC input pins for VGA H CSYNC input pin for NTSC/PAL L Separate SYNC input pins for NTSC/PAL • Clock input pins The CXD2436Q has two clock input pin systems to support two types of PLL circuits. 1) When using EXT-CKI (using an external PLL IC) The 1/N frequency divider output is output from the HDN and XHDN pins for the external PLL IC. The used pins are shown in the following table. (SLCKI = Low) Pin No. Symbol Application 30 EXT-CKI 68 HDN Clock input Phase comparison output (positive polarity) Phase comparison output (negative polarity) 69 XHDN HSYNC HDN OUTPUT 400 clk 2) When using CKI This system uses the built-in phase comparator and an externally attached VCO circuit (see the Application Circuit). This system is used during AV mode (NTSC/PAL). The used pins are shown in the following table. (Effective when SLCKI is set to High.) Pin No. 31 32 33 34 35 38 39 Symbol PEO PWM CKO CKI RPD FPD TC Application Loop filter integrator output Loop filter integrator input Clock output (oscillation cell output) Clock input (oscillation cell input) Phase comparator output Phase comparator output FPD pin pulse width adjustment HSYNC An outline of the output waveforms during PLL lock is shown in the figure to the left. RPD FPD —9— CXD2436Q • Connections supporting up/down and/or right/left inversion The CXD2436Q is designed for use with three-panel projectors, and has a system configuration which permits both normal and reverse scan. The RGT and XRGT output to the panel are switched according to the SLRGT input, and the DWN output is switched according to the SLDWN input in the same manner. LCX012 RGT Normal scanning panel DWN SLRGT 12 82 83 RGT LCX012 XRGT RGT panel SLDWN 11 71 Normal scanning DWN DWN LCX012 RGT DWN Example of supporting a three-panel system Reverse scanning panel • AC driving of LCD panels for no signal The following measures have been adopted to allow AC driving of LCD panels even when there is no signal. • Horizontal direction pulse: The PLL is set to free running status. Therefore, the frequency of the horizontal direction pulse is dependent on the PLL free running frequency. • Vertical direction pulse: The number of lines is counted by an internal counter and VST and FRP are output at a specified cycle. • VST cycle for no signal • Free running detection timing NTSC PAL VGA 269H 321H 526H NTSC PAL VGA 291H 339H 873H Free running operates at the following cycles. (No signal is judged if there is no VSYNC input for longer than the following periods.) • Description of the MODE selector switch • VGA/AV (NTSC/PAL) switching is performed with two pins. VGAV H H L L PLNT H L H L MODE VGA VGA NTSC PAL • The HD1IN, HD2IN, VD1IN, VD2IN and CSYNC input polarities are supported by two pins. HPOL VPOL H H L L H L H L HD1IN HD2IN Positive polarity Positive polarity Negative polarity Negative polarity VD1IN VD2IN Positive polarity Negative polarity Positive polarity Negative polarity —10— CSYNC Positive polarity — — Negative polarity CXD2436Q • XCLR (External clear) Reset should be performed during startup in order to initialize the serial interface. Performing external clear sets all serial interface modes to Low. • Serial interface specifications The CXD2436Q can set and switch the driving mode with the serial interface. Set the corresponding timing data for each VGA signal according to the format in the diagram below. Be sure to make the initial mode settings. (See the AC characteristics for detailed timing specifications.) CS SCK SI D0 D1 D2 D3 D4 D5 D6 D7 Fig. 1. Timing chart for the serial interface input block Note) D0 to D7 internal transfer is completed by the CS signal switching from a Low to High pulse. Therefore, the data should be transferred in 1-byte units with the CS signal reset each time. • Description of mode switching settings using the serial interface The CXD2436Q can set the following six modes. (1) Frequency division ratio setting for the 1/N frequency divider of the master clock PLL circuit block. (2) H screen center adjustment. The center changes by one dot with LSB. (3) V screen center adjustment. The center changes by one line with LSB. (4) Sample-and-hold circuit phase adjustment. The phase changes by a half-dot with LSB. (See the Description of Sample-and-Hold Timing for details.) (5) Clamp pulse timing adjustment (4-way) (6) Data output (Serial data is held and output.) Upper 4-bit address value D7 to D4 0H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH Lower 4-bit data D3 PHP3 PHP7 — HP3 — VP3 — SHP3 — PO3 PO7 PO11 D2 PHP2 PHP6 PHP10 HP2 HP6 VP2 VP6 SHP2 — PO2 PO6 PO10 D1 PHP1 PHP5 PHP9 HP1 HP5 VP1 VP5 SHP1 CLPP1 PO1 PO5 PO9 Functions D0 PHP0 PHP4 PHP8 HP0 HP4 VP0 VP4 SHP0 CLPP0 PO0 PO4 PO8 —11— PLL 1/N frequency divisions H screen center adjustment V screen center adjustment S/H timing Clamp timing Data output ∗ PHP0, HP0, VP0, SHP0, CLPP0 CXD2436Q • PLL 1/N frequency division ratio setting For the frequency division ratio setting during VGA mode, set the value of the number of dots for the horizontal period –1 in PHP0-10. (Example) When the horizontal period is set to 800 dots PHP setting value = 800-1 799 (01100011111 LSB) PHP 10 0 9 1 8 1 7 0 6 0 5 0 4 1 3 1 2 1 1 1 0 1 Set the value of the number of dots fixed to 816 during NTSC/PAL. PHP setting value = 816-1 815 (01100101111 LSB) PHP 10 0 9 1 8 1 7 0 6 0 5 1 4 0 3 1 2 1 1 1 0 1 • Horizontal position setting The horizontal display start position setting can be changed one dot at a time by the HP0 to 6 setting. HSYNC Thp 644dots Image display period The maximum and minimum Thp values which can be set are shown in the following table. HP Minimum value Maximum value 6 1 0 5 1 0 4 1 0 3 1 0 2 1 0 1 1 0 0 1 0 VGA 110 dots 237 dots NTSC 5.8 µs 15.7 µs PAL 5.8 µs 15.8 µs • Vertical position setting The vertical display start position setting can be changed one dot at a time by the VP0 to 6 setting. VSYNC HSYNC 484 line Tvp Image display period The maximum and minimum Tvp values which can be set are shown in the following table. VP Minimum value Maximum value 6 1 0 5 1 0 4 1 0 3 1 0 2 1 0 1 1 0 0 1 0 (This table shows the ODD field values for NTSC and PAL.) —12— VGA 5H 133 H NTSC 14 H 141 H PAL 14 H 141 H CXD2436Q • CLP pulse position setting The XCLP pulse position can be changed to four different positions. Each of these positions is shown below. The XCLP pulse is linked with the horizontal position setting, and is indicated with the HP (1000000 LSB) setting. HSYNC Wclp1 XCLP1 tclp1 XCLP2 The centers of the XCLP1 tclp2 and XCLP2 pulses match. Wclp2 • VGA mode CLPP1 CLPP0 0 0 0 1 1 0 1 1 tclp1 74 dot 81 dot 88 dot 95 dot Wclp1 40 dot 40 dot 40 dot 40 dot tclp2 61 dot 68 dot 75 dot 82 dot Wclp2 67 dot 67 dot 67 dot 67 dot CLPP1 CLPP0 tclp1 Wclp1 0 0 4.83 µs 1.17 µs 0 1 5.30 µs 1.17 µs 1 0 5.76 µs 1.17 µs 1 1 6.23 µs 1.17 µs tclp2 4.36 µs 4.83 µs 5.30 µs 5.76 µs Wclp2 2.18 µs 2.18 µs 2.18 µs 2.18 µs tclp2 4.39 µs 4.86 µs 5.33 µs 5.80 µs Wclp2 2.20 µs 2.20 µs 2.20 µs 2.20 µs • NTSC mode • PAL mode CLPP1 CLPP0 tclp1 Wclp1 0 0 4.87 µs 1.18 µs 0 1 5.33 µs 1.18 µs 1 0 5.80 µs 1.18 µs 1 1 6.27 µs 1.18 µs —13— CXD2436Q • Switching the SH pulse timing The phase relationship between the sample-and-hold pulses and HCK can be switched in 12 different ways with SHP0, SHP1, SHP2 and SHP3. (This timing generator has a 0.5 DOT OFFSET function in order to ensure the phase margin.) In addition, the timing differs according to the scanning direction (right/left scan). Right scanning pulse (RGT = H) HCK SH1 SH2 SH3 SH4 SH5 SH6 SH7 SHP0=L SHP0=H SHP0=L SHP0=H SHP1=L SHP1=L SHP1=H SHP1=H SHP2=L SHP2=L SHP2=L SHP2=L SHP3=L SHP3=L SHP3=L SHP3=L HCK SH1 SH2 SH3 SH4 SH5 SH6 SH7 SHP0=L SHP0=H SHP0=L SHP0=H SHP1=L SHP1=L SHP1=H SHP1=H SHP2=H SHP2=H SHP2=H SHP2=H SHP3=L SHP3=L SHP3=L SHP3=L —14— CXD2436Q HCK SH1 SH2 SH3 SH4 SH5 SH6 SH7 SHP0=L SHP0=H SHP0H=L SHP0=H SHP1=L SHP1=L SHP1=H SHP1=H SHP2=L SHP2=L SHP2=L SHP2=L SHP3=H SHP3=H SHP3=H SHP3=H Left scanning pulse (RGT = L) HCK SH1 SH2 SH3 SH4 SH5 SH6 SH7 SHP0=L SHP0=H SHP0=L SHP0=H SHP1=L SHP1=L SHP1=H SHP1=H SHP2=L SHP2=L SHP2=L SHP2=L SHP3=L SHP3=L SHP3=L SHP3=L —15— CXD2436Q HCK SH1 SH2 SH3 SH4 SH5 SH6 SH7 SHP0=L SHP0=H SHP0=L SHP0=H SHP1=L SHP1=L SHP1=H SHP1=H SHP2=H SHP2=H SHP2=H SHP2=H SHP3=L SHP3=L SHP3=L SHP3=L SHP0=L SHP0=H SHP0=L SHP0=H SHP1=L SHP1=L SHP1=H SHP1=H SHP2=L SHP2=L SHP2=L SHP2=L SHP3=H SHP3=H SHP3=H SHP3=H HCK SH1 SH2 SH3 SH4 SH5 SH6 SH7 —16— —17— INT VST1 FRP PCG PRG VCK ENB CLR SH7 SH6 SH5 SH4 SH3 SH2 SH1 HCK2 HCK1 HST XCLP2 XCLP1 HDO MCK CSYNC /HD1IN (BLK) 770 780 790 0 10 55fh 30 15fh 42fh 20 40 60 1fh 76fh 36fh 50 100fh Horizontal Direction Timing Chart (IBM-VGA 640 x 480) SLRGT: H (Normal scan) HP: 1100001 LSB CLPP: 10 LSB SHP: 0000 LSB 70 76fh 67fh 40fh 90 30fh 40fh 24fh 80 100 34fh 110 120 130 140 150 160 170 180 189 CXD2436Q —18— INT VST1 FRP PCG PRG VCK ENB CLR SH7 SH6 SH5 SH4 SH3 SH2 SH1 HCK2 HCK1 HST XCLP2 XCLP1 HDO CSYNC /HD1IN (BLK) MCK 770 780 790 0 10 55fh 30 15fh 42fh 20 40 60 1fh 76fh 36fh 50 100fh Horizontal Direction Timing Chart (IBM-VGA 640 x 480) SLRGT: L (Reverse scan) HP: 1100001 LSB CLPP: 10 LSB SHP: 0000 LSB 70 76fh 67fh 40fh 90 30fh 40fh 24fh 80 100 34fh 110 120 130 140 150 160 170 180 189 CXD2436Q 460 —19— (Internal reset) VRST VDO (1F inversed) FRP CLR ENB INT HST (1H inversed) FRP VCK VST1 (BLK) HDO HD1IN VD1IN 470 480 Vertical Direction Timing Chart (IBM-VGA 640 x 480) SLDWN: H (Down scan) VP: 1100100 LSB 1 10 20 30 40 46 CXD2436Q 462 —20— (Internal reset) VRST VDO (1F inversed) FRP CLR ENB INT HST (1H inversed) FRP VCK VST1 (BLK) HDO HD1IN VD1IN 470 480 Vertical Direction Timing Chart (IBM-VGA 640 x 480) SLDWN: L (Up scan) VP: 1100100 LSB 1 10 20 30 40 46 CXD2436Q —21— INT VST1 FRP PCG PRG VCK ENB CLR SH7 SH6 SH5 SH4 SH3 SH2 SH1 HCK2 HCK1 HST XCLP2 XCLP1 HDO (BLK) CSYNC /HD2IN MCK 776 786 806 0 1.32 µs (17fh) 796 10 30 4.75 µs (61fh) 20 Horizontal Direction Timing Chart (NTSC) RGT: H (Normal scan) HP: 1000000 LSB CLPP: 10 LSB SHP: 0000 LSB 40 60 0.55µs (7fh) 0.55 µs (7fh) 1.01 µs (13fh) 50 80 100 4.98 µs (64fh) 90 2.03 µs (26fh) 1.48 µs (19fh) 3.04 µs (39fh) 3.51 µs (45fh) 2.18 µs (28fh) 1.17 µs (15fh) 70 130 0.78 µs (10fh) 1.01 µs (13fh) 140 1.48 µs (19fh) 0.47 µs (6fh) 120 1.01 µs (13fh) 110 150 160 170 180 MCK: 12.84 MHz (77.89 ns) Loop Counter: 816 fh CXD2436Q 776 —22— INT VST1 FRP PCG PRG VCK ENB CLR SH7 SH6 SH5 SH4 SH3 SH2 SH1 HCK2 HCK1 HST XCLP2 XCLP1 HDO (BLK) CSYNC /HD2IN MCK 786 796 0 1.32µs (17fh) 806 10 30 4.75µs (61fh) 20 Horizontal Direction Timing Chart (NTSC) RGT: L (Reverse scan) HP: 1000000 LSB CLPP: 10 LSB SHP: 0000 LSB 40 60 0.55µs (7fh) 0.55µs (7fh) 1.01µs (7fh) 50 90 110 2.03µs (26fh) 130 0.78µs (10fh) 1.01µs (13fh) 140 1.48µs (19fh) 0.47µs (6fh) 120 1.01µs (13fh) 4.98 µs (64fh) 100 3.04µs (39fh) 3.51µs (45fh) 2.18µs (28fh) 1.17µs (15fh) 80 1.48µs (19fh) 70 150 160 170 180 MCK: 12.84 MHz (77.89 ns) Loop Counter: 816 fh CXD2436Q 214 —23— (Internal reset) VRST VDO FLD (1F inversed) FRP CLR ENB INT HST (1H inversed) FRP VCK VST1 (BLK) CSYNC VD2IN HD2IN 220 230 240 243 Vertical Direction Timing Chart (NTSC, odd field) SLDWN: H (Down scan) VP: 1111010 LSB 1 10 20 30 40 50 60 CXD2436Q 213 —24— (Internal reset) VRST VDO FLD (1F inversed) FRP CLR ENB INT HST (1H inversed) FRP VCK VST1 (BLK) CSYNC VD2IN HD2IN 220 230 240 243 Vertical Direction Timing Chart (NTSC, even field) SLDWN: H (Down scan) VP: 1111010 LSB 1 10 20 30 40 50 60 CXD2436Q 214 —25— (Internal reset) VRST VDO FLD (1F inversed) FRP CLR ENB INT HST (1H inversed) FRP VCK VST1 (BLK) CSYNC VD2IN HD2IN 220 230 240 243 Vertical Direction Timing Chart (NTSC, odd field) SLDWN: L (Up scan) VP: 1111010 LSB 1 10 20 30 40 50 60 CXD2436Q 214 —26— (Internal reset) VRST VDO FLD (1F inversed) FRP CLR ENB INT HST (1H inversed) FRP VCK VST1 (BLK) CSYNC VD2IN HD2IN 220 230 240 243 Vertical Direction Timing Chart (NTSC, even field) SLDWN: L (Up scan) VP: 1111010 LSB 1 10 20 30 40 50 60 CXD2436Q —27— INT VST1 FRP PCG PRG VCK ENB CLR SH7 SH6 SH5 SH4 SH3 SH2 SH1 HCK2 HCK1 HST XCLP2 XCLP1 HDO (BLK) 776 MCK CSYNC /HD2IN 786 806 0 1.49 µs (19fh) 796 10 30 60 1.02 µs (13fh) 50 0.55 µs (7fh) 0.55 µs (7fh) 40 70 90 110 140 0.78 µs (10fh) 1.02 µs (13fh) 150 160 170 180 MCK: 12.75 MHz (78.43 ns) Loop Counter: 816 fh 1.49 µs (19fh) 0.47 µs (6fh) 130 2.04 µs (26fh) 120 1.02 µs (13fh) 5.73 µs (73fh) 100 3.06 µs (39fh) 3.53 µs (45fh) 2.20 µs (28fh) 1.18 µs (15fh) 80 1.49 µs (19fh) VCK inversion timing for the decimation cycle 4.78 µs (61fh) 20 Horizontal Direction Timing Chart (PAL) SLRGT: H (Normal scan) HP: 1000000 LSB CLPP: 10 LSB SHP: 0000 LSB CXD2436Q —28— 806 0 30 4.78 µs (61fh) 20 60 1.02 µs (13fh) 50 0.55 µs (7fh) 0.55 µs (7fh) 40 70 3.06 µs (39fh) 3.53 µs (45fh) 2.20 µs (28fh) 110 130 1.49µs (26fh) 1.02µs (13fh) 0.78µs (10fh) VST1 INT 140 150 160 170 180 MCK: 12.75 MHz (78.43 ns) Loop Counter: 816fh 2.04 µs (19fh) 0.47 µs (6fh) 120 1.02µs (13fh) 5.73 µs (73fh) 100 FRP PCG 90 1.18 µs (15fh) 80 VCK inversion timing for the decimation cycle 10 PRG 1.49 µs (19fh) 796 1.49 µs (19fh) 786 VCK ENB CLR SH7 SH6 SH5 SH4 SH3 SH2 SH1 HCK2 HCK1 HST XCLP2 XCLP1 HDO (BLK) 776 MCK SYNC /HD2IN Horizontal Direction Timing Chart (PAL) SLRGT: L (Reverse scan) HP: 1000000 LSB CLPP: 10 LSB SHP: 0000 LSB CXD2436Q 258260 —29— (Internal reset) VRST VDO FLD (1F inversed) FRP CLR ENB INT HST (1H inversed) FRP VCK VST1 (BLK) CSYNC VD2IN HD2IN 270 280 288 Vertical Direction Timing Chart (PAL, odd field) SLDWN: H (Down scan) VP: 1110010 LSB 1 10 20 30 40 50 55 CXD2436Q 259 —30— (Internal reset) VRST VDO FLD (1F inversed) FRP CLR ENB INT HST (1H inversed) FRP VCK VST1 (BLK) CSYNC VD2IN HD2IN 270 280 288 Vertical Direction Timing Chart (PAL, even field) SLDWN: H (Down scan) VP: 1110010 LSB 1 10 20 30 40 50 55 CXD2436Q 258 —31— (Internal reset) VRST VDO FLD (1F inversed) FRP CLR ENB INT HST (1H inversed) FRP VCK VST1 (BLK) CSYNC VD2IN HD2IN 270 280 288 Vertical Direction Timing Chart (PAL, odd field) SLDWN: L (Up scan) VP: 1110010 LSB 1 10 20 30 40 50 CXD2436Q 259 —32— (Internal reset) VRST VDO FLD (1F inversed) FRP CLR ENB INT HST (1H inversed) FRP VCK VST1 (BLK) CSYNC VD2IN HD2IN 270 280 280 Vertical Direction Timing Chart (PAL, even field) SLDWN: L (Up scan) VP: 1110010 LSB 1 10 20 30 40 50 55 CXD2436Q —33— VD2 IN HD2 IN CSYNC VD1 IN HD1 IN to the RGB driver 75 PRG 76 XCLP1 77 XCLP2 78 VDD 79 VSS 80 FRP VPOL VD1IN HD1IN 68 69 CXD2436QA 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 VSS 49 TST10 50 VSS 48 PLNT 83 XRGT 82 RGT 70 71 72 73 74 XHDO VDD 81 XFRP 99 SH6 47µ/16V 1 GND +5V 100 SH7 6 HPOL VPOL NEGA 5 NEGA 4 POSI 3 POSI 2 7 8 13 PLNT 14 VGAV AV 12 PAL 11 VGA 10 NT 9 15 17 18 SLDWN UP DOWN 16 19 21 22 SLRGT REV NOR 20 23 24 IN 27 28 CLK PLL IC FB IN 26 29 30 47µ /16V SLFR 1F 1H SLSY HVD CSYNC ∗1. PLL IC • Fall lock type • VCO variable range: 20 to 35MHz 25 PEO 31 PWM 32 CKO 33 CKI 34 98 SH5 97 SH4 95 SH2 RP D 35 TST 9 37 SL CKI 36 94 SH1 96 SH3 FP D 38 93 VST1 TC 39 VSS 40 91 PCG 92 VCK SCK 41 90 VSS 3.3µ /25V 10k GND SLCKI EXT-CKI CKI GND 0.1µ 1k 3300p SCK SI SI 43 VSS 42 89 INT CS 44 87 CLR TST1 88 ENB CS VSS 45 86 HCK2 +5V GND 0.1µ 3-line serial input 47µ/16V +5V VSS 47 VSS VSS 46 CSYNC 85 HCK1 SLDWN 84 HST HD2IN Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party and other right due to same. 1µ 10k GND +5V GND 0.1µ +5V GND VDO HDO HPOL 0.1µ TST3 47µ/16V XCLR FLD DWN VGAV PO10 PO11 VSS to the panel EXT-CKI +5V HDN XHDN SLRGT PO9 VSS SLFR PO7 SLSY PO8 VD2IN PO5 TST2 PO6 SLMNB PO3 PO4 NC PO1 TST4 PO2 TST5 VSS TST7 PO0 TST6 VSS TST8 VDD VDD VSS VSS Application Circuit 33k 0.1µ 5.1k 1M 1M 3.3µ/ 35V 0.01µ +5V 50k 10k 33k +12A 33k GND GND 100p 50k +5V 0.01µ 1T363 1000p 6.8µ 47µ/16V 56p 0.01µ CXD2436Q CXD2436Q Package Outline Unit : mm 100PIN QFP (PLASTIC) + 0.4 14.0 – 0.01 17.9 ± 0.4 15.8 ± 0.4 + 0.1 0.15 – 0.05 23.9 ± 0.4 + 0.4 20.0 – 0.1 A 0.65 + 0.35 2.75 – 0.15 ±0.12 M 0° to 15° DETAIL A 0.8 ± 0.2 (16.3) 0.15 PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE QFP-100P-L01 LEAD TREATMENT SOLDER PLATING EIAJ CODE ∗QFP100-P-1420-A LEAD MATERIAL COPPER / 42 ALLOY PACKAGE WEIGHT 1.4g JEDEC CODE —34—