MICRON MT46V8M16

PRELIMINARY‡
128Mb: x4, x8, x16
DDR333 SDRAM Addendum
MT46V32M4 – 8 Meg x 4 x 4 banks
MT46V16M8 – 4 Meg x 8 x 4 banks
MT46V8M16 – 2 Meg x 16 x 4 banks
DOUBLE DATA RATE
(DDR) SDRAM
For the latest data sheet revisions, please refer to the Micron
Web site: www.micron.com/dramds
FEATURES
DDR333 COMPATIBILITY
• 167 MHz Clock, 333 Mb/s/p data rate
• VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V
• Bidirectional data strobe (DQS) transmitted/
received with data, i.e., source-synchronous data
capture (x16 has two - one per byte)
• Internal, pipelined double-data-rate (DDR)
architecture; two data accesses per clock cycle
• Differential clock inputs (CK and CK#)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; centeraligned with data for WRITEs
• DLL to align DQ and DQS transitions with CK
• Four internal banks for concurrent operation
• Data mask (DM) for masking write data (x16 has
two - one per byte)
• Programmable burst lengths: 2, 4, or 8
• Concurrent Auto Precharge option supported
• Auto Refresh and Self Refresh Modes
• FBGA package available
• 2.5V I/O (SSTL_2 compatible)
• tRAS lockout (tRAP = tRCD)
• Backwards compatible with DDR200 and DDR266
DDR333 meets or surpasses all DDR266 timing requirements thus assuring full backwards compatibility
with current DDR designs. In addition, these devices
support concurrent auto-precharge and tRAS lockout
for improved timing performance. The 128Mb, DDR333
device will support an (tREFI) average periodic refresh
interval of 15.6µs.
The standard 66-pin TSOP package is offered for
point-to-point applications where the FBGA package
is intended for the multi-drop systems.
The Micron 128Mb data sheet provides full specifications and functionality unless specified herein.
OPTIONS
CONFIGURATION
Architecture
Configuration
Refresh Count
Row Addressing
Bank Addressing
Column Addressing
PART NUMBER
• Configuration
32 Meg x 4 (8 Meg x 4 x 4 banks)
16 Meg x 8 (4 Meg x 8 x 4 banks)
8 Meg x 16 (2 Meg x 16 x 4 banks)
• Plastic Package
66-Pin TSOP (OCPL)
60-Ball FBGA (16x9mm)
• Timing - Cycle Time
6ns @ CL = 2.5 (DDR333B–FBGA)1
6ns @ CL = 2.5 (DDR333B–TSOP)1
7.5ns @ CL = 2 (DDR266A)2
• Self Refresh
Standard
32 Meg x 4
16 Meg x 8
8 Meg x 16
8 Meg x 4 x 4 banks 4 Meg x 8 x 4 banks 2 Meg x 16 x 4 banks
4K
4K (A0–A11)
4 (BA0, BA1)
2K (A0–A9, A11)
4K
4K (A0–A11)
4 (BA0, BA1)
1K (A0–A9)
4K
4K (A0–A11)
4 (BA0, BA1)
512 (A0– A8)
KEY TIMING PARAMETERS3
32M4
16M8
8M16
SPEED
TG
FJ
CL = 21
-6
-6T
-75Z
133 MHz
133 MHz
133 MHz
NOTE:
-6
-6T
-75Z
CLOCK RATE
GRADE
DATA-OUT ACCESS DQS-DQ
CL = 2.51 WINDOW2 WINDOW
167 MHz
167 MHz
133 MHz
2.15ns
2.0ns
2.5ns
±0.70ns
±0.75ns
±0.75ns
SKEW
+0.35ns
+0.45ns
+0.50ns
1. CL = CAS (Read) Latency
2. With a 50/50 clock duty cycle and a minimum clock
rate @ CL = 2 ( -75Z) and CL = 2.5 (-6, -6T).
3. Slower speeds are included in the 128Mb base data
sheet (-75, -8).
none
NOTE: 1. Supports PC2700 modules with 2.5-3-3 timing
2. Supports PC2100 modules with 2-3-3 timing
256Mb: x4, x8, x16 DDR333 SDRAM
128Mx4x8x16DDR333.p65 – Rev. A; Pub. 10/01
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
‡ PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY
MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION AND DATA SHEET SPECIFICATIONS.
PRELIMINARY
128Mb: x4, x8, x16
DDR333 SDRAM Addendum
FBGA 60-BALL PACKAGE DIMENSION
FBGA PACKAGE PINOUT
0.850 ±0.075
x4 (Top View)
SEATING PLANE
0.10 C
1
A
C
B
61X ∅0.45
SOLDER BALL DIAMETER
REFERS TO POST REFLOW
CONDITION. THE PREREFLOW DIAMETER IS Ø 0.40
BALL A9
6.40
C
1.80
CTR
D
0.80 TYP
E
1.20 MAX
PIN A1 ID
F
G
BALL A1
H
J
8.00 ±0.05
K
L
CL
11.00
M
16.00 ±0.10
2
3
4
5
6
VSSQ NC
VSS
NC VDDQ DQ3
NC VSSQ NC
NC VDDQ DQ2
NC VSSQ DQS
VSS
VREF
DM
CK
CK#
A12 CKE
A11
A9
A8
A7
A6
A5
A4
VSS
7
A
B
C
D
E
F
G
H
J
K
L
M
VDD
DQ0
NC
DQ1
NC
NC
WE#
RAS#
BA1
A0
A2
VDD
8
9
NC VDDQ
VSSQ NC
VDDQ NC
VSSQ NC
VDDQ NC
VDD A13
CAS#
CS#
BA0
A10
A1
A3
1.00
TYP
5.50 ±0.05
x8 (Top View)
1
Bottom View
A
CL
B
3.20 ±0.05
C
4.50 ±0.05
9 .00 ±0.10
D
SUBSTRATE: PLASTIC LAMINATE
E
SOLDER BALL MATERIAL: EUTECTIC 63% Sn, 37% Pb or
62% Sn, 36% Pb, 2%Ag
SOLDER BALL PAD: Ø .33mm
F
MOLD COMPOUND: EPOXY NOVOLAC
G
H
FBGA PACKAGE MARKING
J
K
Due to the physical size of the FBGA package, the full
ordering part number is not printed on the package.
Instead the following package code is utilized.
Top mark contains five fields
• Field 1 (Product Family)
DRAM
DRAM - ES
• Field 2 (Product Type)
2.5 Volt, DDR SDRAM, 60-ball
• Field 3 (Width)
x4 devices
x8 devices
x16 devices
L
M
2
VSSQ DQ7
NC VDDQ
NC VSSQ
NC VDDQ
NC VSSQ
VSS
VREF
CK
A12
A11
A8
A6
A4
3
12345
A
B
C
D
E
L
F
G
H
B
C
D
J
K
L
M
F
• Filed 5 (Speed Grade)
-6
-75Z
-75
-8
J
P
F
C
5
6
7
A
B
C
D
E
F
G
H
J
K
L
M
VDD
DQ1
DQ2
DQ3
NC
NC
WE#
RAS#
BA1
A0
A2
VDD
8
9
DQ0 VDDQ
VSSQ NC
VDDQ NC
VSSQ NC
VDDQ NC
VDD A13
CAS#
CS#
BA0
A10
A1
A3
x16 (Top View)
D
Z
• Field 4 (Density / Size)
128Mb
4
VSS
DQ6
DQ5
DQ4
DQS
DM
CK#
CKE
A9
A7
A5
VSS
1
2
3
VSSQ
DQ14
DQ12
DQ10
DQ8
VREF
DQ15
VDDQ
VSSQ
VDDQ
VSSQ
VSS
CK
A12
A11
A8
A6
A4
VSS
DQ13
DQ11
DQ9
UDQS
UDM
CK#
CKE
A9
A7
A5
VSS
4
5
6
A
B
C
D
E
F
G
H
J
K
L
M
7
8
VDD
DQ2
DQ4
DQ6
LDQS
LDM
WE#
RAS#
BA1
A0
A2
VDD
DQ0
VSSQ
VDDQ
VSSQ
VDDQ
VDD
CAS#
CS#
BA0
A10
A1
A3
9
VDDQ
DQ1
DQ3
DQ5
DQ7
A13
Example top mark for a MT46V32M4FJ-6: DLBFJ
256Mb: x4, x8, x16 DDR333 SDRAM
128Mx4x8x16DDR333.p65 – Rev. A; Pub. 10/01
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
‡ THIS DATA SHEET CONTAINS THE PRESENT DESCRIPTION OF A PRODUCT IN DEFINITION WITH NO FORMAL DESIGN IN PROGRESS.
PRELIMINARY
128Mb: x4, x8, x16
DDR333 SDRAM Addendum
66-PIN TSOP PACKAGE DIMENSION
66-PIN TSOP PACKAGE PIN ASSIGMENT
(TOP VIEW)
SEE DETAIL A
22.22 ± 0.08
0.71
0.65 TYP
0.10 (2X)
0.32 ± .075 TYP
x4
x8
x16
VDD
VDD
VDD
NC
DQ0
DQ0
VDDQ VDDQ VDDQ
NC
DQ1
NC
DQ0
DQ1
DQ2
VSSQ
VSSQ
VssQ
NC
DQ3
NC
NC
DQ2
DQ4
VDDQ VDDQ VDDQ
NC
NC
DQ5
DQ1
DQ3
DQ6
VSSQ
VSSQ
VssQ
NC
DQ7
NC
NC
NC
NC
VDDQ VDDQ VDDQ
NC
NC LDQS
NC
NC
NC
VDD
VDD
VDD
DNU
DNU
DNU
NC
NC
LDM
WE#
WE#
WE#
CAS#
CAS#
CAS#
RAS#
RAS#
RAS#
CS#
CS#
CS#
NC
NC
NC
BA0
BA0
BA0
BA1
BA1
BA1
A10/AP A10/AP A10/AP
A0
A0
A0
A1
A1
A1
A2
A2
A2
A3
A3
A3
VDD
VDD
VDD
11.76 ±0.10
10.16 ±0.08
+0.03
0.15 -0.02
PIN #1 ID
0.10
1.20 MAX
GAGE PLANE
0.10
0.25
+0.10
-0.05
0.80 TYP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
x16
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
NC
VSSQ
UDQS
DNU
VREF
VSS
UDM
CK#
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
VSS
x8
VSS
DQ7
VSSQ
NC
DQ6
VDDQ
NC
DQ5
VSSQ
NC
DQ4
VDDQ
NC
NC
VSSQ
DQS
DNU
VREF
VSS
DM
CK#
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
VSS
x4
VSS
NC
VSSQ
NC
DQ3
VDDQ
NC
NC
VSSQ
NC
DQ2
VDDQ
NC
NC
VSSQ
DQS
DNU
VREF
VSS
DM
CK#
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
VSS
0.50 ±0.10
DETAIL A
NOTE:
1. All dimensions in millimeters.
2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm
per side.
256Mb: x4, x8, x16 DDR333 SDRAM
128Mx4x8x16DDR333.p65 – Rev. A; Pub. 10/01
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
‡ THIS DATA SHEET CONTAINS THE PRESENT DESCRIPTION OF A PRODUCT IN DEFINITION WITH NO FORMAL DESIGN IN PROGRESS.
PRELIMINARY
128Mb: x4, x8, x16
DDR333 SDRAM Addendum
PIN DESCRIPTIONS
BALL / PIN NUMBERS
FBGA
TSOP
SYMBOL
TYPE
DESCRIPTION
G2, G3
45, 46
CK, CK#
Input
Clock: CK and CK# are differential clock inputs. All address and
control input signals are sampled on the crossing of the positive
edge of CK and negative edge of CK#. Output data (DQs and
DQS) is referenced to the crossings of CK and CK#.
H3
44
CKE
Input
Clock Enable: CKE HIGH activates and CKE LOW deactivates the
internal clock, input buffers and output drivers. Taking CKE LOW
provides PRECHARGE POWER-DOWN and SELF REFRESH
operations (all banks idle), or ACTIVE POWER-DOWN (row
ACTIVE in any bank). CKE is synchronous for POWER-DOWN
entry and exit, and for SELF REFRESH entry. CKE is asynchronous
for SELF REFRESH exit and for disabling the outputs. CKE must be
maintained HIGH throughout read and write accesses. Input
buffers (excluding CK, CK# and CKE) are disabled during POWERDOWN. Input buffers (excluding CKE) are disabled during SELF
REFRESH. CKE is an SSTL_2 input but will detect an LVCMOS
LOW level after VDD is applied.
H8
24
CS#
Input
Chip Select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked
when CS# is registered HIGH. CS# provides for external bank
selection on systems with multiple banks. CS# is considered part
of the command code.
H7, G8, G7
23, 22, 21
RAS#, CAS#,
WE#
Input
Command Inputs: RAS#, CAS#, and WE# (along with CS#) define the
command being entered.
3F
F7, 3F
47
20, 47
DM
LDM, UDM
Input
Input Data Mask: DM is an input mask signal for write data. Input
data is masked when DM is sampled HIGH along with that input
data during a WRITE access. DM is sampled on both edges of
DQS. Although DM pins are input-only, the DM loading is
designed to match that of DQ and DQS pins. For the x16 , LDM is
DM for DQ0-DQ7 and UDM is DM for DQ8-DQ15. Pin 20 is a NC
on x4 and x8
J8,J7
26, 27
BA0, BA1
Input
Bank Address Inputs: BA0 and BA1 define to which bank an
ACTIVE, READ, WRITE, or PRECHARGE command is being applied.
K7, L8, L7
M8, M2, L3
L2, K3, K2
J3, K8, J2
29-32
32, 35, 36
36, 38, 39
40, 29, 41
A0, A1, A2 Input
A3, A4, A5
A6, A7, A8
A9, A10, A11
Address Inputs: Provide the row address for ACTIVE commands, and
the column address and auto precharge bit (A10) for READ/WRITE
commands, to select one location out of the memory array in the
respective bank. A10 sampled during a PRECHARGE command
determines whether the PRECHARGE applies to one bank (A10 LOW,
bank selected by BA0, BA1) or all banks (A10 HIGH). The address inputs
also provide the op-code during a MODE REGISTER SET command. BA0
and BA1 define which mode register (mode register or extended mode
register) is loaded during the LOAD MODE REGISTER command.
(continued on next page)
256Mb: x4, x8, x16 DDR333 SDRAM
128Mx4x8x16DDR333.p65 – Rev. A; Pub. 10/01
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
‡ THIS DATA SHEET CONTAINS THE PRESENT DESCRIPTION OF A PRODUCT IN DEFINITION WITH NO FORMAL DESIGN IN PROGRESS.
PRELIMINARY
128Mb: x4, x8, x16
DDR333 SDRAM Addendum
PIN DESCRIPTIONS (continued)
BALL / PIN NUMBERS
FBGA
TSOP
SYMBOL
TYPE
DESCRIPTION
A8, B9, B7
C9, C7, D9
D7, E9, E1
D3, D1, C3
C1, B3, B1,
A2
2, 4, 5,
7, 8, 10
11, 13, 54
56, 57, 59
60, 62, 63,
65
DQ0-2
DQ3-5
DQ6-8
DQ9-11
DQ12-14
DQ15
I/O
Data Input/Output: Data bus for x16
A8, B7, C7,
D7, D3, C3,
B3, A2
2, 5, 8,
11, 56, 59
62, 65
DQ0-2
DQ3-5
DQ6-7
I/O
Data Input/Output: Data bus for x8
B7, D7, D3,
B3
5, 11, 56
62
DQ0-2
DQ2
I/O
Data Input/Output: Data bus for x4
E3
E7, E3
51
16, 51
DQS
LDQS, UDQS
I/O
Data Strobe: Output with read data, input with write data. DQS is
edge-aligned with read data, centered in write data. It is used to
capture data. For the x16 , LDQS is DQS for DQ0-DQ7 and UDQS
IS DQS for DQ8-DQ15. Pin 16 (H7) is NC on x4 and x8.
14, 17, 25,
43, 53
NC
-
No Connect: These pins should be left unconnected.
19, 50
DNU
–
Do Not Use: Must float to minimize noise on Vref
VDDQ
Supply
VSSQ
Supply
DQ Power Supply: +2.5V ±0.2V. Isolated on the die for improved
noise immunity.
DQ Ground. Isolated on the die for improved noise immunity.
B2, D2, C8, 3, 9, 15, 55,
E8, A9
61
A1, E2, B8, 6, 12, 52,
D8
58, 64
F8, M7, A7
1, 18, 33
VDD
Supply
Power Supply: +2.5V ±0.2V.
A1, A3, F2,
34, 48, 66
VSS
Supply
Ground.
F1
49
VREF
Supply
SSTL_2 reference voltage.
F9
17
A13
I
Address input A13 for 1Gb devices.
H2
42
A12
I
For 256Mb and greater devices.
M3
256Mb: x4, x8, x16 DDR333 SDRAM
128Mx4x8x16DDR333.p65 – Rev. A; Pub. 10/01
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
‡ THIS DATA SHEET CONTAINS THE PRESENT DESCRIPTION OF A PRODUCT IN DEFINITION WITH NO FORMAL DESIGN IN PROGRESS.
PRELIMINARY
128Mb: x4, x8, x16
DDR333 SDRAM Addendum
GENERAL DESCRIPTION
The DDR333 SDRAM is a high-speed CMOS, dynamic random-access memory that operates at a frequency of 167 MHz (tCK=6ns) with a peak data transfer rate of 333Mb/s/p. DDR333 continues to use the
JEDEC standard SSTL_2 interface and the 2n-prefetch
architecture.
The standard DDR200/DDR266 data sheets also
pertain to the DDR333 device and should be referenced
for a complete description of DDR SDRAM function-
ality and operating modes. However, to meet the faster
DDR333 operating frequencies, some of the AC timing
parameters are slightly tighter. This addendum data
sheet will concentrate on the key differences required
to support the enhanced speeds.
In addition to the standard 66-pin TSOP package,
a 60-ball FBGA package is utilized for DDR333. This
JEDEC-defined package promotes better package parasitic parameters and a smaller footprint.
CAPACITANCE (FBGA)
(Notes: 1-5, 14-17, 33; notes appear in DDR200/266 data sheets)
(0°C ≤ TA ≤ 70°C; VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V)
PARAMETER
SYMBOL
MIN
MAX
UNITS
NOTES
DQs, DQS, DM (for x4 or x8 devices)
DCIO
–
0.50
pF
13, 24
DQ0-DQ7, LDQS, LDM (for lower byte of x16 devices),
DCIO
–
0.50
pF
13, 24
DQ8-DQ15, UDQS, UDM (for upper byte of x16 devices)
Delta Input/Output Capacitance:
DCIO
–
0.50
pF
13, 29
Delta Input Capacitance: Command and Address
DCI1
–
0.50
pF
13, 29
Delta Input Capacitance: CK, CK#
DCI2
–
0.25
pF
13, 29
Input/Output Capacitance: DQs, DQS, DM (LDQS, LDM, UDM)
CIO
3.50
4.00
pF
13
Input Capacitance: Command and Address
CI1
1.50
2.50
pF
13
Input Capacitance: CK, CK#
CI2
1.50
2.50
pF
13
Input Capacitance: CKE
CI3
1.50
2.50
pF
13
SYMBOL
MIN
MAX
UNITS
NOTES
DQs, DQS, DM (for x4 or x8 devices)
DCIO
–
0.50
pF
13, 24
DQ0-DQ7, LDQS, LDM (for lower byte of x16 devices),
DCIO
–
0.50
pF
13, 24
DQ8-DQ15, UDQS, UDM (for upper byte of x16 devices)
DCIO
–
0.50
pF
13, 24
Delta Input Capacitance: Command and Address
DCI1
–
0.50
pF
13, 29
Delta Input Capacitance: CK, CK#
DCI 2
–
0.25
pF
13, 29
Input/Output Capacitance: DQs, DQS, DM (LDQS, LDM, UDM)
CIO
4.0
5.0
pF
13
Input Capacitance: Command and Address
CI 1
2.0
3.0
pF
13
Input Capacitance: CK, CK#
CI2
2.0
3.0
pF
13
Input Capacitance: CKE
CI 3
2.0
3.0
pF
13
CAPACITANCE (TSOP)
(Notes: 1-5, 14-17, 33; notes appear in DDR200/266 data sheets)
(0°C ≤ TA ≤ 70°C; VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V)
PARAMETER
Delta Input/Output Capacitance:
256Mb: x4, x8, x16 DDR333 SDRAM
128Mx4x8x16DDR333.p65 – Rev. A; Pub. 10/01
6
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
‡ THIS DATA SHEET CONTAINS THE PRESENT DESCRIPTION OF A PRODUCT IN DEFINITION WITH NO FORMAL DESIGN IN PROGRESS.
PRELIMINARY
128Mb: x4, x8, x16
DDR333 SDRAM Addendum
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 1-5, 14-17, 33; notes appear in DDR200/266 data sheets)
(0°C ≤ TA ≤ 70°C; VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V)
AC CHARACTERISTICS
PARAMETER
Access window of DQs from CK/CK#
CK high-level width
CK low-level width
Clock cycle time
-6 (FBGA)
MIN
MAX
-0.7
+0.7
0.45
0.55
0.45
0.55
6
13
7.5
13
0.45
0.45
1.75
-0.60
+0.60
0.35
0.35
0.35
0.75
1.25
0.2
0.2
tCH,tCL
+0.70
-0.70
0.75
0.75
0.80
0.80
2.2
12
tHP
- tQHS
0.50
18
42
70,000
60
72
18
18
0.9
1.1
0.4
0.6
12
0.25
0
0.4
0.6
15
1
tQH - tDQSQ
140.6
15.6
0
75
200
SYMBOL
tAC
tCH
tCL
t
CL = 2.5
CK (2.5)
tCK (2)
CL = 2
tDH
DQ and DM input hold time relative to DQS
tDS
DQ and DM input setup time relative to DQS
t
DQ and DM input pulse width (for each input)
DIPW
tDQSCK
Access window of DQS from CK/CK#
tDQSH
DQS input high pulse width
tDQSL
DQS input low pulse width
t
DQS-DQ skew, DQS to last DQ valid, per group, per access
DQSQ
tDQSS
Write command to first DQS latching transition
tDSS
DQS falling edge to CK rising - setup time
t
DQS falling edge from CK rising - hold time
DSH
tHP
Half clock period
tHZ
Data-out high-impedance window from CK/CK#
tLZ
Data-out low-impedance window from CK/CK#
t
Address and control input hold time (fast slew rate)
IHF
t IS
Address and control input setup time (fast slew rate)
F
tIH
Address and control input hold time (slow slew rate)
S
t IS
Address and control input setup time (slow slew rate)
S
tIPW
Address and control input pulse width
t
LOAD MODE REGISTER command cycle time
MRD
tQH
DQ-DQS hold, DQS to first DQ to go non-valid, per access
Data Hold Skew Factor
ACTIVE to AUTOPRECHARGE command
ACTIVE to PRECHARGE command
ACTIVE to ACTIVE/AUTO REFRESH command period
AUTO REFRESH command period
ACTIVE to READ or WRITE delay
PRECHARGE command period
DQS read preamble
DQS read postamble
ACTIVE bank a to ACTIVE bank b command
DQS write preamble
DQS write preamble setup time
DQS write postamble
Write recovery time
Internal WRITE to READ command delay
Data valid output window
REFRESH to REFRESH command interval
Average periodic refresh interval
Terminating voltage delay to VDD
Exit SELF REFRESH to non-READ command
Exit SELF REFRESH to READ command
256Mb: x4, x8, x16 DDR333 SDRAM
128Mx4x8x16DDR333.p65 – Rev. A; Pub. 10/01
tQHS
tRAP
tRAS
tRC
tRFC
tRCD
tRP
tRPRE
tRPST
tRRD
tWPRE
tWPRES
tWPST
tWR
tWTR
na
tREFC
tREFI
tVTD
tXSNR
tXSRD
7
-6T (TSOP)
MIN
MAX
-0.7
+0.7
0.45
0.55
0.45
0.55
6
13
7.5
13
0.45
0.45
1.75
-0.60
+0.60
0.35
0.35
0.45
0.75
1.25
0.2
0.2
tCH,tCL
+0.70
-0.70
0.75
0.75
0.80
0.80
2.2
12
tHP
- tQHS
0.60
18
42
70,000
60
72
18
18
0.9
1.1
0.4
0.6
12
0.25
0
0.4
0.6
15
1
tQH - tDQSQ
140.6
15.6
0
75
200
-75Z
MIN
MAX UNITS NOTES
-0.75
+0.75
ns
tCK
0.45
0.55
30
tCK
0.45
0.55
30
7.5
13
ns
45,52
7.5
13
ns
45,52
0.50
ns
26,31
0.50
ns
26,31
1.75
ns
31
-0.75
+0.75
ns
tCK
0.35
tCK
0.35
0.50
ns
25, 26
tCK
0.75
1.25
tCK
0.2
tCK
0.2
tCH,tCL
ns
34
+0.75
ns
18,42
-0.75
ns
18,43
0.90
ns
14
0.90
ns
14
1
ns
14
1
ns
14
2.2
ns
15
ns
tHP
ns
25, 26
- tQHS
0.75
ns
20
ns
46
40
120,000 ns
35
65
ns
75
ns
50
20
ns
20
ns
tCK
0.9
1.1
42
tCK
0.4
0.6
15
ns
tCK
0.25
0
ns
20, 21
tCK
0.4
0.6
19
15
ns
tCK
1
tQH - tDQSQ
ns
25
140.6
µs
23
15.6
µs
23
0
ns
75
ns
tCK
200
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
‡ THIS DATA SHEET CONTAINS THE PRESENT DESCRIPTION OF A PRODUCT IN DEFINITION WITH NO FORMAL DESIGN IN PROGRESS.
PRELIMINARY
128Mb: x4, x8, x16
DDR333 SDRAM Addendum
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
E-mail: [email protected], Internet: http://www.micron.com, Customer Comment Line: 800-932-4992
Micron is a registered trademark and the Micron logo and M logo are trademarks of Micron Technology, Inc.
256Mb: x4, x8, x16 DDR333 SDRAM
128Mx4x8x16DDR333.p65 – Rev. A; Pub. 10/01
8
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
‡ THIS DATA SHEET CONTAINS THE PRESENT DESCRIPTION OF A PRODUCT IN DEFINITION WITH NO FORMAL DESIGN IN PROGRESS.