256MB / 512MB (x64) 168-PIN SDRAM DIMMs SYNCHRONOUS DRAM MODULE MT8LSDT3264A(I) - 256MB MT16LSDT6464A(I) - 512MB For the latest data sheet, please refer to the Micron Web site: www.micron.com/moduleds Features Figure 1: 168-Pin DIMM (MO–161) • PC100- and PC133-compliant • JEDEC-standard 168-pin, dual in-line memory module (DIMM) • Unbuffered • 256MB (32 Meg x 64), 512MB (64 Meg x 64) • Single +3.3V ±0.3V power supply • Fully synchronous; all signals registered on positive edge of system clock • Internal pipelined operation; column address can be changed every clock cycle • Internal SDRAM banks for hiding row access/precharge • Programmable burst lengths: 1, 2, 4, 8, or full page • Auto Precharge, including Concurrent Auto Precharge, and Auto Refresh Modes • 64ms, 8,192 cycle Auto Refresh cycle • Self Refresh Mode • LVTTL-compatible inputs and outputs • Serial Presence-Detect (SPD) OPTIONS Standard Low Profile Table 2: MARKING • Package Unbuffered 168-pin DIMM (gold) • Operating Temperature Range Commercial (0°C to +70°C) Industrial (-40°C to +85°C)1 • Memory Clock/CAS Latency (133 MHz)/CL = 2 (133 MHz)/CL = 3 (100 MHz)/CL = 2 A 32,64 Meg x 64 SDRAM DIMMs SD8_16C32_64x64AG_C.fm - Rev. C 11/02 -13E -133 -10E 2-2-2 2-2-2 2-2-2 2-2-2 3-3-3 NA Part Numbers PARTNUMBER1 MT8LSDT3264AG-13E_ MT8LSDT3264AG(I)-133_ MT8LSDT3264AG-10E_ MT16LSDT6464AG-13E_ MT16LSDT6464AG(I)-133_ MT16LSDT6464AG-10E_ Address Table Refresh Count Device Banks Device Configuration Row Addressing Column Addressing Module Banks PC133 CL - tRCD - tRP Table 3: 1. Consult Micron for availability; Industrial Temperature Option available in -133 speed only. 256MB MODULE 8K 4 (BA0, BA1) 32 Meg x 8 8K (A0–A12) 1K (A0–A9) 1 (S0,S2) PC100 CL - tRCD - tRP None I NOTE: Table 1: MODULE MARKINGS G -13E -133 -10E Timing parameters 512MB MODULE 8K 4 (BA0, BA1) 32 Meg x 8 8K (A0–A12) 1K (A0–A9) 2 (S0,S2; S1,S3) SYSTEM CONFIGURATION BUS SPEED 32 Meg x 64 32 Meg x 64 32 Meg x 64 64 Meg x 64 64 Meg x 64 64 Meg x 64 133 MHz 133 MHz 100 MHz 133 MHz 133 MHz 100 MHz NOTE: 1. The designators for component and PCB revision are the last two characters of each part number. Consult factory for current revision codes. Example: MT8LSDT3264AG-133B1. 1 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology Inc. 256MB / 512MB (x64) 168-PIN SDRAM DIMMs Table 4: Pin Assignment, Standard PCB (168-Pin DIMM Front) Table 5: PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 VSS DQ0 DQ1 DQ2 DQ3 VDD DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VDD DQ14 DQ15 NC 22 NC 43 VSS 64 23 VSS 44 NC 65 24 NC 45 S2# 66 25 NC 46 DQMB2 67 26 VDD 47 DQMB3 68 27 WE# 48 NC 69 28 DQMB0 49 VDD 70 29 DQMB1 50 NC 71 30 S0# 51 NC 72 31 NC 52 NC 73 32 VSS 53 NC 74 33 A0 54 VSS 75 34 A2 55 DQ16 76 35 A4 56 DQ17 77 36 A6 57 DQ18 78 37 A8 58 DQ19 79 38 A10 59 VDD 80 39 BA1 60 DQ20 81 40 VDD 61 NC 82 41 VDD 62 NC 83 42 CK0 63 CKE1 84 Pin Assignment, Standard PCB (168-Pin DIMM Back) PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 VDD DQ28 DQ29 DQ30 DQ31 VSS CK2 NC NC SDA SCL VDD 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 VSS DQ32 DQ33 DQ34 DQ35 VDD DQ36 DQ37 DQ38 DQ39 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 VDD DQ46 DQ47 NC 106 NC 127 VSS 148 107 VSS 128 CKE0 149 108 NC 129 S3# 150 109 NC 130 DQMB6 151 110 VDD 131 DQMB7 152 111 CAS# 132 NC 153 112 DQMB4 133 VDD 154 113 DQMB5 134 NC 155 114 S1# 135 NC 156 115 RAS# 136 NC 157 116 VSS 137 NC 158 117 A1 138 VSS 159 118 A3 139 DQ48 160 119 A5 140 DQ49 161 120 A7 141 DQ50 162 121 A9 142 DQ51 163 122 BA0 143 VDD 164 123 A11 144 DQ52 165 124 VDD 145 NC 166 125 CK1 146 NC 167 126 A12 147 NC 168 VSS DQ53 DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 VDD DQ60 DQ61 DQ62 DQ63 VSS CK3 NC SA0 SA1 SA2 VDD Figure 2: PIN Locations (168-PIN DIMM) Front View U1 U2 U3 U4 U6 U7 U8 U9 U10 PIN 84 PIN 41 PIN 1 Back View (Populated only for 512MB module) U11 U12 U13 U14 PIN 168 U16 U17 U19 PIN 85 PIN125 Indicates a VDD pin U18 Indicates a VSS pin See Figure 10, 256MB Module Dimensions, on page 23 and Figure 11, 512MB Module Dimensions, on page 24 for module dimensions. 32,64 Meg x 64 SDRAM DIMMs SD8_16C32_64x64AG_C.fm - Rev. C 11/02 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology Inc. 256MB / 512MB (x64) 168-PIN SDRAM DIMMs Table 6: Pin Descriptions Pin numbers may not correlate with symbols. Refer to the Pin Assignment table for pin number and symbol information. PIN NUMBERS SYMBOL TYPE DESCRIPTION 27, 111, 115 Input 42, 79, 125, 163 RAS#, CAS#, WE# CK0-CK3 63, 128 CKE0, CKE1 Input 30, 45,114, 129 S0# -S3# Input 28, 29, 46, 47, 112, 113, 130, 131 DQMB0-DQMB7 Input 39, 122 BA0, BA1 Input 33 - 38, 117 - 121, 123, 126 A0-A12 Input 83 SCL Input 165-167 SA0-SA2 Input 2-5, 7-11, 13-17, 19-20, 55-58, 60, 65-67, 69-72, 74-77, 86-89, 91-95, 97-101, 103-104, 139-142, 144, 149-151, 153-156,158-161 82 DQ0-DQ63 Input/ Output Command Inputs: RAS#, CAS#, and WE# (along with S#) define the command being entered. Clock: CK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CK. CK also increments the internal burst counter and controls the output registers. Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CK signal. Deactivating the clock provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all device banks idle) or CLOCK SUSPEND OPERATION (burst access in progress). CKE is synchronous except after the device enters power- down and self refresh modes, where CKE becomes asynchronous until after exiting the same mode. The input buffers, including CK, are disabled during power-down and self refresh modes, providing low standby power. Chip Select: S# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when S# is registered HIGH. S# is considered part of the command code. Input/Output Mask: DQMB is an input mask signal for write accesses and an output enable signal for read accesses. Input data is masked when DQMB is sampled HIGH during a WRITE cycle. The output buffers are placed in a High-Z state (twoclock latency) when DQMB is sampled HIGH during a READ cycle. Bank Address: BA0 and BA1 define to which device bank the ACTIVE, READ, WRITE, or PRECHARGE command is being applied. Address Inputs: Provide the row address for ACTIVE commands, and the column address and auto prcharge bit (A10) for READ/WRITE commands, to select one location out of the memory arrary in the respective device bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one device bank (A10 LOW, device bank selected by BA0, BA1) or all device banks (A10 HIGH). The address inputs also provide the op-code during a MODE REGISTER SET command. Serial Clock for Presence-Detect: SCL is used to synchronize the presence-detect data transfer to and from the module. Presence-Detect Address Inputs: These pins are used to configure the presence-detect device. Data I/O: Data bus. 32,64 Meg x 64 SDRAM DIMMs SD8_16C32_64x64AG_C.fm - Rev. C 11/02 SDA Input Input/ Serial Presence-Detect Data: SDA is a bidirectional pin used to Output transfer addresses and data into and out of the presencedetect portion of the module. 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology Inc. 256MB / 512MB (x64) 168-PIN SDRAM DIMMs Table 6: Pin Descriptions (Continued) Pin numbers may not correlate with symbols. Refer to the Pin Assignment table for pin number and symbol information. PIN NUMBERS SYMBOL TYPE DESCRIPTION 6, 18, 26, 40, 41, 49, 59, 73, 84, 90, 102, 110, 124, 133, 143, 157, 168 1, 12, 23, 32, 43, 54, 64, 68, 78, 85, 96, 107, 116, 127, 138, 148, 152, 162 21-22, 24-25, 31, 44, 48, 50-53, 61-62, 80, 81, 105-106, 108-109, 132, 134-137, 145-147, 164 VDD Supply Power Supply: +3.3V ±0.3V. VSS Supply Ground. NC – 32,64 Meg x 64 SDRAM DIMMs SD8_16C32_64x64AG_C.fm - Rev. C 11/02 Not Connected: These pins are not connected on these modules. 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology Inc. 256MB / 512MB (x64) 168-PIN SDRAM DIMMs Figure 3: Functional Block Diagram Single Bank Modules S0# DQMB0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQMB4 DQM CS# DQ DQ DQ DQ U1 DQ DQ DQ DQ DQMB1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQM CS# DQ DQ DQ DQ U2 DQ DQ DQ DQ DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQMB5 DQM CS# DQ DQ DQ DQ U3 DQ DQ DQ DQ DQM CS# DQ DQ DQ U4 DQ DQ DQ DQ DQ DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 S2# DQMB2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQMB6 DQM CS# DQ DQ DQ DQ U7 DQ DQ DQ DQ DQMB3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQMB7 DQM CS# DQ DQ DQ DQ U9 DQ DQ DQ DQ RAS# RAS#: SDRAMs CAS# CAS#: SDRAMs CKE0 CKE0: SDRAMs WE# WE#: SDRAMs A0-A11 BA0: SDRAMs BA1 VDD BA1: SDRAMs SCL WP DQM CS# DQ DQ DQ DQ U8 DQ DQ DQ DQ DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 CK0 U1 U2 U3 U4 U5 CK2 U6 U7 U8 U9 A0-A11: SDRAMs BA0 VSS DQM CS# DQ DQ DQ DQ U6 DQ DQ DQ DQ DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 SDRAMs 3.3pF SDRAMs SPD U10 A0 A1 A2 CK1, CK3 10pF SDA SA0 SA1 SA2 Notes: All resistor values are 10W unless otherwise specified. Per industry standard, Micron modules use various component speed grades as referenced in the module part numbering guide at: www.micron.com/numberguide. 32,64 Meg x 64 SDRAM DIMMs SD8_16C32_64x64AG_C.fm - Rev. C 11/02 5 SDRAMs = MT48LC32M8A2TG, Commercial Temperature SDRAMs = MT48LC32M8A2TG-75 IT, Industrial Temperature Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology Inc. 256MB / 512MB (x64) 168-PIN SDRAM DIMMs Figure 4: Functional Block Diagram Dual Bank Modules S0# S1# DQMB0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQMB4 DQM CS# DQ DQ DQ DQ U1 DQ DQ DQ DQ DQM CS# DQ DQ DQ DQ U19 DQ DQ DQ DQ DQM CS# DQ DQ DQ DQ U3 DQ DQ DQ DQ DQM CS# DQ DQ DQ DQ U17 DQ DQ DQ DQ DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQMB1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQM CS# DQ DQ DQ U2 DQ DQ DQ DQ DQ DQM CS# DQ DQ DQ DQ U18 DQ DQ DQ DQ DQM CS# DQ DQ DQ DQ U4 DQ DQ DQ DQ DQM CS# DQ DQ DQ DQ U16 DQ DQ DQ DQ DQM CS# DQ DQ DQ DQ U6 DQ DQ DQ DQ DQM CS# DQ DQ DQ DQ U14 DQ DQ DQ DQ DQM CS# DQ DQ DQ DQ U8 DQ DQ DQ DQ DQM CS# DQ DQ DQ DQ U12 DQ DQ DQ DQ DQMB5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 S2# S3# DQMB2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQMB6 DQM CS# DQ DQ DQ DQ U7 DQ DQ DQ DQ DQM CS# DQ DQ DQ DQ U13 DQ DQ DQ DQ DQM CS# DQ DQ DQ DQ U9 DQ DQ DQ DQ DQM CS# DQ DQ DQ DQ U11 DQ DQ DQ DQ DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQMB3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQMB7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 VDD CKE1 10K Ω CKE0 CKE: SDRAMs U1-U9 CAS# CAS#: SDRAMs RAS# RAS#: SDRAMs WE# WE#: SDRAMs A0-A11 CK0 U1 U2 U3 U4 U5 CK2 U6 U7 U8 U9 CKE: SDRAMs U11-U19 A0-A11: SDRAMs BA0 BA0: SDRAMs BA1 BA1: SDRAMs VDD SDRAMs VSS SDRAMs 3.3pF SCL WP U15 U16 U17 U18 U19 CK1 U11 U12 U13 U14 CK3 3.3pF SPD U10 A0 A1 A2 SDA SA0 SA1 SA2 Notes: All resistor values are 10W unless otherwise specified. SDRAMs = MT48LC32M8A2TG, Commercial Temperature SDRAMs = MT48LC32M8A2TG-75 IT, Industrial Temperature Per industry standard, Micron modules use various component speed grades as referenced in the module part numbering guide at: www.micron.com/numberguide. 32,64 Meg x 64 SDRAM DIMMs SD8_16C32_64x64AG_C.fm - Rev. C 11/02 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology Inc. 256MB / 512MB (x64) 168-PIN SDRAM DIMMs General Description Serial Presence-Detect Operation The MT8LSDT13264A(I) and MT16LSDT6464A(I) are high-speed CMOS, dynamic random-access, 256MB and 512MB memory modules organized in x64 configurations. These modules use internally configured quad-bank SDRAMS with a synchronous interface (all signals are registered on the positive edge of the clock signals CK0-CK3). Read and write accesses to the SDRAM modules are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the device bank and row to be accessed (BA0, BA1 select the device bank; A0–A12 select the device row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. The modules provide for programmable READ or WRITE burst length of 1, 2, 4, or 8 locations, or the full page, with a burst terminate option. An AUTO PRECHARGE function may be enabled to provide a selftimed row precharge that is initiateda the end of the burst sequence. The modules use an internal pipelined architecture to achieve high-speed operation. This architecture is compatible with the 2n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a high-speed, fully random access. Precharging one device bank while accessing one of the other three device banks will hide the precharge cycles and provide seamless, high-speed, random-access operation. The modules are designed to operate in 3.3V, lowpower memory systems. An auto refresh mode is provided, along with a power-saving, power-down mode. All inputs and outputs are LVTTL-compatible. SDRAM modules offer substantial advances in DRAM operating performance, including the ability to syncronously burst data at a high data rate with automatic column-address generation, the ability to interleave between intenal banks in order to hide precharge time and the capability to randomly change column addresses on each clock cycle during a burst access. For more information regarding SDRAM operation, refer to the 256Mb SDRAM component data sheet. 32,64 Meg x 64 SDRAM DIMMs SD8_16C32_64x64AG_C.fm - Rev. C 11/02 These modules incorporate serial presence-detect (SPD). The SPD function is implemented using a 2,048-bit EEPROM. This nonvolatile storage device contains 256 bytes. The first 128 bytes can be programmed by Micron to identify the module type and various SDRAM organizations and timing parameters. The remaining 128 bytes of storage are available for use by the customer. System READ/WRITE operations between the master (system logic) and the slave EEPROM device (DIMM) occur via a standard I2C bus using the DIMM’s SCL (clock) and SDA (data) signals, together with SA (2:0), which provide eight unique DIMM/EEPROM addresses. SDRAM Functional Description In general, the 256Mb SDRAMs are quad-bank DRAMs that operate at 3.3V and include a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). The four banks of the x8 configured devices used for these modules are configured as 8,192 bit-rows by 1,024 bit-columns, by 8 input/output bits. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the active command are used to select the device bank and row to be accessed; BA0 and BA1 select the device bank, A0–A12 select the device row. The address bits A0–A9 registered coincident with the READ or WRITE command are used to select the starting device column location for the burst access. Prior to normal operation, the SDRAM must be initialized. The following sections provide detailed information covering device initialization, register definition, command descriptions and device operation. Initialization SDRAMS must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Once power is applied to VDD and VDDQ (simultaneously) and the clock is stable (stable clock is defined as a signal cycling within timing constrants specified for the clock pin), the SDRAM requires a 100µs delay prior to issuing any command other than a COM- 7 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology Inc. 256MB / 512MB (x64) 168-PIN SDRAM DIMMs MAND INHIBIT or NOP. Starting at some point during this 100µs period and continuing at least through the end of this period, COMMAND INHIBIT or NOP commands should be applied. Once the 100µs delay has been satisfied with at least one COMMAND INHIBIT or NOP command having been applied, a PRECHARGE command should be applied. All device banks must then be precharged, thereby placing the device in the all banks idle state. Once in the idle state, two AUTO REFRESH cycles must be performed. After the AUTO REFRESH cycles are complete, the SDRAM is ready for mode register programming. Because the mode register will power up in an unknown state, it should be loaded prior to applying any operational command. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached, as shown in the Burst Definition Table. The block is uniquely selected by A1– A9 when the burst length is set to two; A2–A9 when the burst length is set to four; and by A3–A9 when the burst length is set to eight. The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. Full-page bursts wrap within the page if the boundary is reached, as shown in Table 7, Burst Definitions, on page 9. Mode Register Definition The mode register is used to define the specific mode of operation of the SDRAM. This definition includes the selection of a burst length, a burst type, a CAS latency, an operating mode and a write burst mode, as shown in Figure 5, Mode Register Definition Diagram, on page 8. The mode register is programmed via the LOAD MODE REGISTER command and will retain the stored information until it is programmed again or the device loses power. Mode register bits M0–M2 specify the burst length, M3 specifies the type of burst (sequential or interleaved), M4–M6 specify the CAS latency, M7 and M8 specify the operating mode, M9 specifies the write burst mode, and M10 and M11 are reserved for future use. The mode register must be loaded when all device banks are idle, and the controller must wait the specified time before initiating the subsequent operation. Violating either of these requirements will result in unspecified operation. Burst Type Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit M3. The ordering of the accesses within a burst is determined by the burst length, the burst type, and the starting column adress, as shown in Table 7, Burst Definitions, on page 9. Burst Length Read and write accesses to the SDRAM are burst oriented, with the burst length being programmable, as shown in Figure 5, Mode Register Definition Diagram, on page 8. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths of 1, 2, 4, or 8 locations are available for both the sequential and the interleaved burst types, and a full-page burst is available for the sequential type. The full-page burst is used in conjunction with the BURST TERMINATE command to generate arbitrary burst lengths. Figure 5: Mode Register Definition 32,64 Meg x 64 SDRAM DIMMs SD8_16C32_64x64AG_C.fm - Rev. C 11/02 8 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology Inc. 256MB / 512MB (x64) 168-PIN SDRAM DIMMs Diagram Table 7: BURST LENGTH 2 4 8 Full Page (y) Burst Definitions STARTING COLUMN ADDRESS A0 0 1 A1 A0 0 0 0 1 1 0 1 1 A2 A1 A0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 n= A0-A11/9/8 (location 0 - y) ORDER OF ACCESSES WITHIN A BURST TYPE = SEQUENTIAL TYPE = INTERLEAVED 0-1 1-0 0-1 1-0 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 Cn, Cn+1, Cn+2 Cn+3, Cn+4... ...Cn-1, Cn... 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 Not Supported NOTE: 1. For full-page accesses: y = 1,024 2. For a burst length of two, A1–A9 select the block of two burst; A0 selects the starting column within the block. 3. For a burst length of four, A2–A9 select the block of four burst; A0–A1 select the starting column within the block. 4. For a burst length of eight, A3–A9 select the block of eight burst; A0–A2 select the starting column within the block. 5. For a full-page burst, the full row is selected and A0–A9 select the starting column. 6. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 7. For a burst length of one, A0–A9 select the unique column to be accessed, and Mode Register bit M3 is ignored. For a full-page burst, the full row is selected and A0–A8 select the starting column. 32,64 Meg x 64 SDRAM DIMMs SD8_16C32_64x64AG_C.fm - Rev. C 11/02 9 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology Inc. 256MB / 512MB (x64) 168-PIN SDRAM DIMMs CAS Latency Operating Mode The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to two or three clocks. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge n + m. The DQs will start driving as a result of the clock edge one cycle earlier (n + m - 1), and provided that the relevant access times are met, the data will be valid by clock edge n + m. For example, assuming that the clock cycle time is such that all relevant access times are met, if a READ command is registered at T0 and the latency is programmed to two clocks, the DQs will start driving after T1 and the data will be valid by T2, as shown in Figure 6, CAS Latency Diagram. Table 8, CAS Latency Table, indicates the operating frequencies at which each CAS latency setting can be used. Reserved states should not be used as unknown operation or incompatibility with future versions may result. The normal operating mode is selected by setting M7 and M8 to zero; the other combinations of values for M7 and M8 are reserved for future use and/or test modes. The programmed burst length applies to both READ and WRITE bursts. Test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result. Write Burst Mode When M9 = 0, the burst length programmed via M0– M2 applies to both READ and WRITE bursts; when M9 = 1, the programmed burst length applies to READ bursts, but write accesses are single-location (nonburst) accesses. Table 8: ALLOWABLE OPERATING CLOCK FREQUENCY (MHZ) Figure 6: CAS Latency Diagram T0 T1 T2 T3 READ NOP NOP CLK COMMAND tLZ CAS Latency Table SPEED CAS LATENCY = 2 CAS LATENCY = 3 -13E -133 -10E £ 133 £ 100 £ 100 £ 143 £ 133 NA tOH DOUT DQ tAC CAS Latency = 2 T0 T1 T2 T3 T4 READ NOP NOP NOP CLK COMMAND tLZ tOH DOUT DQ tAC CAS Latency = 3 DON’T CARE UNDEFINED 32,64 Meg x 64 SDRAM DIMMs SD8_16C32_64x64AG_C.fm - Rev. C 11/02 10 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology Inc. 256MB / 512MB (x64) 168-PIN SDRAM DIMMs Commands The Truth Table provides a quick reference of available commands. This is followed by written description of each command. For a more detailed descrip- Table 9: tion of commands and operations, refer to the 256Mb SDRAM component data sheet. Truth Table – SDRAM Commands and DQMB Operation CKE is HIGH for all commands shown except SELF REFRESH; notes appear following the Truth Table NAME (FUNCTION) COMMAND INHIBIT (NOP) NO OPERATION (NOP) ACTIVE (Select bank and activate row) READ (Select bank and column, and start READ burst) WRITE (Select bank and column, and start WRITE burst) BURST TERMINATE PRECHARGE (Deactivate row in bank or banks) AUTO REFRESH or SELF REFRESH (Enter self refresh mode) LOAD MODE REGISTER Write Enable/Output Enable Write Inhibit/Output High-Z CS# RAS# CAS# WE# DQMB ADDR DQ NOTES H L L L L X H L H H X H H L L X H H H L X X X L/H L/H X X Bank/Row Bank/Col Bank/Col X X X X Valid 1 2 2 L L L H L L H H L L L H X X X X Code X Active X X 3 4, 5 L – – L – – L – – L – – X L H Op-code – – X Active High-Z 6 7 7 NOTE: 1. A0–A12 provide row address; BA0–BA1 determine which device bank is made active. 2. A0–A9 provide column address; A10 HIGH enables the auto-precharge feature (nonpersistent), while A10 LOW disables the auto-precharge feature; BA0-BA1 determine which device bank is being read from or written to. 3. A10 LOW: BA0–BA1 determine which device bank is being precharged. A10 HIGH: all device banks are precharged and BA0, BA1 are “Don’t Care.” 4. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW. 5. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE. 6. A0–A11 define the op-code written to the mode register and A12 should be driven LOW. 7. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay). 32,64 Meg x 64 SDRAM DIMMs SD8_16C32_64x64AG_C.fm - Rev. C 11/02 11 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology Inc. 256MB / 512MB (x64) 168-PIN SDRAM DIMMs Absolute Maximum Ratings Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the opera- tional sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Voltage on VDD, VDDQ Supply Relative to VSS . . . . . . . . . . . . . . . . . . . . . -1V to +4.6V Voltage on Inputs NC or I/O Pins Relative to VSS . . . . . . . . . . . . . . . . . . . . -1V to +4.6V Operating Temperature TA (Commercial) . . . . . . . . . . . . . . . . .. 0°C to +70°C TA (Industrial). . . . . . . . . . . . . . . . . .. -40°C to +85°C Storage Temperature (plastic) . . . . . . -55°C to +150°C Power Dissipation, 256MB . . . . . . . . . . . . . . . . . . . . 8W Power Dissipation, 512MB . . . . . . . . . . . . . . . . . . . 16W Table 10: DC Electrical Characteristics and Operating Conditions – 256MB Module Notes: 1, 5, 6; notes appear on page 17; VDD, VDDQ = +3.3V ±0.3V PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Logic 1; All inputs INPUT LOW VOLTAGE: Logic 0; All inputs INPUT LEAKAGE CURRENT: Command and Address Any input 0V £ VIN £ VDD Inputs, CKE (All other pins not under test = 0V) CK, S# DQ, DQMB OUTPUT LEAKAGE CURRENT: DQ pins are disabled; 0V £ VOUT £ VDDQ OUTPUT LEVELS: Output High Voltage (IOUT = -4mA) Output Low Voltage (IOUT = 4mA) VDD, VDDQ VIH VIL 3 2 -0.3 -40 3.6 VDD + 0.3 0.8 40 V V V µA 22 22 33 IOZ -20 -5 -5 20 5 5 µA µA µA 33 VOH VOL 2.4 – – 0.4 V V II Table 11: DC Electrical Characteristics and Operating Conditions – 512MB Module Notes: 1, 5, 6; notes appear on page 17; VDD, VDDQ = +3.3V ±0.3V PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Logic 1; All inputs INPUT LOW VOLTAGE: Logic 0; All inputs INPUT LEAKAGE CURRENT: Command and Address Any input 0V £ VIN £ VDD Inputs, CKE (All other pins not under test = 0V) CK, S# DQ, DQMB OUTPUT LEAKAGE CURRENT: DQ pins are disabled; 0V £ VOUT £ VDDQ OUTPUT LEVELS: Output High Voltage (IOUT = -4mA) Output Low Voltage (IOUT = 4mA) VDD, VDDQ VIH VIL 3 2 -0.3 -80 3.6 VDD + 0.3 0.8 80 V V V µA 22 22 33 II IOZ -20 -10 -10 20 10 10 µA µA µA 33 VOH VOL 2.4 – – 0.4 V V 32,64 Meg x 64 SDRAM DIMMs SD8_16C32_64x64AG_C.fm - Rev. C 11/02 12 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology Inc. 256MB / 512MB (x64) 168-PIN SDRAM DIMMs Table 12: IDD Specifications and Conditions – 256MB Module Notes: 1, 5, 6, 11, 13; notes appear on page 17; VDD, VDDQ = +3.3v ±0.3v; SDRAM component values only MAX PARAMETER/CONDITION SYMBOL OPERATING CURRENT: Active Mode; Burst = 2; READ or WRITE; t RC = tRC (MIN) STANDBY CURRENT: Power-Down Mode; All device device banks idle; CKE = LOW STANDBY CURRENT: Active Mode;CKE = HIGH; CS# = HIGH; All device banks active after tRCD met; No accesses in progress OPERATING CURRENT: Burst Mode; Continuous burst; READ or WRITE; All device banks active t AUTO REFRESH CURRENT RFC = tRFC (MIN) CKE = HIGH; CS# = HIGH t RFC = 7.8125µs SELF REFRESH CURRENT: CKE £ 0.2V IDD1 -13E -133 -10E 1,080 1,080 1,080 UNITS NOTES mA 3, 18,19, 22 IDD2 16 16 16 mA 22 IDD3 320 320 320 mA 3, 12, 19, 22 IDD4 1,080 1,080 1,080 mA 3, 18, 19, 22 IDD5 2,280 2,160 2,160 mA 3, 12 IDD6 28 28 28 mA 18, 19, 22, 31 IDD7 20 20 20 mA 4 Table 13: IDD Specifications and Conditions – 512MB Module Notes: 1, 6, 11, 13; notes appear on page 17; VDD, VDDQ = +3.3V ±0.3V; SDRAM component values only MAX PARAMETER/CONDITION SYMBOL OPERATING CURRENT: Active Mode; Burst = 2; READ or WRITE; RC = tRC (MIN) STANDBY CURRENT: Power-Down Mode; All device device banks idle; CKE = LOW STANDBY CURRENT: Active Mode; CKE = HIGH; CS# = HIGH; All device banks active after tRCD met; No accesses in progress OPERATING CURRENT: Burst Mode; Continuous burst; READ or WRITE; All device banks active t AUTO REFRESH CURRENT RFC = tRFC (MIN) IDD1a -13E -133 -10E 1,096 1,016 1,016 UNITS NOTES mA 3, 18,19, 22 t CKE = HIGH; CS# = HIGH t RFC = 7.8125µs SELF REFRESH CURRENT: CKE £ 0.2V IDD2b 32 32 32 mA 22 IDD3a 336 336 336 mA 3, 12, 19, 22 mA 3, 18, 19, 22 IDD4a 1,096 1,096 1,096 IDD5b 4,560 4,320 4,320 mA 3, 12 b 56 56 56 mA 18, 19, 22, 31 IDD7b 40 40 40 mA 4 IDD6 NOTE: a - Value calculated as one module bank in this condition, and all other module banks in Power-Down Mode (IDD2). b - Value calculated reflects all module banks in this condition. 32,64 Meg x 64 SDRAM DIMMs SD8_16C32_64x64AG_C.fm - Rev. C 11/02 13 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology Inc. 256MB / 512MB (x64) 168-PIN SDRAM DIMMs . Table 14: Capacitance – 256MB Module Note 2; notes appear on page 17 PARAMETER Input Capacitance: A0-A12, BA0, BA1, RAS#, CAS#, WE# Input Capacitance: CK Input Capacitance: S# Input Capacitance: CKE Input Capacitance: DQMB Input/Output Capacitance: SCL, SA, SDA Input/Output Capacitance: DQ SYMBOL MIN MAX UNITS CI1 CI2 CI3 CI4 CI5 CI 6 CI0 20 13.3 10 20 2.5 – 4 30.4 17.3 15.2 30.4 3.8 10 6 pF pF pF pF pF pF pF SYMBOL MIN MAX UNITS CI 1 CI 2 CI 3 CI 4 CI 5 CI 6 CIO 40 13.3 10 20 5 – 8 60.8 17.3 15.2 30.4 7.6 10 12 pF pF pF pF pF pF pF Table 15: Capacitance – 512MB Module Note 2; notes appear on page 17 PARAMETER Input Capacitance: A0-A12, BA0, BA1, RAS#, CAS#, WE# Input Capacitance: CK Input Capacitance: S# Input Capacitance: CKE Input Capacitance: DQMB Input/Output Capacitance: SCL, SA, SDA Input/Output Capacitance: DQ 32,64 Meg x 64 SDRAM DIMMs SD8_16C32_64x64AG_C.fm - Rev. C 11/02 14 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology Inc. 256MB / 512MB (x64) 168-PIN SDRAM DIMMs Table 16: Electrical Characteristics and Recommended AC Operating Conditions Notes: 5, 6, 8, 9, 11; notes appear on page 17 Module AC timing parameters comply with PC100 and PC133 Design Specs, based on component parameters ACCHARACTERISTICS -13E PARAMETER Access timefrom CLK (pos.edge) SYMBOL CL=3 t AC(3) CL=2 t AC(2) MIN -133 MAX MIN 5.4 -10E MAX MIN 5.4 5.4 6 MAX UNITS NOTES 6 ns 27 6 ns Address hold time t AH 0.8 Address setup time t AS 1.5 1.5 2 ns CLK high-level width t CH 2.5 2.5 3 ns CLK low-level width t CL 2.5 2.5 3 ns CK(3) Clock cycle time 0.8 1 ns CL=3 t 7 7.5 8 ns 23 CL = 2 t 7.5 10 10 ns 23 CK(2) CKE hold time t CKH 0.8 0.8 1 ns CKE setup time t CKS 1.5 1.5 2 ns CS#, RAS#, CAS#, WE#, DQM hold time t CMH 0.8 0.8 1 ns CS#, RAS#, CAS#, WE#, DQM setup time t CMS 1.5 1.5 2 ns t DH 0.8 0.8 1 ns t 1.5 1.5 2 ns Data-in hold time Data-in setup time Data-out high-impedance time DS CL = 3 t 5.4 5.4 6 ns 10 CL = 2 t 5.4 6 6 ns 10 HZ(3) HZ(2) Data-out low-impedance time t LZ 1 1 1 ns Data-out hold time (load) t OH 3 3 3 ns Data-out hold time (no load) t OHN 1.8 1.8 1.8 ns 28 ACTIVE to PRECHARGE command t ns 29 ACTIVE to ACTIVE command period ACTIVE to READ or WRITE delay t RAS 37 t RC 60 66 70 ns RCD 15 20 20 ns Refresh period (8,192 rows) t AUTOREFRESH period t 44 64 REF PRECHARGE command period 120,000 50 64 120,000 64 ms RFC 66 66 70 ns t RP 15 20 20 ns RRD 14 15 20 ns ACTIVE bank a to ACTIVE bank b command Transition time t WRITE recovery time t Exit SELF REFRESH to ACTIVE command t 32,64 Meg x 64 SDRAM DIMMs SD8_16C32_64x64AG_C.fm - Rev. C 11/02 120,000 T 0.3 WR 1 CLK + 7ns 14 67 t XSR 1.2 0.3 1 CLK + 7.5ns 15 75 15 1.2 0.3 1 CLK + 7ns 15 80 1.2 ns 7 ns 24 ns ns 25 20 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology Inc. 256MB / 512MB (x64) 168-PIN SDRAM DIMMs . Table 17: AC Functional Characteristics Notes: 5, 6, 7, 8, 9, 11; notes appear on page 17 PARAMETER SYMBOL -13E -133 -10E CCD 1 1 t READ/WRITE command to READ/WRITE command UNITS NOTES 1 t 17 14 CK CKED 1 1 1 t CKE to clock enable or power-down exit setup mode t PED 1 1 1 t 14 DQM to input data delay t DQD 0 0 0 t 17 DQM to data mask during WRITEs t DQM 0 0 0 t 17 DQMto data high-impedance during READs t DQZ 2 2 2 t 17 WRITE command to input data delay t t CKE to clock disable or power-down entry mode CK CK CK CK CK DWD 0 0 0 t 17 Data-into ACTIVE command t DAL 4 5 4 t 15, 21 Data-into PRECHARGE command t DPL 2 2 2 t 16, 21 Last data-in to burst STOP command t BDL 1 1 1 t 17 Last data-in to new READ/WRITE command t 1 1 1 t 17 Lastdata-into PRECHARGE command t RDL 2 2 2 t 16, 21 LOADMODEREGISTER command to ACTIVE or REFRESH command Data-out to high-impedance from PRECHARGE CL = 3 command CL = 2 t MRD 2 2 2 t 26 t ROH(3) 3 3 3 t 17 t 2 2 2 t 17 32,64 Meg x 64 SDRAM DIMMs SD8_16C32_64x64AG_C.fm - Rev. C 11/02 CDL ROH(2) 16 CK CK CK CK CK CK CK CK CK Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology Inc. 256MB / 512MB (x64) 168-PIN SDRAM DIMMs Notes 1. All voltages referenced to VSS. 2. This parameter is sampled. VDD, VDDQ = +3.3V; TA = 25°C; pin under test biased at 1.4; f = 1 MHz. 3. IDD is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the outputs open. 4. Enables on-chip refresh and address counters. 5. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range is ensured (Commercial Temperature: 0°C £ TA +70°C and Industrial Temperature: -40°C £ TA £ +85°C). 6. An initial pause of 100µs is required after power-up, followed by two AUTO REFRESH commands, before proper device operation is ensured. (VDD and VDDQ must be powered up simultaneously. VSS and VSSQ must be at same potential.) The two AUTO REFRESH command wake-ups should be repeated any time the tREF refresh requirement is exceeded. 7. AC characteristics assume tT = 1ns. 8. In addition to meeting the transition rate specification, the clock and CKE must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner. 9. Outputs measured at 1.5V with equivalent load: 16. Timing actually specified by tWR. 17. Required clocks are specified by JEDEC functionality and are not dependent on any timing parameter. 18. The IDD current will increase or decrease proportionally according to the amount of frequency alteration for the test condition. 19. Address transitions average one transition every two clocks. 20. CLK must be toggled a minimum of two times during this period. 21. Based on tCK = 10ns for -10E, and tCK = 7.5ns for 133 and -13E. 22. VIH overshoot: VIH (MAX) = VDDQ + 2V for a pulse width £ 3ns, and the pulse width cannot be greater than one third of the cycle rate. VIL undershoot: VIL (MIN) = -2V for a pulse width £ 3ns. 23. The clock frequency must remain constant (stable clock is defined as a signal cycling within timing constraints specified for the clock pin) during access or precharge states (READ, WRITE, including tWR, and PRECHARGE commands). CKE may be used to reduce the data rate. 24. Auto precharge mode only. The precharge timing budget (tRP) begins 7ns for -13E; 7.5ns for -133 and 7ns for -10E after the first clock delay, after the last WRITE is executed. May not exceed limit set for precharge mode. 25. Precharge mode only. 26. JEDEC and PC100 specify three clocks. 27. tAC for -133/-13E at CL = 3 with no load is 4.6ns and is guaranteed by design. 28. Parameter guaranteed by design. 29. The value of tRAS used in -13E speed grade module SPDs is calculated from tRC - tRP = 45ns. 30. For -10E, CL= 2 and tCK = 10ns; for -133, CL = 3 and tCK = 7.5ns; for -13E, CL = 2 and tCK = 7.5ns. 31. CKE is HIGH during refresh command period t RFC (MIN) else CKE is LOW. The IDD6 limit is actually a nominal value and does not result in a fail value. 32. Leakage number reflects the worst-case leakage possible through the module pin, not what each memory device contributes. 33. Leakage number reflects the worst-case leakage possible through the module pin, not what each memory device contributes. Q 50pF 10. tHZ defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL. The last valid data element will meet t OH before going High-Z. 11. AC timing and IDD tests have VIL = 0V and VIH = 3V, with timing referenced to 1.5V crossover point. If the input transition time is longer than 1ns, then the timing is referenced at VIL (MAX) and VIH (MIN) and no longer at the 1.5V crossover point. 12. Other input signals are allowed to transition no more than once every two clocks and are otherwise at valid VIH or VIL levels. 13. IDD specifications are tested after the device is properly initialized. 14. Timing actually specified by tCKS; clock(s) specified as a reference only at minimum cycle rate. 15. Timing actually specified by tWR plus tRP; clock(s) specified as a reference only at minimum cycle rate. 32,64 Meg x 64 SDRAM DIMMs SD8_16C32_64x64AG_C.fm - Rev. C 11/02 17 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology Inc. 256MB / 512MB (x64) 168-PIN SDRAM DIMMs SPD Clock and Data Conventions SPD Acknowledge Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions (as shown in Figure 7 and Figure 8). Acknowledge is a software convention used to indicate successful data transfers. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle, the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data (as shown in Figure 9). The SPD device will always respond with an acknowledge after recognition of a start condition and its slave address. If both the device and a WRITE operation have been selected, the SPD device will respond with an acknowledge after the receipt of each subsequent eight bit word. In the read mode the SPD device will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is generated by the master, the slave will continue to transmit data. If an acknowledge is not detected, the slave will terminate further data transmissions and await the stop condition to return to standby power mode. SPD Start Condition All commands are preceded by the start condition, which is a HIGH-to-LOW transition of SDA when SCL is HIGH. The SPD device continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met. SPD Stop Condition All communications are terminated by a stop condition, which is a LOW-to-HIGH transition of SDA when SCL is HIGH. The stop condition is also used to place the SPD device into standby power mode. Figure 7: Data Validity Figure 8: Definition of Start and Stop SCL SCL SDA SDA DATA STABLE DATA CHANGE DATA STABLE START BIT STOP BIT Figure 9: Acknowledge Response From Receiver SCL from Master 8 9 Data Output from Transmitter Data Output from Receiver Acknowledge 32,64 Meg x 64 SDRAM DIMMs SD8_16C32_64x64AG_C.fm - Rev. C 11/02 18 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology Inc. 256MB / 512MB (x64) 168-PIN SDRAM DIMMs Table 18: EEPROM Device Select Code The most significant bit (b7) is sent first DEVICE TYPE IDENTIFIER Memory Area Select Code (two arrays) Protection Register Select Code CHIP ENABLE RW b7 b6 b5 b4 b3 b2 b1 b0 1 0 0 1 1 1 0 0 SA2 SA2 SA1 SA1 SA0 SA0 RW RW Table 19: EEPROM Operating Modes MODE RW BIT WC BYTES Current Address Read RandomAddressRead 1 0 VIH or VIL 1 VIH or VIL Sequential Read Byte Write Page Write 1 1 0 0 VIH or VIL VIH or VIL VIL VIL INITIAL SEQUENCE Start, Device Select, RW = 1 Start, Device Select, RW= 0, Address RESTART, Device Select, RW= 1 1 ³1 1 £ 16 Similar to Current or Random Address Read START, Device Select, RW = 0 START, Device Select, RW = 0 Table 20: SERIAL Presence-Detect EEPROM DC Operating Conditions VDD = +3.3V ±0.3V; All voltages referenced to VSS PARAMETER/CONDITION SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Logic 1; All inputs INPUT LOW VOLTAGE: Logic 0; All inputs OUTPUT LOW VOLTAGE: IOUT = 3mA INPUT LEAKAGE CURRENT: VIN = GND to VDD OUTPUT LEAKAGE CURRENT: VOUT = GND to VDD STANDBY CURRENT: SCL = SDA = VDD - 0.3V; All other inputs = GND or 3.3V ±10% POWER SUPPLY CURRENT: SCL Clock frequency = 100 KHz 32,64 Meg x 64 SDRAM DIMMs SD8_16C32_64x64AG_C.fm - Rev. C 11/02 19 SYMBOL MIN MAX UNITS VDD VIH VIL VOL ILI ILO ICCS 3 VDD x 0.7 -1 – – – – 3.6 VDD + 0.5 VDD x 0.3 0.4 10 10 30 V V V V µA µA µA ICC Write ICC Read – – 3 1 mA Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology Inc. 256MB / 512MB (x64) 168-PIN SDRAM DIMMs SPD EEPROM TIMING DIAGRAM tF t HIGH tR t LOW SCL t SU:STA t HD:STA t SU:DAT t HD:DAT t SU:STO SDA IN t DH t AA t BUF SDA OUT UNDEFINED Table 21: Serial Presence-Detect EEPROM AC Operating Conditions VDD = +3.3V ±0.3V; All voltages referenced to VSS PARAMETER/CONDITION SYMBOL MIN MAX UNITS SCL LOW to SDA data-out valid t AA 0.3 3.5 µs Time the bus must be free before a new transition can start Data-out hold time t BUF 4.7 – µs t 300 DH ns 300 t SDA and SCL fall time F ns Data-in hold time t HD:DAT 0 µs Start condition hold time t HD:STA 4 µs t 4 µs ClockHIGHperiod HIGH 100 ns R 1 µs SCL 100 KHz t Noise suppression time constant at SCL, SDA inputs Clock LOW period t I 4.7 LOW t SDA and SCL rise time f SCL clock frequency µs SU:DAT 250 ns Start condition setup time t SU:STA 4.7 µs Stop condition setup time t SU:STO 4.7 µs Data-in setup time t WRITE cycle time t WRC NOTES 10 ms 1 NOTE: 1. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a write sequence to the end of the EEPROM internal erase/program cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resistor, and the EEPROM does not respond to its slave address. 32,64 Meg x 64 SDRAM DIMMs SD8_16C32_64x64AG_C.fm - Rev. C 11/02 20 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology Inc. 256MB / 512MB (x64) 168-PIN SDRAM DIMMs Table 22: Serial Presence-Detect Matrix VDD = +3.3V ±0.3V; “1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW” BYTE 0 1 2 3 4 5 6 7 8 9 ENTRY (VERSION) DESCRIPTION MT8LSDT3264A(I) MT16LSDT6464A(I) 128 256 SDRAM 13 10 1 or 2 64 0 LVTTL 7ns (-13E) 7.5ns (-133) 8ns (-10E) 5.4ns (-13E/-133) 6ns (-10E) 80 08 04 0D 0A 01 40 00 01 70 75 80 54 60 80 08 04 0D 0A 02 40 00 01 70 75 80 54 60 NONPARITY 7.8125µs/SELF 8 NONE 1 00 82 08 00 01 00 82 08 00 01 SDRAM CYCLE TIME , tCK (CAS LATENCY = 2) 10 (-133/-10E) A0 1, 2, 4, 8, PAGE 4 2, 3 0 0 UNBUFFERED 0E 7.5ns (13E) 10ns (-133/-10E) 8F 04 06 01 01 00 0E 75 A0 8F 04 06 01 01 00 0E 75 A0 24 SDRAMACCESSFROMCLK, tAC (CAS LATENCY = 2) 5.4ns (-13E) 6ns (-133/-10E) 54 60 54 60 25 SDRAM CYCLE TIME, tCK (CAS LATENCY = 1) 00 00 26 SDRAM ACCESS FROM CLK, tAC (CAS LATENCY = 1) 00 00 27 MINIMUM ROW PRECHARGE TIME, tRP 28 MINIMUM ROW ACTIVE TO ROW ACTIVE, tRRD 29 MINIMUM RAS# TO CAS# DELAY, tRCD 30 MINIMUM RAS# PULSE WIDTH, tRAS (See note 1) 0F 14 0E 0F 14 0F 14 2D 2C 32 0F 14 0E 0F 14 0F 14 2D 2C 32 10 11 12 13 14 15 16 17 18 19 20 21 22 23 NUMBER OF BYTES USED BY MICRON TOTAL NUMBER OF SPD MEMORY BYTES MEMORY TYPE NUMBER OF ROWADDRESSES NUMBER OF COLUMN ADDRESSES NUMBER OF MODULE BANKS MODULE DATA WIDTH MODULE DATA WIDTH (continued) MODULE VOLTAGE INTERFACE LEVELS SDRAM CYCLE TIME, tCK (CAS LATENCY = 3) SDRAM ACCESS FROM CLK, tAC (CAS LATENCY = 3) MODULE CONFIGURATION TYPE REFRESH RATE/TYPE SDRAM WIDTH (PRIMARY SDRAM) ERROR-CHECKING SDRAM DATA WIDTH MINIMUM CLOCK DELAY FROM BACK-TO-BACK RANDOM COLUMN ADDRESSES,tCCD BURST LENGTHS SUPPORTED NUMBER OF BANKS ONS DRAM DEVICE CAS LATENCIES SUPPORTED CS LATENCY WE LATENCY SDRAM MODULE ATTRIBUTES SDRAM DEVICE ATTRIBUTES:GENERAL 32,64 Meg x 64 SDRAM DIMMs SD8_16C32_64x64AG_C.fm - Rev. C 11/02 21 15ns (-13E) 20ns (-133/-10E) 14ns (-13E) 15ns (-133) 20ns (-10E) 15ns (-13E) 20ns (-133/-10E) 45ns (-13E) 44ns (133) 50ns (-10E) Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology Inc. 256MB / 512MB (x64) 168-PIN SDRAM DIMMs Table 22: Serial Presence-Detect Matrix (Continued) VDD = +3.3V ±0.3V; “1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW” BYTE ENTRY (VERSION) DESCRIPTION 31 32 MODULE BANK DENSITY 33 COMMAND AND ADDRESS HOLD TIME, tAH, tCMH 34 DATA SIGNAL INPUT SETUP TIME, tDS 35 DATA SIGNAL INPUT HOLD TIME, tDH COMMAND AND ADDRESS SETUP TIME, tAS, tCMS 36-61 62 63 RESERVED SPD REVISION CHECKSUM FOR BYTES 0-62 64 65-71 72 73-90 91 92 93 94 95-98 99-125 126 MANUFACTURER’S JEDEC ID CODE MANUFACTURER’S JEDEC ID CODE(CONT.) MANUFACTURING LOCATION MODULE PART NUMBER (ASCII) PCB IDENTIFICATION CODE IDENTIFICATION CODE (CONT.) YEAR OF MANUFACTURE IN BCD WEEK OF MANUFACTURE IN BCD MODULE SERIAL NUMBER MANUFACTURER-SPECIFIC DATA (RSVD) SYSTEM FREQUENCY 127 256MB 1.5ns (-13E/-133) 2ns (-10E) 0.8ns (-13E/-133) 1ns (-10E) 1.5ns (-13E/-133) 2ns (-10E) 0.8ns (-13E/-133) 1ns (-10E) REV. 1.2 (-13E) (-133) (-10E) MICRON 0 100 MHz (-13E/ -133/-10E) SDRAM COMPONENT & CLOCK DETAIL MT8LSDT3264A(I) MT16LSDT6464A(I) 40 15 20 08 10 15 20 08 10 00 12 8B D1 19 2C FF 01 - 06 Variable Data 01-04 00 Variable Data Variable Data Variable Data 40 15 20 08 10 15 20 08 10 00 12 8C D2 1A 2C FF 01 - 06 Variable Data 01-04 00 Variable Data Variable Data Variable Data 64 64 AF FF NOTE: 1. The value of tRAS used for -13E modules is calculated from tRC - tRP. Actual device spec. value is 37ns. 32,64 Meg x 64 SDRAM DIMMs SD8_16C32_64x64AG_C.fm - Rev. C 11/02 22 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology Inc. 256MB / 512MB (x64) 168-PIN SDRAM DIMMs Figure 10: 256MB Module Dimensions STANDARD PCB FRONT VIEW .125 (3.18) MAX 5.256 (133.50) 5.244 (133.20) .079 (2.00) R (2X) U1 U2 U4 U3 U7 U6 U8 U9 .118 (3.00) (2X) 1.380 (35.05) 1.370 (34.80) .700 (17.78) TYP U10 .118 (3.00) TYP .250 (6.35) TYP .118 (3.00) TYP 1.661 (42.18) 2.625 (66.68) .054 (1.37) .046 (1.17) .128 (3.25) (2X) .118 (3.00) .039 (1.00)R (2X) .039 (1.00) TYP .050 (1.27) TYP PIN 84 (PIN 168 ON BACKSIDE) PIN 1 (PIN 85 ON BACKSIDE) 4.550 (115.57) LOW PROFILE PCB .125 (3.18) MAX FRONT VIEW 5.256 (133.50) 5.244 (133.20) .079 (2.00) R (2X) U10 U1 U2 U4 U3 U6 U7 U8 U9 1.131 (28.73) .700 (17.78) 1.119 (28.42) TYP .118 (3.00) (2X) .118 (3.00) TYP .250 (6.35) TYP .118 (3.00) TYP 1.661 (42.18) .039 (1.00)R (2X) 2.625 (66.68) PIN 1 (PIN 85 ON BACKSIDE) .128 (3.25) (2X) .118 (3.00) .039 (1.00) TYP .050 (1.27) TYP .054 (1.37) .046 (1.17) PIN 84 (PIN 168 ON BACKSIDE) 4.550 (115.57) NOTE: MAX All dimensions in inches (millimeters) MIN or typical where noted. 32,64 Meg x 64 SDRAM DIMMs SD8_16C32_64x64AG_C.fm - Rev. C 11/02 23 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology Inc. 256MB / 512MB (x64) 168-PIN SDRAM DIMMs Figure 11: 512MB Module Dimensions STANDARD PCB FRONT VIEW .157 (3.99) MAX 5.256 (133.50) 5.244 (133.20) .079 (2.00) R (2X) U3 U2 U1 U4 U7 U6 U8 U9 .118 (3.00) (2X) 1.380 (35.05) 1.370 (34.80) .700 (17.78) TYP U10 .118 (3.00) TYP .250 (6.35) TYP .118 (3.00) TYP 1.661 (42.18) .039 (1.00)R (2X) 2.625 (66.68) .128 (3.25) (2X) .118 (3.00) .039 (1.00) TYP .050 (1.27) TYP .054 (1.37) .046 (1.17) PIN 84 PIN 1 4.550 (115.57) BACK VIEW U12 U11 U13 U14 U17 U16 U18 U19 PIN 168 PIN 85 LOW PROFILE PCB .157 (3.99) MAX FRONT VIEW 5.256 (133.50) 5.244 (133.20) .079 (2.00) R (2X) U10 U1 U3 U2 U4 U6 U7 U8 U9 1.131 (28.73) .700 (17.78) 1.119 (28.42) TYP .118 (3.00) (2X) .118 (3.00) TYP .250 (6.35) TYP .118 (3.00) TYP 1.661 (42.18) .039 (1.00)R (2X) 2.625 (66.68) .128 (3.25) (2X) .118 (3.00) .039 (1.00) TYP .050 (1.27) TYP .054 (1.37) .046 (1.17) PIN 84 PIN 1 4.550 (115.57) BACK VIEW U11 U12 U13 U14 U17 U16 PIN 168 U18 U19 PIN 85 NOTE: MAX All dimensions in inches (millimeters) MIN or typical where noted. ® 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: [email protected], Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron and the M logo are registered trademarks and the Micron logo is a trademark of Micron Technology, Inc. 32,64 Meg x 64 SDRAM DIMMs SD8_16C32_64x64AG_C.fm - Rev. C 11/02 24 ©2002, Micron Technology Inc.