MITEL MT90863AG1

MT90863
3V Rate Conversion Digital Switch
Advance Information
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
DS5034
2,048 × 512 and 512 x 512 switching among
backplane and local streams
Rate conversion between 2.048, 4.096 and
8.192Mb/s
Optioal sub-rate switch configuration for
2.048 Mb/s streams
Per-channel variable or constant throughput
delay
Compatible to HMVIP and H.100 specifications
Automatic frame offset delay measurement
Per-stream frame delay offset programming
Per-channel message mode
Per-channel direction control
Per-channel high impedance output control
Non-multiplexed microprocessor interface
Connection memory block programming
3.3V local I/O with 5V tolerant inputs and
TTL-compatible outputs
IEEE-1149.1 (JTAG) Test Port
Applications
•
•
•
•
Medium and large switching platforms
CTI application
Voice/data multiplexer
Support ST-BUS, HMVIP and H.100 interfaces
ODE
VDD VSS
Backplane
Interface
Multiple Buffer
Data Memory
(2,048 channels)
ISSUE 3
Ordering Information
MT90863AL1
MT90863AG1
128 Pin MQFP
144 Pin BGA
-40 to +85 C
Description
The MT90863 Rate Conversion Switch provides
switching capacities of 2,048 × 512 channels
between backplane and local streams, and 512 x
512 channels for local streams. The connected serial
inputs and outputs may have 32, 64 and 128 64kb/s
channels per frame with data rates of 2.048Mb/s,
4.096Mb/s and 8.192Mb/s respectively.
The MT90863 also offers a sub-rate switching
configuration which allows 2-bit wide 16kb/s data
channels to be switched within the device.
The device has features (such as: message mode;
input and output offset delay; direction control; and,
high
impedance
output
control)
that
are
programmable on per-stream or per-channel basis.
ODE
STio0/
FEi0
STio15/
FEi15
STio16/
FEi16
STio23/
FEi23
STio24
STo0
S/P
&
P/S
Converter
Internal
Registers
Local
Connection
Memory High/Low
(512 locations)
STio31
C16i
F0i
C4i/C8i
March 1999
Backplane
Connection
Memory
(2,048 locations)
Timing
Unit
Microprocessor Interface
F0o C4o
DS CS R/W
A7-A0
DTA D15-D0
Output
Mux
Local
Interface
P/S
Converter
Multiple Buffer
Data Memory
(512 channels)
STo15
STi0
Local
Interface
Multiple Buffer
Data Memory
(512 channels)
STo11
STo12
STo13
S/P
Converter
Test Port
STi11
STi12
STi13
STi15
RESET
IC1
IC2
TMS TDI TDO TCK TRST
Figure 1 - Functional Block Diagram
1
MT90863
VSS
C4o
F0o
VSS
C4i/C8i
F0i
VSS
C16i
VSS
ST015
STo14
STo13
STo12
STo11
STo10
STo9
STo8
VDD
VSS
STo7
STo6
STo5
STo4
STo3
STo2
STo1
STo0
ODE
VSS
VDD
STi15
STi14
Advance Information
95
93
91
89
87
85
83
81
79
77
75
73
71
69
67
65
97
63
99
61
101
59
103
57
105
55
107
53
109
51
111
128 Pin PQFP
49
113
47
115
45
117
43
119
41
121
39
123
37
125
35
127
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
STio25
STio26
STio27
STio28
STio29
STio30
STio31
VSS
TMS
TDI
TDO
TCK
TRST
IC1
RESET
IC2
VSS
A0
A1
A2
A3
A4
A5
A6
A7
DS
R/W
CS
VSS
VDD
D0
D1
VDD
STio0/FEi0
STio1/FEi1
STio2/FEi2
STio3/FEi3
STio4/FEi4
STio5/FEi5
STio6/FEi6
STio7/FEi7
VSS
VDD
STio8/FEi8
STio9/FEi9
STio10/FEi10
STio11/FEi11
STio12/FEi12
STio13/FEi13
STio14/FEi14
STio15/FEi15
VSS
VDD
STio16/FEi16
STio17/FEi17
STio18/FEi18
STio19/FEi19
STio20/FEi20
STio21/FEi21
STio22/FEi22
STio23/FEi23
VSS
VDD
STio24
Figure 2 - MQFP Pin Connections
2
33
STi13
STi12
STi11
STi10
STi9
STi8
STi7
STi6
STi5
STi4
STi3
STi2
STi1
STi0
VDD
VSS
DTA
D15
D14
D13
D12
D11
D10
D9
D8
VSS
D7
D6
D5
D4
D3
D2
MT90863
Advance Information
1
1
2
3
4
5
6
7
8
9
10
11
12
13
A
STio26 STio24 STio22 STio19 STio17 STio15 STio14 STio11 STio8 STio6 STio4 STio3
F0o
B
STio29 STio25 STio23 STio20 STio18 STio16 STio13 STio10 STio7 STio5 STio2 STio1 C4i/C8i
C
TMS STio28 STio27 STio21 VDD
VSS STio12 STio9 VDD
VSS STio0
C4o STo15
D
TDI STio31 STio30 VSS
VDD
VSS
VDD
VSS
VDD
VSS
F0i
C16i STo13
E
TDO
VSS
VSS
VDD STo14 STo12 STo11
RESET TRST
IC1
VDD
VSS
VSS
STo10 STo9
VDD
VDD
STo8 STo7
TCK
F
G
A0
VSS
IC2
TOP VIEW
VSS
H
A1
A2
A3
VDD
VSS
STo4
STo6 STo5
A5
A4
A6
VSS
VSS
VSS
STo3 STo2
A7
DS
VDD
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VDD
STo1 STo0
CS
R/W
VSS
D5
D7
D11
VSS
VDD
STi6
STi8 STi12 STi15 ODE
D0
D2
D4
D8
D10
D12
D15
STi1
STi4
STi7 STi10 STi13 STi14
D1
D3
D6
D9
D13
D14
DTA
STi0
STi2
STi3
J
K
L
M
N
1
STi5
STi9 STi11
- A1 corner is identified by metallized markings.
Figure 3 - BGA Pin Connections
Pin Description
128 MQFP
Pin#
144 BGA
Pin#
Name
Description
30,50,67, C5,C9,D5,D7,
79,97,107, D9,E10,F4,G10
117,127
,G11,H4,
K3,K4,K6,K8
K10,K11,L8
VDD
+3.3 Volt Power Supply
8,17,29,39, C6,C10,D4,D6,
49,68,78,8 D8,D10,E3,E4,
8,90,93,96, F10,F11,G2,
106,
G4,H10,J4,
116,126
J10,J11,K5
K7,K9,L3,L7
Vss
Ground
89
D12
C16i
Master Clock (5V Tolerant Input): Serial clock for shifting data in/out
on the serial streams. This pin accepts a 16.384 MHz clock.
91
D11
F0i
Master Frame Pulse (5V Tolerant Input): In ST-BUS mode, this input
accepts a 61ns wide negative frame pulse. In CT Bus mode, it accepts
a 122ns wide negative frame pulse. In HMVIP mode, it accepts a
244ns wide negative frame pulse.
3
MT90863
Advance Information
Pin Description (continued)
128 MQFP
Pin#
144 BGA
Pin#
Name
92
B13
C4i/C8i
HMVIP/CT Bus Clock (5V Tolerant Input): When HMVIP mode is
enabled, this pin accepts a 4.096MHz clock for HMVIP frame pulse
alignment. When CT Bus mode is enabled, it accepts a 8.192MHz
clock for CT frame pulse alignment.
94
A13
F0o
Frame Pulse (5V Tolerant Output): A 244ns wide negative frame
pulse that is phase locked to the master frame pulse (F0i).
95
C12
C4o
C4 Clock (5V Tolerant Output): A 4.096MHz clock that is phase
locked to the master clock (C16i).
98-105,
108-115
C11, B12, B11,
A12, A11, B10,
A10, B9, A9,
C8, B8, A8, C7,
B7, A7, A6,
118-125
B6, A5, B5, A4, STio16 - 23 Serial Input Streams 16 to 23 (5V Tolerant I/O). In 2Mb/s or 4Mb/s
B4, C4, A3, B3 FEi16 - 23 mode, these pins accept serial TDM data streams at 2.048 or 4.096
Mb/s with 32 or 64 channels per stream respectively. In HMVIP mode,
these pins have a data rate of 8.192Mb/s with 128 channels per
stream. In Frame Evaluation Mode (FEM), they are frame evaluation
inputs.
128,
1-7
A2, B2, A1, C3, STio24 - 31 Serial Input Streams 24 to 31 (5V Tolerant I/O). These pins are only
C2, B1, D3, D2
used for 2Mb/s or 4Mb/s mode. They accept serial TDM data streams
at 2.048 or 4.096 Mb/s with 32 or 64 channels per stream respectively.
4
Description
STio0 - 15 Serial Input Streams 0 to 15 / Frame Evaluation Inputs 0 to 15 (5V
FEi0 - 15 Tolerant I/O). In 2Mb/s and HMVIP modes, these pins accept serial
TDM data streams at 2.048 Mb/s with 32 channels per stream. In 4Mb/
s or 8Mb/s mode, these pins accept serial TDM data streams at 4.096
or 8.192 Mb/s with 64 or 128 channels per stream respectively. In
Frame Evaluation Mode (FEM), they are frame evaluation inputs.
9
C1
TMS
Test Mode Select (3.3V Input with internal pull-up): JTAG signal
that controls the state transitions of the TAP controller.
10
D1
TDI
Test Serial Data In (3.3V Input with internal pull-up): JTAG serial
test instructions and data are shifted in on this pin.
11
E2
TDO
Test Serial Data Out (3.3V Output): JTAG serial data is output on this
pin on the falling edge of TCK. This pin is held in a high impedance
state when JTAG scan is not enabled.
12
E1
TCK
Test Clock (5V Tolerant Input): Provides the clock to the JTAG test
logic.
13
F2
TRST
14
F3
IC1
15
F1
RESET
16
G3
IC2
Test Reset (3.3 V Input with internal pull-up): Asynchronously
initializes the JTAG TAP controller by putting it in the Test-Logic-Reset
state. This pin should be pulsed low on power-up, or held low
continuously, to ensure that the MT90863 is in the normal operation
mode.
Internal Connection 1 (3.3V Input with internal pull-down):
Connect to VSS for normal operation.
Device Reset (5V Tolerant Input): This input (active LOW) puts the
MT90863 in its reset state. This clears the device’s internal counters
and registers. It also brings microport data bus STio0 - 31 and STo0 15 to a high impedance state.
Internal Connection 2 (3.3V Input):
Connect to VSS for normal operation.
MT90863
Advance Information
Pin Description (continued)
128 MQFP
Pin#
144 BGA
Pin#
Name
18-25
G1, H1, H2,
H3, J2, J1,J3,
K1
A0 - A7
26
K2
DS
Data Strobe (5V Tolerant Input): This active low input works in
conjunction with CS to enable the read and write operations.
27
L2
R/W
Read/Write (5V Tolerant Input): This input controls the direction of
the data bus lines (D0-D15) during a microprocessor access.
28
L1
CS
Chip Select (5V Tolerant Input): Active low input used by a
microprocessor to activate the microprocessor port.
31-38,
40-47
M1, N1, M2, N2,
M3, L4, N3, L5,
M4, N4, M5,
L6, M6, N5, N6,
M7,
D0 - 7,
D8 - D15
Data Bus 0 -15 (5V Tolerant I/O): These pins form the 16-bit data bus
of the microprocessor port.
48
N7
DTA
Data Transfer Acknowledgment (5V Tolerant Three-state Output):
This active low output indicates that a data bus transfer is complete. A
pull-up resistor is required to hold a HIGH level when the pin is tristated.
51-54
N8, M8, N9,
N10
STi0 - 3
Serial Input Streams 0 to 3 (5V Tolerant Inputs): In 2Mb/s or
Subrate Switching mode, these inputs accept data rates of 2.048 Mb/s
with 32 channels per stream. In 8Mb/s mode, these inputs accept data
rates of 8.192 Mb/s with 128 channels per stream.
55-62
M9, N11, L9,
M10, L10, N12,
M11, N13
STi4 - 11
Serial Input Streams 4 to 11 (5V Tolerant Inputs): In 2Mb/s or Subrate Switching mode, these inputs accept data rates of 2.048Mb/s
with 32 channels per stream.
63
L11
STi12
Serial Input Streams 12 (5V Tolerant Input): In 2Mb/s mode, this
input accepts data rate of 2.048Mb/s with 32 channels per stream
respectively. In Sub-rate Switching mode, this pin accepts 2.048Mb/s
with 128 channels per stream for Sub-rate switching application.
64-66
M12, M13, L12
69
L13
ODE
Output Drive Enable (5V Tolerant Input): This is the output enable
control for the STo0 to STo15 serial outputs and STio0 to STio31 serial
bidirectional outputs.
70-73
K13, K12, J13,
J12
STo0 - 3
Serial Output Streams 0 to 3 (5V Tolerant Three-state Outputs): In
2Mb/s or Sub-rate Switching mode, these outputs have data rates of
2.048 Mb/s with 32 channels per stream respectively. In 8Mb/s mode,
these outputs have data rates of 8.192 Mb/s with 128 channels per
stream
74-77,
80-83
H11, H13, H12,
G13, G12, F13,
F12, E13
STo4 - 7, Serial Output Streams 4 to 11 (5V Tolerant Three-state Outputs):
STo8 - 11 In 2Mb/s or Sub-rate Switching mode, these outputs have data rates of
2.048Mb/s with 32 channels per stream
Description
Address 0 - 7 (5V Tolerant Input): These lines provide the A0 to A7
address lines to the internal memories.
STi13 - 15 Serial Input Streams 13 to 15 (5V Tolerant Inputs): In 2Mb/s mode,
these inputs accept a data rate of 2.048Mb/s with 32 channels per
stream.
5
MT90863
Advance Information
Pin Description (continued)
128 MQFP
Pin#
144 BGA
Pin#
Name
Description
84
E12
STo12
Serial Output Streams 12 (5V Tolerant Three-state Output): In
2Mb/s mode, this output has data rate of 2.048Mb/s with 32 channels
per stream. In Sub-rate Switching mode, this pin has data rate of
2.048Mb/s with 128 channels per stream for Sub-rate switching
application.
85-87
D13, E11, C13
STo13 - 15 Serial Output Streams 13 to 15 (5V Tolerant Three-state Outputs):
In 2Mb/s mode, these outputs have a data rate of 2.048Mb/s with 32
channels per stream.
Device Overview
The Rate conversion Switch (MT90863) can switch
up to 2,048 × 512 channels while also providing a
rate conversion capability. It is designed to switch 64
kb/s PCM or N X 64 kb/s data between the
backplane and local interfaces. When the device is in
the sub-rate switching mode, 2-bit wide 16 kb/s data
channels can be switched within the device. The
device maintains frame integrity in data applications
and minimum throughput delay for voice application
on a per channel basis.
The backplane interface can operate at 2.048, 4.096
or 8.192 Mb/s, arranged in 125µs wide frames that
contain 32, 64 or 128 channels, respectively. A builtin rate conversion circuit allows users to interface
between backplane interface and the local interface
which operates at 2.048 Mb/s or 8.192 Mb/s.
By using Mitel’s message mode capability, the
microprocessor can access input and output timeslots on a per channel basis. This feature is useful
for transferring control and status information for
external circuits or other ST-Bus devices.
The frame offset calibration function allows users to
measure the frame offset delay for streams STio0 to
STio23. The offset calibration is activated by a frame
evaluation bit in the frame evaluation register. The
evaluation result is stored in the frame evaluation
registers and can be used to programme the input
offset delay for individual streams using internal
frame input offset registers.
Functional Description
A functional Block Diagram of the MT90863 is shown
in Figure 1. One end of the MT90863 is used to
interface with backplane applications, such as
HMVIP or H.100 environments, while the other end
supports the local switching environments.
6
Frame Alignment Timing
The Device Mode Selection (DMS) register allows
users to select three different frame alignment timing
modes. In ST-BUS modes, the master clock (C16i) is
always at 16.384 MHz. The frame pulse (F0i) input
accepts a negative frame pulse at 8kHz. The frame
pulse goes low at the frame boundary for 61ns. The
frame pulse output F0o provides a 244ns wide
negative frame pulse and the C4o output provides a
4.094MHz clock. These two signals are used to
support local switching applications. See Figure 4 for
the ST-BUS timings.
In CT Bus mode, the C4i/C8i pin accepts 8.192MHz
clock for the CT Bus frame pulse alignment. The F0i
is the CT bus frame pulse input. The CT frame pulse
goes low at the frame boundary for 122ns. See
Figure 5 for the CT Bus timing.
In HMVIP mode, the C4i/C8i pin accepts 4.096MHz
clock for the HMVIP frame pulse alignment. The F0i
is the HMVIP frame pulse input. The HMVIP frame
pulse goes low at the frame boundary for 244ns. See
Figure 6 for the HMVIP timing.
Table 1 describes the input timing requirements for
ST-BUS, CT Bus and HMVIP modes.
Switching Configuration
The device has four operation modes for the
backplane interface and three operation modes for
the local interface. These modes can be
programmed via the Device Mode Selection (DMS)
register. Mode selections between the backplane
and local interfaces are independent. See Table 2
and Table 3 for the selection of various operation
modes via the programming of the DMS register.
MT90863
Advance Information
F0i
C16i
F0o
C4o
STio 0 - 15
STi/STo 0 - 3
(8Mb/s mode)
Channel 0
7
0
1
6
5
4
Channel 127
3
2
1
0
6
5
4
Channel 0
STio 0 - 31
(4Mb/s mode)
7
0
6
5
4
3
2
6
0
1
0
7
0
1
Channel 0
STi12/STo12
(Sub-rate
Switching)
1
7
Channel 31
7
0
2
Channel 63
Channel 0
STio 0 - 31
STi/STo 0 - 15
(2Mb/s mode)
3
0
7
0
Bit 1
Channel 127
1
0
1
Figure 4 - ST-BUS Timing for 2, 4 and 8 Mb/s Data Streams
F0i
(CT_FRAME)
C4i/C8i
(8.192MHz)
C16i
F0o
C4o
STio 0 - 15
STi/STo 0 - 3
(8Mb/s mode)
Channel 0
0
1
7
6
5
4
Channel 127
3
2
1
0
6
5
Channel 0
STio 0 - 31
(4Mb/s mode)
0
7
6
0
7
5
4
3
2
0
1
2
1
0
7
1
0
7
Channel 31
6
1
Channel 0
STi12/STo12
(Sub-rate
Switching)
3
Channel 63
Channel 0
STio 0 - 31
STi/STo 0 - 15
(2Mb/s mode)
4
0
7
0
Bit 1
Channel 127
0
1
Figure 5 - CT Bus Mode Timing for 2, 4 and 8 Mb/s Data Streams
7
MT90863
Advance Information
F0i
(HMVIP Frame)
C4i/C8i
(4.096MHz)
C16i
F0o
C4o
Channel 0
STio 0 - 15
STi/STo 0 - 15
(2Mb/s mode)
STio 16 - 23
(8Mb/s mode)
Channel 31
7
0
6
1
Channel 0
0
1
7
6
5
4
3
Channel 127
2
1
0
6
5
Channel 0
STi12/STo12
(Sub-rate
Switching)
0
1
7
0
4
3
2
1
0
7
Channel 127
0
1
0
Bit 1
Figure 6- HMVIP Mode Timing for 2 and 8 Mb/s Data Streams
Backplane Interface
The backplane interface can be programmed to
accept data streams of 2Mb/s, 4Mb/s or 8Mb/s.
When 2Mb/s mode is enabled, STio0 to STio31 have
a data rate of 2.048Mb/s. When 4Mb/s mode is
enabled, STio0 to STio31 have a data rate of
4.096Mb/s. When 8Mb/s mode is enabled, STio0 to
STio15 have a data rate of 8.192Mb/s. When HMVIP
mode is enabled, STio0 to STio15 have a data rate
of 2.048Mb/s and STio16 to STio23 have a data rate
of 8.192Mb/s.
Table 2 describes the data rates and mode selection
for the backplane interface.
Local Interface
Three operation modes, 2Mb/s, 8Mb/s and Sub-rate
Switching mode, can be selected for the local
interface. When 2Mb/s mode is selected, STi0 to
STi15 and STo0 to STo15 have a 2.048Mb/s data
rate. When 8Mb/s mode is selected, STi0 to STi3
and STo0 to STo3 have an 8.192Mb/s data rate.
When Sub-rate Switching mode is selected, STi0 to
STi11 and STo0 to STo11 have 2.048Mb/s data with
64kb/s data channels and STi12 and STo12 have a
2.048Mb/s data rate with 16kb/s data channels.
Table 3 describes the data rates and mode selection
for the local interface.
Input Frame Offset Selection
Input frame offset selection allows the channel
alignment of individual backplane input streams, that
8
operate at 8.192Mb/s (STio0-23), to be shifted
against the input frame pulse (F0i). This feature
compensates for the variable path delays caused by
serial backplanes of variable length. Such delays can
be occur in large centralized and distributed
switching systems.
Each backplane input stream can have its own delay
offset value by programming the input delay offset
registers (DOS0 to DOS5). Possible adjustment can
range up to +4 master clock (C16i) periods forward
with resolution of half master clock period. See Table
10 and Table 11, and Figure 9, for frame input delay
offset programming.
Output Advance Offset Selection
The MT90863 allows users to advance individual
backplane output streams which operate at 8.192Mb/
s (STio0-23) by half a master clock (C16i) cycle. This
feature is useful in compensating for variable output
delays caused by various output loading conditions.
The frame output offset registers (FOR0 & FOR1)
control the output offset delays for each backplane
output stream via the OFn bit programming. Table 12
and Figure 10 detail frame output offset
programming.
Serial Input Frame Alignment Evaluation
The MT90863 provides the frame evaluation inputs,
FEi0 to FEi23, to determine different data input
delays with respect to the frame pulse F0i. By using
the frame evaluation input select bits (FE0 to FE4) of
MT90863
Advance Information
Timing Signals
ST-BUS Mode
CT Bus Mode
HMVIP Mode
F0i Width
61ns
122ns
244ns
C4i/C8i
Not Required
8.192MHz
4.096MHz
C16i
16.384MHz
F0o Width
244ns
C4o
4.096MHz
Table 1 - Timing Signals Requirements for Various Operation Modes
DMS Register Bits
Modes
Backplane Interface
Data Rate
2Mb/s, ST-BUS Mode
STio0 - 31
2.048 Mb/s
1
2Mb/s, CT Bus Mode
STio0 - 31
2.048 Mb/s
1
0
4Mb/s, ST-BUS Mode
STio0 - 31
4.096 Mb/s
0
1
1
4Mb/s, CT Bus Mode
STio0 - 31
4.096 Mb/s
1
0
0
8Mb/s, ST-BUS Mode
STio0 - 15
8.192 Mb/s
STio16 - 31
Not available
STio0 - 15
8.192 Mb/s
STio16 - 31
Not available
STio0 - 15
2.048 Mb/s
STio16 - 23
8.192 Mb/s
STio24 - 31
Not available
BMS2
BMS1
BMS0
0
0
0
0
0
0
1
1
0
1
1
8Mb/s, CT Bus Mode
0
HMVIP Mode
Table 2 - . Mode Selection for Backplane interface
DMS Register Bits
Modes
LMS1
LMS0
0
0
0
1
1
0
2Mb/s Mode
Sub-Rate
Switching
Mode
8Mb/s Mode
Local Interface
Data Rate
STi0 - 15
2.048 Mb/s
STo0 - 15
2.048 Mb/s
STi0 - 11
2.048 Mb/s
STi12
Sub-rate Switching Input Stream at 2.048 Mb/s
STi13 - 15
Not available
STo0 - 11
2.048 Mb/s
STo12
Sub-rate Switching Output Stream at 2.048Mb/s
STo13 - 15
Not available
STi0 - 3
8.192 Mb/s
STi4 - 15
Not available
STo0 - 3
8.192 Mb/s
STo4 - 15
Not available
Table 3 - . Mode Selection for Local Interface
9
MT90863
the frame alignment register (FAR), users can select
one of the twenty-four frame evaluation inputs for the
frame alignment measurement.
A measurement cycle is started by setting the start
frame evaluation (SFE) bit low for at least one frame.
Then the evaluation starts when the SFE bit in the
Internal Mode Selection (IMS) register is changed
from low to high. One frame later, the complete
frame evaluation (CFE) bit of the frame alignment
register changes from low to high to signal that a
valid offset measurement is ready to be read from
bits 0 to 9 of the FAR register. The SFE bit must be
set to zero before a new measurement cycle is
started.
The falling edge of the frame measurement signal
(FEi) is evaluated against the falling edge of the
frame pulse (F0i). Table 8 and Figure 8 describe the
frame alignment register.
Memory Block Programming
The MT90863 has two connection memories: the
backplane connection memory and the local
connection memory. The local connection memory is
partitioned into high and low parts. The IMS register
provides users with the capability of initializing the
local connection memory low and the backplane
connection memory in two frames. Bit 11 to bit 13 of
every backplane connection memory location will be
programmed with the pattern stored in bit 7 to bit 9 of
the IMS register. Bit 12 to 15 of every local
connection memory low location will be programmed
with the pattern stored in bits 3 to 6 of the IMS
register.
The block programming mode is enabled by setting
the memory block program (MBP) bit of the control
register high. When the block programming enable
(BPE) bit of the IMS register is set to high, the block
programming data will be loaded into bits 11 to 13 of
every backplane connection memory and bits 12 to
15 of every local connection memory low. The other
connection memory bits are loaded with zeros. When
the memory block programming is complete, the
device resets the BPE bit to zero. See Figure 7 for
the connection memory contents when the device is
in block programming mode.
Delay Through the MT90863
The switching of information from the input serial
streams to the output serial streams results in a
throughput delay. The device can be programmed to
perform time-slot interchange functions with different
throughput delay capabilities on a per-channel basis.
For voice applications, select variable throughput
10
Advance Information
delay to ensure minimum delay between input and
output data. In wideband data applications, select
constant throughput delay to maintain the frame
integrity of the information through the switch.
The delay through the device varies according to the
type of throughput delay selected in the LV/C and
BV/C bits of the local and backplane connection
memory as described in Table 16 and Table 19.
Variable Delay Mode (LV/C or BV/C bit = 0)
The delay in this mode is dependent only on the
combination of source and destination channels and
is independent of input and output streams.
Constant Delay Mode (LV/C bit or BV/C= 1)
In this mode a multiple data memory buffer is used
to maintain frame integrity in all switching
configurations.
Microprocessor Interface
The MT90863 provides a parallel microprocessor
interface for non-multiplexed bus structures. This
interface is compatible with Motorola non-multiplexed
buses. The required microprocessor signals are the
16-bit data bus (D0-D15), 8-bit address bus (A0-A7)
and 4 control lines (CS, DS, R/W and DTA). See
Figure 16 for Motorola non-multiplexed bus timing.
The MT90863 microprocessor port provides access
to the internal registers, connection and data
memories. All locations provide read/write access
except for the Data Memory and the Data Read
Register which are read only.
Memory Mapping
The address bus on the microprocessor interface
selects the internal registers and memories of the
MT90863. If the A7 address input is low, then the
registers are addressed by A6 to A0 as shown in
Table 4.
If the A7 is high, the remaining address input lines
are used to select the serial input or output data
streams corresponding to the subsection of memory
positions. For data memory reads, the serial inputs
are selected. For connection memory writes, the
serial outputs are selected.
The control, device mode selection and internal
mode selection registers control all the major
functions of the device. The device mode selection
register and internal mode selection register should
be programmed immediately after system power-up
MT90863
Advance Information
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
BBPD
2
BBPD
1
BBPD
0
0
0
0
0
0
0
0
0
0
0
0
Backplane Connection Memory (BCM)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
LBPD
3
LBPD
2
LBPD
1
LBPD
0
0
0
0
0
0
0
0
0
0
0
0
0
Local Connection Memory Low (LCML)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Local Connection Memory High (LCMH)
Figure 7 - Block Programming Data in the Connection Memories
A7
A6
A5
A4
A3
A2
A1
A0
0
0
0
0
0
0
0
0
Control Register, CR
0
0
0
0
0
0
0
1
Device Mode Selection Register, DMS
0
0
0
0
0
0
1
0
Internal Mode Selection Register, IMS
0
0
0
0
0
0
1
1
Frame Alignment Register, FAR
0
0
0
0
0
1
0
0
Input Offset Selection Register 0, DOS0
0
0
0
0
0
1
0
1
Input Offset Selection Register 1, DOS1
0
0
0
0
0
1
1
0
Input Offset Selection Register 2, DOS2
0
0
0
0
0
1
1
1
Input Offset Selection Register 3, DOS3
0
0
0
0
1
0
0
0
Input Offset Selection Register 4, DOS4
0
0
0
0
1
0
0
1
Input Offset Selection Register 5, DOS5
0
0
0
0
1
0
1
0
Frame Output Offset Register, FOR0
0
0
0
0
1
0
1
1
Frame Output Offset Register, FOR1
0
0
0
0
1
1
0
0
Address Buffer Register, ABR
0
0
0
0
1
1
0
1
Data Write Register, DWR
0
0
0
0
1
1
1
0
Data Read Register, DRR
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
.
1
1
0
0
.
1
1
0
0
.
1
1
0
0
.
1
1
0
1
.
0
1
Ch 0
Ch 1
.
Ch 30
Ch 31
1
1
.
1
1
0
0
.
1
1
1
1
.
1
1
0
0
.
1
1
0
0
.
1
1
0
0
.
1
1
0
0
.
1
1
0
1
.
0
1
Ch 32
Ch 33
.
Ch 126
Ch 127
(Note 1)
Location
(Note
(Note
2)
3)
Notes:
1. Bit A7 must be high for access to data and connection memory positions. Bit A7 must be low for access to registers.
2. Channels 0 to 31 are used when serial stream is at 2Mb/s.
3. Channels 0 to 127 are used when serial stream is at 8Mb/s
Table 4 - Address Memory Map
11
MT90863
Advance Information
to establish the desired switching configuration as
explained in the Frame Alignment Timing and
Switching Configurations sections.
The control register is used to control the switching
operations in the MT90863. It selects the internal
memory locations that specify the input and output
channels selected for switching.
Control register data consists of: the memory block
programming bit (MBP): the memory select bits
(MS0-2); and, the stream address bits (STA0-4). The
memory block programming bit allows users to
program the entire connection memory block, (see
Memory Block Programming section). The memory
select bits control the selection of the connection
memory or the data memory. The stream address
bits define an internal memory subsections
corresponding to serial input or serial output
streams.
The data in the DMS register consists of the local
and backplane mode selection bits (LMS0-1 and
BMS0-2) to enable various switching modes for local
and backplane interfaces respectively.
The data in the IMS register consists of block
programming bits (LBPD0-3 and BBPD0-2), block
programming enable bit (BPE), output standby bit
(OSB) and start frame evaluation bit (SFE). The
block programming enable bit allows users to
program the entire backplane and local connection
memories, (see Memory Block Programming
section). If the ODE pin is low, the OSB bit enables
(if high) or disables (if low) all ST-BUS output drivers.
If the ODE pin is high, the contents of the OSB bit is
ignored and all ST-BUS output drivers are enabled.
See Table 5 for the output high impedance control.
Address Buffer Mode
The implementation of the address buffer, data read
and data write registers allows faster memory read/
write operation for the microprocessor port. See
Table 6 and following for bit assignments.
The address buffer mode is controlled by the AB bit
in the control register. The targeted memory for data
read/write is selected by the MS0-2 bits in the control
register.
The data write register (DWR) contains the data to
be transferred to the memory. The data read register
(DRR) contains the data transferred from the
memory.
The address buffer register (ABR) allow users to
specify the read or write address by programming
the stream address bits (SA0-4) and the channel
address bits (CA0-6). Data transfer from/to the
memory is controlled by the read/write select bits
(RS, WS). The complete data access (CDA) bit
indicates the completion of data transfer between the
memory and DWR or DRR register.
Write Operation Using Address Buffer Mode
Enable the address buffer mode by setting the AB bit
from low to high. Program the DWR register with
data to be transferred to memory. Load the ABR
register with proper channel and stream information.
Change the WS bit in the ABR register from low to
high to initiate the data transfer from the DWR
register to the memory. After several master clock
cycles, the CDA bit in the ABR register changes
from low to high to signal the completion of data
transfer and resets the WS bit to low. Repeat the
above steps for subsequent memory write
operations. Disable the address buffer write
operation by setting the AB bit to low.
Read Operation Using Address Buffer Mode
Enable the address buffer mode by setting the AB bit
from low to high. Program the ABR register with
proper channel and stream information. Change the
RS bit in the ABR register from low to high to initiate
the data transfer from the memory to the DRR
I
ODE pin
OSB bit
in
IMS register
DC bit in
Backplane CM
STio0-31
Output Driver
Status
Don’t Care
Don’t Care
0
Per Channel
High Impedance
0
0
Don’t care
High Impedance
0
1
1
Enable
1
Enable
1
Don’t care
1
Enable
1
Enable
OE bit in Local CM
0
Don’t care
Table 5 -. Output High Impedance Control
12
STo0-15
Output Driver
Status
Per Channel
High Impedance
High Impedance
MT90863
Advance Information
Read/Write Address:
15
14
13
12
0
0
0
0
11
00H,
Reset Value:
10
9
8
0
AB
CT
MBP
7
0000H.
6
MS2
MS1
5
MS0
4
3
STA4 STA3
2
1
0
STA2
STA1
STA0
Bit
Name
Description
15-11
Unused
10
AB
Address Buffer. When 1, enables the address buffer, data write and data read registers for
accessing various memory locations for fast microport access. When 0, disables the address
buffer, data write & data read registers.
9
CT
Channel Tri-state. When 1, the last bit of each output channel is tri-stated for -22ns against
the channel boundary. When 0, the last bit of each channel is not tri-stated.
8
MBP
7-5
MS2-0
Memory Select Bits. These three bits are used to select connection and data memory
functions as follows:
MS2-0 Memory Selection
000
Local Connection Memory Low Read/Write,
001
Local Connection Memory High Read/Write,
010
Backplane Connection Memory Read/Write,
011
Local Data Memory Read,
100
Backplane Data Memory Read,
4-0
STA4-0
Stream Address Bits. The binary value expressed by these bits refers to the input or output
data stream, which corresponds to the subsection of memory made accessible for subsequent
operations. (STA4 = MSB, STA0 = LSB)
Must be zero for normal operation.
Memory Block Program. When 1, the connection memory block programming feature is ready
for the programming of bit 11 to 13 for backplane connection memory, bit 12 to 15 for local
connection memory low. When 0, this feature is disabled.
Table 6 - Control (CR) Register Bits
Read/Write Address:
15
14
13
12
0
0
0
Bit
Name
15 - 5
unused
4-3
LMS
2-0
BMS2-0
0
01H,
Reset Value:
11
10
9
8
0
0
0
0
0000H.
7
6
5
4
0
0
LMS1
0
3
2
1
0
LMS0 BMS2 BMS1 BMS0
Description
Reserved
Local Mode Selection Bit. The binary value expressed by these bits refers to the following
backplane interface switching modes:
LMS1-0
Local Switching Mode
00
2Mb/s ST-BUS Mode
01
2Mb/s Sub-rate Switching Mode
10
8Mb/s ST-Bus Mode
Backplane Mode Selection Bits. The binary value expressed by these bits refers to the following backplane interface switching modes:
BMS2-0
Backplane Switching Mode
000
2Mb/s ST-BUS Mode
001
2Mb/s CT Bus Mode
010
4Mb/s ST-BUS Mode
011
4Mb/s CT Bus Mode
100
8Mb/s ST-BUS Mode
101
8Mb/s CT Bus Mode
110
HMVIP Mode
Table 7 - Device Mode Selection (DMS) Register Bits
13
MT90863
register. After several master clock cycles, the CDA
bit in the ABR register changes from low to high to
signal the completion of data transfer and resets the
RS bit to low. Read the DRR register to obtain the
data transferred from the memory. Repeat the above
steps for subsequent memory read operations.
Disable the address buffer read operation by setting
the AB bit to low.
Backplane Connection Memory Control
The backplane connection memory controls the
switching configuration of the backplane interface.
Locations in the backplane connection memory are
associated with particular STio output streams.
The BV/C (Variable/Constant Delay) bit of each
backplane connection memory location allows the
per-channel selection between variable and constant
throughput delay modes for all STio channels.
In message mode, the message channel (BMC) bit
of the backplane connection memory enables (if
high) an associated STio output channel. If the BMC
bit is low, the contents of the backplane connection
memory stream address bit (BSAB) and channel
address bit (BCAB) defines the source information
(stream and channel) of the time-slot that will be
switched to the STio streams. When message mode
is enabled, only the lower half (8 least significant
bits) of the backplane connection memory is
transferred to the STio pins.
Local Connection Memory Control
The local connection memory controls the local
interface switching configuration. Local connection
memory is split into high and low parts. Locations in
local connection memory are associated with
particular STo output streams.
The L/B (Local/Backplane Select) bit of each local
connection memory location allows per-channel
selection of source streams from local or backplane
interface.
The LV/C (Variable/Constant Delay) bit of each local
connection memory location allows the per-channel
selection between variable and constant throughput
delay modes for all STo channels.
In message mode, the local connection memory
message channel (LMC) bit enables (if high) an
associated STo output channel. If the LMC bit is low,
the contents of the stream address bit (LSAB) and
the channel address bit (LCAB) of the local
connection memory defines the source information
(stream and channel) of the time-slot that will be
switched to the STo streams. When message mode
is enabled, only the lower half (8 least significant
14
Advance Information
bits) of the local connection memory low bits are
transferred to the STo pins.
When sub-rate switching is enabled, the LSR0-1 bits
in the local connection memory high define which bit
position contains the sub-rate data.
DTA Data Transfer Acknowledgment Pin
The DTA pin is driven LOW by internal logic to
indicate (to the CPU) that a data bus transfer is
complete. When the bus cycle ends, this pin drives
HIGH and then switches to the high-impedance
state. If a short or signal contention prevents the DTA
pin from reaching a valid logic HIGH, it will continue
to drive for approximately 15nsec before switching to
the high-impedance state.
Initialization of the MT90863
During power up, the TRST pin should be pulsed low,
or held low continuously, to ensure that the MT90863
is in the normal operation mode. A 5KΩ pull-down
resistor can be connected to this pin so that the
device will not enter the JTAG test mode during
power up.
After power up, the contents of the connection
memory can be in any state. The ODE pin should be
held low after power up to keep all serial outputs in a
high impedance state until the microprocessor has
initialized the switching matrix. This procedure
prevents two serial outputs from driving the same
stream simultaneously.
During the microprocessor initialization routine, the
microprocessor should program the desired active
paths through the switch. The memory block
programming feature can also be used to quickly
initialize the DC and OE bit in the backplane and
local connection memory respectively.
When this process is complete, the microprocessor
controlling the matrices can either bring the ODE pin
high or enable the OSB bit in IMS register to
relinquish the high impedance state control.
MT90863
Advance Information
Read/Write Address:
Reset Value:
02H,
0000H.
15
14
13
12
11
10
0
0
0
0
0
0
9
8
7
6
5
4
3
BBPD BBPD BBPD LBPD LBPD LBPD LBPD
2
1
0
3
2
1
0
2
1
0
BPE
OSB
SFE
Bit
Name
Description
15-10
Unused
9-7
BBPD2-0
Backplane Block Programming Data. These bits carry the value to be loaded into
the backplane connection memory block when the Memory Block Programming
feature is active. After the MBP bit in the control register is set to 1 and the BPE bit is
set to 1, the contents of bits BBPD2-0 are loaded into the bit 13 to bit 11 position of
the backplane connection memory. Bit 15, bit 14 and bit 10 to bit 0 of the backplane
connection memory are zeroed.
6-3
LBPD3-0
Local Block Programming Data. These bits carry the value to be loaded into the
local connection memory block when the Memory Block Programming feature is
active. After the MBP bit in the control register is set to 1 and the BPE bit is set to 1,
the contents of bits LBPD3-0 are loaded into the bit 15 to bit 12 position of the local
connection memory. Bit 11 to bit 0 of the local connection memory low are zeroed. Bit
15 to bit 0 of local connection memory high are zeroed.
2
BPE
Begin Block Programming Enable. A zero to one transition of this bit enables the
memory block programming function. The BPE, BBPD2-0 and LBPD3-0 bits in the
IMS register must be defined in the same write operation. Once the BPE bit is set
high, the device requires two frames to complete the block programming. After the
programming function has finished, the BPE bit returns to zero to indicate the
operation is completed. When the BPE = 1, the BPE or MBP can be set to 0 to abort
the programming operation.
When BPE = 1, the other bits in the IMS register must not be changed for two frames
to ensure proper operation.
1
OSB
Output Stand By. This bit controls the device output drivers.
OSB bit ODE pin OE bit STio0 - 31, STo0 - 15
0
0
1
High impedance state
1
0
1
Enable
X
1
1
Enable
X
X
0
Per-channel high impedance
0
SFE
Start Frame Evaluation. A zero to one transition in this bit starts the frame evaluation
procedure. When the CFE bit in the FAR register changes from zero to one, the
evaluation procedure stops. Set this bit to zero for at least one frame (125µs) to start
another frame evaluation.
Must be zero for normal operation.
Table 8 - Internal Mode Selection (IMS) Register Bits
15
MT90863
Advance Information
Read/Write Address:
Reset Value:
03H,
0000H.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
FE4
FE3
FE2
FE1
FE0
CFE
FD9
FD8
FD7
FD6
FD5
FD4
FD3
FD2
FD1
FD0
Bit
Name
Description
15-11
FE4-0
Frame Evaluation Input Select. The binary value expressed in these bits refers
to the frame evaluation inputs, FEi0 to FEi23.
10
CFE
Complete Frame Evaluation. When CFE = 1, the frame evaluation is completed
and bits FD9 to FD0 bits contains a valid frame alignment offset. This bit is reset to
zero, when SFE bit in the IMS register is changed from 1 to 0. This bit is read-only.
9
FD9
Frame Delay Bit 11. The falling edge of FE is sampled during the CLK-high
phase (FD9 = 1) or during the CLK-low phase (FD9 = 0). This bit allows the
measurement resolution to 1/2 CLK cycle. This bit is read-only.
8-0
FD8-0
Frame Delay Bits. The binary value expressed in these bits refers to the
measured input offset value. These bits are reset to zero when the SFE bit of the
IMS register changes from 1 to 0. (FD8 = MSB, FD0 = LSB). These bits are also
read-only
Table 9 - Frame Alignment (FAR) Register Bit
ST-BUS F0i
C16i
Offset Value
0
1
2
3
4
5
6
7
8
9
10
11 12
13
14
FEi Input
(FD[8:0] = 06H)
(FD9 = 0, sample at CLK low phase)
C4i
HMVIP F0i
C16i
Offset Value
0
1
2
3
4
5
6
7
8
9
10
11 12
13
14
15
FEi Input
(FD[8:0] = 08H)
(FD9 = 1, sample at CLK high phase)
Figure 8 - Example for Frame Alignment Measurement
16
16
15
16
MT90863
Advance Information
Read/Write Address:
Reset value:
04H for DOS0 register,
05H for DOS1 register,
06H for DOS2 register,
07H for DOS3 register,
08H for DOS4 register,
09H for DOS5 register,
0000H for all DOS registers.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
IF32
IF31
IF30
DLE3
IF22
IF21
IF20
DLE2
IF12
IF11
IF10
DLE1
IF02
IF01
IF00
DLE0
DOS0 register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
IF72
IF71
IF70
DLE7
IF62
IF61
IF60
DLE6
IF52
IF51
IF50
DLE5
IF42
IF41
IF40
DLE4
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
IF112
IF111
IF110
DLE11
IF102
IF101
IF100
DLE10
IF92
IF91
IF90
DLE9
IF82
IF81
IF80
DLE8
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
IF152
IF151
IF150
DLE15
IF142
IF141
IF140
DLE14
IF132
IF131
IF130
DLE13
IF122
IF121
IF120
DLE12
DOS1 register
DOS2 register
DOS3 register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
IF192
IF191
IF190
DLE19
IF182
IF181
IF180
DLE18
IF172
IF171
IF170
DLE17
IF162
IF161
IF160
DLE16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
IF232
IF231
IF230
DLE23
IF222
IF221
IF220
DLE22
IF212
IF211
IF210
DLE21
IF202
IF201
IF200
DLE20
DOS4 register
DOS5 register
Name
(Note 1)
Description
IFn2, IFn1, IFn0
Input Offset Bits 2,1 & 0. These three bits define how long the serial interface receiver
takes to recognize and store bit 0 from the STio pin: i.e., to start a new frame. The input
frame offset can be selected to +4 clock periods from the point where the external frame
pulse input signal is applied to the F0i inputs of the device.
DLEn
Data Latch Edge.
ST-BUS mode: DLEn =0, if clock rising edge is at the 3/4 point of the bit cell.
DLEn =1, if clock falling edge is at the 3/4 point of the bit cell.
Note 1: n denotes a STio stream number from 0 to 23.
Table 10 - Frame Delay Offset (DOS) Register Bits
17
MT90863
Advance Information
Measurement Result from
Frame Delay Bits
Input Stream
Offset
Corresponding
Offset Bits
FD9
FD2
FD1
FD0
IFn2
IFn1
IFn0
DLEn
No clock period shift (Default)
1
0
0
0
0
0
0
0
+ 0.5 clock period shift
0
0
0
0
0
0
0
1
+1.0 clock period shift
1
0
0
1
0
0
1
0
+1.5 clock period shift
0
0
0
1
0
0
1
1
+2.0 clock period shift
1
0
1
0
0
1
0
0
+2.5 clock period shift
0
0
1
0
0
1
0
1
+3.0 clock period shift
1
0
1
1
0
1
1
0
+3.5 clock period shift
0
0
1
1
0
1
1
1
+4.0 clock period shift
1
1
0
0
1
0
0
0
+4.5 clock period shift
0
1
0
0
1
0
0
1
Table 11 - Offset Bits (IFn2, IFn1, IFn0, DLEn) & Input Offset Bits (FD9, FD2-0)
ST-BUS F0i
C16i
STio Stream
offset=0, DLE=0
Bit 7
STio Stream
STio Stream
STio Stream
offset=1, DLE=0
Bit 7
offset=0, DLE=1
Bit 7
offset=1, DLE=1
Bit 7
denotes the 3/4 point of the bit cell
Figure 9 - Examples for Input Offset Delay Timing
18
MT90863
Advance Information
Read/Write Address:
Reset value:
0AH for FOR0 register,
0BH for FOR1 register,
0000H for all FOR registers.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
OF15
OF14
OF13
OF12
OF11
OF10
OF09
OF08
OF07
OF06
OF05
OF04
OF03
OF02
OF01
OF00
FOR0 register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
OF23
OF22
OF21
OF20
OF19
OF18
OF17
OF16
FOR1 register
Bit
Name
(Note 1)
Description
15-0 (FOR0)
7-0 (FOR1)
OFn
Output Offset Bit. When 0, the first bit of the serial output stream has normal
alignment with the frame pulse. When 1, the first bit of the serial output stream is
advanced by 1/2 CLK cycle with respect to the frame pulse. See .
15-8 (FOR1)
Unused
Must be zero for normal operation.
Note 1: n denotes a STio stream number from 0 to 23
Table 12 - Frame Output Offset (FOR) Register Bits
ST-BUS F0i
C16i
STio Stream
STio Stream
Bit 7
offset=0
offset=1
Bit 7
HMVIP F0i
HCLK
C16i
STo Stream
STo Stream
Bit 7
Bit 7
offset=0
offset=1
denotes the starting point of the bit cell
Figure 10 - Examples for Frame Output Offset Timing
19
MT90863
Advance Information
Read/Write Address:
Reset value:
0CH for ABR register,
0000H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
CDA
RS
WS
CA6
CA5
CA4
CA3
CA2
CA1
CA0
SA4
SA3
SA2
SA1
SA0
Bit
Name
Description
15
unused
14
CDA
Complete Data Access. This bit is read only. This bit changes from 0 to 1
when data transfer is completed between memory and the data read register or
data write register. When the RS or WS bit in this register is changed from 1 to
0, this bit is reset to zero.
13
RS
Read Select. A zero to one transition of this bit initiates the data transfer from
memory to the data read register. This bit is reset to zero when the CDA bit
changes from 0 to 1.
12
WS
Write Select. A zero to one transition of this bit initiates the data transfer from
the data write register to memory. This bit is reset to zero when the CDA bit
changes from 0 to 1.
11 - 5
CA6 - CA0
Channel Address Bits. These bits perform the same function as the external
address bits when used to access various memory locations. The number
(expressed in binary notation) on these bits refers to the input or output data
stream channel that corresponds to the subsection of memory.
4-0
SA4 - SA0
Stream Address Bits. These bits perform the same function as the STA bits in
the control register. The number (expressed in binary notation) on these bits
refers to the input or output data stream which corresponds to the subsection of
memory.
Reserved
Table 13 -. Address Buffer (ABR) Register Bits
Read/Write Address:
Reset value:
0DH for DWR register,
0000H
15
14
13
12
11
WR15
WR14
WR13
WR12
WR11
Bit
Name
15 - 0
WR15 - WR0
10
WR10
9
8
7
WR9
WR8
WR7
6
5
WR6
WR5
4
WR4
WR3
2
WR2
1
WR1
Description
Write Data Bits. Data to be transferred to one of the internal memory
locations.
.Table 14 - Data Write (DWR) Register Bits
20
3
0
WR0
MT90863
Advance Information
Read Address:
Reset value:
0EH for DRR register,
0000H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RD15
RD14
RD13
RD12
RD11
RD10
RD9
RD8
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
Bit
Name
15 - 0
RD15 - RD0
Description
Read Data Bits. Data transferred from one of the internal memory locations.
Table 15 -. Data Read (DRR) Register Bits
15
14
13
12
11
0
0
BV/C
BMC
DC
10
9
8
7
6
5
4
3
2
1
0
BSAB BSAB BSAB BSAB BCAB BCAB BCAB BCAB BCAB BCAB BCAB
3
2
1
0
6
5
4
3
2
1
0
Bit
Name
Description
15,14
Unused
13
BV/C
Variable /Constant Throughput Delay. This bit is used to select either
variable (low) or constant delay (high) modes on a per-channel basis for the
local interface streams.
12
BMC
Message Channel. When 1, the backplane connection memory contents are
output on the corresponding output channel and stream. Only the lower byte
(bit 7 - bit 0) will be output to the backplane interface STio pins. When 0, the
local data memory address of the switched STi input channel and stream is
loaded into the backplane connection memory.
11
DC
Directional Control. This bit enables the STio pindrivers on a per-channel
basis. When 1, the STio output driver functions normally. When 0, the STio
output driver is in a high-impedance state.
10-7
(Note 1)
BSAB3-0
Source Stream Address Bits. The binary value is the number of the data
stream for the source of the connection.
6-0
(Note 1)
BCAB6-0
Source Channel Address Bits. The binary value identifies the channel for
the connection source.
Must be zero for normal operation.
Note 1: If bit 12 (BMC) of the corresponding backplane connection memory location is 1 (device in message mode), then these
entire 8 bits (BSAB0, BCAB6 - BCAB0) are output on the output channel and stream associated with this location.
Table 16 - Blackplane Connection Memory Bits
Data Rate
BSAB3 to BSAB0 Bits Used to Determine
the Source Stream of the connection
2.048 Mb/s
STi0 to STi15
8.192 Mb/s
STi0 to STi3
2.048 Mb/s
Sub-rate Switching
STi0 to STi12
Table 17 - BSAB Bits Programming for Different Local Interface mode
21
MT90863
Advance Information
Data Rate
BCAB Bits Used to Determine the Source Channel of the Connection
2.048 Mb/s
BCAB4 to BCAB0 (32 channel/frame)
8.192 Mb/s
BCAB6 to BCAB0 (128 channel/frame)
2.048 Mb/s
Sub-rate Switching
BCAB4 to BCAB0 (32 channel/frame)
BCAB6 to BCAB0 (128 channel/frame)
Table 18 -. BCAB Bits Programming for Different Data Rates
15
14
13
12
11
L/B
BV/C
BMC
OE
LSAB
4
10
9
8
7
6
5
4
3
2
1
0
LSAB LSAB LSAB LSAB LCAB LCAB LCAB LCAB LCAB LCAB LCAB
3
2
1
0
6
5
4
3
2
1
0
Bit
Name
Description
15
L/B
14
LV/C
Variable /Constant Throughput Delay. This bit is used to select either
variable (low) or constant delay (high) modes on a per-channel basis for the
source streams.
13
LMC
Message Channel. When 1, the contents of the local connection memory are
output on the corresponding output channel and stream. Only the lower byte
(bit 7 - bit 0) will be output to the STo pins of the local interface. When 0, the
backplane or local data memory address of the switched input channel and
stream is loaded into the local connection memory.
12
OE
11-7
(Note 1)
LSAB4-0
Source Stream Address Bits. The binary value identifies the data stream for
the source of the connection.
6-0
(Note 1)
LCAB6-0
Source Channel Address Bits. The binary value identifies the channel for the
source of the connection.
Local/Backplane Select
When 1, the output channel of STo0-15 comes from STi0-15 (local)
When 0, the output channel of STo0-15 comes from:
STio0-31 (backplane, 2Mb/s mode)
STio0-31 (backplane, 4Mb/s mode)
STio0-15 (blackplane, 8Mb/s mode)
STio0-23 (blackplane, HMVIP mode)
Output Enable. This bit enables the drivers of STo pins on a per-channel
basis. When 1, the STo output driver functions normally. When 0, the STo
output driver is in a high-impedance state.
Note 1: If bit 12 (LMC) of the corresponding local connection memory location is 1 (device in message mode), then these entire 8
bits (LSAB0, LCAB6 - LCAB0) are output on the output channel and stream associated with this location.
Table 19 -. Local Connection Memory Low Bits
22
MT90863
Advance Information
Data Rate
LSAB3 to LSAB0 Bits Used to Determine
the Source Stream of the Connection
2.048 Mb/s
STio0 to STio31 or STi0 to STi15
4.096 Mb/s
STio0 to STio31
8.192 Mb/s
STio0 to STio15 or STi0 to STi3
HMVIP
STio0 to STio23
2.048 Mb/s
Sub-rate Switching
STi0 to STi12
Table 20 - LSAB Bits Programming for Different Local Interface Modes
Data Rate
LCAB Bits Used to Determine the Source Channel of the Connection
2.048 Mb/s
LCAB4 to LCAB0 (32 channel/frame)
4.096 Mb/s
LCAB5 to LCAB0 (64 channel/frame)
8.192 Mb/s
LCAB6 to LCAB0 (128 channel/frame)
HMVIP
LCAB4 to LCAB0 (32 channel/frame)
LCAB6 to LCAB0 (128 channel/frame)
2.048 Mb/s
Sub-rate Switching
LCAB4 to LCAB0 (32 channel/frame)
LCAB6 to LCAB0 (128 channel/frame)
Table 21 - LCAB Bits Programming for Different Data Rates
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LSR1
LSR0
Bit
Name
15-2
(Note1)
Unused
1,0
(Note1)
LSR1, LSR0
Description
Must be zero for normal operation.
Local Sub-rate Switching Bit
When 11
Bit7-6 will be the output of the subrate switching stream
When 10
Bit5-4 will be the output of the subrate switching stream
When 01
Bit3-2 will be the output of the subrate switching stream
When 00
Bit1-0 will be the output of the subrate switching stream
Note 1: If bit 12 (LMC) of the corresponding local connection memory location is 1 (device in message mode), then these entire 8
bits (Bit7-0) are output on the output channel and stream associated with this location.
Table 22 - Local Connection Memory High Bits
23
MT90863
JTAG Support
The MT90863 JTAG interface conforms to the
Boundary-Scan IEEE1149.1 standard. This standard specifies a design-for-testability technique
called Boundary-Scan Test (BST). The operation of
the boundary-scan circuitry is controlled by an
external Test Access Port (TAP) Controller.
Test Access Port (TAP)
The Test Access Port (TAP) accesses the MT90863
test functions. It consists of three input pins and one
output pin as follows:
•
•
•
•
24
Test Clock Input (TCK)
TCK provides the clock for the test logic.
The TCK does not interfere with any on-chip
clock and thus remains independent. The
TCK permits shifting of test data into or out
of the Boundary-Scan register cells
concurrently with the operation of the device
and without interfering with the on-chip
logic.
Advance Information
•
Test Reset (TRST)
Reset the JTAG scan structure. This pin is
internally pulled to VDD.
Instruction Register
The MT90863 uses the public instructions defined in
the IEEE 1149.1 standard. The JTAG Interface
contains a two-bit instruction register. Instructions
are serially loaded into the instruction register from
the TDI when the TAP Controller is in its shifted-IR
state. These instructions are subsequently de-coded
to achieve two basic functions: to select the test data
register that may operate while the instruction is
current; and, to define the serial test data register
path that is used to shift data between TDI and DO
during data register scan-ning.
Test Data Register
As specified in IEEE 1149.1, the MT90863 JTAG
Interface contains three test data registers:
•
The Boundary-Scan Register
The Boundary-Scan register consists of a
series of Boundary-Scan cells arranged to
form a scan path around the boundary of
the MT90863 core logic.
•
The Bypass Register
The Bypass register is a single stage shift
register that provides a one-bit path from
TDI to its TDO.
Test Data Input (TDI)
Serial input data applied to this port is fed
either into the instruction register or into a
test data register, depending on the
sequence previously applied to the TMS
input. Both registers are described in a
subsequent section. The received input data
is sampled at the rising edge of TCK pulses.
This pin is internally pulled to Vdd when it is
not driven from an external source.
•
The Device Identification Register
The device identification register is a 32-bit
register. The register contents are:
Test Data Output (TDO)
Depending on the sequence previously
applied to the TMS input, the contents of
either the instruction register or data
register are serially shifted out towards the
TDO. The data out of the TDO is clocked on
the falling edge of the TCK pulses. When no
data is shifted through the boundary scan
cells, the TDO driver is set to a high
impedance state.
The MT90863 scan register contains 212 bits. Bit 0
in Table 23 Boundary Scan Register is the first bit
clocked out. All tri-state enable bits are active high.
Test Mode Select Input (TMS)
The TAP Controller uses the logic signals
received at the TMS input to control test
operations. The TMS signals are sampled at
the rising edge of the TCK pulse. This pin is
internally pulled to Vdd when it is not driven
from an external source.
MSB
LSB
0000 0000 1000 0110 0011 0001 0100 1011
The LSB bit in the device identification register is
the first bit clock out.
MT90863
Advance Information
Boundary Scan Bit 0 to Bit 213
Boundary Scan Bit 0 to Bit 213
Device Pin
Device Pin
Tri-state
Control
Output
Scan Cell
A0
A1
A2
A3
A4
A5
A6
A7
DS
R/W
CS
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
DTA
Input
Scan Cell
0
1
2
3
4
5
6
7
8
9
10
11
14
17
20
23
26
29
32
35
38
41
44
47
50
53
56
12
15
18
21
24
27
30
33
36
39
42
45
48
51
54
57
13
16
19
22
25
28
31
34
37
40
43
46
49
52
55
58
59
STi0
STi1
STi2
STi3
STi4
STi5
STi6
STi7
60
61
62
63
64
65
66
67
STi8
STi9
STi10
STi11
STi12
STi13
STi14
STi15
ODE
68
69
70
71
72
73
74
75
76
Table 23 - Boundary Scan Register Bits
STo0
STo1
STo2
STo3
STo4
STo5
STo6
STo7
STo8
STo9
STo10
STo11
STo12
STo13
STo14
STo15
Tri-state
Control
Output
Scan Cell
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
Input
Scan Cell
C16i
F0i
C4i/C8i
F0o
C4o
109
110
111
112
114
113
115
STio0/FE0
STio1/FE1
STio2/FE2
STio3/FE3
STio4/FE4
STio5/FE5
STio6/FE6
STio7/FE7
116
119
122
125
128
131
134
137
117
120
123
126
129
132
135
138
118
121
124
127
130
133
136
139
STio8/FE8
STio9/FE9
STio10/FE10
STio11/FE11
STio12/FE12
STio13/FE13
STio14/FE14
STio15/FE15
140
143
146
149
152
155
158
161
141
144
147
150
153
156
159
162
142
145
148
151
154
157
160
163
STio16/FE16
STio17/FE17
STio18/FE18
STio19/FE19
STio20/FE20
STio21/FE21
STio22/FE22
STio23/FE23
164
167
170
173
176
179
182
185
165
168
171
174
177
180
183
186
166
169
172
175
178
181
184
187
STio24
STio25
STio26
STio27
STio28
STio29
STio30
STio31
RESET
188
191
194
197
200
203
206
209
189
192
195
198
201
204
207
210
190
193
196
199
202
205
208
211
212
Table 23 - Boundary Scan Register Bits
25
MT90863
Advance Information
Absolute Maximum Ratings*
Parameter
Symbol
Min
Max
Units
VDD
-0.5
5.0
V
1
Supply Voltage
2
Input Voltage
VI
-0.5
VDD +0.5
V
3
Output Voltage
Vo
-0.5
VDD +0.5
V
4
Package power dissipation
PD
2
W
5
Storage temperature
TS
+125
°C
- 55
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Recommended Operating Conditions - Voltages are with respect to ground (Vss) unless otherwise stated.
Characteristics
Sym
Min
Typ
Max
Units
1
Operating Temperature
TOP
-40
+85
°C
2
Positive Supply
VDD
3.0
3.6
V
3
Input High Voltage
VIH
0.7VDD
VDD
V
4
Input High Voltage on 5V Tolerant Inputs
VIH
5.5
V
5
Input Low Voltage
VIL
0.3VDD
V
VSS
Test Conditions
AC Electrical Characteristics - Voltages are with respect to ground (Vss) unless otherwise stated.
Characteristics
1
2
3
4
I
N
P
U
T
S
5
6
7
8
O
U
T
P
U
T
S
Sym
Min
Typ
Max
Supply Current
IDD
Input High Voltage
VIH
Input Low Voltage
VIL
0.3VDD
V
Input Leakage (input pins)
Input Leakage (bi-directional pins)
IIL
IBL
15
50
µA
µA
Input Pin Capacitance
CI
10
pF
Output High Voltage
VOH
Output Low Voltage
VOL
High Impedance Leakage
IOZ
45
Units
mA
0.7VDD
Test Conditions
Output unloaded
V
0.8VDD
0≤<V≤VDD See
Note 1
V
IOH = 10mA
0.4
V
IOL = 10mA
5
µA
0 < V < VDD See
Note 1
9
Output Pin Capacitance
CO
10
Note:
1. Maximum leakage on pins (output or I/O pins in high impedance state) is over an applied voltage (V)
pF
AC Electrical Characteristics - Timing Parameter Measurement Voltage Levels
Characteristics
Sym
Level
Units
1
CMOS Threshold
VCT
0.5VDD
V
2
Rise/Fall Threshold Voltage High
VHM
0.7VDD
V
3
Rise/Fall Threshold Voltage Low
VLM
0.3VDD
V
Conditions
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied
26
MT90863
Advance Information
AC Electrical Characteristics - Frame Pulse and CLK
Characteristic
Sym
Min
Typ
Max
Units
1
Frame pulse width
tFPW
60
ns
2
Frame Pulse Setup time before
C16i falling
tFPS
10
ns
3
Frame Pulse Hold Time from C16i
falling
tFPH
10
ns
4
C16i Period
tCP
60
ns
5
C16i Pulse Width High
tCH
30
ns
6
C16i Pulse Width Low
tCL
30
ns
7
Clock Rise/Fall Time
tr, tf
10
ns
8
FPo Frame pulse output width
tFPOW
244
ns
9
FPo Frame Pulse output setup
time before C4o falling
tFPOS
10
10 FPo Frame Pulse output Hold
Time from C4o falling
tFPOH
20
11 C4o Period
tC4OP
244
ns
12 C4o Pulse Width High
tC40H
122
ns
13 C4o Pulse Width Low
tC40L
122
ns
14 CT frame pulse width
tCFPW
122
ns
15 CT Frame Pulse Setup Time
before C8i rising
tCFPS
45
90
ns
16 CT Frame Pulse Hold Time from
C8i rising
tCFPH
45
90
ns
17 C8i Period
tHCP
122
ns
18 C8i Pulse Width High
tHCH
61
ns
19 C8i Pulse Width Low
tHCL
61
ns
20 HMVIP frame pulse width
tHFPW
244
ns
21 Frame Pulse Setup Time before
C4i falling
tHFPS
50
150
ns
22 Frame Pulse Hold Time from C4i
falling
tHFPH
50
150
ns
23 C4i Period
tHCP
244
ns
24 C4i Pulse Width High
tHCH
122
ns
25 C4i Pulse Width Low
tHCL
122
ns
tHr, tHf
10
ns
26 C4i/C8i Rise/Fall Time
10
150
ns
150
ns
27 Delay between falling edge of C4i/
C8i and rising edge of C16i
tDIF
-10
10
ns
28 Delay between falling edge of C16i
and falling edge of C4o
tDC4O
-10
10
ns
Notes
ST-BUS mode
ST-BUS, CT Bus
or HMVIP mode
CT Bus mode
HMVIP mode
HMVIP or CT Bus mode
27
MT90863
Advance Information
AC Electrical Characteristics - Serial Streams for Backplane and Local Interfaces
Characteristic
Sym
Min
Typ
Max
Units
Test Conditions
1
STio/STi Set-up Time
tSIS
10
ns
2
STio/STi Hold Time
tSIH
20
ns
3
STo Delay - Active to Active
tSOD
40
ns
CL=200pF
4
STo delay
tZD
40
ns
RL=1K, CL=200pF, See Note 1
5
Output Driver Enable (ODE)
Delay
tODE
40
ns
- Active to High-Z
- High-Z to Active
Note:
1. High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL.
tFPiW
F0i
VTT
tFPiS tFPiH
tCP
tCH
tCL
tr
C16i
16.384MHz
VTT
tFPoS
tFPoW
tf
tFPoH
F0o
tC4L
C4o
4.096MHz
VHM
VTT
VLM
tDC4o
tSOD8
STo/STio (8Mb/s)
output
STi/STio (8Mb/s)
input
STio (4Mb/s)
output
STio (4Mb/s)
input
Bit 1, Ch 127
Bit 0, Ch 127
Bit 0, Ch 127
tr
tf
Bit 7, Ch 0
tSIS8
Bit 1, Ch 127
VTT
tC4P
tC4H
Bit 7, Ch 0
Bit 6, Ch 0
Bit 5, Ch 0
VTT
Bit 4, Ch 0
tSIH8
Bit 6, Ch 0
Bit 5, Ch 0
VTT
Bit 4, Ch 0
tSOD4
Bit 0, Ch63
Bit 7, Ch 0
Bit 0, Ch 63
VTT
Bit 6, Ch 0
tSIS4
tSIH4
Bit 7, Ch 0
VTT
Bit 6, Ch 0
tSOD2
STo/STio (2Mb/s)
output
STi/STio (2Mb/s)
input
Bit 0, Ch 31
Bit 7, Ch 0
Bit 6, Ch 0
tSIS2
Bit 0, Ch 31
Bit 7, Ch 0
Figure 11 - ST-BUS Timing for Stream rate of 2.048, 4.096 or 8.192 Mb/s
28
VTT
tSIH2
VTT
MT90863
Advance Information
tCFPW
F0i
VTT
tCFPS
tCFPH
tCP
tCH
C16i
16.384MHz
tCL
tr
VTT
tC8P
C4i/C8i
8.192MHz
tC8H
tr tf
tf
VTT
tFPoW
tC8L
tf
VTT
F0o
tC4P
tC4L
tC4H
C4o
4.096MHz
VHM
VTT
VLM
tDC4o
tSOD8
ST0/STio (8Mb/s)
output
STi/STio (8Mb/s)
input
STio (4Mb/s)
output
STio (4Mb/s)
input
Bit 1, Ch 127
Bit 0, Ch 127
Bit 0, Ch 127
tf
Bit 7, Ch 0
tSIS8
Bit 1, Ch 127
tr
Bit 7, Ch 0
Bit 6, Ch 0
Bit 5, Ch 0
VTT
Bit 4, Ch 0
tSIH8
Bit 6, Ch 0
Bit 5, Ch 0
VTT
Bit 4, Ch 0
tSOD4
Bit 0, Ch63
Bit 7, Ch 0
tSIS4
Bit 0, Ch 63
VTT
Bit 6, Ch 0
tSIH4
Bit 7, Ch 0
VTT
Bit 6, Ch 0
tSOD2
STo/STio (2Mb/s)
output
STi/STio (2Mb/s)
input
Bit 0, Ch 31
Bit 7, Ch 0
Bit 6, Ch 0
tSIS2
Bit 0, Ch 31
VTT
tSIH2
Bit 7, Ch 0
VTT
Figure 12 - CT Bus Timing for Stream rate of 2.048, 4.096 or 8.192 Mb/s
29
MT90863
Advance Information
tHFPW
tHFPS
tHFPH
VTT
F0i
tHCP
tHCL
tHCH
C4i/C8i
4.096MHz
VHM
VTT
VLM
tDC4otDIF
tHr
tCP
tHf
tCH
tCL
tr
C16i
16.384MHz
VTT
tFPoW
tFPoS
tC8L tf
tFPoH
VTT
F0o
tC4L
tC4P
tC4H
C4o
4.096MHz
VHM
VTT
VLM
tDC4o
tSOD8
STio (8Mb/s)
output
STio (8Mb/s)
input
Bit 0, Ch 127
Bit 1, Ch 127
Bit 7, Ch 0
tSIS8
Bit 0, Ch 127
Bit 1, Ch 127
Bit 7, Ch 0
tr
tf
Bit 6, Ch 0
Bit 5, Ch 0
VTT
Bit 4, Ch 0
tSIH8
Bit 6, Ch 0
Bit 5, Ch 0
VTT
Bit 4, Ch 0
tSOD2
STio (2Mb/s)
output
Bit 7, Ch 0
Bit 0, Ch 31
Bit 6, Ch 0
tSIS2
STio (2Mb/s)
input
Bit 0, Ch 31
VTT
tSIH2
VTT
Bit 7, Ch 0
Figure 13 - HMVIP Bus Timing for Stream rate of 2.048 Mb/s or 8.192 Mb/s
VTT
CLK
VTT
ODE
tODE
tDZ
STo
HiZ
Valid Data
VTT
tZD
STo
HiZ
HiZ
Valid Data
HiZ
VTT
Figure 15 - Output Driver Enable (ODE)
Valid Data
VTT
Figure 14 - Serial Output and External Control
30
STo
tODE
MT90863
Advance Information
AC Electrical Characteristics - Motorola Non-Multiplexed Bus Mode
Characteristics
Sym
Min
Typ
Max
Units
1
CS setup from DS falling
tCSS
0
ns
2
R/W setup from DS falling
tRWS
10
ns
3
Address setup from DS falling
tADS
4
CS hold after DS rising
tCSH
10
ns
5
R/W hold after DS rising
tRWH
10
ns
6
Address hold after DS rising
tADH
6
7
Data setup from DTA low on read
Reading registers
Reading Memory
tDDR_REG
tDDR_MEM
16
440
tDHR
5
Test
Conditions
ns
ns
ns
CL=50pF
11
ns
CL=50pF,
RL=1K
Note 1
8
Data hold on read
9
Data setup on write (fast write)
tDSW_REG
2
ns
10 Valid data delay on write (slow write)
tSWD
150
ns
11 Data hold on write
tDHW
5
ns
12 Acknowledgment delay:
Reading/writing registers
Reading/writing memory
tAKD_REG
tAKD_MEM
40
470
13 Acknowledgment hold time
tAKH
17
ns
CL=50pF
ns
CL=50pF,
RL=1K,
Note
Note:
1. High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL.
VTT
DS
tCSH
tCSS
VTT
CS
tRWH
tRWS
VTT
R/W
tADS
tADH
VTT
VALID ADDRESS
A0-A7
tDHR
VTT
VALID READ DATA
D0-D15
READ
tDSW
tSWD
tDHW
VTT
VALID WRITE DATA
D0-D15
WRITE
tDDR
DTA
VTT
tAKD
tAKH
Figure 16 - Motorola Non-Multiplexed Bus Timing
31
Package Outlines
Pin #1 Corner
1 2 3 4 5 6 7 8 9 10 11 12 13
20.00 REF
A
B
C
D
E
F
G
H
J
K
L
M
N
Ø 1.00(3X) REF.
Ø 0.75 ± 0.15 (169X)
13 12 11 10 9 8 7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
0.97 REF
20.00 REF
18.00
1.50
23.00 ± 0.20
3.00*45 ° (4x)
1.50
B
30 ° Typ.
18.00
23.00 ± 0.20
A
0.60 ± 0.10
2.13 ± 0.13
0.56 REF
C Seating Plane
Note: All governing dimensions are in millimetres for design purposes
Ball Gate Array
120-BGA
144-BGA
160-BGA
MT90823
MT90863
MT90826
Package Outlines
L1
A
A2
A1
L
e
b
D
D1
E1
Notes:
1) Not to scale
2) Top dimensions in inches
3) The governing controlling
dimensions are in millimeters
for design purposes ( )
E
Index
WARNING:
This package diagram does not apply to the MT90810AK
100 Pin Package. Please refer to the data sheet for
exact dimensions.
Pin 1
Metric Quad Flat Pack - L Suffix
44-Pin
64-Pin
100-Pin
128-Pin
Dim
Min
Max
Min
Max
Min
Max
Min
Max
A
-
0.096
(2.45)
-
0.134
(3.40)
-
0.134
(3.40)
-
0.154
(3.85)
A1
0.01
(0.25)
-
0.01
(0.25)
-
0.01
(0.25)
-
0.00
0.01
(0.25)
A2
0.077
(1.95)
0.083
(2.10)
0.1
(2.55)
0.12
(3.05)
0.1
(2.55)
0.12
(3.05)
0.125
(3.17)
0.144
(3.60)
b
0.01
(0.30)
0.018
(0.45)
0.013
(0.35)
0.02
(0.50)
0.009
(0.22)
0.015
(0.38)
0.019
(0.30)
0.018
(0.45)
D
0.547 BSC
(13.90 BSC)
0.941 BSC
(23.90 BSC)
0.941 BSC
(23.90 BSC)
1.23 BSC
(31.2 BSC)
D1
0.394 BSC
(10.00 BSC)
0.787 BSC
(20.00 BSC)
0.787 BSC
(20.00 BSC)
1.102 BSC
(28.00 BSC)
E
0.547 BSC
(13.90 BSC)
0.705 BSC
(17.90 BSC)
0.705 BSC
(17.90 BSC)
1.23 BSC
(31.2 BSC)
E1
0.394 BSC
(10.00 BSC)
0.551 BSC
(14.00 BSC)
0.551 BSC
(14.00 BSC)
1.102 BSC
(28.00 BSC)
e
0.031 BSC
(0.80 BSC)
0.039 BSC
(1.0 BSC)
0.256 BSC
(0.65 BSC)
0.031 BSC
(0.80 BSC)
L
L1
0.029
(0.73)
0.04
(1.03)
0.077 REF
(1.95 REF)
0.029
(0.73)
0.04
(1.03)
0.077 REF
(1.95 REF)
0.029
(0.73)
0.04
(1.03)
0.077 REF
(1.95 REF)
NOTE: Governing controlling dimensions in parenthesis ( ) are in millimeters.
0.029
(0.73)
0.04
(1.03)
0.063 REF
(1.60 REF)
Package Outlines
160-Pin
208-Pin
240-Pin
Dim
A
Min
Max
-
0.154
(3.92)
A1
Min
Max
Min
Max
.161
(4.10)
-
0.161
(4.10)
0.01
(0.25)
0.01
(0.25)
0.02
(0.50)
0.01
(0.25)
0.02
(0.50)
A2
0.125
(3.17)
0.144
(3.67)
.126
(3.20)
.142
(3.60)
0.126
(3.2)
0.142
(3.60)
b
0.009
(0.22)
0.015
(0.38)
.007
(0.17)
.011
(0.27)
0.007
(0.17)
0.010
(0.27)
D
1.23 BSC
(31.2 BSC)
1.204
(30.6)
1.360 BSC
(34.6 BSC)
D1
1.102 BSC
(28.00 BSC)
1.102
(28.00)
1.26 BSC
(32.00 BSC)
E
1.23 BSC
(31.2 BSC)
1.204 BSC
(30.6 BSC)
1.360 BSC
(34.6 BSC)
E1
1.102 BSC
(28.00 BSC)
1.102 BSC
(28.00 BSC)
1.26 BSC
(32.00 BSC)
e
0.025 BSC
(0.65 BSC)
0.020 BSC
(0.50 BSC)
0.0197 BSC
(0.50 BSC)
L
L1
0.029
(0.73)
0.04
(1.03)
0.063 REF
(1.60 REF)
0.018
(0.45)
0.029
(0.75)
0.051 REF
(1.30 REF)
NOTE: Governing controlling dimensions in parenthesis ( ) are in millimeters.
0.018
(0.45)
0.029
(0.75)
0.051 REF
(1.30 REF)
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