MITSUMI I2C BUS Control 4-Input 1-Output AV Switch MM1311 I2C BUS Control 4-Input 1-Output AV Switch Monolithic IC MM1311 Outline This IC is a 4-input 1-output AV switch with I2C control, developed for use in televisions. Features 1. Serial control by I2C BUS. 2. 4 inputs, 1 output. 3. Video and audio system switches can be controlled independently. 4. 6 dB amplifier built in to video system. 5. Built-in Y/C MIX circuit. 6. Slave address can be changed : 90H or 92H. 7. Audio muting possible by external pin. 8. Maintains high impedance even when I2C BUS line (SDA, SCL) power supply is off. 9. Built-in 3 value discrimination function. 10. On-chip power ON reset function. 11. Two types of audio input impedance : 60kΩ and 30kΩ. MM1311AD : 60kΩ MM1311BD : 30kΩ Package SDIP-32A (MM1311AD, MM1311BD) Applications 1. Television 2. Other video equipment MITSUMI Equivalent Block Diagram I2C BUS Control 4-Input 1-Output AV Switch MM1311 I2C BUS Control 4-Input 1-Output AV Switch MM1311 MITSUMI Pin Description Pin No. Name 31 MTV-V 27 YOUT 1 V1-V 29 COUT 7 V2-V 13 V3-V 3 V1-Y 9 V2-Y 24 LOUT 22 YIN 23 ROUT 5 V1-C 11 V2-C 20 CIN 26 BIAS 18 SCL 17 SDA 6 S1 12 S2 16 ADR 19 Mute 32 MTV-L 2 V1-L 8 V2-L 14 V3-L 30 MTV-R 4 V1-R 10 V2-R 15 V3-R 25 VOUT Internal equivalent circuit diagram Pin No. Absolute Maximum Ratings Name Internal equivalent circuit diagram (Ta=25°C) Item Symbol Ratings Units Storage temperature TSTG -40~+125 °C Operating temperature TOPR -20~+75 °C Power supply voltage VCC 12 V Allowable power dissipation Pd 950 mW I2C BUS Control 4-Input 1-Output AV Switch MM1311 MITSUMI Electrical Characteristics (Ta=25°C, VCC=9V) Measure ment pin Conditions (unless otherwise indicated, Measurement Circuit Figure 1) VCC ICC 28 VCC=9V, no signal, no load GV FV TP1 TP1 Differential gain DGV TP1 Differential phase DPV TP1 Input dynamic range DV 1 SG 1~3 GY1 GY2 TP2 TP2 FY1 TP2 FY2 TP2 Differential gain DGY TP2 Differential phase DPY TP2 DY1 SG2 Item Symbol Operating power supply voltage Current consumption VOUT output Voltage gain Frequency characteristics Min. Typ. Max. Units 8 9 27 10 35 V mA Sine wave, 1.0VP-P, 100kHz 5.5 Sine wave, 1.0VP-P, 10MHz/100kHz -1.0 Vn-V : Staircase, 1VP-P APL=10~90% Vn-Y : Staircase (luminance signal) 1VP-P -3 Vn-C : Chroma signal 0.3VP-P APL=10~90% Vn-V : Staircase, 1VP-P APL=10~90% Vn-Y : Staircase (luminance signal) 1VP-P -3 Vn-C : Chroma signal 0.3VP-P APL=10~90% Sine wave, 100kHz Maximum input for total higher 1.6 harmonic distortion factor < 1.0% 6.0 0 6.5 1.0 dB dB 0 3 % 0 3 deg Vn-Y : Sine wave, 1.0VP-P, 100kHz YIN : Sine wave, 2.0VP-P, 100kHz Vn-Y : Sine wave, 1.0VP-P 10MHz/100kHz YIN : Sine wave, 2.0VP-P, 10MHz/100kHz Vn-Y : Staircase, 1VP-P APL=10~90% YIN : Staircase, 2VP-P, APL=10~90% Vn-Y : Staircase, 1VP-P APL=10~90% YIN : Staircase, 2VP-P, APL=10~90% Vn-Y : Sine wave100kHz Maximum input for total higher harmonic distortion factor < 1.0% YIN : Sine wave, 100kHz Maximum input for total higher harmonic distortion factor < 1.0% 5.5 -0.5 6.0 0 6.5 0.5 -1.0 0 1.0 -1.0 0 1.0 -3 0 3 % -3 0 3 deg 1.6 1.9 1.9 VP-P YOUT output Voltage gain Frequency characteristics Input dynamic range DY2 Output impedance COUT output Voltage gain Frequency characteristics Differential gain Differential phase SG4 FC1 TP3 FC2 DGC DPC TP3 TP3 TP3 DC1 SG3 Input dynamic range DC2 Input impedance Output impedance LOUT output Voltage gain Frequency characteristics 3.2 SG5 ZIC ZOC GL1 GL2 FL 3.8 Ω 50 TP3 TP3 TP4 TP4 TP4 Vn-C : Sine wave, 1.0VP-P, 100kHz CIN : Sine wave, 2.0VP-P, 100kHz Vn-C : Sine wave, 1.0VP-P 10MHz/100kHz CIN : Sine wave, 2.0VP-P, 10MHz/100kHz CIN : Staircase, 2VP-P, APL=10~90% CIN : Staircase, 2VP-P, APL=10~90% Vn-C : Sine wave, 100kHz Maximum input for total higher harmonic distortion factor < 1.0% CIN : Sine wave, 100kHz Maximum input for total higher harmonic distortion factor < 1.0% Vn-C, CIN b7=0, Sine wave, 2.5VP-P, 1kHz b7=1, Sine wave, 2.5VP-P, 1kHz Sine wave, 2.5VP-P, 1MHz/1kHz dB VP-P ZOY GC1 GC2 dB 5.5 -0.5 6.0 0 6.5 0.5 -1.0 0 1.0 -1.0 -3 -3 0 0 0 1.0 3 3 2.75 3.25 dB dB % deg VP-P 5.5 6.5 10 15 50 20 -6.5 -0.5 -3.0 -6.0 0 0 -5.5 0.5 1.0 kΩ Ω dB dB I2C BUS Control 4-Input 1-Output AV Switch MM1311 MITSUMI Item Symbol Total higher harmonic distortion THDL SG6 VOFFL ZIL ZOL 24 GR1 GR2 Frequency characteristics FR Total higher harmonic distortion THDR Voltage gain TP5 TP5 TP5 TP5 DR SG7 VOFFR ZIR ZOR 23 CTV CTY CTC CTL CTR TP1 TP2 TP3 TP4 TP5 Input dynamic range Output offset voltage Input impedance Output impedance Crosstalk VOUT YOUT COUT LOUT ROUT Video I/O Pin Voltage Input pin voltage TP4 DL Input dynamic range Output offset voltage Input impedance Output impedance ROUT output Measure ment pin Conditions (unless otherwise indicated, Min. Typ. Max. Units Measurement Circuit Figure 1) Sine wave, 2.5VP-P, 1kHz 0.03 0.1 % Sine wave, 1kHz Maximum input for total higher 2.6 2.8 Vrms harmonic distortion factor < 0.5% LOUT pin DC difference during SW switching 0 ±15 mV 42 60 78 kΩ 120 Ω b7=0, Sine wave, 2.5VP-P, 1kHz b7=1, Sine wave, 2.5VP-P, 1kHz Sine wave, 2.5V P-P , 1MHz/1kHz Sine wave, 2.5VP-P, 1kHz Sine wave, 1kHz Maximum input for total higher harmonic distortion factor < 0.5% ROUT pin DC difference during switching Audio I/O Pin Voltage Input pin voltage VAIP Output pin voltage VAOP Logic section (Refer to figure below) Input voltage L VIL Input voltage H VIH Low level output voltage (SDA) VOL High level input current IIH Low level input current IIL Clock frequency fSCL Data transmission waiting time tBUF SCL start hold time tHD : STA SCL low level hold time tLOW SCL high level hold time tHIGH SCL start set-up time tSU : STA SDA data hold time tHD : DAT SDA data set-up time tSU : DAT SCL rise time tR SCL fall time tF SCL stop set-up time tSU : STO -6.0 0 0 0.03 2.6 2.8 42 0 60 120 ±15 78 mV kΩ Ω -60 -60 -60 -90 -90 -53 -53 -53 -80 -80 dB dB dB dB dB Measurement Circuit Figure 2 SG1 input : 4.43MHz, 1VP-P SG2 input : 4.43MHz, 0.5VP-P Measurement Circuit Figure 2 1kHz, 2.5VP-P VVIP VVOP VSOP Output pin voltage -6.5 -0.5 -3.0 -5.5 -0.5 1.0 0.1 No signal, no load VOUT pin, No signal, no load YOUT pin, COUT pin, No signal, no load 4.0 4.1 3.3 4.3 4.4 3.6 4.6 4.7 3.9 V V V No signal, no load No signal, no load 4.6 3.9 4.9 4.2 5.2 4.5 V V I2C logic low level discrimination value I2C logic high level discrimination value SDA for 3mA inflow when SDA, SCL=4.5V impressed when SDA, SCL=0.4V impressed 0.0 3.0 0.0 -10 -10 4.7 4.0 4.7 4.0 4.7 200 250 4.0 1.5 5.0 0.4 +10 +10 100 V V V µA µA kHz µS µS µS µS µS nS nS 1000 nS 300 nS µS SDA tR tF SCL P S tHD:STA tLOW tHD:DAT tHIGH dB % Vrms I2C BUS Control Signal tBUF dB tSU:DAT tSU:STA Sr tSU:STO P MITSUMI Measurement Circuit Measurement Circuit 1 I2C BUS Control 4-Input 1-Output AV Switch MM1311 MITSUMI I2C BUS Control 4-Input 1-Output AV Switch MM1311 Measurement Circuit 2 (Crosstalk measurement) I2C BUS Control 4-Input 1-Output AV Switch MM1311 MITSUMI I2C BUS SDA SCL S 1 2 3 4 5 6 7 8 A 1 2 3 ·· 8 A P S:Start Condition P:Stop Condition ACK:Acknowledge The I2C BUS is a BUS system developed by Philips for internal use in equipment. Data transmission is carried out by the two SDA and SCL lines, in byte units, with the MSB first from start condition. Control Register The control register contains data sent from the master in order to determine the status of each switch. S Slave address 1 0 0 1 R/W 0 0 0/1 0 A Control register b7 b6 b5 Address byte b4 b3 b2 b1 b0 A P Control data The data format is set as shown in the figure above. The first 7 bits in the address byte are allocated to the slave address, and the remaining 1 bit is allocated to the read/write bit. The read/write bit is set at 0 when using as a control register. The MM1311 slave address can be selected as 90H/92H depending on the status of the ADR pin. When the ADR pin is low it is 90H. The relationship between the control register bits and switch control is as shown below. b7 b6 Audio S/Comp Gain Select b5 b4 Video-Select b3 b2 b1 b0 Audio-Select The control register bits are reset to 0 when power is applied. MM1311 control is carried out by the 2-byte structure of the 1 address byte and 1 control data byte. All of the remaining data (third byte and after) are ignored. Refer to the separate tables for details on switch control. I2C BUS Control 4-Input 1-Output AV Switch MM1311 MITSUMI Status Register The status register contains data for sending device status to the master. S Slave address 1 0 0 1 R/W 0 0 0/1 1 A Control register b7 b6 b5 Address byte b4 b3 b2 b1 b0 NA P Control data The data format is set as shown in the figure above. The first 7 bits in the address byte are allocated to the slave address, and the remaining 1 bit is allocated to the read/write bit. The read/write bit is set at 1 when using as a status register. The MM1311 slave address can be selected as 91H/93H depending on the status of the ADR pin. When the ADR pin is low it is 91H. However, the confirmation response after completion of the status register should be non-acknowledge. The status register output data as shown below. b7 b6 b5 b4 b3 b2 P-ON S1 S1 S2 S2 RESET OPEN SEL OPEN SEL b1 b0 P-ON RESET : Returns 1 for power on reset. However once data read begins, 0 is returned next. S1/S2 OPEN : Returns 0 when the S1/S2 pin is not open, and returns 1 when the S1/S2 pin is open S1/S2 SEL : Returns 0 when the S1/S2 pin is not grounded, and returns 1 when the S1/S2 pin is grounded. S1/S2 OPEN, SEL have 3-value discrimination, and the combinations are as shown below. S1/S2 pin DC voltage S1/S2 OPEN S1/S2 SEL 0.8V or less 0 1 1.3V or more, 3.5V or less 0 0 4.5V or more 1 0 Power On Reset Power on reset is built in to reset each control register to 0 when power is turned on. Power on reset threshold has hysteresis as shown in the figure below. The IC power on reset status can be discriminated by reading the status register P-ON RESET. Reset released Undefined Reset status 0.6V 4.3V 5.4V VCC I2C BUS Control 4-Input 1-Output AV Switch MM1311 MITSUMI Switch Control Table 1. Video Output b5 b4 b3 VOUT YOUT COUT 0 0 0 0 Mute Mute Mute 0 0 0 1 MTV-V YIN CIN 0 0 1 0 V1-V YIN CIN 0 0 1 1 V2-V YIN CIN 0 1 0 0 V3-V YIN CIN 0 1 0 1 Mute Mute Mute 1 ~ b6 1 0 0 0 Mute Mute Mute 1 0 0 1 MTV-V YIN CIN 1 0 1 0 V1-Y+C V1-Y V1-C 1 0 1 1 V2-Y+C V2-Y V2-C 1 1 0 0 V3-V YIN CIN 1 1 0 1 Mute Mute Mute ~ 1 1 1 2. Audio Output Mute pin 1.5V or less (OPEN) b1 b0 LOUT ROUT 0 0 0 Mute Mute 0 0 1 MTV-L MTV-R 0 1 0 V1-L V1-R 0 1 1 V2-L V2-R 1 0 0 V3-L V3-R 0 1 Mute Mute Mute Mute 1 3.0V or more - ~ b2 1 1 - - 3. Audio Gain Switching b7 Output gain 0 -6dB output 1 0dB output I2C BUS Control 4-Input 1-Output AV Switch MM1311 MITSUMI Example of Application Circuit Notes 1 : VOUT is set at 4.4V and CIN at 4.3V. Please note that capacitance polarity may vary depending on comb filter bias. Notes 2 : Each audio output can be muted by making pin 19 high. Mute is off when it is open or low.