SONY CXA2089

CXA2089Q/S
S2-Compatible 5-Input 2-Output Audio/Video Switch
Description
The CXA2089Q/S is a 5-input, 2-output audio/video
switch featuring I2C bus compatibility for TVs. This IC
has input pins that are compatible with S2 protocol.
Features
• 3 inputs that are compatible with S2 protocol
• Serial control with I2C bus
• 5 inputs, 2 outputs
• The desired inputs can be selected independently
for each of the 2 outputs
• Wide band video amplifier (20MHz, –3dB)
• Y/C MIX circuit
• Slave address can be changed (90H/92H)
• Audio muting from external pin
• High impedance maintained by I2C bus lines (SDA,
SCL) even when power is OFF
• Wide audio dynamic range (3Vrms typ.)
CXA2089Q
48 pin QFP (Plastic)
CXA2089S
48 pin SDIP (Plastic)
Absolute Maximum Ratings
• Supply voltage
VCC
• Operating temperature Topr
• Storage temperature
Tstg
• Allowable power dissipation
PD
Operating Conditions
Supply voltage
12
–20 to +75
–65 to +150
1500
V
°C
°C
mW
9 ± 0.5
V
Applications
Audio/video switch featuring I2C bus compatibility
for TVs
Structure
Bipolar silicon monolithic IC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E97431B7Z-PS
CXA2089Q/S
Block Diagram
CXA2089Q
TV 47
40 VOUT1
6dB
V1 1
36 YIN1
V2 8
V3 15
43 YOUT1
6dB
V4 23
42 TRAP1
6dB
45
COUT1
38 CIN1
Y1
3
Y2 10
6dB
33 VOUT2
6dB
31 YOUT2
6dB
29 COUT2
Y3 17
C1
5
C2 12
44
C3 19
37 BIAS
BIAS
S2-1
34 VCC
6
S2-2 13
S2-3 20
S-1
GND
28 DC OUT
26 SCL
Logic
27 SDA
7
S-2 14
25 ADR
S-3 21
35 MUTE
6dB
LTV 46
LV1
2
LV2
9
39 LOUT1
0dB
LV3 16
6dB
LV4 22
41 ROUT1
0dB
RTV 48
LOUT2
6dB
30
6dB
32 ROUT2
RV1 4
RV2 11
RV3 18
RV4 24
Audio system is attenuated by 6dB for 6kΩ resistor input, and a total gain is 0dB (LOUT1 and ROUT1 can be changed to –6dB).
–2–
CXA2089Q/S
CXA2089S
TV 5
V1
46 VOUT1
6dB
7
42 YIN1
V2 14
V3 21
1
6dB
YOUT1
V4 29
48 TRAP1
6dB
3
COUT1
44 CIN1
Y1
9
Y2 16
6dB
39 VOUT2
6dB
37 YOUT2
6dB
35 COUT2
Y3 23
C1 11
C2 18
2
C3 25
GND
43 BIAS
BIAS
40 VCC
S2-1 12
S2-2 19
34 DC OUT
S2-3 26
32 SCL
Logic
33 SDA
S-1 13
S-2 20
31 ADR
S-3 27
41 MUTE
LTV
4
LV1
8
6dB
45 LOUT1
0dB
LV2 15
LV3 22
6dB
LV4 28
47 ROUT1
0dB
RTV 6
6dB
36 LOUT2
6dB
38 ROUT2
RV1 10
RV2 17
RV3 24
RV4 30
Audio system is attenuated by 6dB for 6kΩ resistor input, and a total gain is 0dB (LOUT1 and ROUT1 can be changed to –6dB).
–3–
CXA2089Q/S
ADR
SCL
SDA
DC OUT
LOUT2
COUT2
YOUT2
ROUT2
VOUT2
VCC
YIN1
CXA2089Q
MUTE
Pin Configuration
36 35 34 33 32 31 30 29 28 27 26 25
BIAS 37
24 RV4
CIN1 38
23 V4
LOUT1 39
22 LV4
VOUT1 40
21 S-3
ROUT1 41
20 S2-3
TRAP1 42
19 C3
YOUT1 43
18 RV3
GND 44
17 Y3
COUT1 45
16 LV3
LTV 46
15 V3
TV 47
14 S-2
13 S2-2
RTV 48
C1
S-1
V2
LV2
YOUT2
LOUT2
COUT2
C2
9 10 11 12
Y2
8
5
RV2
7
S2-1
6
ROUT2
4
VOUT2
Y1
3
RV1
V1
2
LV1
1
C3
S2-3
S-3
LV4
V4
RV4
ADR
SCL
SDA
DC OUT
VCC
MUTE
YIN1
BIAS
CIN1
LOUT1
VOUT1
ROUT1
TRAP1
CXA2089S
LV1
Y1
RV3
V1
Y3
RTV
LV3
TV
V3
LTV
S-2
COUT1
S2-2
GND
–4–
C2
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
RV2
8
Y2
7
LV2
6
V2
5
S-1
4
S2-1
3
C1
2
RV1
1
YOUT1
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
CXA2089Q/S
Pin Description
Pin
No.
Symbol
Pin numbers in brackets are for the CXA2089S.
Pin
voltage
Equivalent circuit
Description
VCC
47 (5)
1 (7)
8 (14)
15 (21)
23 (29)
TV
V1
V2
V3
V4
47 15
4.0V
150
Video signal inputs.
Input composite video signals.
1 23
3µA
8
VCC
3 (9)
10 (16)
17 (23)
36 (42)
Y1
Y2
Y3
YIN1
3
4.0V
Y/C separation signal inputs.
Input luminance signals.
The YIN1 pin inputs the signal
obtained by Y/C separating the
VOUT1 pin output.
150
10
3µA
17
36
VCC
5 (11)
12 (18)
19 (25)
38 (44)
C1
C2
C3
CIN1
Y/C separation signal inputs.
Input chrominance signals.
The CIN1 pin inputs the signal
obtained by Y/C separating the
VOUT1 pin output.
20k
5
4.5V
150
12
19
27k
38
46 (4)
2 (8)
9 (15)
16 (22)
22 (28)
48 (6)
4 (10)
11 (17)
18 (24)
24 (30)
LTV
LV1
LV2
LV3
LV4
RTV
RV1
RV2
RV3
RV4
46 48
2
4.5V
VCC
33k
4
27k
Audio signal inputs.
9 11
16 18
15k
22 24
VCC
250
VCC
40 (46) VOUT1
33 (39) VOUT2
3.9V
Video signal outputs.
Output composite video signals.
30k
40
33
27k
–5–
23.5k
CXA2089Q/S
Pin
No.
Symbol
Pin
voltage
Equivalent circuit
Description
VCC VCC VCC
43 (1)
YOUT1
VCC
3.3V
43
Video signal outputs.
Output luminance signals.
31
31 (37) YOUT2
3.5V
VCC VCC VCC
VCC
45 (3) COUT1
29 (35) COUT2
4.5V
Video signal outputs.
Output chrominance signals.
45
29
VCC
39 (45)
30 (36)
41 (47)
32 (38)
LOUT1
LOUT2
ROUT1
ROUT2
VCC
39
56
Audio signal outputs.
Zo = 50Ω (within DC ± 2mA)
30
4.5V
20k
41
20k
32
VCC
VCC
VCC
6 (12) S2-1
13 (19) S2-2
20 (26) S2-3
6
—
147
13
100k
20
5V
7 (13) S-1
14 (20) S-2
21 (27) S-3
VCC
VCC
100k
—
7
50k
50k
14
21
10k
VCC
25 (31) ADR
—
147
72k
25
28k
–6–
VCC
Detects the S2-compatible DC
superimposed onto the C signal.
4:3 video signal at 1.3V or less
4:3 letter-box signal at 1.3V or more
to 2.5V or less
16:9 picture squeezed signal at 2.5V
or more
These pins are pulled down to GND
by a 100kΩ resistor, so the 4:3 video
signals are selected when open.
Composite video/S selector.
The detection results are written to
the status register.
S signal at 3.5V or less
Composite video signal at 3.5V or
more
These pins are pulled up to 5V by a
100kΩ resistor, so the composite
video signals are selected when
open.
Selects the slave address for the I2C
bus.
90H at 1.5V or less
92H at 2.5V or more
90H when open
CXA2089Q/S
Pin
No.
Symbol
Pin
voltage
Equivalent circuit
Description
VCC
26 (32) SCL
I2C bus signal input
VILmax = 1.5V
VIHmin = 3.0V
4k
—
26
10k
VCC
27 (33) SDA
—
I2C bus signal input
VILmax = 1.5V
VIHmin = 3.0V
VOLmax = 0.4V
4k
27
VCC
28 (34) DC OUT
—
4k
1k
28
Q1
28k
Outputs the S2-compatible DC
superimposed onto the COUT2
output. The DC is superimposed by
connecting this pin to the COUT2
output via a capacitor.
Control is performed by the I2C bus.
When 0V is output, Q1 is ON and
the impedance is 5kΩ.
S2 protocol output DC impedance of
10 ± 3kΩ is realized by attaching
external resistance of 4.7kΩ.
DC OUT (bus)
Output DC
0
4.5V
1
0V
2
1.9V
3
4.5V
VCC
100
42 (48) TRAP1
3.8V
42
Connects trap circuit for subcarrier.
1k
VCC
35 (41) MUTE
—
147
Audio signal output mute.
Mute OFF at 1.5V or less
Mute ON at 2.5V or more
Mute OFF when open
72k
35
28k
VCC
VCC
37 (43) BIAS
VCC
20k
4.5V
147
37
20k
–7–
Internal reference bias (Vcc/2).
Connects to GND via a capacitor.
CXA2089Q/S
Electrical Characteristics
Item
Current consumption
(Ta = 25°C, VCC = 9V)
Symbol
ICC
Conditions
No signal, no load
Min.
Typ.
Max.
Unit
30
45
62
mA
5.9
6.4
6.9
dB
15
20
—
MHz
10
15
—
MHz
Video system (Measurement circuit; Fig. 1)
Gain
GVv
f = 100kHz, 0.3Vp-p input
Frequency response
characteristics
FBWv1
Frequency response
characteristics
(Y/C mix)
FBWv2
Input dynamic range
Ddv
f = 100kHz,
maximum with distortion < 1.0%
1.4
—
—
Vp-p
Cross talk
Vctv
f = 4.43MHz, 1Vp-p input
—
—
–50
dB
f = 100kHz, input frequency where
output amplitude is –3dB with 0.3Vp-p
output serving as 0dB
Audio system (Measurement circuits; Fig. 2 to Fig. 5)
Gain
GVA
f = 1kHz, 1Vp-p input,
5.7kΩ resistor inserted to input
–1
0
1
dB
Frequency response
characteristics
FBWA
f = 1kHz, input frequency where
output amplitude is –3dB with 1Vp-p
output serving as 0dB
50
—
—
kHz
Total harmonic
distortion
THD
f=1kHz, 2.2Vp-p input, where 400Hz
HPF + 80kHz LPF are inserted
—
0.03
0.05
%
Input dynamic range
DdA
f=1kHz, maximum with distortion < 0.3%
2.8
3.0
—
Vrms
Cross talk
VctA
f=1kHz, 1Vp-p input
—
–90
–80
dB
Ripple rejection ratio
VctA
f=100Hz, 0.3Vp-p applied to Vcc
—
–55
–40
dB
Output DC offset
Voff
Offset voltage between input and
output
–30
—
30
mV
Residual noise
VNA
When 400Hz HPF+ 30kHz LPF are
inserted
0
20
30
µVrms
S/N ratio
S/N
f=1kHz, 1Vrms input
When 400Hz HPF + 30kHz LPF are
inserted
–100
–90
dB
–8–
CXA2089Q/S
Logic system
Item
Symbol
Conditions
Min.
Typ.
Max.
Unit
High level input voltage
VIH
3.0
—
5.0
V
Low level input voltage
VIL
0
—
1.5
V
Low level output voltage VOL
With SDA 3mA current supplied
0
—
0.4
V
High level input current
IIH
VIH = 4.5V
0
—
10
µA
Low level input current
IIL
VIL = 0.4V
0
—
10
µA
Maximum clock
frequency
fSCL
0
—
100
kHz
Minimum waiting time
for data change
tBUF
4.7
—
—
µs
Minimum waiting time
for data transfer start
tHD;STA
4.0
—
—
µs
Low level clock pulse
width
tLOW
4.7
—
—
µs
High level clock pulse
width
tHIGH
4.0
—
—
µs
Minimum waiting time
for start preparation
tSU;STA
4.7
—
—
µs
Minimum data hold time
tHD;DAT
150
—
—
ns
Minimum data
preparation time
tSU;DAT
0
—
—
ns
—
—
1
µs
Fall time
tR
tF
—
—
300
ns
Minimum waiting time
for stop preparation
tSU;STO
4.7
—
—
µs
Rise time
–9–
48
47
46
45
44
75
1µ
600
3
75
0.47µ
2
0.47µ
1
RTV
TV
LTV
COUT1
GND
43 YOUT1
600
4
75
8
75
0.47µ
7
6
5
0.1µ
1µ
600
9
10
75
0.47µ
600
1µ
11
12
0.1µ
75
S2-2 13
S-2 14
V3 15
LV3 16
Y3 17
RV3 18
C3 19
S-3 21
LV4 22
42 TRAP1
1µ
24
V4 23
RV4
0.47µ
1µ
0.47µ
1µ
0.1µ
1µ
0.47µ
1µ
75
600
75
600
75
600
75
600
µ-com
Measurement point
S2-3 20
Y1
41 ROUT1
40 VOUT1
RV1
Signal is input from one of the following pins: 1, 3, 5, 8, 10, 12, 15, 17, 19, 23 and 47.
Output signal is measured from one of the following pins: 29, 31, 33, 40, 43 and 45.
1µ
0.47µ
1µ
10µ
10µ
10µ
10µ
V2
Fig. 1-a. Video system (gain, frequency response characteristics, input dynamic range, cross talk) measurement circuit (CXA2089Q)
Input signal
600
75
600
10k
10k
10k
10k
39 LOUT1
V1
10µ
LV1
10k
38 CIN1
C1
0.1µ
BIAS
YIN1
S2-1
75
37
25
26
27
28
29
30
31
32
33
MUTE
S-1
– 10 –
C2
10µ
22µ
34
VCC
10k
10µ
VOUT2
35
10µ
ROUT2
10k
10µ
YOUT2
36
10µ
LOUT2
10k
10µ
COUT2
1k
10k
DC OUT
Y2
0.47µ
10k
SDA
RV2
75
SCL
LV2
ADR
Electrical Characteristics Measurement Circuit
CXA2089Q/S
– 11 –
GND
YOUT1
10k
10µ
10k
600
10µ
1µ
4
TV
75
600
Y1
10
RV1
75
600
0.47µ 1µ
9
C1
75
0.1µ
11
S2-1
12
LV2
16
17
75
75
600
S-1
600
15
Y2
0.47µ 1µ
14
RV2
0.47µ 1µ
V2
13
75
S2-2
19
0.1µ
18
C2
Signal is input from one of the following pins: 5, 7, 9, 11, 14, 16, 18, 21, 23, 25 and 29.
Output signal is measured from one of the following pins: 1, 3, 35, 37, 39 and 46.
75
600
8
LV1
0.47µ 1µ
7
RTV
0.47µ 1µ
5
V1
6
47
ROUT1
3
46
VOUT1
COUT1
2
45
LOUT1
LTV
1
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
CIN1
S-2
20
22
75
600
0.47µ 1µ
21
V3
48
BIAS
0.1µ
YIN1
1µ
MUTE
1µ 0.47µ
75
VCC
600
VOUT2
10µ
75
ROUT2
10µ
600
YOUT2
10µ
10k
LOUT2
10µ
10k
COUT2
10µ
10k
DC-OUT
22µ
10k
SDA
1k
10k
SCL
10µ 0.47µ
75
ADR
10µ 0.1µ
75
RV4
10µ
10k
V4
10µ
10k
LV4
LV3
10k
S-3
24
75
600
0.47µ 1µ
23
Y3
TRAP
+9V
S2-3
µ-COM
C3
RV3
Input signal
Fig. 1-b. Video system (gain, frequency response characteristics, input dynamic range, cross talk) measurement circuit (CXA2089S)
Measurement point
CXA2089Q/S
75
1µ
3
0.1µ
75
600
600
4
75
1µ
0.47µ 5.7k
2
1
RTV
TV
0.47µ
48
47
5.7k
COUT1
GND
46 LTV
45
44
43 YOUT1
75
0.47µ
7
6
5
8
5.7k
1µ
9
10
11
600
75
1µ
0.47µ 5.7k
12
0.1µ
600
75
S2-2 13
S-2 14
V3 15
LV3 16
Y3 17
RV3 18
C3 19
42 TRAP1
S-3 21
LV4 22
V4 23
24
S2-3 20
Y1
41 ROUT1
40 VOUT1
RV1
Signal is input from one of the following pins: 2, 4, 9, 11, 16, 18, 22, 24, 46 and 48.
Output signal is measured from one of the following pins: 30, 32, 39 and 41.
1µ 5.7k
0.47µ
1µ 5.7k
10µ
10µ
10µ
10µ
V2
75
600
75
75
0.47µ
75
5.7k 1µ 600
0.47µ
5.7k 1µ 600
0.1µ
5.7k 1µ 600
0.47µ
5.7k 1µ
µ-com
Fig. 2-a. Audio system (gain, frequency response characteristics, total harmonic distortion, input dynamic range, cross talk) measurement circuit (CXA2089Q)
Input signal
600
75
600
10k
10k
10k
10k
39 LOUT1
V1
10µ
LV1
10k
38 CIN1
C1
0.1µ
RV4
YIN1
BIAS
MUTE
S2-1
75
37
VCC
S-1
– 12 –
C2
10µ
25
26
27
28
29
30
31
32
33
22µ
10µ
VOUT2
10k
10µ
ROUT2
34
10µ
YOUT2
10k
10µ
LOUT2
35
10µ
10k
COUT2
36
1k
10k
DC OUT
Y2
0.47µ
10k
SDA
RV2
75
SCL
LV2
ADR
Measurement point
CXA2089Q/S
– 13 –
TRAP
10k
10µ
42
1k
41
8
40
22µ
9
14
13
10
11
600
1µ
600
75
600
1µ
75
600
1µ
75
16
17
18
19
75
600
1µ
75
600
1µ
75
0.47µ 5.7k 0.47µ 5.7k 0.1µ
15
Signal is input from one of the following pins: 4, 6, 8, 10, 15, 17, 22, 24, 28 and 30.
Output signal is measured from one of the following pins: 36, 38, 45 and 47.
75
1µ
12
36
25
37
26
38
27
39
28
0.1µ
29
5.7k
30
5.7k 0.47µ
31
10µ
32
10µ
33
10µ
75
34
10µ
1µ
35
10µ
5.7k 0.47µ 5.7k 0.47µ 5.7k 0.47µ 5.7k 0.1µ
5
7
43
6
44
10µ 0.47µ
75
20
22
23
24
75
600
1µ
75
600
1µ
0.47µ 5.7k 0.47µ 5.7k
21
Input signal
Fig. 2-b. Audio system (gain, frequency response characteristics, total harmonic distortion, input dynamic range, cross talk) measurement circuit (CXA2089S)
10k
10µ
4
1
3
2
YOUT1
45
ROUT1
GND
46
VOUT1
COUT1
47
LOUT1
LTV
48
10µ 0.1µ
CIN1
TV
1µ
VOUT2
RV1
10k
ROUT2
C1
10µ
BIAS
RTV
10k
YOUT2
S2-1
10µ
YIN1
V1
10k
LOUT2
S-1
LV2
MUTE
LV1
10k
COUT2
V2
Y2
10k
DC-OUT
RV2
75
SDA
C2
75
SCL
S2-2
10k
ADR
S-2
10k
RV4
V3
10k
V4
600
LV4
LV3
VCC
Y1
600
S-3
Y3
+9V
S2-3
µ-COM
C3
RV3
Measurement point
CXA2089Q/S
1µ
0.47µ
1µ
10µ
10µ
10µ
10µ
COUT1
GND
TV
1µ
600
0.47µ
75
3
75
0.47µ
2
1
48 RTV
47
46 LTV
45
44
43 YOUT1
42
1µ
600
4
75
0.1µ
75
0.47µ
7
6
5
8
1µ
600
9
10
75
0.47µ
1µ
600
11
75
12
0.1µ
S2-2 13
S-2 14
V3 15
LV3 16
Y3 17
RV3 18
C3 19
S-3 21
LV4 22
V4 23
24
TRAP1
Y1
S2-3 20
RV1
41 ROUT1
40 VOUT1
LOUT1
V2
0.47µ
1µ
0.47µ
1µ
0.1µ
1µ
0.47µ
1µ
75
600
75
600
75
600
75
600
µ-com
Fig. 3-a. Audio system (ripple rejection ratio) measurement circuit (CXA2089Q)
A f=100Hz, 0.3Vp-p signal is applied to Vcc and the output signals from Pins 30, 32, 39 and 41 are measured.
600
75
600
10k
10k
10k
10k
39
V1
10µ
CIN1
LV1
10k
38
C1
0.1µ
YIN1
RV4
MUTE
BIAS
VCC
S2-1
75
37
25
26
27
28
29
30
31
32
33
34
10µ
VOUT2
35
10µ
10k
ROUT2
10k
10µ
YOUT2
36
10µ
10k
LOUT2
10k
10µ
COUT2
S-1
– 14 –
C2
10µ
1k
10k
DC OUT
Y2
0.47µ
Input signal
SDA
RV2
75
SCL
LV2
ADR
Measurement point
CXA2089Q/S
75
46
VOUT1
COUT1
47
ROUT1
GND
2
48
TRAP
YOUT1
1
10k
10k
75
600
75
600
0.47µ 1µ
RTV
0.47µ 1µ
Y1
75
600 75
0.1µ
12
15
75
Y2
17
RV2
75
C2
75
S2-2
19
0.1µ
18
600
0.47µ 1µ
16
600
0.47µ 1µ
RV1
11
C1
10
S2-1
0.47µ 1µ
9
20
V3
600
600
75
24
75
23
Y3
0.47µ 1µ
22
RV3
0.47µ 1µ
21
LV3
A f=100Hz, 0.3Vp-p signal is applied to Vcc and the output signals from Pins 36, 38, 45 and 47 are measured.
600
1µ
LV1
8
S-2
Fig. 3-b. Audio system (ripple rejection ratio) measurement circuit (CXA2089S)
10µ
10µ
TV
5
14
45
LOUT1
LTV
S-1
13
44
CIN1
7
43
BIAS
V1
6
42
YIN1
4
41
MUTE
3
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
VCC
0.1µ
VOUT2
1µ
75
ROUT2
600
YOUT2
1µ 0.47µ
75
LOUT2
10µ
600
COUT2
10µ
10k
DC-OUT
10µ
10k
SDA
10µ
10k
10k
SCL
10µ
10k
ADR
1k
Input
signal
RV4
10µ 0.47µ
75
V4
10µ 0.1µ
10k
LV4
10µ
10k
S-3
10µ
10k
+9V
S2-3
µ-COM
C3
V2
– 15 –
LV2
Measurement point
CXA2089Q/S
Measurement point
1µ
10µ
10µ
10µ
10µ
COUT1
GND
TV
75
0.47µ
2
1
48 RTV
47
46 LTV
45
44
43 YOUT1
3
0.1µ
1µ
75
600
600
4
1µ
75
0.47µ
75
0.47µ
7
6
5
8
9
10
600
1µ
75
0.47µ
11
12
1µ
75
0.1µ
600
S2-2 13
S-2 14
V3 15
LV3 16
Y3 17
RV3 18
C3 19
S-3 21
LV4 22
V4 23
24
42 TRAP1
Y1
S2-3 20
RV1
41 ROUT1
40 VOUT1
V2
75
0.47µ
75
1µ 600
75
1µ 600
0.47µ
0.1µ
75
600
1µ 600
0.47µ
1µ
µ-com
Fig. 4-a. Audio system (output DC offset voltage) measurement circuit (CXA2089Q)
600
1µ
75 0.47µ
600
10k
10k
10k
10k
39 LOUT1
V1
10µ
LV1
10k
38 CIN1
C1
0.1µ
RV4
YIN1
BIAS
MUTE
S2-1
75
37
25
26
27
28
29
30
VCC
S-1
– 16 –
C2
10µ
33
VOUT2
10µ
31
32
ROUT2
10µ
YOUT2
34
10µ
10k
LOUT2
35
22µ
10k
10k
10µ
COUT2
36
1k
10k
10µ
DC OUT
Y2
0.47µ
10k
SDA
RV2
75
SCL
LV2
ADR
Measurement point
CXA2089Q/S
10k
– 17 –
10k
10k
YOUT1
10µ
GND
10µ
TV
75
LV1
9
Y1
600
0.47µ
1µ
8
75
RV1
C1
75
0.1µ
11
600
1µ
10
S2-1
12
75
S-1
0.47µ
LV2
16
Y2
600
0.47µ
1µ
15
75
RV2
C2
75
S2-2
19
0.1µ
18
600
1µ
17
S-2
21
75
0.47µ
20
V3
Fig. 4-b. Audio system (output DC offset voltage) measurement circuit (CXA2089S)
600
0.47µ
75
0.47µ
600
1µ
RTV
1µ
5
14
47
ROUT1
V2
13
46
VOUT1
COUT1
7
45
LOUT1
LTV
V1
6
44
CIN1
4
43
BIAS
3
42
YIN1
2
41
MUTE
1
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
VCC
0.1µ
75
VOUT2
1µ
0.47µ
600
ROUT2
75
YOUT2
1µ
600
LOUT2
10µ
10k
COUT2
10µ 10µ
10k
DC-OUT
10µ 10µ
10k
SDA
22µ
10k
SCL
1k
75
ADR
10µ 0.47µ
0.1µ
75
RV4
24
75
600
0.47µ 1µ
23
600
1µ
22
LV3
48
10k
V4
10µ 10µ
10k
LV4
10µ
10k
S-3
Y3
TRAP
+9V
S2-3
µ-COM
C3
RV3
Measurement point
Measurement point
CXA2089Q/S
1µ
0.47µ
1µ
10µ
10µ
10µ
10µ
10µ
VOUT1
LOUT1
TRAP1
COUT1
GND
1µ
600
75
2
1
RTV
TV
0.47µ
48
47
46 LTV
45
44
43 YOUT1
42
41 ROUT1
40
39
CIN1
75
0.47µ
3
Y1
1µ
600
4
75
0.1µ
75
0.47µ
7
6
5
8
1µ
600
9
10
75
0.47µ
1µ
600
11
75
24
12
0.1µ
S2-2 13
S-2 14
V3 15
LV3 16
Y3 17
RV3 18
C3 19
S2-3 20
S-3 21
LV4 22
V4 23
RV4
0.47µ
1µ
0.47µ
1µ
0.1µ
1µ
0.47µ
1µ
Fig. 5-a. Audio system (residual noise) measurement circuit (CXA2089Q)
600
75
600
10k
10k
10k
10k
10k
38
V1
0.1µ
BIAS
LV1
75
37
25
26
27
28
29
30
31
32
33
34
YIN1
RV1
10µ
10µ
MUTE
10k
10µ
35
10µ
VCC
36
22µ
10k
10µ
VOUT2
V2
4.5V
10µ
10k
ROUT2
1k
10k
YOUT2
Y2
0.47µ
10k
LOUT2
RV2
75
COUT2
C1
DC OUT
S2-1
SDA
C2
– 18 –
S-1
SCL
LV2
ADR
75
600
75
600
75
600
75
600
µ-com
Measurement point
CXA2089Q/S
10k
1
10µ
10k
10µ
10k
TV
75
LV1
9
Y1
600
0.47µ
1µ
8
600
1µ
75
0.1µ
75
RV1
0.47µ
C1
12
S2-1
11
S-1
10
16
Y2
600
0.47µ
1µ
15
RV2
C2
19
75
0.1µ
18
600
1µ
17
S2-2
Fig. 5-B. Audio system (residual noise) measurement circuit (CXA2089S)
600
0.47µ
0.47µ
600
1µ
RTV
1µ
5
75
2
48
TRAP
YOUT1
75
47
ROUT1
GND
75
46
VOUT1
COUT1
14
45
LOUT1
LTV
V2
13
44
CIN1
7
43
BIAS
V1
6
42
YIN1
4
41
MUTE
LV2
– 19 –
3
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
VCC
0.1µ
75
VOUT2
1µ
600
ROUT2
0.47µ
YOUT2
75
LOUT2
1µ
600
COUT2
10µ
10k
DC-OUT
10µ
10k
SDA
10µ
10k
SCL
10µ 10µ
10k
ADR
22µ
10k
RV4
1k
75
V4
10µ 0.47µ
0.1µ
75
LV4
10µ 10µ
10k
S-3
10µ
10k
+9V
S2-3
µ-COM
C3
Measurement point
S-2
75
21
V3
0.47µ
20
LV3
Y3
24
RV3
75
600
0.47µ 1µ
23
600
1µ
22
CXA2089Q/S
CXA2089Q/S
I2C BUS Control Signal
34 SDA
tBUF
33 SCL
tLOW
tR
tHD;STA
P
tHIGH
tF
tSU;DAT
tSU;STA
tSU;STO
tHD;DAT
S
S
P
Fig. 6. I2C BUS Control Signal Timing Chart
Description of Operation
The CXA2089Q/S is a TV I2C bus-compatible AV switch IC. The video system and the stereo audio system
both have 5 inputs and 2 outputs each. 3 of the 5 video system inputs support S2 and S protocols.
The desired inputs can be independently assigned to each output (in the audio system, the left and right
channels are processed as one unit) by I2C bus control. However, the same input is assigned to both the video
and audio system output 2.
I2C BUS Registers
1) I2C BUS
The I2C bus (inter-IC bus) is an inter-IC bus system developed by Philips. Two lines (SDA – serial data, SCL –
serial clock) provide control over start, stop, data transfer, synchronization, and collision avoidance. The IC
outputs are either open collector or open drain, forming a bus line in the wired OR format.
SDA
A
MSB
LSB
A
MSB
LSB
SCL
S
P
1
2
3
4
5
6
7
8
9
1
2
9
S: Start condition; SDA is set "Low" when SCL is "High"
P: Stop condition; SDA is set "High" when SCL is "High"
A: Acknowledge; signal sent from the slave
Data is transmitted by MSB-first. One data unit consists of 8 bits, to which the acknowledge signal, which
indicates that the data has been accepted by the slave, is attached at the end. Normally, the slave∗1 IC
receives data at the rising edge of SCL and the master∗2 IC changes data at the falling edge of SCL.
∗1 Slave: An IC that is placed under the control of the master. In a normal system, all devices excluding the
central microcomputer are slaves.
∗2 Master: A central microcomputer or other controlling IC.
– 20 –
CXA2089Q/S
2) Control Registers
The CXA2089Q/S control is exercised by writing 2-byte data into the two 8-bit control registers which control
the output selector circuits for the 2 outputs.
S
Slave address
A
DATA1
A
DATA2
A P
S: Start condition
A: Acknowledge
P: Stop condition
Control register structure (DATA1 and DATA2)
• All registers are set to "0" during IC power on.
• "∗" indicates undefined.
b7
b6
b5
b4
b3
b2
b1
b0
Slave add.
1
0
0
1
0
0
ADR
R/W
DATA1
A-GAIN
S/COMP1
V-IN1
DATA2
∗
S/COMP2
AV-IN2
A-IN1
DC OUT
∗
R/W (1): Read/write mode
0: Control data write
1: Status register read
ADR (1): This bit sets the slave address set by the address pin.
0: 90H
1: 92H
A-GAIN (1): LOUT1/ROUT1 output gain selector
0: 0dB output
1: –6dB output
S/COMP1 and S/COMP2 (1 each): S terminal input/composite signal input selectors
By setting S/COMP1 to "0", when composite signal input is selected, YOUT1/COUT1 output the
inputs from YIN1/CIN1.
0: Composite signal inputs (TV, V1 to V4 inputs)
1: S terminal inputs (Y1/C1 to Y3/C3 inputs)
V-IN1 (3 each): This bit selects the input signals output to each video output.
0: Mute
1: Selects the TV input
2: Selects the V1 and Y1/C1 inputs
3: Selects the V2 and Y2/C2 inputs
4: Selects the V3 and Y3/C3 inputs
5: Selects the V4 inputs
6: Mute
7: Mute
– 21 –
CXA2089Q/S
A-IN1 (3 each): This bit selects the input signals output to each audio output.
0: Mute
1: Selects the LTV/RTV inputs
2: Selects the LV1/RV1 inputs
3: Selects the LV2/RV2 inputs
4: Selects the LV3/RV3 inputs
5: Selects the LV4/RV4 inputs
6: Mute
7: Mute
AV-IN2 (3): This bit selects the input signals output to output 2 (VOUT2, YOUT2/COUT2, LOUT2/ROUT2).
Note) Both the video output and the audio output are selected at the same time only for AV-IN2.
0: Mute
1: Selects the TV and LTV/RTV inputs
2: Selects the V1, Y1/C1 and LV1/RV1 inputs
3: Selects the V2, Y2/C2 and LV2/RV2 inputs
4: Selects the V3, Y3/C3 and LV3/RV3 inputs
5: Selects the V4 and LV4/RV4 inputs
6: Mute
7: Mute
DC OUT (2): This bit sets the DC voltage output from DC OUT.
0: 4.5V
1: 0V
2: 1.9V
3: 4.5V
3) Status Registers
• When reading two bytes
S
Slave address
A
DATA1
A
DATA1
A
DATA2
NA P
• When reading one byte
S
Slave address
NA P
S: Start condition
A: Acknowledge
NA: No acknowledge
P: Stop condition
When communication is to be terminated in the status register reading mode, the no-acknowledge signal is
needed to assure that the master does not issue the acknowledge signal to the slave.
It is possible to read only DATA1 of the status register by sending the no-acknowledge signal after DATA1.
– 22 –
CXA2089Q/S
Status register structure (DATA1 and DATA2)
"∗" indicates undefined.
b7
b6
b5
b4
b3
b2
b1
b0
Slave add.
1
0
0
1
0
0
ADR
1
DATA1
S1SEL
S2SEL
S3SEL
∗
S-C1
S-C2
DATA2
S1SEL
S2SEL
S3SEL
∗
S-C3
∗
S1SEL to S3SEL (1 each): S-1 to S-3 pin status
0: S-1 to S-3 pins are not grounded.
1: S-1 to S-3 pins are grounded.
S1SEL to S3SEL are actually determined by comparing the S-1 to S-3 pin DC voltages with 3.5V.
S-1 to S-3 pin DC voltage
S1SEL to S3SEL
3.5V or more
0
3.5V or less
1
S-C1, S-C2, S-C3 (2 each): S2-1, S2-2 and S2-3 pin status
0: 4:3 video signal
1: 4:3 letter-box signal
2: 16:9 video squeezed signal
3: No signal
S-C1 to S-C3 are actually determined by comparing the S2-1 to S2-3 pin DC voltages with two
threshold. However, when the S-1 to S-3 pins are open, the outputs are fixed to "3".
S2-1 to S2-3 pin DC voltage
S-C1 to S-C3
1.3V or less
0
1.3V or more to 2.5V or less
1
2.5V or more
2
S-1 to S-3 OPEN
3
4) Power-on Reset
The CXA2089Q/S has an internal power-on reset function that sets each control register to "0" during IC power
ON.
The power-on reset VTH has hysteresis.
Power-on reset
released
Power-on reset
VCC
4.5V
5.6V
– 23 –
TV input
75
10p
10µ
1µ 1.2k
0.47µ
1µ 1.2k
180µ
620
RTV
75
1µ
9
10
11
12
VIDEO 2 input
0.1µ
75
0.1µ
0.47µ
1.2k 1µ
0.47µ
1.2k 1µ
1µ
S2-2 13
S-2 14
V3 15
LV3 16
Y3 17
RV3 18
C3 19
S2-3 20
1.2k 1µ
0.47µ
1.2k 1µ
75
470k
75
470k
75
1µ
75
VIDEO 3 input
VIDEO 4 input
• Depending on the output bias of the comb filters, pay
attention to the polarities of the capacitors since the
bias at Pins 36 and 38 is approximately 3.1V and
4.5V, respectively.
• Connect Pin 25 to Vcc when setting the slave address
of the IC to 92H.
• The audio output can be muted by setting Pin 35 to
3.5V or more.
• The TRAP (Pin 42) are of 3.58MHz subcarrier.
• Pay attention to the polarities of the capacitors since
each output of video system and audio system has
optional bias, respectively.
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
VIDEO 1 input
470k
75
8
0.47µ 1.2k 0.47µ 1.2k
1µ
1µ
75 470k
75 470k
7
6
5
0.1µ
4
470k
3
2
0.47µ 1.2k
1µ
1
0.47µ 1.2k
1µ
75
48
47 TV
46 LTV
45 COUT1
44 GND
43 YOUT1
42 TRAP1
41 ROUT1
V1
VIDEO 1 output
S-3 21
V4 23
RV4
24
40 VOUT1
LV1
10µ
Y1
LV4 22
V2
39 LOUT1
RV1
10µ
38 CIN1
BIAS
YIN1
C1
0.1µ
MUTE
S2-1
COMB
FILTER
37
25
26
VCC
220
27
220
28
VOUT2
4.7k
29
30
31
32
10µ
ROUT2
33
10µ
YOUT2
Y2
10µ
10µ
LOUT2
34
10µ
COUT2
35
22µ
DC OUT
36
1k
0.1µ
75
SDA
RV2
0.47µ
VIDEO 2 output
µ-com
SCL
LV2
ADR
S-1
– 24 –
C2
Application Circuit (CXA2089Q)
CXA2089Q/S
– 25 –
3
10µ
5
7
6
8
75
1µ
75
470k
1µ
0.47µ 1.2k 0.47µ 1.2k
TV input
1µ
1.2k
4
10
470k
1µ
75
0.1µ
11
Video1 input
75
0.47µ 1.2k
9
1µ
12
• Depending on the output bias of the comb filters, pay attention to the polarities of the capacitors
since the bias at Pins 42 and 44 is approximately 3.1V and 4.5V, respectively.
• Connect Pin 31 to Vcc when setting the slave address of the IC to 92H.
• The audio output can be muted by setting Pin 41 to 3.5V or more.
• The TRAP (Pin 48) are of 3.58MHz subcarrier.
• Pay attention to the polarities of the capacitors since each output of video system and audio
system has optional bias, respectively.
10µ
2
1
15
16
17
75
470k
1µ
470k
1µ
19
20
22
23
24
75
75
1µ
470k
Video3 input
470k
1µ
0.47µ 1.2k 0.47µ 1.2k
21
0.1µ
Application circuits shown are typical examples illustrating the operation
of the devices. Sony cannot assume responsibility for any problems
arising out of the use of these circuits or for any infringement of third
party patent and other right due to same.
75 1µ
0.1µ
18
Video2 input
75
0.47µ 1.2k 0.47µ 1.2k
14
13
25
26
27
28
29
30
31
32
33
34
35
36
37
38
1.2k
39
10µ
40
22µ
10µ
41
10µ
75
42
10µ
1µ
43
1k
1µ
44
10µ 0.47µ
220
1µ 75
220
1.2k
0.47µ
45
0.1µ
4.7k
46
10µ
0.1µ
75
47
10µ
+9V
Video4 input
48
620
180µ
COMB
FILTER
Video2 output
µ-COM
TRAP
YOUT1
ROUT1
GND
VOUT1
COUT1
LOUT1
LTV
CIN1
TV
BIAS
RTV
YIN1
V1
MUTE
LV1
VCC
Y1
VOUT2
RV1
ROUT2
C1
YOUT2
S2-1
LOUT2
S-1
COUT2
V2
DC-OUT
LV2
SDA
Y2
SCL
RV2
ADR
C2
RV4
S2-2
V4
S-2
LV4
V3
S-3
LV3
S2-3
Y3
C3
RV3
10p
Video1 output
Application Circuit (CXA2089S)
CXA2089Q/S
CXA2089Q/S
Example of Representative Characteristics
Video system frequency response characteristics
Y1/C1 to Y3/C3
→ VOUT1, VOUT2
2
0
–2
100k
2
Audio system input/output gain [dB]
6
4
Audio system frequency response characteristics
TV, V1 to V4 → VOUT1, VOUT2
Y1 to Y3 → YOUT1, YOUT2
C1 to C3 → COUT1, COUT2
L/RTV, L/R1 to L/R4 → LOUT1 (0dB)
L/RTV, L/R1 to L/R4 → LOUT2
0
–2
–4
L/RTV, L/R1 to L/R4 → LOUT1 (–6dB)
–6
–8
1M
10M
Frequency [Hz]
10k
1k
100M
100k
Frequency [Hz]
Audio system distortion vs. Input amplitude
10
f = 1kHz
400Hz HPF, 80kHz LPF
1
Total harmonic distortion [%]
Video system input/output gain [dB]
8
0.1
LOUT1 output (0dB gain)
LOUT2 output
0.01
0.002
0
1
2
Input amplitude [Vrms]
– 26 –
3
4
1M
CXA2089Q/S
Package Outline
Unit: mm
CXA2089Q
48PIN QFP (PLASTIC)
15.3 ± 0.4
+ 0.1
0.15 – 0.05
+ 0.4
12.0 – 0.1
36
25
0.15
24
48
13
13.5
37
12
0.8
+ 0.15
0.3 – 0.1
± 0.12 M
0.9 ± 0.2
1
+ 0.2
0.1 – 0.1
+ 0.35
2.2 – 0.15
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
QFP-48P-L04
LEAD TREATMENT
SOLDER / PALLADIUM
PLATING
EIAJ CODE
∗QFP048-P-1212-B
LEAD MATERIAL
COPPER / 42 ALLOY
PACKAGE WEIGHT
0.7g
JEDEC CODE
NOTE : PALLADIUM PLATING
This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame).
– 27 –
CXA2089Q/S
CXA2089S
+ 0.1 5
0.0
0.25 –
48PIN SDIP (PLASTIC)
+ 0.4
43.2 – 0.1
25
15.24
+ 0.3
13.0 – 0.1
48
1
0° to 15°
24
0.5 ± 0.1
0.9 ± 0.15
Two kinds of package surface:
1.All mat surface type.
2.Center part is mirror surface.
+ 0.4
4.6 – 0.1
3.0 MIN
0.5 MIN
1.778
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
SDIP-48P-02
LEAD TREATMENT
SOLDER/PALLADIUM
PLATING
EIAJ CODE
SDIP048-P-0600
LEAD MATERIAL
42/COPPER ALLOY
PACKAGE MASS
5.1g
JEDEC CODE
– 28 –