CXA2079Q S2-Compatible 6-Input 2-Output Audio/Video Switch Description The CXA2079Q is a 6-input, 2-output audio/video switch featuring I2C bus compatibility for TVs. This IC has input pins that are compatible with S2 protocol. Features • 4 inputs that are compatible with S2 protocol • Serial control with I2C bus • 6 inputs, 2 outputs • The desired inputs can be selected independently for each of the 2 outputs • Wide band video amplifier (20MHz, –3dB) • Y/C MIX circuit • Slave address can be changed (90H/92H) • Audio muting from external pin • High impedance maintained by I2C bus lines (SDA, SCL) even when power is OFF • Wide audio dynamic range (3Vrms typ.) 64 pin QFP (Plastic) Absolute Maximum Ratings • Supply voltage VCC • Operating temperature Topr • Storage temperature Tstg • Allowable power dissipation PD Operating Conditions Supply voltage 12 –20 to +75 –65 to +150 1300 V °C °C mW 9 ± 0.5 V Applications Audio/video switch featuring I2C bus compatibility for TVs Structure Bipolar silicon monolithic IC Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E97430A7Y CXA2079Q Block Diagram TV 63 V1 1 V2 8 6dB 53 VOUT1 49 YIN1 V3 15 56 YOUT1 6dB V4 22 55 TRAP1 V5 60 6dB 58 COUT1 Y1 3 51 CIN1 Y2 10 6dB 41 VOUT2 Y3 17 45 Y4 24 39 YOUT2 6dB C1 5 YIN2 6dB C2 12 37 COUT2 C3 19 43 CIN2 57 VGND C4 26 BIAS 50 BIAS 42 VCC 35 AGND 6dB LTV 62 LV1 44 AGND2 52 LOUT1 2 0dB LV2 9 54 ROUT1 LV3 16 6dB LV4 23 LV5 59 38 LOUT2 0dB 40 ROUT2 6dB 36 DC OUT RTV 64 RV1 33 SCL 6dB 4 34 SDA RV2 11 32 ADR RV3 18 7 RV4 25 S-1 14 S-2 RV5 61 Logic 21 S-3 28 S-4 NC 29 6 NC 30 13 S2-2 NC 31 20 S2-3 S2-1 NC 46 27 S2-4 NC 47 48 MUTE Audio system is attenuated by 6dB for 6kΩ resistor input, and a total gain is 0dB (LOUT1 and ROUT1 can be changed to –6dB). –2– CXA2079Q SCL SDA AGND DC OUT COUT2 YOUT2 LOUT2 ROUT2 VOUT2 VCC CIN2 AGND2 YIN2 NC NC MUTE YIN1 BIAS CIN1 Pin Configuration 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 LOUT1 52 ADR VOUT1 53 31 NC ROUT1 54 30 NC TRAP1 55 29 NC YOUT1 56 28 S-4 VGND 57 27 S2-4 COUT1 58 26 C4 LV5 59 25 RV4 V5 60 24 Y4 RV5 61 23 LV4 LTV 62 22 V4 TV 63 21 S-3 RTV 64 Y1 RV1 C1 S2-1 S-1 V2 LV2 C3 LV1 –3– Y3 9 10 11 12 13 14 15 16 17 18 19 RV3 8 V3 7 LV3 6 S-2 5 S2-2 4 C2 3 RV2 2 Y2 1 V1 20 S2-3 CXA2079Q Pin Description Pin No. Symbol 63 1 8 15 22 60 TV V1 V2 V3 V4 V5 3 10 17 24 49 45 Y1 Y2 Y3 Y4 YIN1 YIN2 Pin voltage Equivalent circuit VCC 63 15 4.0V 1 150 Video signal inputs. Input composite video signals. 22 3µA 60 8 3 Y/C separation signal inputs. Input luminance signals. The YIN1 pin inputs the signal obtained by Y/C separating the VOUT1 pin output. The YIN2 pin inputs the signal obtained by Y/C separating the VOUT2 pin output. VCC 10 150 17 4.0V 3µA 24 49 45 5 12 19 26 51 43 C1 C2 C3 C4 CIN1 CIN2 5 Y/C separation signal inputs. Input chrominance signals. The CIN1 pin inputs the signal obtained by Y/C separating the VOUT1 pin output. The CIN2 pin inputs the signal obtained by Y/C separating the VOUT2 pin output. VCC 20k 12 150 19 4.5V 26 27k 51 43 62 2 9 16 23 59 64 4 11 18 25 61 LTV LV1 LV2 LV3 LV4 LV5 RTV RV1 RV2 RV3 RV4 RV5 Description 62 64 2 4.5V VCC 33k 4 27k 9 11 Audio signal inputs. 16 18 15k 23 25 59 61 VCC 250 VCC 53 41 VOUT1 VOUT2 3.9V Video signal outputs. Output composite video signals. 30k 53 41 27k –4– 23.5k CXA2079Q Pin No. Symbol Pin voltage Equivalent circuit Description VCC VCC VCC VCC 56 39 YOUT1 YOUT2 3.3V Video signal outputs. Output luminance signals. 56 39 VCC VCC VCC VCC 58 37 COUT1 COUT2 4.5V Video signal outputs. Output chrominance signals. 58 37 VCC 52 38 54 40 LOUT1 LOUT2 ROUT1 ROUT2 VCC 52 56 38 4.5V 54 20k 40 20k VCC 6 13 20 27 S2-1 S2-2 S2-3 S2-4 6 — S-1 S-2 S-3 S-4 13 147 20 100k 27 7 — VCC 50k VCC 100k 14 50k 21 28 10k VCC 32 ADR VCC VCC 5V 7 14 21 28 Audio signal outputs. Zo = 50Ω (within DC ± 2mA) — 147 72k 32 28k –5– VCC Detects the S2-compatible DC superimposed onto the C signal. 4:3 video signal at 1.3V or less 4:3 letter-box signal at 1.3V or more to 2.5V or less 16:9 picture squeezed signal at 2.5V or more These pins are pulled down to GND by a 100kΩ resistor, so the 4:3 video signals are selected when open. Composite video/S selector. The detection results are written to the status register. S signal at 3.5V or less Composite video signal at 3.5V or more These pins are pulled up to 5V by a 100kΩ resistor, so the composite video signals are selected when open. Selects the slave address for the I2C bus. 90H at 1.5V or less 92H at 2.5V or more 90H when open CXA2079Q Pin No. Symbol Pin voltage Equivalent circuit Description VCC 33 SCL I2C bus signal input VILmax = 1.5V VIHmin = 3.0V 4k — 33 10k VCC 34 SDA — I2C bus signal input VILmax = 1.5V VIHmin = 3.0V VOLmax = 0.4V 4k 34 VCC 36 DC OUT — 4k 1k 36 Q1 28k Outputs the S2-compatible DC superimposed onto the COUT2 output. The DC is superimposed by connecting this pin to the COUT2 output via a capacitor. Control is performed by the I2C bus. When 0V is output, Q1 is ON and the impedance is 5kΩ. S2 protocol output DC impedance of 10 ± 3kΩ is realized by attaching external resistance of 4.7kΩ. DC OUT (bus) Output DC 0 4.5V 1 0V 2 1.9V 3 4.5V VCC 100 55 TRAP1 55 3.8V Connects trap circuit for subcarrier. 1k VCC 48 MUTE — 147 Audio signal output mute. Mute OFF at 1.5V or less Mute ON at 2.5V or more Mute OFF when open 72k 48 28k VCC VCC 50 BIAS 4.5V VCC 20k 147 50 20k –6– Internal reference bias (Vcc/2). Connects to GND via a capacitor. CXA2079Q Electrical Characteristics Item Current consumption (Ta = 25°C, VCC = 9V) Symbol ICC Conditions No signal, no load Min. Typ. Max. Unit 30 45 62 mA 5.9 6.4 6.9 dB 15 20 — MHz 10 15 — MHz Video system (Measurement circuit; Fig. 1) Gain GVv f = 100kHz, 0.3Vp-p input Frequency response characteristics FBWv1 Frequency response characteristics (Y/C mix) FBWv2 Input dynamic range Ddv f = 100kHz, maximum with distortion < 1.0% 1.4 — — Vp-p Cross talk Vctv f = 4.43MHz, 1Vp-p input — — –50 dB f = 100kHz, input frequency where output amplitude is –3dB with 0.3Vp-p output serving as 0dB Audio system (Measurement circuits; Fig. 2 to Fig. 5) Gain GVA f = 1kHz, 1Vp-p input, 5.7kΩ resistor inserted to input –1 0 1 dB Frequency response characteristics FBWA f = 1kHz, input frequency where output amplitude is –3dB with 1Vp-p output serving as 0dB 50 — — kHz Total harmonic distortion THD f=1kHz, 2.2Vp-p input, where 400Hz HPF + 80kHz LPF are inserted — 0.03 0.05 % Input dynamic range DdA f=1kHz, maximum with distortion < 0.3% 2.8 3.0 — Vrms Cross talk VctA f=1kHz, 1Vp-p input — –90 –80 dB Ripple rejection ratio VctA f=100Hz, 0.3Vp-p applied to Vcc — –55 –40 dB Output DC offset Voff Offset voltage between input and output –30 — 30 mV Residual noise VNA When 400Hz HPF+ 30kHz LPF are inserted 0 20 30 µVrms S/N ratio S/N f=1kHz, 1Vrms input When 400Hz HPF + 30kHz LPF are inserted –100 –90 dB –7– CXA2079Q Logic system Item Symbol Conditions Min. Typ. Max. Unit High level input voltage VIH 3.0 — 5.0 V Low level input voltage VIL 0 — 1.5 V Low level output voltage VOL With SDA 3mA current supplied 0 — 0.4 V High level input current IIH VIH = 4.5V 0 — 10 µA Low level input current IIL VIL = 0.4V 0 — 10 µA Maximum clock frequency fSCL 0 — 100 kHz Minimum waiting time for data change tBUF 4.7 — — µs Minimum waiting time for data transfer start tHD;STA 4.0 — — µs Low level clock pulse width tLOW 4.7 — — µs High level clock pulse width tHIGH 4.0 — — µs Minimum waiting time for start preparation tSU;STA 4.7 — — µs Minimum data hold time tHD;DAT 0 — — ns Minimum data preparation time tSU;DAT 250 — — ns — — 1 µs Fall time tR tF — — 300 ns Minimum waiting time for stop preparation tSU;STO 4.7 — — µs Rise time –8– 1µ 0.47µ 1µ 1µ 0.47µ 1µ 10µ 1µ 1µ LV2 V2 RV1 Y1 1µ 1µ 1µ NC 31 32 1µ 600 75 3 600 4 75 75 0.47µ 7 6 5 0.1µ 8 600 9 10 75 0.47µ 600 11 12 75 0.1µ 15 75 0.47µ 14 13 600 17 75 0.47µ 16 600 Signal is input from one of the following pins: 1, 3, 5, 8, 10, 12, 15, 17, 19, 22, 24, 26, 60 and 63. Output signal is measured from one of the following pins: 37, 39, 41, 53, 56 and 58. 75 0.47µ 2 0.47µ 1 64 RTV 63 TV 62 LTV 61 RV5 60 V5 59 LV5 18 S2-3 20 19 75 0.1µ S-3 21 V4 22 LV4 23 Y4 24 RV4 25 C4 26 S2-4 27 57 VGND 58 COUT1 S-4 28 56 YOUT1 0.47µ 1µ 0.47µ 1µ 0.1µ 75 600 75 600 75 µ-com Fig. 1. Video system (gain, frequency response characteristics, input dynamic range, cross talk) measurement circuit Input signal 600 75 600 600 75 600 10k Y2 NC 29 V1 10k RV2 55 TRAP1 C2 NC 30 V3 54 ROUT1 VOUT1 LV1 10µ CIN1 C1 10k 53 BIAS S2-1 10µ YIN1 ADR 48 MUTE LOUT1 47 NC S-1 10k 52 46 NC S2-2 10µ 33 34 35 36 37 38 39 40 41 42 43 44 45 YIN2 10k 10µ AGND2 49 10µ CIN2 50 22µ 10µ VCC 51 0.1µ 10k VOUT2 10k 10µ ROUT2 0.47µ 10k YOUT2 10k 10µ LOUT2 Y3 10k 1k 75 COUT2 0.47µ 75 DC OUT S-2 –9– C3 10µ 10µ 75 AGND RV3 0.1µ 75 SDA LV3 SCL Measurement point CXA2079Q 1µ 5.7k 75 V2 RV1 Y1 5.7k 75 75 NC 31 32 75 600 75 1µ 5.7k 4 600 0.1µ 75 0.47µ 7 6 5 8 1µ 9 10 600 75 0.47µ 11 1µ 5.7k 600 12 0.1µ 75 0.47µ 14 13 15 17 1µ 600 75 5.7k 0.47µ 16 Signal is input from one of the following pins: 2, 4, 9, 11, 16, 18, 23, 25, 59, 61, 62 and 64. Output signal is measured from one of the following pins: 38, 40, 52 and 54. 1µ 3 0.47µ 2 5.7k 1 RTV TV LTV 0.47µ 64 63 62 61 RV5 60 V5 59 LV5 1µ 5.7k 18 600 19 0.1µ S2-3 20 S-3 21 V4 22 LV4 23 Y4 24 RV4 25 C4 26 S2-4 27 57 VGND 58 COUT1 S-4 28 0.47µ 5.7k 1µ 0.47µ 5.7k 1µ 0.1µ 75 75 75 600 600 µ-com Fig. 2. Audio system (gain, frequency response characteristics, total harmonic distortion, input dynamic range, cross talk) measurement circuit Input signal 600 1µ 5.7k 600 75 0.47µ 1µ 5.7k 75 0.47µ 1µ 5.7k 600 600 10k 10µ LV2 56 YOUT1 V1 10k Y2 NC 29 RV2 55 TRAP1 LV1 10µ C2 NC 30 V3 54 ROUT1 VOUT1 C1 10k 53 CIN1 S2-1 10µ BIAS ADR YIN1 LOUT1 MUTE S-1 10k 52 47 NC S2-2 10µ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 NC 48 10µ YIN2 49 10µ AGND2 50 10µ CIN2 51 22µ 10k VCC 10k 10µ VOUT2 0.1µ 10k ROUT2 10k 10µ YOUT2 0.47µ 10k LOUT2 Y3 10µ 1k 75 COUT2 0.47µ 75 DC OUT S-2 – 10 – C3 10k 10µ 75 AGND RV3 0.1µ 75 SDA LV3 SCL Measurement point CXA2079Q 1µ 10µ 1µ 1µ 600 1µ 75 0.47µ 600 600 75 0.47µ 600 10k 1µ 75 1µ Y2 LV2 V2 RV1 Y1 1µ 75 1µ 1µ NC 31 32 1µ 600 0.47µ 75 3 600 4 0.1µ 75 0.47µ 7 6 5 8 600 9 10 75 0.47µ 600 11 12 0.1µ 15 75 0.47µ 14 13 600 17 75 0.47µ 16 600 18 75 19 0.1µ S2-3 20 S-3 21 V4 22 LV4 23 Y4 24 RV4 25 0.47µ 1µ 0.47µ 1µ 0.1µ Fig. 3. Audio system (ripple rejection ratio) measurement circuit 75 600 75 600 75 µ-com A f=100Hz, 0.3Vp-p signal is applied to Vcc and the output signals from Pins 38, 40, 52 and 54 are measured. 75 0.47µ 2 1 64 RTV 63 TV 62 LTV 61 RV5 60 V5 59 LV5 C4 26 S2-4 27 57 VGND 58 COUT1 S-4 28 56 YOUT1 NC 29 RV2 55 TRAP1 V1 10µ C2 NC 30 V3 54 ROUT1 VOUT1 LV1 10k CIN1 C1 10k 53 BIAS S2-1 10µ YIN1 ADR MUTE LOUT1 47 NC S-1 10k 52 46 NC S2-2 10µ 33 34 35 36 37 38 39 40 41 42 43 44 45 YIN2 48 10µ AGND2 49 10µ CIN2 50 10µ 10k VCC 10k 10µ VOUT2 51 0.1µ 10k ROUT2 10k 10µ YOUT2 0.47µ 10k LOUT2 Y3 10k 1k 75 COUT2 0.47µ 75 DC OUT S-2 – 11 – C3 10µ 10µ 75 AGND RV3 0.1µ 75 100Hz, 0.3Vp-p SDA LV3 SCL Measurement point CXA2079Q Measurement point 600 1µ 5.7k 600 1µ 5.7k 75 0.47µ 1µ 5.7k 75 0.47µ 1µ 5.7k 10µ 600 600 10k 75 5.7k Y2 LV2 V2 RV1 Y1 75 75 NC 31 32 75 600 75 1µ 600 0.1µ 75 0.47µ 7 6 5 8 1µ 9 10 600 75 0.47µ 11 1µ 5.7k 600 12 0.1µ 15 75 0.47µ 14 13 16 17 1µ 600 75 5.7k 0.47µ Fig. 4. Audio system (output DC offset voltage) measurement circuit 1µ 4 5.7k 3 2 5.7k 0.47µ 1 RTV 0.47µ 64 63 TV 62 LTV 61 RV5 60 V5 59 LV5 18 1µ 5.7k 600 19 0.1µ S2-3 20 S-3 21 V4 22 LV4 23 Y4 24 RV4 25 C4 26 S2-4 27 57 VGND 58 COUT1 S-4 28 56 YOUT1 NC 29 RV2 55 TRAP1 V1 10µ LV1 10k C2 NC 30 V3 54 ROUT1 53 VOUT1 C1 10µ ADR CIN1 LOUT1 BIAS S2-1 10k 52 YIN1 S-1 10µ MUTE S2-2 10k NC Y3 10k 33 34 35 36 37 38 39 40 41 42 43 44 45 46 NC 47 10µ YIN2 10k 10µ AGND2 48 10µ CIN2 10k 10µ VCC 49 10µ VOUT2 50 22µ 10k ROUT2 51 0.1µ 10k YOUT2 0.47µ 10k LOUT2 1k 75 COUT2 0.47µ 75 DC OUT S-2 – 12 – C3 10µ 10µ 75 AGND RV3 0.1µ 75 SDA LV3 SCL 75 0.47µ 75 0.47µ 5.7k 1µ 600 75 5.7k 1µ 600 0.1µ µ-com Measurement point CXA2079Q 1µ 1µ 1µ 600 1µ 75 0.47µ 600 600 75 0.47µ 600 10k 10µ 10µ 1µ 600 0.47µ 75 2 1 64 RTV 63 TV 62 LTV 61 RV5 60 V5 59 LV5 58 COUT1 57 VGND 56 YOUT1 3 75 0.47µ 1µ 75 0.1µ 75 0.47µ 7 6 5 8 1µ 600 9 10 75 0.47µ 1µ 600 11 75 12 0.1µ 15 75 0.47µ 14 13 1µ 600 17 75 0.47µ 16 Fig. 5. Audio system (residual noise) measurement circuit 600 4 1µ 600 18 75 19 0.1µ S2-3 20 S-3 21 V4 22 LV4 23 Y4 24 RV4 25 C4 26 S2-4 27 S-4 28 NC 29 55 TRAP1 V1 10k 32 NC 31 ADR NC 30 VOUT1 V2 54 ROUT1 53 LV1 10µ LOUT1 C1 10k 52 S2-1 10µ S-1 10k NC S2-2 10µ 33 34 35 36 37 38 39 40 41 42 43 10µ 44 10µ 45 10µ 46 22µ NC 47 0.1µ YIN2 0.47µ AGND2 S-2 – 13 – C3 10k 1k CIN2 LV2 CIN1 10k VCC 10k 10µ VOUT2 Y2 51 BIAS 10k ROUT2 10k 10µ YOUT2 RV2 0.47µ 4.5V 49 50 48 YIN1 Y1 10k LOUT2 C2 10µ MUTE RV1 75 COUT2 V3 0.1µ 75 DC OUT 75 AGND Y3 75 SDA LV3 SCL RV3 40dB 0.47µ 1µ 0.47µ 1µ 0.1µ 75 600 75 600 75 µ-com Measurement point CXA2079Q CXA2079Q I2C BUS Control Signal 34 SDA tBUF 33 SCL tLOW tR tHD;STA P tHIGH tF tSU;DAT tSU;STA tSU;STO tHD;DAT S S P Fig. 6. I2C BUS Control Signal Timing Chart Description of Operation The CXA2079Q is a TV I2C bus-compatible AV switch IC. The video system and the stereo audio system both have 6 inputs and 2 outputs each. 4 of the 6 video system inputs support S2 and S protocols. The desired inputs can be independently assigned to each output (in the audio system, the left and right channels are processed as one unit) by I2C bus control. However, the same input is assigned to both the video and audio system output 2. I2C BUS Registers 1) I2C BUS The I2C bus (inter-IC bus) is an inter-IC bus system developed by Philips. Two lines (SDA – serial data, SCL – serial clock) provide control over start, stop, data transfer, synchronization, and collision avoidance. The IC outputs are either open collector or open drain, forming a bus line in the wired OR format. SDA A MSB LSB A MSB LSB SCL S P 1 2 3 4 5 6 7 8 9 1 2 9 S: Start condition; SDA is set "Low" when SCL is "High" P: Stop condition; SDA is set "High" when SCL is "High" A: Acknowledge; signal sent from the slave Data is transmitted by MSB-first. One data unit consists of 8 bits, to which the acknowledge signal, which indicates that the data has been accepted by the slave, is attached at the end. Normally, the slave∗1 IC receives data at the rising edge of SCL and the master∗2 IC changes data at the falling edge of SCL. ∗1 Slave: An IC that is placed under the control of the master. In a normal system, all devices excluding the central microcomputer are slaves. ∗2 Master: A central microcomputer or other controlling IC. – 14 – CXA2079Q 2) Control Registers The CXA2079Q control is exercised by writing 2-byte data into the two 8-bit control registers which control the output selector circuits for the 2 outputs. S Slave address A DATA1 A DATA2 A P S: Start condition A: Acknowledge P: Stop condition Control register structure (DATA1 and DATA2) • All registers are set to "0" during IC power on. • "∗" indicates undefined. b7 b6 b5 b4 b3 b2 b1 b0 Slave add. 1 0 0 1 0 0 ADR R/W DATA1 A-GAIN S/COMP1 V-IN1 DATA2 ∗ S/COMP2 AV-IN2 A-IN1 DC OUT ∗ R/W (1): Read/write mode 0: Control data write 1: Status register read ADR (1): This bit sets the slave address set by the address pin. 0: 90H 1: 92H A-GAIN (1): LOUT1/ROUT1 output gain selector 0: 0dB output 1: –6dB output S/COMP1 and S/COMP2 (1 each): S terminal input/composite signal input selectors By setting these bits to "0", when composite signal input is selected, YOUT/COUT output the inputs from YIN/CIN during video 1/2 output. 0: Composite signal inputs (TV, V1 to V5 inputs) 1: S terminal inputs (Y1/C1 to Y4/C4 inputs) V-IN1 (3 each): This bit selects the input signals output to each video output. 0: Mute 1: Selects the TV input 2: Selects the V1 and Y1/C1 inputs 3: Selects the V2 and Y2/C2 inputs 4: Selects the V3 and Y3/C3 inputs 5: Selects the V4 and Y4/C4 inputs 6: Selects the V5 input 7: Mute – 15 – CXA2079Q A-IN1 (3 each): This bit selects the input signals output to each audio output. 0: Mute 1: Selects the LTV/RTV inputs 2: Selects the LV1/RV1 inputs 3: Selects the LV2/RV2 inputs 4: Selects the LV3/RV3 inputs 5: Selects the LV4/RV4 inputs 6: Selects the LV5/RV5 inputs 7: Mute AV-IN2 (3): This bit selects the input signals output to output 2 (VOUT2, YOUT2/COUT2, LOUT2/ROUT2). Note) Both the video output and the audio output are selected at the same time only for AV-IN2. 0: Mute 1: Selects the TV and LTV/RTV inputs 2: Selects the V1, Y1/C1 and LV1/RV1 inputs 3: Selects the V2, Y2/C2 and LV2/RV2 inputs 4: Selects the V3, Y3/C3 and LV3/RV3 inputs 5: Selects the V4, Y4/C4 and LV4/RV4 inputs 6: Selects the V5 and LV5/RV5 inputs 7: Mute DC OUT (2): This bit sets the DC voltage output from Pin 36 (DC OUT). 0: 4.5V 1: 0V 2: 1.9V 3: 4.5V 3) Status Registers • When reading two bytes S Slave address A DATA1 A DATA1 A DATA2 NA P • When reading one byte S Slave address NA P S: Start condition A: Acknowledge NA: No acknowledge P: Stop condition When communication is to be terminated in the status register reading mode, the no-acknowledge signal is needed to assure that the master does not issue the acknowledge signal to the slave. It is possible to read only DATA1 of the status register by sending the no-acknowledge signal after DATA1. – 16 – CXA2079Q Status register structure (DATA1 and DATA2) b7 b6 b5 b4 b3 b2 b1 b0 Slave add. 1 0 0 1 0 0 ADR 1 DATA1 S1SEL S2SEL S3SEL S4SEL S-C1 S-C2 DATA2 S1SEL S2SEL S3SEL S4SEL S-C3 S-C4 S1SEL to S4SEL (1 each): S-1 to S-4 pin status 0: S-1 to S-4 pins are not grounded. 1: S-1 to S-4 pins are grounded. S1SEL to S4SEL are actually determined by comparing the S-1 to S-4 pin DC voltages with 3.5V. S-1 to S-4 pin DC voltage S1SEL to S4SEL 3.5V or more 0 3.5V or less 1 S-C1, S-C2, S-C3, S-C4 (2 each): S2-1, S2-2, S2-3 and S2-4 pin status 0: 4:3 video signal 1: 4:3 letter-box signal 2: 16:9 video squeezed signal 3: No signal S-C1 to S-C4 are actually determined by comparing the S2-1 to S2-4 pin DC voltages with two threshold. However, when the S-1 to S-4 pins are open, the outputs are fixed to "3". S2-1 to S2-4 pin DC voltage S-C1 to S-C4 1.3V or less 0 1.3V or more to 2.5V or less 1 2.5V or more 2 S-1 to S-4 OPEN 3 4) Power-on Reset The CXA2079Q has an internal power-on reset function that sets each control register to "0" during IC power ON. The power-on reset VTH has hysteresis. Power-on reset released Power-on reset VCC 4.5V 5.6V – 17 – TV input 1µ 0.47µ 1µ 1µ 0.47µ 0.1µ 75 C2 RV2 V2 RV1 75 32 NC 29 LV5 75 0.47µ 1µ 470k 3 1µ 470k 4 VIDEO 1 input 75 0.47µ 2 1 64 RTV 63 TV 62 LTV 61 RV5 60 V5 59 58 COUT1 1µ 8 10 75 0.47µ 11 1µ 470k VIDEO 2 input 1µ 470k 9 12 0.1µ 1µ 15 75 0.47µ 14 13 75 18 1µ 470k VIDEO 3 input 1µ 470k 17 0.47µ 16 19 0.1µ 75 1µ 0.47µ 1µ 0.47µ 1µ 0.1µ 75 1µ VIDEO 4 input • Depending on the output bias of the comb filters, pay attention to the polarities of the capacitors since the bias at Pins 43, 45, 49 and 51 is approximately 3.1V and 4.5V, respectively. • Connect Pin 32 to Vcc when setting the slave address of the IC to 92H. • The audio output can be muted by setting Pin 48 to 3.5V or more. • The TRAP (Pin 55) are of 3.58MHz subcarrier. • Pay attention to the polarities of the capacitors since each output of video system and audio system has optional bias, respectively. Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. 75 0.47µ 7 6 5 S2-3 20 S-3 21 V4 22 LV4 23 Y4 24 RV4 25 C4 26 S2-4 27 V3 57 VGND LV3 S-4 28 V1 VIDEO 5 input ADR 33 34 220 35 Y3 56 YOUT1 55 TRAP1 LV1 1µ 4.7k 36 220 NC 30 Y1 54 ROUT1 C1 180µ CIN1 S2-1 620 BIAS S-1 10p 22µ 41 VOUT2 NC 31 37 38 39 40 ROUT2 S2-2 VIDEO 1 output YIN1 LOUT1 49 YOUT2 53 VOUT1 52 42 43 44 45 46 47 48 MUTE 0.1µ NC 50 1k NC 0.47µ YIN2 51 10µ AGND2 LV2 0.1µ LOUT2 0.1µ CIN2 0.47µ VCC Y2 75 AGND COMB FILTER SDA RV3 COMB FILTER DC OUT µ-com SCL VIDEO 2 output COUT2 S-2 – 18 – C3 Application Circuit CXA2079Q CXA2079Q Example of Representative Characteristics Video system frequency response characteristics Y1/C1 to Y4/C4 → VOUT1, VOUT2 2 0 –2 100k 2 Audio system input/output gain [dB] 6 4 Audio system frequency response characteristics TV, V1 to V5 → VOUT1, VOUT2 Y1 to Y4 → YOUT1, YOUT2 C1 to C4 → COUT1, COUT2 L/RTV, L/R1 to L/R5 → LOUT1 (0dB) L/RTV, L/R1 to L/R5 → LOUT2 0 –2 –4 L/RTV, L/R1 to L/R5 → LOUT1 (–6dB) –6 –8 1M 10M Frequency [Hz] 10k 1k 100M 100k Frequency [Hz] Audio system distortion vs. Input amplitude 10 f = 1kHz 400Hz HPF, 80kHz LPF 1 Total harmonic distortion [%] Video system input/output gain [dB] 8 0.1 LOUT1 output (0dB gain) LOUT2 output 0.01 0.002 0 1 2 Input amplitude [Vrms] – 19 – 3 4 1M CXA2079Q Package Outline Unit: mm 64PIN QFP(PLASTIC) 23.9 ± 0.4 + 0.4 20.0 – 0.1 + 0.1 0.15 – 0.05 51 0.15 64 20 1 16.3 32 + 0.4 14.0 – 0.1 52 17.9 ± 0.4 33 + 0.2 0.1 – 0.05 1.0 0.8 ± 0.2 19 + 0.35 2.75 – 0.15 + 0.15 0.4 – 0.1 ± 0.12 M PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE QFP–64P–L01 LEAD TREATMENT SOLDER/PALLADIUM PLATING EIAJ CODE QFP064–P–1420 LEAD MATERIAL 42/COPPER ALLOY PACKAGE MASS 1.5g JEDEC CODE – 20 –