TC7135 4-1/2 Digit A/D Converter Features General Description • • • • • • • • The TC7135 4-1/2 digit A/D converter (ADC) offers 50ppm (1 part in 20,000) resolution with a maximum nonlinearity error of 1 count. An auto zero cycle reduces zero error to below 10µV and zero drift to 0.5µV/°C. Source impedance errors are minimized by a 10pA maximum input current. Rollover error is limited to ±1 count. • • • • • Low Rollover Error: ±1 Count Max Nonlinearity Error: ±1 Count Max Reading for 0V Input True Polarity Indication at Zero for Null Detection Multiplexed BCD Data Output TTL-Compatible Outputs Differential Input Control Signals Permit Interface to UARTs and Microprocessors Blinking Display Visually Indicates Overrange Condition Low Input Current: 1pA Low Zero Reading Drift: 2µV/°C Auto-Ranging Supported with Overrange and Underrange Signals Available in PDIP and Surface-Mount Packages Microprocessor based measurement systems are supported by BUSY, STROBE and RUN/HOLD control signals. Remote data acquisition systems with data transfer via UARTs are also possible. The additional control pins and multiplexed BCD outputs make the TC7135 the ideal converter for display or microprocessor based measurement systems. Functional Block Diagram SET VREF = 1V VREF IN Applications 100kΩ • Precision Analog Signal Processor • Precision Sensor Interface • High Accuracy DC Measurements Device Selection Table Part Number Package Temperature Range TC7135CLI 28-Pin PLCC 0°C to +70°C TC7135CPI 28-Pin PDIP 0°C to +70°C TC7135CBU 64-Pin PQFP 0°C to +70°C 2002 Microchip Technology Inc. TC7135 –5V 1 2 V- UNDERRANGE REF IN OVERRANGE 3 ANALOG STROBE COMMON Analog GND 4 RUN/HOLD INT OUT 1µF 0.47µF 5 DIGTAL GND AZ IN 6 BUFF OUT POLARITY 100kΩ 7 CLOCK IN C 100 Signal 1µF 8 REF kΩ BUSY Input CREF+ 9 -INPUT (LSD) D1 0.1µF 10 D2 +INPUT 11 D3 +5V V+ 12 D5 (MSD) D4 13 B1 (LSB) (MSB) B8 14 B2 B4 28 27 26 25 24 23 22 21 Clock Input 120kHz 20 19 18 17 16 15 DS21460B-page 1 TC7135 Package Types 28-Pin PDIP UR 1 28 27 26 3 2 V- 1 28 UNDERRANGE REF IN ANALOG COM INT OUT 2 27 3 26 STROBE 4 25 RUN/HOLD AZ IN 5 24 DIGTAL GND BUFF OUT 6 23 POLARITY 23 POLARITY C REF- 7 22 CLOCK IN CREF+ 8 21 BUSY – INPUT 9 20 D1 (LSD) +INPUT 10 19 D2 V+ 11 18 D3 STROBE V– 4 OR INT OUT ANALOG COM REF IN 28-Pin PDIP AZ IN 5 25 RUN/HOLD BUFF OUT 6 24 DIGTAL GND REF CAP– 7 TC7135 REF CAP+ 8 –INPUT 9 21 BUSY +INPUT 10 20 D1 (LSD) V + 11 19 D2 (MSD) D5 12 D3 D4 B4 (MSB) B8 B2 (LSB) B1 (MSD) D5 12 13 14 15 16 17 18 (LSB) B1 13 B2 14 TC7135 OVERRANGE 22 CLOCK IN 17 D4 16 B8 (MSB) 15 B4 NC NC NC D2 D1 BUSY CLOCK IN NC POL DGND RUN/HOLD STROBE NC NC NC NC 64-Pin PQFP 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 NC 1 48 NC l NC 2 47 NC NC 3 46 NC NC 4 45 D3 NC 5 44 D4 NC 6 43 B8 42 B4 OVERRANGE 7 TC7135 UNDERRANGE 8 41 B2 40 NC NC 9 V- 10 39 B1 REF IN 11 38 D5 ANALOG COM 12 37 NC NC 13 NC 14 36 NC NC 15 NC 16 34 NC 35 NC 33 NC V+ NC +INPUT NC –INPUT NC C REF + NC NC C REF - BUFF OUT NC AZ IN NC NC INT OUT 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 NOTE: NC = No internal connection. DS21460B-page 2 2002 Microchip Technology Inc. TC7135 1.0 ELECTRICAL SPECIFICATIONS *Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operation sections of the specifications is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Absolute Maximum Ratings* Positive Supply Voltage..........................................+6V Negative Supply Voltage ....................................... - 9V Analog Input Voltage (Pin 9 or 10) .... V+ to V- (Note 2) Reference Input Voltage (Pin 2) ...................... V+ to VClock Input Voltage ........................................ 0V to V+ Operating Temperature Range ............... 0°C to +70°C Storage Temperature Range ............ – 65°C to +150°C Package Power Dissipation; (TA ≤ 70°C) 28-Pin PDIP ..................................... 1.14Ω 28-Pin PLCC .................................... 1.00Ω 64-Pin PQFP .....................................1.14Ω TC7135 ELECTRICAL SPECIFICATIONS Electrical Characteristics: TA = +25°C, FCLOCK = 120kHz, V+ = +5V, V- = -5V, unless otherwise specified (see Functional Block Diagram). Symbol Parameter Min Typ Max Unit Test Conditions Analog -0.0000 ±0.0000 +0.0000 Display Reading Note 2 and Note 3 TC Z Display Reading with Zero Volt Input Zero Reading Temperature Coefficient — 0.5 2 µV/°C VIN = 0V, (Note 4) TC FS Full Scale Temperature Coefficient — — 5 ppm/°C Nonlinearity Error — 0.5 1 Count Note 6 Note 6 NL DNL Differential Linearity Error Display Reading in Ratiometric Operation ±FSE ± Full Scale Symmetry Error (Rollover Error) VIN = 2V, (Note 4 and Note 5) — 0.01 — LSB +0.9996 +0.9999 +1.0000 Display Reading VIN = VREF, (Note 2) — 0.5 1 Count -VIN = +VIN, (Note 7) IIN Input Leakage Current — 1 10 pA eN Noise — 15 — µVP-P µA µA Note 3 Peak-to-Peak Value not Exceeded 95% of Time Digital IIL Input Low Current — 10 100 IIH Input High Current — 0.08 10 VOL Output Low Voltage — 0.2 0.4 V IOL = 1.6mA V OH Output High Voltage; B1, B2, B4, B8, D 1 –D5 Busy, Polarity, Overrange, Underrange, Strobe 2.4 4.4 5 V IOH = 1mA 4.9 4.99 5 V IOH = 10µA 0 200 1200 kHz FCLK Note 1: 2: 3: 4: 5: 6: 7: 8: Clock Frequency VIN = 0V VIN = +5V Note 8 Limit input current to under 100µA if input voltages exceed supply voltage. Full scale voltage = 2V. VIN = 0V. 30°C ≤ TA ≤ +70°C .External reference temperature coefficient less than 0.01ppm/°C. -2V ≤ VIN ≤ +2V. Error of reading from best fit straight line. IVIN| = 1.9959. Specification related to clock frequency range over which the TC7135 correctly performs its various functions. Increased errors result at higher operating frequencies. 2002 Microchip Technology Inc. DS21460B-page 3 TC7135 TC7135 ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: TA = +25°C, FCLOCK = 120kHz, V+ = +5V, V- = -5V, unless otherwise specified (see Functional Block Diagram). Symbol Parameter Min Typ Max Unit V Test Conditions Power Supply V+ Positive Supply Voltage 4 5 6 V- Negative Supply Voltage -3 -5 -8 V I+ Positive Supply Current — 1 3 mA I- Negative Supply Current — 0.7 3 mA FCLK = 0Hz Power Dissipation — 8.5 30 mW FCLK = 0Hz PD Note 1: 2: 3: 4: 5: 6: 7: 8: FCLK = 0Hz Limit input current to under 100µA if input voltages exceed supply voltage. Full scale voltage = 2V. VIN = 0V. 30°C ≤ TA ≤ +70°C .External reference temperature coefficient less than 0.01ppm/°C. -2V ≤ VIN ≤ +2V. Error of reading from best fit straight line. IVIN| = 1.9959. Specification related to clock frequency range over which the TC7135 correctly performs its various functions. Increased errors result at higher operating frequencies. DS21460B-page 4 2002 Microchip Technology Inc. TC7135 2.0 PIN DESCRIPTIONS The description of the pins are listed in Table 2-1. TABLE 2-1: PIN FUNCTION TABLE Pin Number 28-Pin PDIP Symbol 1 V- Description Negative power supply input. 2 REF IN 3 ANALOG COMMON External reference input. 4 INT OUT 5 AZ IN 6 BUFF OUT 7 CREF- Reference capacitor input. Reference capacitor negative connection. Reference point for REF IN. Integrator output. Integrator capacitor connection. Auto zero inpt. Auto-zero capacitor connection. Analog input buffer output. Integrator resistor connection. 8 CREF+ Reference capacitor input. Reference capacitor positive connection. 9 -INPUT Analog input. Analog input negative connection. 10 +INPUT 11 V+ Positive power supply input. 12 D5 Digit drive output. Most Significant Digit (MSD) 13 B1 Binary Coded Decimal (BCD) output. Least Significant Bit (LSB) 14 B2 BCD output. 15 B4 BCD output. 16 B8 BCD output. Most Significant Bit (MSB) 17 D4 Digit drive output. 18 D3 Digit drive output. 19 D2 Digit drive output. 20 D1 Digit drive output. Least Significant Digit (LSD) 21 BUSY Analog input. Analog input positive connection. Busy output. At the beginning of the signal-integration phase, BUSY goes High and remains High until the first clock pulse after the integrator zero crossing. 22 CLOCK IN Clock input. Conversion clock connection. 23 POLARITY Polarity output. A positive input is indicated by a logic High output. The polarity output is valid at the beginning of the reference integrate phase and remains valid until determined during the next conversion. 24 DGND 25 RUN/HOLD Digital logic reference input. Run / Hold input. When at a logic High, conversions are performed continuously. A logic Low holds the current data as long as the Low condition exists. Strobe output. The STROBE output pulses low in the center of the digit drive outputs. 26 STROBE 27 OVERRANGE Over range output. A logic High indicates that the analog input exceeds the full scale input range. 28 UNDERRANGE Under range output. A logic High indicates that the analog input is less than 9% of the full scale input range. 2002 Microchip Technology Inc. DS21460B-page 5 TC7135 3.0 DETAILED DESCRIPTION ent benefit is noise immunity. Noise spikes are integrated, or averaged, to zero during the integration periods. (All Pin Designations Refer to 28-Pin DIP) 3.1 Dual Slope Conversion Principles The TC7135 is a dual slope, integrating A/D converter. An understanding of the dual slope conversion technique will aid in following the detailed TC7135 operational theory. The conventional dual slope converter measurement cycle has two distinct phases: 1. 2. Input signal integration Reference voltage integration (de-integration) Integrating ADCs are immune to the large conversion errors that plague successive approximation converters in high-noise environments (see Figure 3-1). FIGURE 3-1: Analog Input Signal REF Voltage = Signal integration time (fixed) 3.2 1. 2. 3. 4. EQUATION 3-2: VREF TDEINT TINT The dual slope converter accuracy is unrelated to the integrating resistor and capacitor values, as long as they are stable during a measurement cycle. An inher- Variable Reference Integrate Time TC7135 Operational Theory System zero Analog input signal integration Reference voltage integration Integrator output zero Internal analog gate status for each phase is shown in Figure 3-1. INTERNAL ANALOG GATE STATUS Conversion Cycle Phase SWI SWRI+ System Zero Input Signal Integration Reference Voltage Integration Integrator Output Zero *Note: Counter The TC7135 measurement cycle contains four phases: For a constant VIN: TABLE 3-1: Clock Control Logic The TC7135 incorporates a system zero phase and integrator output voltage zero phase to the normal twophase dual-slope measurement cycle. Reduced system errors, fewer calibration steps, and a shorter overrange recovery time result. TDEINT = Reference voltage integration time (variable). VIN = Phase Control Polarity Control Integrator Output EQUATION 3-1: TINT + VIN ≈ VREF VIN ≈ 1/2 VREF Fixed Signal Integrate Time where: Comparator Display A simple mathematical equation relates the input signal, reference voltage, and integration time: TINT VREF T DEINT 1 VIN(T)DT = R C ∫ RINTC INT 0 INT INT - Switch Drive In a simple dual slope converter, a complete conversion requires the integrator output to "ramp-up" and "ramp-down." = Reference voltage Integrator + The input signal being converted is integrated for a fixed time period. Time is measured by counting clock pulses. An opposite polarity constant reference voltage is then integrated until the integrator output voltage returns to zero. The reference integration time is directly proportional to the input signal. VREF BASIC DUAL SLOPE CONVERTER SWRI- SWZ SWR SW1 Closed Closed Closed SWIZ Reference Figures Figure 3-2 Closed Figure 3-3 Closed* Closed Closed Figure 3-4 Closed Figure 3-5 Assumes a positive polarity input signal. SWRI would be closed for a negative input signal. DS21460B-page 6 2002 Microchip Technology Inc. TC7135 3.2.1 3.2.3 SYSTEM ZERO During this phase, errors due to buffer, integrator, and comparator offset voltages are compensated for by charging CAZ (auto zero capacitor) with a compensating error voltage. With a zero input voltage the integrator output will remain at zero. The external input signal is disconnected from the internal circuitry by opening the two SWI switches. The internal input points connect to ANALOG COMMON. The reference capacitor charges to the reference voltage potential through SWR. A feedback loop, closed around the integrator and comparator, charges the CAZ capacitor with a voltage to compensate for buffer amplifier, integrator, and comparator offset voltages (see Figure 3-2). REFERENCE VOLTAGE INTEGRATION The previously-charged reference capacitor is connected with the proper polarity to ramp the integrator output back to zero (see Figure 3-4). The digital reading displayed is: EQUATION 3-3: Reading = 10,000 FIGURE 3-4: REFERENCE VOLTAGE INTEGRATION CYCLE Analog Input Buffer SWI FIGURE 3-2: SYSTEM ZERO PHASE + +IN SWRI- SWRI+ REF IN SWZ - CREF SWR SWZ CREF - - Analog Common - To Digital Section Integrator SWZ SWRI+ SWRI- Comparator + SWZ To Digital Section Integrator SWZ SWZ + REF IN Comparator + + CSZ SWIZ SWR SWIZ CINT - SWRI- SWRI+ CINT CSZ RINT + +IN RINT - Analog Input Buffer SWI [Differential Input] VREF SW1 SWI Switch Open Switch Closed – IN SWRI+ SWRI- Analog Common SW1 SWI 3.2.2 3.2.4 Switch Open Switch Closed – IN ANALOG INPUT SIGNAL INTEGRATION The TC7135 integrates the differential voltage between the +INPUT and -INPUT pins. The differential voltage must be within the device Common mode range; - 1V from either supply rail, typically. The input signal polarity is determined at the end of this phase. See Figure 2-3 FIGURE 3-3: INPUT SIGNAL INTEGRATION PHASE SWI + SWRI- SWRI+ FIGURE 3-5: Analog Input Buffer SWI + IN + SWRI- SWRI+ RINT SWR CINT SWZ CREF + Comparator SWZ Integrator To Digital Section SWRI+ SWRI- Comparator + SWZ SWZ + SWZ + REF IN CINT CSZ REF IN CSZ RINT - SWIZ CREF SWZ INTEGRATOR OUTPUT ZERO PHASE - SWIZ SWR This phase ensures the integrator output is at 0V when the system zero phase is entered. It also ensures that the true system offset voltages are compensated for. This phase normally lasts 100 to 200 clock cycles. If an overrange condition exists, the phase is extended to 6200 clock cycles (see Figure 3-5). Analog Input Buffer +IN INTEGRATOR OUTPUT ZERO Integrator To Digital Section Analog Common SWI – IN SW1 Switch Open Switch Closed SWRI+ SWRI- Analog Common SWI SW1 – IN Switch Open Switch Closed . 2002 Microchip Technology Inc. DS21460B-page 7 TC7135 4.0 ANALOG SECTION FUNCTIONAL DESCRIPTION 4.1 Differential Inputs The TC7135 operates with differential voltages (+INPUT, pin 10 and -INPUT, pin 9) within the input amplifier Common mode range, which extends from 1V below the positive supply to 1V above the negative supply. Within this Common mode voltage range, an 86dB Common mode rejection ratio is typical. The integrator output also follows the Common mode voltage and must not be allowed to saturate. A worstcase condition exists, for example, when a large positive Common mode voltage with a near full scale negative differential input voltage is applied. The negative input signal drives the integrator positive when most of its swing has been used up by the positive Common mode voltage. For these critical applications, the integrator swing can be reduced to less than the recommended 4V full scale swing, with some loss of accuracy. The integrator output can swing within 0.3V of either supply without loss of linearity. 4.2 FIGURE 4-1: USING AN EXTERNAL REFERENCE V+ V+ TC7135 REF IN 10k MCP1525 2.5 VREF 10k 1µF ANALOG COMMON Analog Ground Analog Common Input ANALOG COMMON is used as the -INPUT return during auto zero and de-integrate. If -INPUT is different from ANALOG COMMON, a Common mode voltage exists in the system. However, this signal is rejected by the excellent CMRR of the converter. In most applications, –INPUT will be set at a fixed, known voltage (power supply common, for instance). In this application, ANALOG COMMON should be tied to the same point, thus removing the Common mode voltage from the converter. The reference voltage is referenced to ANALOG COMMON. 4.3 Reference Voltage Input The reference voltage input (REF IN) must be a positive voltage with respect to ANALOG COMMON. A reference voltage circuit is shown in Figure 4-1. DS21460B-page 8 2002 Microchip Technology Inc. TC7135 5.0 DIGITAL SECTION FUNCTIONAL DESCRIPTION The major digital subsystems within the TC7135 are illustrated in Figure 5-1, with timing relationships shown in Figure 5-2. The multiplexed BCD output data can be displayed on LCD or LED displays. The digital section is best described through a discussion of the control signals and data outputs. FIGURE 5-1: DIGITAL SECTION FUNCTIONAL DIAGRAM Polarity D5 MSB D4 Digit D3 Drive D2 Signal Multiplexer From Analog Section Latch Polarity FF Latch Latch Latch D1 LSB 13 B1 14 B2 Data 15 B4 Output 16 B8 Latch Counters Zero Cross Detect Control Logic 24 22 25 DGND Clock In RUN/ HOLD 2002 Microchip Technology Inc. 27 28 Overrange Underrange 26 STROBE 21 Busy DS21460B-page 9 TC7135 FIGURE 5-2: Integrator Output TIMING DIAGRAMS FOR OUTPUTS Signal System Integrate Reference 10,000 Zero Integrate 10,001 Counts 20,001 Counts (Fixed) Counts (Max) Full Measurement Cycle 40,002 Counts Busy Underrange when Applicable Expanded Scale Below D4 D3 D2 D1 * First D5 of System Zero and Reference Integrate One Count Longer 100 Counts Auto Zero Digit Scan for Overrange * During the measurement cycle, the STROBE control line is pulsed low five times. The five low pulses occur in the center of the digit drive signals (D 1, D2, D3, D5) (see Figure 5-3). The digit drive signals will continue to permit display scanning. STROBE pulses are not repeated until a new measurement is completed. The digit drive signals will not continue if the previous signal resulted in an overrange condition. D5 STROBE STROBE Output D 5 (MSD) goes high for 201 counts when the measurement cycles end. In the center of the D5 pulse, 101 clock pulses after the end of the measurement cycle, the first STROBE occurs for one half clock pulse. After the D5 digit strobe, D 4 goes high for 200 clock pulses. The STROBE then goes low 100 clock pulses after D4 goes high. This continues through the D 1 digit drive pulse. Overrange when Applicable Digit Scan 5.2 Reference Integrate Signal Integrate The active low STROBE pulses aid BCD data transfer to UARTs, processors and external latches. For more information, please refer to Application Note 784. FIGURE 5-3: STROBE SIGNAL LOW FIVE TIMES PER CONVERSION D5 * D4 TC835 Outputs Busy D3 D2 End of Conversion * D1 5.1 RUN/HOLD Input When left open, this pin assumes a logic "1" level. With a RUN/HOLD = 1, the TC7135 performs conversions continuously, with a new measurement cycle beginning every 40,002 clock pulses. When RUN/HOLD changes to a logic "0," the measurement cycle in progress will be completed, data held and displayed, as long as the logic "0" condition exists. A positive pulse (>300nsec) at RUN/HOLD initiates a new measurement cycle. The measurement cycle in progress when RUN/HOLD initially assumed the logic "0" state must be completed before the positive pulse can be recognized as a single conversion run command. B1–B8 D5 (MSD) Data D4 Data D3 Data D2 Data STROBE D4 D3 D2 D1 D5 Data Note Absence of STROBE 200 Counts D5 D1 (LSD) Data 201 Counts 200 Counts 200 Counts 200 Counts 200 Counts 200 Counts *Delay between Busy going Low and First STROBE pulse is dependent on Analog Input. The new measurement cycle begins with a 10,001count auto zero phase. At the end of this phase the busy signal goes high. DS21460B-page 10 2002 Microchip Technology Inc. TC7135 5.3 BUSY Output At the beginning of the signal integration phase, BUSY goes high and remains high until the first clock pulse after the integrator zero crossing. BUSY returns to the logic "0" state after the measurement cycle ends in an overrange condition. The internal display latches are loaded during the first clock pulse after BUSY and are latched at the clock pulse end. The BUSY signal does not go high at the beginning of the measurement cycle, which starts with the auto zero cycle. 5.4 OVERRANGE Output If the input signal causes the reference voltage integration time to exceed 20,000 clock pulses, the OVERRANGE output is set to a logic "1." The overrange output register is set when BUSY goes low and is reset at the beginning of the next reference integration phase. 5.5 UNDERRANGE Output If the output count is 9% of full scale or less (-1800 counts), the underrange register bit is set at the end of BUSY. The bit is set low at the next signal integration phase. 5.6 POLARITY Output A positive input is registered by a logic "1" polarity signal. The polarity bit is valid at the beginning of reference integrate and remains valid until determined during the next conversion. The polarity bit is valid even for a zero reading. Signals less than the converter's LSB will have the signal polarity determined correctly. This is useful in null applications. 5.7 Digit Drive Outputs Digit drive signals are positive-going signals. The scan sequence is D5 to D1. All positive pulses are 200 clock pulses wide, with the exception D5, which is 201 clock pulses wide. All five digits are scanned continuously, unless an overrange condition occurs. In an overrange condition, all digit drives are held low from the final STROBE pulse until the beginning of the next reference integrate phase. The scanning sequence is then repeated. This provides a blinking visual display indication. 5.8 BCD Data Outputs The binary coded decimal (BCD) bits B8, B4, B2, and B1 are positive-true logic signals. The data bits become active at the same time as the digit drive signals. In an overrange condition, all data bits are at a logic "0" state. 2002 Microchip Technology Inc. DS21460B-page 11 TC7135 6.0 TYPICAL APPLICATIONS 6.1 Component Value Selection 6.1.1 INTEGRATING RESISTOR The dielectric absorption of the reference and auto zero capacitors are only important at power-on or when the circuit is recovering from an overload. Smaller or cheaper capacitors can be used if accurate readings are not required for the first few seconds of recovery. The integrating resistor RINT is determined by the full scale input voltage and the output current of the buffer used to charge the integrator capacitor, CINT. Both the buffer amplifier and the integrator have a class A output stage, with 100µA of quiescent current. A 20µA drive current gives negligible linearity errors. Values of 5µA to 40µA give good results. The exact value of an integrating resistor for a 20µA current is easily calculated. 6.1.4 EQUATION 6-1: 6.2 RINT = 6.1.2 Full scale voltage 20µA INTEGRATING CAPACITOR (C INT) The product of integrating resistor and capacitor should be selected to give the maximum voltage swing that ensures the tolerance buildup will not saturate the integrator swing (approximately 0.3V from either supply). For ±5V supplies and ANALOG COMMON tied to supply ground, a ±3.5V to ±4V full scale integrator swing is adequate. A 0.10µF to 0.47µF is recommended. In general, the value of CINT is given by: EQUATION 6-2: CINT = = REFERENCE VOLTAGE The analog input required to generate a full scale output is VIN = 2 VREF. The stability of the reference voltage is a major factor in the overall absolute accuracy of the converter. For this reason, it is recommended that a high-quality reference be used where high-accuracy absolute measurements are being made. 6.2.1 Conversion Timing LINE FREQUENCY REJECTION A signal integration period at a multiple of the 60Hz line frequency will maximize 60Hz "line noise" rejection. A 100kHz clock frequency will reject 50Hz, 60Hz and 400Hz noise. This corresponds to five readings per second (see Table 6-1 and Table 6-2). TABLE 6-1: CONVERSION RATE VS. CLOCK FREQUENCY Oscillator Frequency (kHz) Conversion Rate (Conv./Sec.) 100 2.5 120 3 [10,000 x clock period] x IINT 200 5 Integrator output voltage swing 300 7.5 400 10 (10,000) (clock period) (20µA) 800 20 Integrator output voltage swing 1200 30 A very important characteristic of the integrating capacitor C INT is that it has low dielectric absorption to prevent rollover or ratiometric errors. A good test for dielectric absorption is to use the capacitor with the input tied to the reference. This ratiometric condition should read half scale 0.9999, with any deviation probably due to dielectric absorption. Polypropylene capacitors give undetectable errors at reasonable cost. Polystyrene and polycarbonate capacitors may also be used in less critical applications. 6.1.3 AUTO ZERO AND REFERENCE CAPACITORS The size of the auto zero capacitor has some influence on the noise of the system. A large capacitor reduces the noise. The reference capacitor should be large enough such that stray capacitance to ground from its nodes is negligible. DS21460B-page 12 2002 Microchip Technology Inc. TC7135 TABLE 6-2: LINE FREQUENCY REJECTION VS. CLOCK FREQUENCY Oscillator Frequency (kHz) Line Frequency Rejection (Hz) 300 60 200 150 120 100 40 33-1/3 250 50 166-2/3 100 50, 60,400 The conversion rate is easily calculated: EQUATION 6-3: Reading 1/sec = Clock Frequency (Hz) 4000 6.3 High Speed Operation The maximum conversion rate of most dual slope A/D converters is limited by the frequency response of the comparator. The comparator in this circuit follows the integrator ramp with a 3µsec delay, at a clock frequency of 160 kHz (6µsec period), Half of the first reference integrate clock period is lost in delay. This means that the meter reading will change from 0 to 1 with a 50µV input, 1 to 2 with 150µV, 2 to 3 at 250µV, etc. This transition at midpoint is considered desirable by most users. However, if the clock frequency is increased appreciably above 200kHz, the instrument will flash "1" on noise peaks, even when the input is shorted. For many dedicated applications where the input signal is always of one polarity, the delay of the comparator need not be a limitation. Since the nonlinearity and noise do not increase substantially with frequency, clock rates of up to ~1MHz may be used. For a fixed clock frequency, the extra count, or counts, caused by comparator delay, will be a constant and can be subtracted out digitally. The clock frequency may be extended above 160kHz without this error, however, by using a low value resistor in series with the integrating capacitor. The effect of the resistor is to introduce a small pedestal voltage on to the integrator output at the beginning of the reference integrate phase. By careful selection of the ratio between this resistor and the integrating resistor (a few tens of ohms in the recommended circuit), the compar- 2002 Microchip Technology Inc. The minimum clock frequency is established by leakage on the auto zero and reference capacitors. With most devices, measurement cycles as long as 10 seconds give no measurable leakage error. The clock used should be free from significant phase or frequency jitter. Several suitable low-cost oscillators are shown in Section 6.0, Typical Applications. The multiplexed output means that if the display takes significant current from the logic supply, the clock should have good PSRR. 6.4 125 100 ator delay can be compensated and the maximum clock frequency extended by approximately a factor of 3. At higher frequencies, ringing and second-order breaks will cause significant nonlinearities in the first few counts of the instrument. Zero Crossing Flip Flop The flip flop interrogates the data once every clock pulse after the transients of the previous clock pulse and half clock pulse have died down. False zero crossings caused by clock pulses are not recognized. Of course, the flip flop delays the true zero crossing by up to one count in every instance. If a correction were not made, the display would always be one count too high. Therefore, the counter is disabled for one clock pulse at the beginning of the reference integrate (de-integrate) phase. This one-count delay compensates for the delay of the zero crossing flip flop and allows the correct number to be latched into the display. Similarly, a one-count delay at the beginning of auto zero gives an overload display of 0000 instead of 0001. No delay occurs during signal integrate so that true ratiometric readings result. 6.5 Generating a Negative Supply A negative voltage can be generated from the positive supply by using a TC7660 (see Figure 6-1). FIGURE 6-1: NEGATIVE SUPPLY VOLTAGE GENERATOR +5V 11 V+ TC7135 V– 8 1 (-5V) 5 TC7660 10µF + 4 24 + 2 3 10µF DS21460B-page 13 TC7135 FIGURE 6-2: 4-1/2 DIGIT ADC WITH MULTIPLEXED COMMON ANODE LED DISPLAY +5V 20 19 18 17 12 D1 D2 D3 D4 D5 4 INT OUT 0.33µF 1µF 100kΩ 200kHz 100kΩ + Analog Input – 5 AZ IN POL 6 BUFF OUT TC7135 22 F IN 10 1µF 9 23 4.7kΩ b CREF- 7 1µF CREF+ 8 c 7 6 D 2 C 1 B 7 A 16 B8 15 B4 14 B2 B1 13 –INPUT 7 7 X7 Blank MSD On Zero +INPUT 3 ANALOG COMMON REF V – IN 1 2 7 9–15 5 RBI 16 DM7447A +5V V+ 11 V+ –5V MCP1525 100kΩ FIGURE 6-3: 1µF RC OSCILLATOR CIRCUIT R2 FIGURE 6-4: COMPARATOR CLOCK CIRCUITS R1 +5V C FO 16kΩ 1kΩ 56kΩ Gates are 74C04 1. F O = 1 2C(0.41 RP + 0.7 R1) , RP = 2 + R1 R2 8 VOUT 0.22µF LM311 3 1 R1 + R2 7 30kΩ 4 16kΩ a. If R1 = R 2 = R 1, F≅ 0.55/RC 390pF b. If R2 >> R 1, F ≅ 0.45/R1C c. If R2 << R 1, F ≅ 0.72/R 1C b. F = 120kHz, C = 420pF, R2 = 50kΩ R1 = 8.93kΩ c. F = 120 kHz, C = 220 pF, R2 = 5kΩ R1 = 27.3kΩ DS21460B-page 14 +5V R2 100kΩ 2. Examples: a. F = 120kHz, C = 420pF R1 = R 2 ≈ 10.9 kΩ 2 + R2 100kΩ C2 10pF 6 LM311 3 4 1 C1 0.1µF R4 2kΩ 7 VOUT R3 50kΩ 2002 Microchip Technology Inc. TC7135 FIGURE 6-5: 4-1/2 DIGIT ADC WITH MULTIPLEXED COMMON CATHODE LED DISPLAY +5V +5V SET VREF = 1V –5V 1 MCP1525 1µF V- TC7135 Analog GND 28 150Ω 47 kΩ 150Ω 25 4 INT RUN/HOLD OUT 24 5 DGND AZ IN 23 6 BUFF POLARITY OUT 100 kΩ 7 22 CREF+ CLK IN 1µF 21 8 C REFBUSY 20 9 –INPUT (LSD) D1 0.1 10 19 +INPUT D2 µF 11 18 D3 +5V V+ 12 17 D4 D5 (MSD) 0.33µF 100 kΩ + SIG IN – UR 27 REF IN OR 26 3 ANALOG STROBE GND 2 100 kΩ 1µF 10 9 11 8 12 7 13 MC14513 6 14 5 15 4 16 3 17 2 18 1 +5V 13 16 B1 (LSB) (MSB) B8 14 B4 15 B2 FOSC = 200kHz 2002 Microchip Technology Inc. DS21460B-page 15 TC7135 7.0 PACKAGING INFORMATION 7.1 Package Marking Information Package marking data not available at this time. 7.2 Taping Forms Component Taping Orientation for 28-Pin PLCC Devices User Direction of Feed PIN 1 W P Standard Reel Component Orientation for TR Suffix Device Carrier Tape, Number of Components Per Reel and Reel Size Package 28-Pin PLCC Carrier Width (W) Pitch (P) Part Per Full Reel Reel Size 24 mm 16 mm 750 13 in Component Taping Orientation for 64-Pin PQFP Devices User Direction of Feed PIN 1 W P Standard Reel Component Orientation for TR Suffix Device Carrier Tape, Number of Components Per Reel and Reel Size Package 64-Pin PQFP Carrier Width (W) Pitch (P) Part Per Full Reel Reel Size 32 mm 24 mm 250 13 in NOTE: Drawing does not represent total number of pins. DS21460B-page 16 2002 Microchip Technology Inc. TC7135 7.3 Package Dimensions 28-Pin PDIP (Wide) PIN 1 .555 (14.10) .530 (13.46) 1.465 (37.21) 1.435 (36.45) .610 (15.49) .590 (14.99) .200 (5.08) .140 (3.56) .040 (1.02) .020 (0.51) .150 (3.81) .115 (2.92) 3˚MIN. .015 (0.38) .008 (0.20) .700 (17.78) .610 (15.50) .110 (2.79) .090 (2.29) .070 (1.78) .045 (1.14) .022 (0.56) .015 (0.38) Dimensions: inches (mm) 28-Pin PLCC PIN 1 .021 (0.53) .013 (0.33) .050 (1.27) TYP. .495 (12.58) .485 (12.32) .456 (11.58) .450 (11.43) .032 (0.81) .026 (0.66) .456 (11.58) .450 (11.43) .495 (12.58) .485 (12.32) .430 (10.92) .390 (9.91) .020 (0.51) MIN. .120 (3.05) .090 (2.29) .180 (4.57) .165 (4.19) Dimensions: inches (mm) 2002 Microchip Technology Inc. DS21460B-page 17 TC7135 7.3 Packaging Dimensions (Continued) 7˚ MAX. 64-Pin PQFP .009 (0.23) .005 (0.13) PIN 1 .018 (0.45) .012 (0.30) .041 (1.03) .031 (0.78) .555 (14.10) .547 (13.90) .687 (17.45) .667 (16.95) .031 (0.80) TYP. .555 (14.10) .547 (13.90) .687 (17.45) .667 (16.95) .010 (0.25) TYP. .120 (3.05) .100 (2.55) .130 (3.30) MAX. Dimensions: inches (mm) DS21460B-page 18 2002 Microchip Technology Inc. TC7135 SALES AND SUPPORT Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. 2. 3. Your local Microchip sales office The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products. 2002 Microchip Technology Inc. DS21460B-page 19 TC7135 NOTES: DS21460B-page 20 2002 Microchip Technology Inc. TC7135 Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, FilterLab, KEELOQ, microID, MPLAB, PIC, PICmicro, PICMASTER, PICSTART, PRO MATE, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. dsPIC, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, microPort, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, MXDEV, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2002, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999 and Mountain View, California in March 2002. The Company’s quality system processes and procedures are QS-9000 compliant for its PICmicro ® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, non-volatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001 certified. 2002 Microchip Technology Inc. DS21460B-page 21 WORLDWIDE SALES AND SERVICE AMERICAS ASIA/PACIFIC Japan Corporate Office Australia 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: 480-792-7627 Web Address: http://www.microchip.com Microchip Technology Australia Pty Ltd Suite 22, 41 Rawson Street Epping 2121, NSW Australia Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 Microchip Technology Japan K.K. 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