1 TC7135 4-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTER FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 2 GENERAL DESCRIPTION Low Roll-Over Error ......................... ±1 Count Max Guaranteed Nonlinearity Error ........ ±1 Count Max Guaranteed Zero Reading for 0V Input True Polarity Indication at Zero for Null Detection Multiplexed BCD Data Output TTL-Compatible Outputs Differential Input Control Signals Permit Interface to UARTs and µProcessors Auto-Ranging Supported With Overrange and Underrange Signals Blinking Display Visually Indicates Overrange Condition Low Input Current ............................................. 1 pA Low Zero Reading Drift ............................... 2 µV/°C Interfaces to TC7211A (LCD) and TC7212A (LED) Display Drivers Available in DIP and Surface-Mount Packages The TC7135 4-1/2 digit analog-to-digital converter (ADC) offers 50 ppm (1 part in 20,000) resolution with a maximum nonlinearity error of 1 count. An auto-zero cycle reduces zero error to below 10 µV and zero drift to 0.5 µV/°C. Source impedance errors are minimized by a 10 pA maximum input current. Roll-over error is limited to ±1 count. By combining the TC7135 with a TC7211A (LCD) or TC7212A (LED) driver, a 4-1/2 digit display DVM or DPM can be constructed. Overrange and underrange signals support automatic range switching and special display blanking/flashing applications. Microprocessor-based measurement systems are supported by BUSY, STROBE, and RUN/HOLD control signals. Remote data acquisition systems with data transfer via UARTs are also possible. The additional control pins and multiplexed BCD outputs make the TC7135 the ideal converter for display or microprocessor-based measurement systems. 3 4 ORDERING INFORMATION Temperature Range Part No. Package TC7135CBU 0°C to +70°C TC7135CLI 64-Pin Plastic Flat Package 28-Pin PLCC TC7135CPI 28-Pin Plastic DIP 0°C to +70°C 0°C to +70°C TYPICAL 4-1/2 DIGIT DVM WITH LCD 6 4-1/2 DIGIT LCD 6.8 k Ω +5V –5V 1 V 2 ANALOG GROUND 1 µF 0.1 µF 100 k Ω UR REF IN OR 3 ANALOG STROBE 0.47 µF 4 COMMON RUN/HOLD INT OUT 5 1 µF DGND AZ IN 6 POL BUFF OUT 100 k Ω 7 – CLOCK CREF 8 + BUSY CREF 9 D1 –INPUT 10 D2 +INPUT 11 +5V D3 V+ 12 D5 D4 13 TC7135 B1 B8 14 B2 B4 100 k Ω TC04 INPUT SEGMENT +5V 0.1 µF 28 27 26 D R I V E 1 16 15 14 12 5 3 4 CD4054A 7 8 13 11 10 9 2 6 BACKPLANE 25 +5V 24 120 Hz = 3 READING/SEC CLOCK IN 23 22 21 20 19 18 1/4 CD4030 +5V CD4081 1 5 BP 31 D1 32 33 17 34 16 30 15 29 28 D2 D3 V+ 7 SEG OUT D4 B3 TC7211A 2,3,4 6–26 37–40 36 +5V B2 OSC B1 OPTIONAL CAP 35 GND 27 B 0 8 TC7135-10 11/6/96 TELCOM SEMICONDUCTOR, INC. 5 3-113 4-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTER TC7135 ABSOLUTE MAXIMUM RATINGS* (Note 1) Positive Supply Voltage ............................................. +6V Negative Supply Voltage .............................................–9V Analog Input Voltage (Pin 9 or 10) ......... V+ to V– (Note 2) Reference Input Voltage (Pin 2) ........................... V+ to V– Clock Input Voltage .............................................. 0V to V+ Operating Temperature Range .................... 0°C to +70°C Storage Temperature Range ................. –65°C to +160°C Lead Temperature (Soldering, 10 sec) ................. +300°C Package Power Dissipation (TA ≤ 70°C) Plastic DIP ........................................................ 1.14W PLCC ................................................................ 1.00W Plastic Flat Package .........................................1.14W *Static-sensitive device. Unused devices must be stored in conductive material to protect them from static discharge and static fields. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. ELECTRICAL CHARACTERISTICS: TA = +25°C, fCLOCK = 120 kHz, V+ = +5V, V– = –5V (Figure 1) Symbol Parameter Test Conditions Min Typ Max Display Reading With Zero Volt Input Zero Reading Temperature Coefficient Full-Scale Temperature Coefficient Nonlinearity Error Differential Linearity Error Display Reading in Ratiometric Operation ± Full-Scale Symmetry Error (Roll-Over Error) Input Leakage Current Noise Notes 2 and 3 Unit –0.0000 ±0.0000 +0.0000 — 0.5 2 Display Reading µV/°C — — 5 ppm/°C — — +0.9996 0.5 0.01 +0.9999 1 — +1.0000 — 0.5 1 Count LSB Display Reading Count — — 1 15 10 — pA µVP-P VIN = 0V VIN = +5V IOL = 1.6 mA — — — 10 0.08 0.2 100 10 0.4 µA µA V IOH = 1 mA IOH = 10 µA 2.4 4.9 4.4 4.99 5 5 V V Note 8 0 120 1200 kHz fCLK = 0 Hz fCLK = 0 Hz fCLK = 0 Hz 4 –3 — — — 5 –5 1 0.7 8.5 6 –8 3 3 30 V V mA mA mW Analog TCZ TCFS NL DNL ±FSE IIN VN Digital IIL IIH VOL VOH Input Low Current Input High Current Output Low Voltage Output High Voltage B1, B2, B4, B8, D1–D5 Busy, Polarity, Overrange, Underrange, Strobe Clock Frequency fCLK Power Supply V+ V– I+ I– PD NOTES: 3-114 Positive Supply Voltage Negative Supply Voltage Positive Supply Current Negative Supply Current Power Dissipation 1. Limit input current to under 100µA if input voltages exceed supply voltage. 2. Full-scale voltage = 2V. 3. VIN = 0V. 4. 0°C ≤ TA ≤ +70°C. VIN = 0V Note 4 VIN = 2V Notes 4 and 5 Note 6 Note 6 VIN = VREF Note 2 –VIN = +VIN Note 7 Note 3 Peak-to-Peak Value Not Exceeded 95% of Time 5. 6. 7. 8. External reference temperature coefficient less than 0.01 ppm/°C. –2V ≤ VIN ≤ +2V. Error of reading from best fit straight line. |VIN| = 1.9959. Specification related to clock frequency range over which the TC7135 correctly performs its various functions. Increased errors result at higher operating frequencies. TELCOM SEMICONDUCTOR, INC. 4-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTER 1 TC7135 NC NC NC D2 D1 CLOCK IN BUSY NC POL DGND RUN/HOLD STROBE NC NC NC NC PIN CONFIGURATIONS V– 1 28 UNDERRANGE 2 27 3 26 STROBE OVERRANGE 48 NC REF IN ANALOG COM INT OUT 4 25 RUN/HOLD NC 2 47 NC AZ IN 5 24 DIGTAL GND NC 3 46 NC 6 23 POLARITY NC 4 45 D3 NC 5 44 D4 BUFF OUT – C REF + CREF – INPUT 9 43 B8 42 B4 UNDERRANGE 8 41 B2 NC 9 40 NC V – 10 39 B1 TC7135CBU (PFP) REF IN 11 38 D5 (NOTES 1) ANALOG COM 12 37 NC NC 13 36 NC NC 14 35 NC NC 15 34 NC NC 16 V+ NC +INPUT NC –INPUT NC + C REF NC NC BUFF OUT – CREF NC AZ IN NC NC INT OUT 20 D1 (LSD) 19 D2 V + 11 18 D3 (MSD) D5 12 17 D4 (LSB) B1 13 16 B8 (MSB) 4 28 27 26 3 2 1 AZ IN 5 25 RUN/HOLD BUFF OUT 6 REF CAP– 7 REF CAP+ 8 –INPUT 9 4 15 B4 B2 14 33 NC NOTES: 1. NC = No internal connection. 21 BUSY +INPUT 10 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 3 22 CLOCK IN TC7135CPI (PDIP) 8 STROBE NC 6 OVERRANGE 7 7 OR ● UR NC 1 INT OUT ANALOG COM REF IN V– 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 2 24 DIGTAL GND 23 POLARITY 5 22 CLOCK IN TC7135CLI (PLCC) 21 BUSY +INPUT 10 V + 11 20 D1 (LSD) 19 D2 D3 B4 (MSB) B8 D4 (MSD) D5 (LSB) B1 B2 12 13 14 15 16 17 18 6 7 8 TELCOM SEMICONDUCTOR, INC. 3-115 4-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTER TC7135 SET VREF = 1V –5V ANALOG INPUT BUFFER SW I 1 VREF IN 2 100 kΩ + IN V– UNDERRANGE REF IN – SW RI 27 OVERRANGE 3 ANALOG STROBE COMMON ANALOG GND 4 RUN/HOLD INT OUT 0.47 1 µF 5 µF DIGTAL GND AZ IN 6 POLARITY BUFF OUT 100 kΩ 7 – CLOCK IN CREF 100 SIGNAL 1 µF 8 + BUSY kΩ INPUT CREF 9 –INPUT (LSD) D1 0.1 µF 10 D2 +INPUT TC7135 11 + D3 +5V V 12 D5 (MSD) D4 13 B1 (LSB) (MSB) B8 14 B2 B4 CSZ SWIZ REF IN 24 21 – COMPARATOR + + – SWZ 23 22 SWZ CREF SWR CINT – SW + RI 26 25 RINT + 28 CLOCK INPUT 120 kHz SW + RI INTEGRATOR SWZ – SW RI ANALOG COM SW1 SW I 20 SWITCH OPEN – IN 19 TO DIGITAL SECTION SWITCH CLOSED 18 Figure 3B. System Zero Phase 17 16 15 Figure 1. Test Circuit ANALOG INPUT BUFFER SW I + IN RINT + – SW RI V+ – SW + RI CSZ SWIZ REF IN SWZ CREF SWR CINT – COMPARATOR + + – SWZ BUFFER SW + RI INTEGRATOR SWZ – SW RI TO DIGITAL SECTION ANALOG COM LOGIC INPUT SW1 SW I SWITCH OPEN – IN SWITCH CLOSED Figure 3C. Input Signal Integration Phase Figure 2. Digital Logic Input ANALOG INPUT BUFFER SW I + IN + – SW RI SW + RI + IN – SW RI SWZ – – SW + RI – SW RI SWZ INTEGRATOR ANALOG COM SW I REF IN CINT – CSZ CREF SWR RINT SWZ – COMPARATOR + + – SWZ SW + RI – SW RI SWZ INTEGRATOR TO DIGITAL SECTION ANALOG COM SW1 – IN SW I – IN Figure 3A. Internal Analog Switches 3-116 TO DIGITAL SECTION SW + RI SWIZ COMPARATOR + + SWZ + CSZ CREF SWR ANALOG INPUT BUFFER SW I CINT – SWIZ REF IN RINT SW1 SWITCH OPEN SWITCH CLOSED Figure 3D. Reference Voltage Integration Phase TELCOM SEMICONDUCTOR, INC. 4-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTER 1 TC7135 For a constant VIN: ANALOG INPUT BUFFER SW I + IN + – SW RI SW + RI CSZ SWZ CREF SWR VIN = VR CINT – SWIZ REF IN RINT – COMPARATOR + + – SWZ SW + RI – SW RI INTEGRATOR SWZ TO DIGITAL SECTION ANALOG COM SW1 SW I SWITCH OPEN – IN 2 [ ] tRI . tSI The dual-slope converter accuracy is unrelated to the integrating resistor and capacitor values, as long as they are stable during a measurement cycle. Noise immunity is an inherent benefit. Noise spikes are integrated, or averaged, to zero during integration periods. Integrating ADCs are immune to the large conversion errors that plague successive approximation converters in high-noise environments. (See Figure 4.) 3 SWITCH CLOSED TC7135 Operational Theory GENERAL THEORY OF OPERATION (All Pin Designations Refer to 28-Pin DIP) Dual-Slope Conversion Principles The TC7135 is a dual-slope, integrating analog-todigital converter. An understanding of the dual-slope conversion technique will aid in following detailed TC7135 operational theory. The conventional dual-slope converter measurement cycle has two distinct phases: (1) Input signal integration (2) Reference voltage integration (deintegration) The input signal being converted is integrated for a fixed time period, measured by counting clock pulses. An opposite polarity constant reference voltage is then integrated until the integrator output voltage returns to zero. The reference integration time is directly proportional to the input signal. In a simple dual-slope converter, a complete conversion requires the integrator output to "ramp-up" and "rampdown." A simple mathematical equation relates the input signal, reference voltage, and integration time: 1 RC ∫0 tSI VIN(t) dt = VR tRI , RC where: VR = Reference voltage tSI = Signal integration time (fixed) tRI = Reference voltage integration time (variable). The TC7135 incorporates a system zero phase and integrator output voltage zero phase to the normal twophase dual-slope measurement cycle. Reduced system errors, fewer calibration steps, and a shorter overrange recovery time result. The TC7135 measurement cycle contains four phases: (1) (2) (3) (4) System zero Analog input signal integration Reference voltage integration Integrator output zero Internal analog gate status for each phase is shown in Table 1. ANALOG INPUT SIGNAL INTEGRATOR – + REF VOLTAGE FIXED SIGNAL INTEGRATE TIME PHASE CONTROL CONTROL LOGIC POLARITY CONTROL CLOCK 7 COUNTER VIN ' VFULL SCALE VIN ' 1/2 VFULL SCALE VARIABLE REFERENCE INTEGRATE TIME 8 Figure 4. Basic Dual-Slope Converter TELCOM SEMICONDUCTOR, INC. 5 6 + DISPLAY 4 COMPARATOR – SWITCH DRIVER INTEGRATOR OUTPUT Figure 3E. Integrator Output Zero Phase 3-117 4-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTER TC7135 Table 1. Internal Analog Gate Status Conversion Cycle Phase SWI + SWR Internal Analog Gate Status SWR– SWZ SWR SW1 Closed Closed System Zero Input Signal Integration Closed SWIZ Reference Schematic 3B Closed Reference Voltage Integration Integrator Output Zero 3C Closed* Closed Closed 3D Closed 3E – *NOTE: Assumes a positive polarity input signal. SWR would be closed for a negative input signal. System Zero Phase During this phase, errors due to buffer, integrator, and comparator offset voltages are compensated for by charging CAZ (auto-zero capacitor) with a compensating error voltage. With zero input voltage, the integrator output remains at zero. The external input signal is disconnected from the internal circuitry by opening the two SWI switches. The internal input points connect to analog common. The reference capacitor charges to the reference voltage potential through SWR. A feedback loop, closed around the integrator and comparator, charges the CAZ with a voltage to compensate for buffer amplifier, integrator, and comparator offset voltages. (See Figure 3B.) Analog Input Signal Integration Phase The TC7135 integrates the differential voltage between the +INPUT and –INPUT. The differential voltage must be within the device's common-mode range; –1V from either supply rail, typically. The input signal polarity is determined at the end of this phase. (See Figure 3C.) Reference Voltage Integration Phase The previously-charged reference capacitor is connected with the proper polarity to ramp the integrator output back to zero. (See Figure 3D.) The digital reading displayed is: Reading = 10,000 [ ] Differential Input . VREF Integrator Output Zero Phase This phase guarantees the integrator output is at 0V when the system zero phase is entered and that the true system offset voltages are compensated for. This phase normally lasts 100 to 200 clock cycles. If an overrange condition exists, the phase is extended to 6200 clock cycles. (See Figure 3E.) 3-118 Analog Section Functional Description Differential Inputs The TC7135 operates with differential voltages (+INPUT, pin 10 and –INPUT, pin 9) within the input amplifier common-mode range which extends from 1V below the positive supply to 1V above the negative supply. Within this common-mode voltage range, an 86 dB common-mode rejection ratio is typical. The integrator output also follows the common-mode voltage and must not be allowed to saturate. A worst-case condition exists, for example, when a large positive common-mode voltage with a near full-scale negative differential input voltage is applied. The negative input signal drives the integrator positive when most of its swing has been used up by the positive common-mode voltage. For these critical applications, the integrator swing can be reduced to less than the recommended 4V full-scale swing, with some loss of accuracy. The integrator output can swing within 0.3V of either supply without loss of linearity. Analog Common ANALOG COMMON (pin 3) is used as the –INPUT return during the auto-zero and deintegrate phases. If – INPUT is different from analog common, a common-mode voltage exists in the system. This signal is rejected by the excellent CMRR of the converter. In most applications, – INPUT will be set at a fixed known voltage (power supply common, for instance). In this application, analog common should be tied to the same point, thus removing the commonmode voltage from the converter. The reference voltage is referenced to analog common. Reference Voltage The reference voltage input (REF IN, pin 2) must be a positive voltage with respect to analog common. Two reference voltage circuits are shown in Figure 5. TELCOM SEMICONDUCTOR, INC. 4-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTER 1 TC7135 Digital Section Functional Description V+ The major digital subsystems within the TC7135 are illustrated in Figure 6, with timing relationships shown in Figure 7. The multiplexed BCD output data can be displayed on an LCD with the TC7211A. The digital section is best described through a discussion of the control signals and data outputs. V+ TC05 REF IN 2.5VREF TC7135 2 I REF ANALOG COMMON RUN/HOLD Input When left open, the RUN/HOLD (R/H) input (pin 25) assumes a logic "1" level. With R/H = 1, the TC7135 performs conversions continuously, with a new measurement cycle beginning every 40,002 clock pulses. When R/H changes to logic "0," the measurement cycle in progress will be completed, and data held and displayed, as long as the logic "0" condition exists. A positive pulse (>300nsec) at R/H initiates a new measurement cycle. The measurement cycle in progress when R/H initially assumed logic "0" must be completed before the positive pulse can be recognized as a single conversion run command. The new measurement cycle begins with a 10,001count auto-zero phase. At the end of this phase, the busy signal goes high. V– V+ 6.8 kΩ V+ TC04 REF IN 20 kΩ TC7135 1.25V REF ANALOG COMMON ANALOG GROUND D5 MSB D4 DIGIT D3 DRIVE D2 SIGNAL D1 13 B1 14 B2 LSB DATA OUTPUT MULTIPLEXER LATCH LATCH LATCH LATCH 6 15 B4 16 B8 FROM ANALOG SECTION POLARITY FF 4 5 Figure 5. Using an External Reference Voltage POLARITY 3 LATCH COUNTERS ZERO CROSS DETECT 7 CONTROL LOGIC 24 DIGITAL GND 22 25 27 CLOCK IN RUN/ HOLD OVER– RANGE 28 UNDER– RANGE 26 STROBE 21 BUSY 8 Figure 6. Digital Section Functional Diagram TELCOM SEMICONDUCTOR, INC. 3-119 4-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTER TC7135 TC7135 OUTPUTS INTEGRATOR OUTPUT BUSY SIGNAL INTE SYSTEM 10,000 ZERO 10,001 COUNTS COUNTS (FIXED) REFERENCE INTEGRATE 20,001 COUNTS (MAX) * B1–B8 FULL MEASUREMENT CYCLE 40,002 COUNTS D5 (MSD) DATA D4 DATA D3 DATA D2 DATA D1 (LSD) DATA D5 DATA ,, STROBE NOTE ABSENCE OF STROBE 200 COUNTS BUSY OVERRANGE WHEN APPLICABLE D5 UNDERRANGE WHEN APPLICABLE D4 EXPANDED SCALE BELOW DIGIT SCAN END OF CONVERSION D3 D5 201 COUNTS 200 COUNTS 200 COUNTS 200 COUNTS D4 100 COUNTS D2 D1 D1 * FIRST D5 OF SYSTEM ZERO AND REFERENCE INTEGRATE ONE COUNT LONGER. STROBE AUTO ZERO DIGIT SCAN FOR OVERRANGE D3 D2 * D5 REFERENCE INTEGRATE SIGNAL INTEGRATE * D4 D3 D2 D1 Figure 7. Timing Diagrams for Outputs STROBE Output During the measurement cycle, the STROBE output (pin 26) control line is pulsed low five times. The five low pulses occur in the center of the digit drive signals (D1, D2, D3, D4 and D5; see Figure 8). D5 goes high for 201 counts when the measurement cycles end. In the center of D5 pulse, 101 clock pulses after the end of the measurement cycle, the first STROBE occurs for one-half clock pulse. After D5 strobe, D4 goes high for 200 clock pulses. STROBE goes low 100 clock pulses after D4 goes high. This continues through the D1 drive pulse. The digit drive signals will continue to permit display scanning. STROBE pulses are not repeated until a new measurement is completed. The digit drive signals will not continue if the previous signal resulted in an overrange condition. 3-120 200 COUNTS 200 COUNTS *DELAY BETWEEN BUSY GOING LOW AND FIRST STROBE PULSE IS DEPENDENT ON ANALOG INPUT. Figure 8. Strobe Signal Pulses Low Five Times per Conversion The active-low STROBE pulses aid BCD data transfer to UARTs, microprocessors, and external latches. (See Application Note AN-16.) BUSY Output At the beginning of the signal-integration phase, BUSY (pin 21) goes high and remains high until the first clock pulse after the integrator zero crossing. BUSY returns to logic "0" after the measurement cycle ends in an overrange condition. The internal display latches are loaded during the first clock pulse after BUSY and are latched at the clock pulse end. The BUSY signal does not go high at the beginning of the measurement cycle, which starts with the auto-zero phase. OVERRANGE Output If the input signal causes the reference voltage integration time to exceed 20,000 clock pulses, the OVERRANGE output (pin 27) is set to logic "1." The OVERRANGE output register is set when BUSY goes low and reset at the beginning of the next reference-integration phase. UNDERRANGE Output If the output count is 9% of full scale or less (≤1800 counts), the UNDERRANGE output (pin 28) register bit is set at the end of BUSY. The bit is set low at the next signalintegration phase. TELCOM SEMICONDUCTOR, INC. 4-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTER 1 TC7135 POLARITY Output A positive input is registered by a logic "1" polarity signal. The POLARITY output (pin 23) is valid at the beginning of reference integrate and remains valid until determined during the next conversion. The POLARITY bit is valid even for a zero reading. Signals less than the converter's LSB will have the signal polarity determined correctly. This is useful in null applications. Digit Drive Outputs Digit drive outputs are positive-going signals. Their scan sequence is D5, D4, D3, D2 and D1 (pins 12, 17, 18, 19 and 20, respectively). All positive signals are 200 clock pulses wide, except D5, which is 201 clock pulses. All five digits are continuously scanned, unless an overrange condition occurs. In an overrange condition, all digit drives are held low from the final STROBE pulse until the beginning of the next reference-integrate phase. The scanning sequence is then repeated, providing a blinking visual display. BCD Data Outputs The binary coded decimal (BCD) outputs, B8, B4, B2 and B1 (pins 16, 15, 14 and 13, respectively) are positive truelogic signals. They become active simultaneously with digit drive signals. In an overrange condition, all data bits are logic "0". APPLICATIONS INFORMATION Component Value Selection Integrating Resistor The integrating resistor (RINT) is determined by the fullscale input voltage and output current of the buffer used to charge the integrator capacitor (CINT). Both the buffer amplifier and the integrator have a Class A output stage, with 100 µA of quiescent current. A 20 µA drive current gives negligible linearity errors. Values of 5 µA to 40 µA give good results. The exact value of RINT for a 20 µA current is easily calculated: Full-scale voltage RINT = . 20 µA Integrating Capacitor The product of RINT and CINT should be selected to give the maximum voltage swing to ensure tolerance build-up will not saturate integrator swing (approximately 0.3V from either supply). For ±5V supplies, and analog common tied to supply ground, a ±3.5V to ±4V full-scale integrator swing is TELCOM SEMICONDUCTOR, INC. adequate. A 0.10 µF to 0.47 µF is recommended. In general, the value of CINT is given by: CINT = = [10,000 x clock period] x IINT Integrator output voltage swing 2 (10,000) (clock period) (20 µA) . Integrator output voltage swing A very important characteristic of the CINT is that it has low dielectric absorption to prevent roll-over or ratiometric errors. A good test for dielectric absorption is to use the capacitor with the input tied to the reference. This ratiometric condition should read half-scale 0.9999. Any deviation is probably due to dielectric absorption. Polypropylene capacitors give undetectable errors at reasonable cost. Polystyrene and polycarbonate capacitors may also be used in less critical applications. Auto-Zero and Reference Capacitors The size of the auto-zero capacitor (CAZ) has some influence on system noise. A large capacitor reduces noise. The reference capacitor (CREF) should be large enough such that stray capacitance from its nodes to ground is negligible. The dielectric absorption of CREF and CAZ is only important at power-on, or when the circuit is recovering from an overload. Smaller or cheaper capacitors can be used if accurate readings are not required during the first few seconds of recovery. Reference Voltage The analog input required to generate a full-scale output is VIN = 2 VREF. The stability of the reference voltage is a major factor in overall absolute accuracy of the converter. Therefore, it is recommended that high-quality references be used where high-accuracy, absolute measurements are being made. Suitable references are: Part Type TC04 TC05 3 4 5 6 Manufacturer TelCom Semiconductor TelCom Semiconductor 7 Conversion Timing Line Frequency Rejection A signal-integration period at a multiple of the 60 Hz line frequency will maximize 60 Hz "line noise" rejection. A 100 kHz clock frequency will reject 50 Hz, 60 Hz and 400 Hz noise, corresponding to 2.5 readings per second. 3-121 8 4-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTER TC7135 Table 2. Line Frequency Rejection High-Speed Operation Oscillator Frequency (kHz) Frequency Rejected (Hz) 300, 200, 150, 120, 100, 40, 33-1/3 250, 166-2/3, 125, 100 100 60 50 50, 60, 400 Table 3. Conversion Rate vs Clock Frequency Conversion Rate (Conv/Sec) Clock Frequency (kHz) 2.5 3.0 5.0 7.5 10.0 20.0 30.0 100 120 200 300 400 800 1200 Displays and Driver Circuits TelCom Semiconductor manufactures three display decoder/driver circuits to interface the TC7135 to LCDs or LED displays. Each driver has 28 outputs for driving four 7segment digit displays. Device Package Description TC7211AIPL 40-Pin Epoxy 4-Digit LCD Driver/Encoder Several sources exist for LCDs and LED displays. Manufacturer Address Hewlett Packard Components AND 640 Page Mill Road Palo Alto, CA 94304 720 Palomar Ave. Sunnyvale, CA 94086 3415 Kanhi Kawa St. Torrance, CA 90505 Epson America, Inc. 3-122 Display Type LED LCD and LED LCD The maximum conversion rate of most dual-slope ADCs is limited by frequency response of the comparator. The comparator in this circuit follows the integrator ramp with a 3 µs delay, and at a clock frequency of 160 kHz (6 µs period), half of the first reference integrate clock period is lost in delay. This means the meter reading will change from 0 to 1 with a 50 µV input, 1 to 2 with 150 µV, 2 to 3 with 250 µV, etc. This transition at midpoint is considered desirable by most users; however, if clock frequency is increased appreciably above 160 kHz, the instrument will flash "1" on noise peaks even when the input is shorted. For many dedicated applications, where the input signal is always of one polarity, comparator delay need not be a limitation. Since nonlinearity and noise do not increase substantially with frequency, clock rates up to ~1 MHz may be used. For a fixed clock frequency, the extra count (or counts) caused by comparator delay will be constant and can be digitally subtracted. The clock frequency may be extended above 160 kHz without this error, however, by using a low value resistor in series with the integrating capacitor. The effect of the resistor is to introduce a small pedestal voltage onto the integrator output at the beginning of reference-integrate phase. By careful selection of the ratio between this resistor and the integrating resistor (a few tens of ohms in the recommended circuit), the comparator delay can be compensated for and maximum clock frequency extended by approximately a factor of 3. At higher frequencies, ringing and second-order breaks will cause significant nonlinearities during the first few counts of the instrument. The minimum clock frequency is established by leakage on the auto-zero and reference capacitors. With most devices, measurement cycles as long as 10 seconds give no measurable leakage error. The clock used should be free from significant phase or frequency jitter. Several suitable low-cost oscillators are shown in the applications section. The multiplexed output means if the display takes significant current from the logic supply, the clock should have good PSRR. Zero-Crossing Flip-Flop The flip-flop interrogates data once every clock pulse after transients of the previous clock pulse and half-clock pulse have died down. False zero-crossings caused by clock pulses are not recognized. Of course, the flip-flop delays the true zero-crossing by up to one count in every instance, and if a correction were not made, the display would always be one count too high. Therefore, the counter TELCOM SEMICONDUCTOR, INC. 4-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTER 1 TC7135 is disabled for one clock pulse at the beginning of the reference integrate (deintegrate) phase. This one-count delay compensates for the delay of the zero-crossing flipflop, and allows the correct number to be latched into the display. Similarly, a one-count delay at the beginning of auto-zero gives an overload display of 0000 instead of 0001. No delay occurs during signal integrate, so true ratiometric readings result. 2 +5V V+ V– 11 8 1 (–5V) 5 10 µF TC7135 Generating a Negative Supply TC7660 + 4 + 2 3 3 24 A negative voltage can be generated from the positive supply by using a TC7660. (See Figure 9.) 10 µF Figure 9. Negative Supply Voltage Generator TYPICAL APPLICATIONS 4 Comparator Clock Circuit RC Oscillator Circuit +5V R2 R1 C 16 kΩ fO GATES ARE 74C04 1. fO ≈ 2 + 0.22 µF 8 VOUT LM311 3 – 1 R1 R2 1 , RP = 2 C[0.41 RP + 0.70 R1] R1 + R2 a. If R = R1 = R2, f ≅ 0.55/RC b. If R2 >> R1, f ≅ 0.45/R1C c. If R2 << R1, f ≅ 0.72/R1C 2. Examples: a. f = 120 kHz, C = 420 pF R1 = R2 ≈ 10.9 kΩ b. f = 120 kHz, C = 420 pF, R2 = 50 kΩ R1 = 8.93 kΩ c. f = 120 kHz, C = 220 pF, R2 = 5 kΩ R1 = 27.3 kΩ 1 kΩ 56 kΩ 5 7 30 kΩ 4 16 kΩ 390 pF +5V R2 100 kΩ 2 + R2 100 kΩ C2 10 pF 6 LM311 3 – 4 1 6 R4 2 kΩ 7 VOUT R3 50 kΩ 7 C1 0.1 µF 8 TELCOM SEMICONDUCTOR, INC. 3-123 4-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTER TC7135 TYPICAL APPLICATIONS (Cont.) 4-1/2 Digit ADC With Multiplexed Common Anode LED Display 20 D1 4 1 µF 0.47 µF + ANALOG INPUT – 17 D4 POL 23 4.7 kΩ b – CREF 7 TC7135 fIN 10 1 µF 12 D5 AZ IN 6 BUFF OUT 22 100 kΩ 18 D3 INT OUT 5 100 kΩ 120 kHz 19 D2 +5V + CREF 8 c 6 D 2 C 1 B 7 A 16 15 B4 14 B2 13 B1 3 ANALOG COMMON REF V – IN 7 7 X7 BLANK MSD ON ZERO B8 –INPUT 7 1 µF +INPUT 9 7 9–15 5 RBI 16 7447 +5V V+ 1 2 6.8 kΩ 11 –5V 100 kΩ TC04 4-1/2 Digit ADC Interfaced to LCD With Digit Blanking on Overrange +5V 4-1/2 DIGIT LCD SEGMENT DRIVE 1/2 CD4030 –5V 1 V– 4 INT OUT D2 0.47 µF 5 AZ IN D3 BUFF OUT D4 fIN B8 1 µF 6 5 23 POL D1 20 CD4081 1/4 CD4030 19 31 32 18 33 17 34 BP D1 D2 D3 D4 100 kΩ 22 120 kHz TC7135 B4 100 kΩ + ANALOG INPUT – 10 9 +INPUT B2 B1 CD4071 16 30 15 29 14 28 13 27 TC7211A B3 B2 V+ B1 GND 1 35 B0 –INPUT D5 12 3 ANALOG STROBE 26 COMMON 27 OR REF + V IN 2 6.8 kΩ D 1/4 CD4081 +5V 1/4 CD4030 1/2 Q CD4013 CLK S R +5V 100 kΩ TC04 3-124 TELCOM SEMICONDUCTOR, INC. 4-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTER 1 TC7135 TYPICAL APPLICATIONS (Cont.) 2 4-1/2 Digit ADC With Multiplexed Common Cathode LED Display +5V +5V SET VREF = 1V –5V 6.8V 1 100 kΩ TC04 2 1.22V V– UR REF IN OR 3 ANALOG GND 28 27 150Ω 26 STROBE 47 kΩ 10 9 11 8 24 12 7 23 13 22 14 CD4513 6 BE 21 15 4 20 16 3 19 17 2 18 18 1 ANALOG GND 0.47 µF 100 kΩ + SIG IN – 4 INT OUT 5 AZ IN 6 BUFF OUT 100 kΩ 7 + CREF 1 µF 8 – CREF 9 –INPUT 1 µF 0.1 µF 10 +5V 11 12 13 14 V+ 25 RUN/HOLD DGND POLARITY CLK IN BUSY (LSD) D1 +INPUT D2 TC7135 D3 D5 (MSD) D4 B1 (LSB) B2 (MSB) B8 150Ω 3 5 +5V 4 17 16 15 B4 fO = 120 kHz 5 4-Channel Data Acquisition System ADDRESS BUS CONTROL + 5V DATA BUS V+ REF CAP +15V –15V 157 6522 -VIA- POL OR INT UR D5 B8 TC7135 B4 + INPUT B2 1B 2B 3B SEL 1A 2A 3A PA3 PA4 PA5 PA6 PA7 CA1 CA2 PB5 PB4 PB0 PB1 PB2 PB3 B1 D1 VR D2 – INPUT D3 D4 ANALOG STB COMMON R/H DGND fIN GAIN SELECTION fIN 11 8 10 LH0084 14 – 1Y 2Y 3Y AZ + PA0 PA1 PA2 6 GAIN: 10, 20, 50, 100 BUF 16 REF VOLTAGE 15 DG529 3 9 DA DB CHANNEL 1 CHANNEL 2 CHANNEL 3 WR A1 A0 EN CHANNEL 4 7 DIFFERENTIAL MULTIPLEXER – 5V 8 CHANNEL SELECTION TELCOM SEMICONDUCTOR, INC. 3-125