■ Packages – 32-pin TSOP – 32-pin 300 mil SOJ Features ■ ■ ■ ■ ■ ■ ■ PRELIMINARY V61C3181024 128K X 8 HIGH SPEED STATIC RAM MOSEL VITELIC High-speed: 10, 12, 15 ns Fully static operation All inputs and outputs directly TTL compatible Three state outputs Low data retention current (VCC = 2V) Single 3.3V ± 0.3 Power Supply Low CMOS Standby current of 5 mA max Description The V61C3181024 is a 1,048,576-bit static random-access memory organized as 131,072 words by 8 bits. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures. The V61C3181024 is available in 32-pin SOJ and TSOP. Functional Block Diagram A0 VCC GND Row Decoder Memory Array A8 I/O0 Column I/O Input Data Circuit Column Decoder I/O7 A9 CE1 CE2 OE WE A16 Control Circuit 3181024 01 Device Usage Chart Operating Temperature Range 0°C to 70°C V61C3181024 Rev. 1.3 February 1999 Package Outline Access Time (ns) T R 10 12 15 Temperature Mark • • • • • Blank 1 V61C3181024 MOSEL VITELIC Pin Descriptions WE Write Enable Input An active LOW input, WE input controls read and write operations. When CE and WE inputs are both LOW, the data present on the I/O pins will be written into the selected memory location. A0–A16 Address Inputs These 17 address inputs select one of the 128K x 8 bit segments in the RAM. CE1, CE2 Chip Enable Inputs CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active to read from or write to the device. If either chip enable is not active, the device is deselected and is in a standby power mode. The I/O pins will be in the high-impedance state when deselected. I/O0–I/O7 Data Input and Data Output Ports These 8 bidirectional ports are used to read data from and write data into the RAM. VCC Power Supply GND Ground Output Enable Input OE The Output Enable input is active LOW. When OE is LOW with CE LOW and WE HIGH, data of the selected memory location will be available on the I/O pins. When OE is HIGH, the I/O pins will be in the high impedance state. Pin Configurations (Top View) 32-Pin SOJ 32-Pin TSOP-I NC 1 32 VCC A10 2 31 A11 A9 3 30 CE2 A8 4 29 WE A7 5 28 A12 A6 6 27 A13 A5 7 26 A14 A4 8 25 A15 A3 9 24 OE A2 10 23 A16 A1 11 22 CE1 A0 12 21 I/O7 I/O0 13 20 I/O6 I/O1 14 19 I/O5 I/O2 15 18 I/O4 GND 16 17 I/O3 A15 A14 A13 A12 WE CE2 A11 VCC NC A10 A9 A8 A7 A6 A5 A4 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 3181024 03 3181024 02 V61C3181024 Rev. 1.3 February 1999 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 2 OE A16 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 VSS I/O2 I/O1 I/O0 A0 A1 A2 A3 V61C3181024 MOSEL VITELIC Part Number Information V 61 C 31 8 1024 – MOSEL-VITELIC TEMP. OPERATING VOLTAGE SRAM FAMILY DENSITY SPEED BLANK = 0°C to 70°C 1024K 61 = HIGH SPEED PKG C = CMOS PROCESS T = TSOP STANDARD R = 300 mil SOJ PWR. 31 = 3.3V ORGANIZATION 10 ns 12 ns 15 ns 8 = 8-bit BLANK = STANDARD 3181024 05 Absolute Maximum Ratings (1) Symbol Parameter Commercial Units VN Input Voltage -0.5 to VCC + 0.5 V VDQ Input/Output Voltage Applied VCC + 0.5 V TBIAS Temperature Under Bias -10 to +125 °C TSTG Storage Temperature -65 to +150 °C NOTE: 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Capacitance* Truth Table TA = 25°C, f = 1.0MHz Symbol Parameter CIN Input Capacitance COUT Output Capacitance Max. Unit Mode CE1 CE2 OE WE I/O Operation VIN = 0V 6 pF Standby H X X X High Z VI/O = 0V 8 pF Standby X L X X High Z Output Disable L H H H High Z Read L H L H DOUT Write L H X L DIN Conditions NOTE: 1. This parameter is guaranteed by design and not tested. NOTE: X = Don’t Care, L = LOW, H = HIGH V61C3181024 Rev. 1.3 February 1999 3 V61C3181024 MOSEL VITELIC DC Electrical Characteristics (over all temperature ranges, VCC = 3.3V ± 0.3) Symbol Parameter Min. Typ. Max. Units VIL Input LOW Voltage(1,2) -0.5 — 0.8 V VIH Input HIGH Voltage(1) 2.2 — VCC + 0.3 V IIL Input Leakage Current VCC = Max, VIN = 0V to VCC -5 — 5 µA IOL Output Leakage Current VCC = Max, CE1 = VIH, VOUT = 0V to VCC -5 — 5 µA VOL Output LOW Voltage IOL = 4mA — — 0.4 V VOH Output HIGH Voltage IOH = -2mA 2.4 — — V Symbol Test Conditions Parameter Com.(4) Units ICC1 Average Operating Current, CE1 = VIL, CE2 = VIH, Output Open, VCC = Max., f = fMAX(3) 100 mA ISB TTL Standby Current CE1 ≥ VIH, CE2 ≤ VIL, VCC = Max. 25 mA ISB1 CMOS Standby Current, CE1 ≥ VCC – 0.2V, CE2 ≤ 0.2V, VIN ≥ VCC – 0.2V or VIN ≤ 0.2V, VCC = Max. 2 mA NOTES: 1. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included. 2. VIL (Min.) = -3.0V for pulse width < 20ns. 3. fMAX = 1/tRC. 4. Maximum values. AC Test Conditions Key to Switching Waveforms Input Pulse Levels 0 to 3V Input Rise and Fall Times 3 ns Timing Reference Levels 1.5V Output Load WAVEFORM see below INPUTS OUTPUTS MUST BE STEADY WILL BE STEADY MAY CHANGE FROM H TO L WILL BE CHANGING FROM H TO L MAY CHANGE FROM L TO H WILL BE CHANGING FROM L TO H DON'T CARE: ANY CHANGE PERMITTED CHANGING: STATE UNKNOWN DOES NOT APPLY CENTER LINE IS HIGH IMPEDANCE “OFF” STATE AC Test Loads and Waveforms 3.3V 3.3V 480 Ω 480 Ω I/O Pins 225 Ω DOUT 255 Ω CL = 5 pF* CL = 30 pF* * Includes scope and jig capacitance 3181024 06 V61C3181024 Rev. 1.3 February 1999 for tCLZ, tCHZ, tOLZ, tWZ, tOW, and tOHZ 3181024 06B 4 V61C3181024 MOSEL VITELIC Data Retention Characteristics Symbol VDR Parameter CE1 ≥ VCC – 0.2V, CE2 ≤ 0.2V, VIN ≥ VCC – 0.2V, or VIN ≤ 0.2V VCC for Data Retention Min. Typ.(2) Max. Units 2.0 — 5.5 V ICCDR Data Retention Current CE1 ≥ VDR –0.2V, CE2 ≤ 0.2V, VIN ≥ VCC – 0.2V, or VIN ≤ 0.2V — 75 150 µA tCDR Chip Deselect to Data Retention Time 0 — — ns — — ns tR Operation Recovery Time (see Retention Waveform) tRC (1) NOTES: 1. tRC = Read Cycle Time 2. TA = +25°C. Low VCC Data Retention Waveform (1) (CE1 Controlled) Data Retention Mode VCC 4.5V VDR ≥ 2V tCDR CE1 2.2V CE1 ≥ VCC – 0.2V 4.5V tR 2.2V 3181024 07 Low VCC Data Retention Waveform (2) (CE2 Controlled) Data Retention Mode VCC 4.5V VDR ≥ 2V tCDR CE2 V61C3181024 Rev. 1.3 February 1999 2.2V 4.5V tR CE2 ≤ 0.2V 5 2.2V 3181024 08 V61C3181024 MOSEL VITELIC AC Electrical Characteristics (over all temperature ranges) Read Cycle Parameter Name -10 Parameter -12 -15 Min. Max. Min. Max. Min. Max. Unit tRC Read Cycle Time 10 — 12 — 15 — ns tAA Address Access Time — 10 — 12 — 15 ns tACS1 Chip Enable Access Time — 10 — 12 — 15 ns tACS2 Chip Enable Access Time — 10 — 12 — 15 ns Output Enable to Output Valid — 6 — 6 — 7 ns tCLZ1 Chip Enable to Output in Low Z 3 — 3 — 3 — ns tCLZ2 Chip Enable to Output in Low Z 3 — 3 — 3 — ns tOLZ Output Enable to Output in Low Z 0 — 0 — 0 — ns tCHZ Chip Disable to Output in High Z 0 3 0 3 0 4 ns tOHZ Output Disable to Output in High Z 0 3 0 3 0 4 ns tOH Output Hold from Address Change 3 — 3 — 3 — ns tOE Write Cycle Parameter Name -10 Parameter -12 -15 Min. Max. Min. Max. Min. Max. Unit tWC Write Cycle Time 10 — 12 — 15 — ns tCW1 Chip Enable to End of Write 8 — 10 — 13 — ns tCW2 Chip Enable to End of Write 8 — 10 — 13 — ns tAS Address Setup Time 0 — 0 — 0 — ns tAW Address Valid to End of Write 8 — 10 — 13 — ns tWP Write Pulse Width 8 — 9 — 11 — ns tAH Address Hold to End of Write 0 — 0 — 0 — ns tWHZ Write to Output High-Z 0 5 0 5 0 5 ns tWLZ Write to Output Low Z 3 — 3 — 5 — ns tDW Data Setup to End of Write 5 — 6 — 8 — ns tDH Data Hold from End of Write 0 — 0 — 0 — ns V61C3181024 Rev. 1.3 February 1999 6 V61C3181024 MOSEL VITELIC Switching Waveforms (Read Cycle) Read Cycle 1(1, 2) tRC ADDRESS tAA OE tOE tOLZ tOH tOHZ(5) I/O 3181024 09 Read Cycle 2(1, 2, 4) tRC ADDRESS tAA tOH tOH I/O 3181024 10 Read Cycle 3(1, 3, 4) ADDRESS CE1 tACS1 CE2 I/O tACS2 tCHZ(5) tCLZ1(5) tCLZ2(5) 3181024 11 NOTES: 1. WE = VIH. 2. CE1 = VIL and CE2 = VIH. 3. Address valid prior to or coincident with CE1 transition LOW and/or CE2 transition HIGH. 4. OE = VIL. 5. Transition is measured ±500mV from steady state with CL = 5pF. This parameter is guaranteed and not 100% tested. V61C3181024 Rev. 1.3 February 1999 7 V61C3181024 MOSEL VITELIC Switching Waveforms (Write Cycle) Write Cycle 1 (WE Controlled)(4) tWC ADDRESS tAH(2) (6) tCW CE1 tAW CE2 tCW(6) tAS WE tWP(1) OUTPUT tDW tWHZ tDH INPUT 3181024 12 Write Cycle 2 (CE Controlled)(4) tWC ADDRESS tAH(2) tCW(6) (4) CE1 tAW tCW(6) CE2 tAS WE OUTPUT High-Z tDW tDH (5) INPUT 3181024 13 NOTES: 1. The internal write time of the memory is defined by the overlap of CE1 and CE2 active and WE low. All signals must be active to initiate and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 2. tAH is measured from the earlier of CE1 or WE going high, or CE2 going LOW at the end of the write cycle. 3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 4. OE = VIL or VIH. However it is recommended to keep OE at VIH during write cycle to avoid bus contention. 5. If CE1 is LOW and CE2 is HIGH during this period, I/O pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 6. tCW is measured from CE1 going low or CE2 going HIGH to the end of write. V61C3181024 Rev. 1.3 February 1999 8 V61C3181024 MOSEL VITELIC Package Diagrams 32-Pin 300 mil SOJ Units in inches 0.825 ± 0.005 32 17 0.300 ± 0.005 1 16 0.028 TYP. (0.032 MAX.) 0.133 TYP. (0.140 MAX.) 0.335 ± 0.005 0.100 ± 0.005 SEATING PLANE 0.050 TYP. 0.048 MAX. 0.018 ± 0.002 0.062 MIN. 0.267 TYP. (0.276 MAX.) 0.004 MAX 32-Pin TSOP-I Units in inches [mm] 0.787 ± 0.008 [19.99 ± 0.203] Detail “A” 0.315 TYP. (0.319 MAX.) 0.010 [.254] 0.800 TYP. (0.810 MAX.) 0.024 ± 0.004 [0.610 ± 0.102] 0.724 TYP. (0.728 MAX.) [18.39 TYP. (18.49 MAX)] 0.035 ± 0.002 [0.889 ± 0.051] SEATING PLANE See Detail “A” 0.032 [0.813] TYP. 0.020 [0.508] MAX. 0.020 [0.508] SBC 0.005 MIN. 0.007 MAX. 0.003 [0.076] MAX. 0.127 MIN. 0.178 MAX. V61C3181024 Rev. 1.3 February 1999 0.047 [1.19] MAX. 9 0.009 ± 0.002 [0.229 ± 0.051] MOSEL VITELIC WORLDWIDE OFFICES V61C3181024 U.S.A. TAIWAN SINGAPORE IRELAND & UK 3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0952 7F, NO. 102 MIN-CHUAN E. ROAD, SEC. 3 TAIPEI PHONE: 886-2-2545-1213 FAX: 886-2-2545-1209 10 ANSON ROAD #23-13 INTERNATIONAL PLAZA SINGAPORE 079903 PHONE: 65-3231801 FAX: 65-3237013 BLOCK A UNIT 2 BROOMFIELD BUSINESS PARK MALAHIDE CO. DUBLIN, IRELAND PHONE: +353 1 8038020 FAX: +353 1 8038049 1 CREATION ROAD I SCIENCE BASED IND. PARK HSIN CHU, TAIWAN, R.O.C. PHONE: 886-3-578-3344 FAX: 886-3-579-2838 JAPAN HONG KONG 19 DAI FU STREET TAIPO INDUSTRIAL ESTATE TAIPO, NT, HONG KONG PHONE: 852-2665-4883 FAX: 852-2664-7535 WBG MARINE WEST 25F 6, NAKASE 2-CHOME MIHAMA-KU, CHIBA-SHI CHIBA 261-71 PHONE: 81-43-299-6000 FAX: 81-43-299-6555 GERMANY (CONTINENTAL EUROPE & ISRAEL ) 71083 HERRENBERG BENZSTR. 32 GERMANY PHONE: +49 7032 2796-0 FAX: +49 7032 2796 22 U.S. SALES OFFICES NORTHWESTERN NORTHEASTERN SOUTHWESTERN 3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0952 SUITE 436 20 TRAFALGAR SQUARE NASHUA, NH 03063 PHONE: 603-889-4393 FAX: 603-889-9347 SUITE 200 5150 E. PACIFIC COAST HWY. LONG BEACH, CA 90804 PHONE: 562-498-3314 FAX: 562-597-2174 CENTRAL & SOUTHEASTERN 604 FIELDWOOD CIRCLE RICHARDSON, TX 75081 PHONE: 972-690-1402 FAX: 972-690-0341 NORTHEASTERN SUITE 436 20 TRAFALGAR SQUARE NASHUA, NH 03063 PHONE: 603-889-4393 FAX: 603-889-9347 © Copyright 1999, 1998, MOSEL VITELIC Inc. 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