MOSEL V62C2184096

MOSEL VITELIC
PRELIMINARY
V62C2184096
512K X 8, CMOS STATIC RAM
Features
Description
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The V62C2184096 is a very low power CMOS
static RAM organized as 524,288 words by 8 bits.
Easy memory expansion is provided by an active
LOW CE1, and active HIGH CE2, an active LOW
OE, and three static I/O’s. This device has an
automatic power-down mode feature when
deselected.
High-speed: 70, 85 ns
Ultra low standby current of 4µA (max.)
Fully static operation
All inputs and outputs directly compatible
Three state outputs
Ultra low data retention current (VCC = 1.2V)
Operating voltage: 2.3V–3.0V
Packages
– 32-Pin TSOP (Standard)
– 36-Ball CSP BGA (8mm x 10mm)
Functional Block Diagram
Input Buffer
I/O8
Sense Amp
Row Decoder
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
1024
x
4096
I/O1
Column Decoder
OE
WE
CE1
CE2
Control
Circuit
A10 A11 A12 A13 A14 A15 A16 A17 A18
Device Usage Chart
Operating
Temperature
Range
Package Outline
Access Time (ns)
Power
T
B
70
85
L
LL
Temperature
Mark
0°C to 70°C
•
•
•
•
•
•
Blank
–40°C to +85°C
•
•
•
•
•
I
V62C2184096 Rev. 1.5 June 2000
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V62C2184096
MOSEL VITELIC
Pin Descriptions
WE
Write Enable Input
The write enable input is active LOW and controls
read and write operations. With the chip enabled,
when WE is HIGH and OE is LOW, output data will
be present at the I/O pins; when WE is LOW and
OE is HIGH, the data present on the I/O pins will be
written into the selected memory locations.
A0–A18
Address Inputs
These 19 address inputs select one of the 512K x 8
bit segments in the RAM.
CE1, CE2* Chip Enable Inputs
CE1 is active LOW and CE2 is active HIGH. Both
chip enables must be active to read from or write to
the device. If either chip enable is not active, the
device is deselected and is in a standby power
mode. The I/O pins will be in the high-impedance
state when deselected.
I/O1–I/O8 Data Input and Data Output Ports
These 8 bidirectional ports are used to read data
from and write data into the RAM.
Output Enable Input
OE
The Output Enable input is active LOW. With chip
enabled, when OE is LOW and WE HIGH, data of
the selected memory location will be available on
the I/O pins. When OE is HIGH, the I/O pins will be
in the high impedance state.
VCC
Power Supply
GND
Ground
*CE2 is available on BGA package only.
Pin Configurations (Top View)
32-Pin TSOP (Standard)
A11
A9
A8
A13
WE
A18
A15
VCC
A17
A16
A14
A12
A7
A6
A5
A4
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
OE
A10
CE1
I/O8
I/O7
I/O6
I/O5
I/O4
GND
I/O3
I/O2
I/O1
A0
A1
A2
A3
36 BGA
1
2
3
4
5
6
1
2
3
4
5
A
A0
A1
CE2
A3
A6
A8
B
I/O5
A2
WE
A4
A7
I/O1
C
I/O6
NB
NC
A5
NB
I/O2
D
VSS
NB
NB
NB
NB
VCC
E
VCC
NB
NB
NB
NB
VSS
F
I/O7
NB
A18
A17
NB
I/O3
F
G
I/O8
OE
CE1
A16
A15
I/O4
G
H
A9
A10
A11
A12
A13
A14
A
B
C
D
E
Note: NC means no connect.
NB means no ball.
H
TOP VIEW
TOP VIEW
V62C2184096 Rev. 1.5 June 2000
2
6
V62C2184096
MOSEL VITELIC
Part Number Information
V
MOSEL-VITELIC
MANUFACTURED
62
C
21
8
4096
–
TEMP.
SRAM
FAMILY
OPERATING
VOLTAGE
PKG
DENSITY
PWR.
4096K
62 = STANDARD
BLANK = 0°C to 70°C
I = -40°C to +85°C
SPEED
70 ns
85 ns
C = CMOS PROCESS
T = TSOP STANDARD
B = BGA
21 = 2.3V–3.0V
ORGANIZATION
L = LOW POWER
LL = LOW LOW POWER
8 = 8-bit
Absolute Maximum Ratings (1)
Symbol
Parameter
Commercial
Industrial
Units
VCC
Supply Voltage
-0.5 to + VCC + 0.5
-0.5 to + VCC + 0.5
V
VN
Input Voltage
-0.5 to + VCC + 0.5
-0.5 to + VCC + 0.5
V
VDQ
Input/Output Voltage Applied
VCC + 0.3
VCC + 0.3
V
TBIAS
Temperature Under Bias
-10 to +125
-65 to +135
°C
TSTG
Storage Temperature
-55 to +125
-65 to +150
°C
NOTE:
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Capacitance*
TA = 25°C, f = 1.0MHz
Symbol
Parameter
CIN
Input Capacitance
COUT
Output Capacitance
Truth Table
Conditions
Max.
Unit
VIN = 0V
6
pF
Mode
CE1
CE2
OE
WE
I/O
Operation
VI/O = 0V
8
pF
Standby
H
X
X
X
High Z
Standby
X
L
X
X
High Z
Output Disable
L
H
H
H
High Z
Read
L
H
L
H
DOUT
Write
L
H
X
L
DIN
NOTE:
1. This parameter is guaranteed and not tested.
NOTE:
X = Don’t Care, L = LOW, H = HIGH
V62C2184096 Rev. 1.5 June 2000
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V62C2184096
MOSEL VITELIC
DC Electrical Characteristics (over all temperature ranges, VCC = 2.3V–3.0V)
Symbol
Min.
Typ.
Max.
Units
VIL
Input LOW Voltage(1,2)
-0.5
—
0.4
V
VIH
Input HIGH Voltage(1)
2.0
—
VCC+0.3
V
IIL
Input Leakage Current
VCC = Max, VIN = 0V to VCC
—
—
1
µA
IOL
Output Leakage Current
VCC = Max, CE1 = VIH, VOUT = 0V to VCC
—
—
1
µA
VOL
Output LOW Voltage
VCC = Min, IOL = 2mA
—
—
0.4
V
VOH
Output HIGH Voltage
VCC = Min, IOH = -0.5mA
VCC–0.4
—
—
V
Comm.(3)
Ind.(3)
Units
f = fmax
35
40
mA
f = 1 MHz
4
5
L
0.5
1
LL
0.3
1
L
10
15
LL
5
7
Symbol
ICC1
ISB
ISB1
Parameter
Test Conditions
Parameter
Average Operating Current, CE1 = VIL, CE2 = VCC – 0.2, Output Open,
VCC = Max.
TTL Standby Current
CE1 ≥ VIH, CE2 ≤ VIL, VCC = Max., f = 0
CMOS Standby Current, CE1 ≥ VCC – 0.2V, CE2 ≤ 0.2V,
VIN ≥ VCC – 0.2V or VIN ≤ 0.2V, VCC = Max., f = 0
NOTES:
1. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included.
2. VIL (Min.) = -3.0V for pulse width < tRC/2.
3. Maximum value.
AC Test Conditions
Input Pulse Levels
AC Test Loads and Waveforms
0 to 2.0V
Input Rise and Fall Times
5 ns
Timing Reference Levels
1.1V
Output Load
CL*
TTL
see below
CL = 30pF + 1TTL Load
* Includes scope and jig capacitance
V62C2184096 Rev. 1.5 June 2000
4
mA
µA
V62C2184096
MOSEL VITELIC
Data Retention Characteristics
Symbol
Parameter
VDR
VCC for Data Retention
CE1 ≥ VCC – 0.2V, CE2 < 0.2V, VIN ≥ VCC – 0.2V,
or VIN ≤ 0.2V
ICCDR
Data Retention Current
CE1 ≥ VDR – 0.2V, CE2 < 0.2V, VIN ≥ VCC – 0.2V,
or VIN ≤ 0.2V, VDR = 1.2V
Com’l
Ind.
tCDR
tR
Min.
Typ.(2)
Max.
Units
1.2
—
3.0
V
L
—
1
3
µA
LL
—
0.5
2
L
—
—
5
LL
—
—
4
0
—
—
ns
—
—
ns
Power
Chip Deselect to Data Retention Time
Operation Recovery Time (see Retention Waveform)
tRC
NOTES:
1. tRC = Read Cycle Time
2. TA = +25°C.
Low VCC Data Retention Waveform (1) (CE1 Controlled)
Data Retention Mode
VCC
VDR ≥ 1.2V
2.3V
tCDR
CE1
2.0V
CE1 ≥ VCC – 0.2V
2.3V
tR
2.0V
Key to Switching Waveforms
WAVEFORM
V62C2184096 Rev. 1.5 June 2000
INPUTS
OUTPUTS
MUST BE
STEADY
WILL BE
STEADY
MAY CHANGE
FROM H TO L
WILL BE
CHANGING
FROM H TO L
MAY CHANGE
FROM L TO H
WILL BE
CHANGING
FROM L TO H
DON'T CARE:
ANY CHANGE
PERMITTED
CHANGING:
STATE
UNKNOWN
DOES NOT
APPLY
CENTER
LINE IS HIGH
IMPEDANCE
“OFF” STATE
5
(1)
V62C2184096
MOSEL VITELIC
AC Electrical Characteristics
(over all temperature ranges)
Read Cycle
Parameter
Name
70
Parameter
85
Min.
Max.
Min.
Max.
Unit
tRC
Read Cycle Time
70
—
85
—
ns
tAA
Address Access Time
—
70
—
85
ns
tACS1
Chip Enable Access Time
—
70
—
85
ns
tACS2
Chip Enable Access Time
—
70
—
85
ns
Output Enable to Output Valid
—
40
—
85
ns
tCLZ1
Chip Enable to Output in Low Z
10
—
10
—
ns
tCLZ2
Chip Enable to Output in Low Z
10
—
10
—
ns
tOLZ
Output Enable to Output in Low Z
5
—
10
—
ns
tCHZ
Chip Disable to Output in High Z
—
30
—
30
ns
tOHZ
Output Disable to Output in High Z
—
25
—
30
ns
tOH
Output Hold from Address Change
10
—
10
—
ns
tOE
Write Cycle
Parameter
Name
70
Parameter
85
Min.
Max.
Min.
Max.
Unit
tWC
Write Cycle Time
70
—
85
—
ns
tCW
Chip Enable to End of Write
60
—
70
—
ns
tAS
Address Setup Time
0
—
0
—
ns
tAW
Address Valid to End of Write
60
—
70
—
ns
tWP
Write Pulse Width
50
—
60
—
ns
tWR
Write Recovery Time
0
—
0
—
ns
tWHZ
Write to Output High-Z
—
20
—
25
ns
tDW
Data Setup to End of Write
35
—
40
—
ns
tDH
Data Hold from End of Write
0
—
0
—
ns
V62C2184096 Rev. 1.5 June 2000
6
V62C2184096
MOSEL VITELIC
Switching Waveforms (Read Cycle)
Read Cycle 1(1, 2, 6)
tRC
ADDRESS
tAA
OE
tOE
tOLZ
tOH
tOHZ(5)
I/O
Read Cycle 2(1, 2, 4, 6)
tRC
ADDRESS
tAA
tOH
tOH
I/O
Read Cycle 3(1, 3, 4, 6)
ADDRESS
CE1
tACS1
CE2
I/O
tACS2
tCHZ(5)
tCLZ1(5)
tCLZ2(5)
NOTES:
1. WE = VIH.
2. CE1 = VIL and CE2 = VIH.
3. Address valid prior to or coincident with CE1 transition LOW and/or CE2 transition HIGH.
4. OE = VIL.
5. Transition is measured ±500mV from steady state with CL = 5pF. This parameter is guaranteed and not 100% tested.
6. CE2 is offered on BGA package only.
V62C2184096 Rev. 1.5 June 2000
7
V62C2184096
MOSEL VITELIC
Switching Waveforms (Write Cycle)
Write Cycle 1 (WE Controlled)(4, 7)
tWC
ADDRESS
tWR(2)
(6)
tCW
CE1
tAW
CE2
tCW(6)
tAS
WE
tWP(1)
OUTPUT
tDW
tWHZ
tDH
INPUT
Write Cycle 2 (CE Controlled)(4, 7)
tWC
ADDRESS
tWR(2)
tCW(6)
(4)
CE1
tAW
tCW(6)
CE2
tAS
WE
OUTPUT
High-Z
tDW
tDH
(5)
INPUT
NOTES:
1. The internal write time of the memory is defined by the overlap of CE1 and CE2 active and WE low. All signals must be active to
initiate and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to
the second transition edge of the signal that terminates the write.
2. tWR is measured from the earlier of CE1 or WE going high, or CE2 going LOW at the end of the write cycle.
3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the outputs must not be applied.
4. OE = VIL or VIH. However it is recommended to keep OE at VIH during write cycle to avoid bus contention.
5. If CE1 is LOW and CE2 is HIGH during this period, I/O pins are in the output state. Then the data input signals of opposite phase
to the outputs must not be applied to them.
6. tCW is measured from CE1 going low or CE2 going HIGH to the end of write.
7. CE2 is offered on BGA package only.
V62C2184096 Rev. 1.5 June 2000
8
V62C2184096
MOSEL VITELIC
Package Diagrams
32-Pin TSOP (Standard)
Units in inches [mm]
0.787 ± 0.008
[19.99 ± 0.203]
Detail “A”
0.315 TYP.
(0.319 MAX.)
0.010 [.254]
8.00 TYP.
(8.10 MAX.)
0.024 ± 0.004
[0.610 ± 0.102]
0.724 TYP. (0.728 MAX.)
[18.39 TYP. (18.49 MAX)]
0.035 ± 0.002
[0.889 ± 0.051]
SEATING
PLANE
0.032 [0.813] TYP.
See Detail “A”
0.047 [1.19] MAX.
0.020 [0.508] MAX.
0.020 [0.508] SBC
0.005 MIN.
0.007 MAX.
0.003 [0.076] MAX.
0.127 MIN.
0.178 MAX.
0.009 ± 0.002
[0.229 ± 0.051]
36 Ball—8x10 BGA
D
D1
e
6
E1
4
E
5
3
2
SYMBOL
UNIT.MM
A
1.05+0.15
A1
0.25±0.05
b
0.35±.0.05
c
0.30(TYP)
D
10.00±0.10
D1
5.25
E
8.00±0.10
E1
3.75
e
0.75TYP
aaa
0.10
1
A
B
C
D
E
F
H
b
SOLDER BALL
aaa
SIDE VIEW
V62C2184096 Rev. 1.5 June 2000
9
A1
C
A
BOTTOM VIEW
G
MOSEL VITELIC
WORLDWIDE OFFICES
V62C2184096
U.S.A.
TAIWAN
SINGAPORE
UK & IRELAND
3910 NORTH FIRST STREET
SAN JOSE, CA 95134
PHONE: 408-433-6000
FAX: 408-433-0952
7F, NO. 102
MIN-CHUAN E. ROAD, SEC. 3
TAIPEI
PHONE: 886-2-2545-1213
FAX: 886-2-2545-1209
10 ANSON ROAD #23-13
INTERNATIONAL PLAZA
SINGAPORE 079903
PHONE: 65-3231801
FAX: 65-3237013
NO 19 LI HSIN RD.
SCIENCE BASED IND. PARK
HSIN CHU, TAIWAN, R.O.C.
PHONE: 886-3-579-5888
FAX: 886-3-566-5888
JAPAN
SUITE 50, GROVEWOOD
BUSINESS CENTRE
STRATHCLYDE BUSINESS
PARK
BELLSHILL, LANARKSHIRE,
SCOTLAND, ML4 3NQ
PHONE: 01698-748515
FAX: 01698-748516
HONG KONG
19 DAI FU STREET
TAIPO INDUSTRIAL ESTATE
TAIPO, NT, HONG KONG
PHONE: 852-2666-3307
FAX: 852-2770-8011
WBG MARIVE WEST 25F
6, NAKASE 2-CHOME
MIHAMA-KU, CHIBA-SHI
CHIBA 261-7125
PHONE: 81-43-299-6000
FAX: 81-43-299-6555
GERMANY
(CONTINENTAL
EUROPE & ISRAEL)
71083 HERRENBERG
BENZSTR. 32
GERMANY
PHONE: +49 7032 2796-0
FAX: +49 7032 2796 22
U.S. SALES OFFICES
NORTHWESTERN
SOUTHWESTERN
3910 NORTH FIRST STREET
SAN JOSE, CA 95134
PHONE: 408-433-6000
FAX: 408-433-0952
302 N. EL CAMINO REAL #200
SAN CLEMENTE, CA 92672
PHONE: 949-361-7873
FAX: 949-361-7807
© Copyright 2000, MOSEL VITELIC Inc.
The information in this document is subject to change without
notice.
MOSEL VITELIC makes no commitment to update or keep current the information contained in this document. No part of this
document may be copied or reproduced in any form or by any
means without the prior written consent of MOSEL-VITELIC.
MOSEL VITELIC
CENTRAL,
NORTHEASTERN &
SOUTHEASTERN
604 FIELDWOOD CIRCLE
RICHARDSON, TX 75081
PHONE: 972-690-1402
FAX: 972-690-0341
6/00
Printed in U.S.A.
MOSEL VITELIC subjects its products to normal quality control
sampling techniques which are intended to provide an assurance
of high quality products suitable for usual commercial applications. MOSEL VITELIC does not do testing appropriate to provide
100% product quality assurance and does not assume any liability for consequential or incidental arising from any use of its products. If such products are to be used in applications in which
personal injury might occur from failure, purchaser must do its
own quality assurance testing appropriate to such applications.
3910 N. First Street, San Jose, CA 95134-1501 Ph: (408) 433-6000 Fax: (408) 433-0952 Tlx: 371-9461