MOSEL V61C51161024

MOSEL VITELIC
PRELIMINARY
V61C51161024
64K x 16 HIGH SPEED
STATIC RAM
Features
Description
■
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The V61C51161024 is a 1,048,576-bit static
random-access memory organized as 65,536
words by 16 bits. Inputs and three-state outputs are
TTL compatible and allow for direct interfacing with
common system bus structures.
High-speed: 10, 12, 15 ns
All inputs and outputs directly TTL compatible
Three state outputs
Byte Control Pins
Single 5V ± 10% Power Supply
Packages
– 44-pin TSOP (Standard)
– 44-pin 400 mil SOJ
Functional Block Diagram
A1
VCC
Row
Decoder
A7
GND
Memory Array
A8
A9
I/O0
Column I/O
Input
Data
Circuit
Column Decoder
I/O15
A0
UBE
LBE
OE
WE
CE
A10
A15
Control
Circuit
6151161024-01
Device Usage Chart
Operating
Temperature
Range
0°C to 70 °C
V61C51161024 Rev. 1.0 July 1998
Package Outline
Access Time (ns)
T
K
10
12
15
Temperature
Mark
•
•
•
•
•
Blank
1
V61C51161024
MOSEL VITELIC
Pin Descriptions
UBE, LEB Byte Enable
Active low inputs. These inputs are used to enable
the upper or lower data byte.
A0–A15
Address Inputs
These 16 address inputs select one of the 64K x 16
bit segments in the RAM.
WE
Write Enable Input
The write enable input is active LOW and controls
read and write operations. With the chip enabled,
when WE is HIGH and OE is LOW, output data will
be present at the I/O pins; when WE is LOW and
OE is HIGH, the data present on the I/O pins will be
written into the selected memory locations.
CE
Chip Enable Input
CE is active LOW. It must be active to read from or
write to the device. If chip enable is not active, the
device is deselected and is in a standby power
mode. The I/O pins will be in the high-impedance
state when deselected.
I/O0–I/O15 Data Input and Data Output Ports
These 16 bidirectional ports are used to read data
from and write data into the RAM.
OE
Output Enable Input
The output enable input is active LOW. When OE
is Low with CE Low and WE High, data will be presented on the I/O pins. The I/O pins will be in the
high impedance state when OE is High.
VCC
Power Supply
GND
Ground
Pin Configurations (Top View)
44-Pin SOJ
44-Pin TSOP-II (Standard)
A4
1
44
A5
A3
2
43
A6
A2
3
42
A7
A1
4
41
OE
A0
5
40
UBE
CE
6
39
LBE
I/O0
7
38
I/O15
I/O1
8
37
I/O14
I/O2
9
36
I/O13
I/O3
10
35
I/O12
VCC
11
34
GND
GND
12
33
VCC
I/O4
13
32
I/O11
I/O5
14
31
I/O10
I/O6
15
30
I/O9
I/O7
16
29
I/O8
WE
17
28
NC
A15
18
27
A8
A14
19
26
A9
A13
20
25
A10
A12
21
24
A11
NC
22
23
NC
A4
A3
A2
A1
A0
CE
I/O0
I/O1
I/O2
I/O3
VCC
GND
I/O4
I/O5
I/O6
I/O7
WE
A15
A14
A13
A12
NC
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
6151161024-03
6151161024-02
V61C51161024 Rev. 1.0 July 1998
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
2
A5
A6
A7
OE
UBE
LBE
I/O15
I/O14
I/O13
I/O12
GND
VCC
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
NC
V61C51161024
MOSEL VITELIC
Part Number Information
V
61
C
51
16
1024
–
MOSEL-VITELIC
TEMP.
SRAM
FAMILY
OPERATING
VOLTAGE
DENSITY
SPEED
PKG
1024K
61 = HIGH SPEED
C = CMOS PROCESS
T = TSOP STANDARD
K = 400 mil SOJ
10 ns
12 ns
15 ns
PWR.
BLANK = 0¡C to 70¡C
51 = 5V
ORGANIZATION
BLANK = STANDARD POWER
6151161024-04
16 = 16-bit
Absolute Maximum Ratings (1)
Symbol
Parameter
VCC
Supply Voltage
Commercial
Units
-0.5 to +7
V
VIN
VDQ
Input Voltage
-0.5 to +7
V
Input/Output Voltage Applied
VCC + 0.5
V
TBIAS
TSTG
Temperature Under Bias
-10 to +85
°C
Storage Temperature
-65 to +150
°C
NOTE:
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Capacitance* TA = 25°C, f = 1.0MHz
Symbol
Parameter
Conditions
CIN
Input Capacitance
COUT
Output Capacitance
Max.
Unit
VIN = 0V
6
pF
VI/O = 0V
8
pF
NOTE:
1. This parameter is guaranteed by design and not tested.
Truth Table
Mode
CE
OE
WE
UBE
LBE
I/O8-15
Operation
I/O0-7
Operation
Standby
H
X
X
X
X
High Z
High Z
Output Disable
L
X
X
H
H
High Z
High Z
Output Disable
L
H
H
X
X
High Z
High Z
Read
L
L
H
L
L
DOUT
DOUT
Read
L
L
H
L
H
DOUT
High Z
Read
L
L
H
H
L
High Z
DOUT
Write
L
X
L
L
L
DIN
DIN
Write
L
X
L
L
H
DIN
High Z
Write
L
X
L
H
L
High Z
DIN
NOTE:
X = Don’t Care, L = LOW, H = HIGH
V61C51161024 Rev. 1.0 July 1998
3
V61C51161024
MOSEL VITELIC
DC Electrical Characteristics (over all temperature ranges, VCC = 5V ± 10%)
-10
Symbol
Parameter
Test Conditions
IIL
Input Leakage Current
IOL
-12
-15
Min.
Max.
Min.
Max.
Min.
Max.
Units
VCC = MAX, VIN = GND to VCC
—
5
—
5
—
5
mA
Output Leakage Current
CE = VIH, VCC = Max,
VOUT = GND to VCC
—
5
—
5
—
5
mA
ICC
Operating Power Supply
Current
CE = VIL, IOUT = 0, f = fmax
—
220
—
210
—
200
mA
ISB
Standby Power Supply
Current (TTL Level)
CE = VIH, f = fmax
—
60
—
50
—
40
mA
ISB1
Standby Power Supply
Current (CMOS Level)
CE ³ VCC – 0.2V, f = 0, VIN £ 0.2V
or VIN > VCC – 0.2V
—
5.0
—
5.0
—
5.0
mA
VOL
Output Low Voltage
IOL = 8mA
—
0.4
—
0.4
—
0.4
V
VOH
Output High Voltage
IOH = -4mA
2.4
—
2.4
—
2.4
—
V
NOTES:
1. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included.
2. VIL (Min.) = -3.0V for pulse width < 20ns.
3. fMAX = 1/tRC.
4. Maximum values.
AC Test Conditions
AC Test Loads and Waveforms
Input Pulse Levels
0 to 3V
Input Rise and Fall Times
3 ns
Timing Reference Levels
1.5V
+5V
480 ½
I/O Pins
Output Load
see below
255 ½
CL = 30 pF*
Key to Switching Waveforms
WAVEFORM
INPUTS
OUTPUTS
MUST BE
STEADY
WILL BE
STEADY
MAY CHANGE
FROM H TO L
WILL BE
CHANGING
FROM H TO L
MAY CHANGE
FROM L TO H
WILL BE
CHANGING
FROM L TO H
DON'T CARE:
ANY CHANGE
PERMITTED
CHANGING:
STATE
UNKNOWN
DOES NOT
APPLY
CENTER
LINE IS HIGH
IMPEDANCE
“OFF” STATE
V61C51161024 Rev. 1.0 July 1998
+5V
480 ½
I/O Pins
255 ½
CL = 5pF*
for tCLZ, tCHZ, tOLZ, tWHZ, tOW, and tOHZ
* Includes scope and jig capacitance
6151161024-05
4
V61C51161024
MOSEL VITELIC
AC Electrical Characteristics
(over all temperature ranges)
Read Cycle
-10
Parameter
Name
Parameter
-12
-15
Min.
Max.
Min.
Max.
Min.
Max.
Unit
tRC
Read Cycle Time
10
—
12
—
15
—
ns
tAA
Address Access Time
—
10
—
12
—
15
ns
tACS
Chip Enable Access Time
—
10
—
12
—
15
ns
tBA
UBE, LBE Access Time
—
5
—
6
—
7
ns
tOE
Output Enable to Output Valid
—
5
—
6
—
7
ns
tCLZ
Chip Enable to Output in Low Z
0
—
0
—
0
—
ns
tBLZ
UBE, LBE to Output in Low Z
0
—
0
—
0
—
ns
tOLZ
Output Enable to Output in Low Z
0
—
0
—
0
—
ns
tCHZ
Chip Disable to Output in High Z
0
5
0
6
0
7
ns
tOHZ
Output Disable to Output in High Z
0
5
0
6
0
7
ns
tBHZ
UBE, LBE to Output in High Z
0
5
0
6
0
7
ns
tOH
Output Hold from Address Change
2
—
3
—
3
—
ns
Write Cycle
-10
Parameter
Name
Parameter
-12
-15
Min.
Max.
Min.
Max.
Min.
Max.
Unit
tWC
Write Cycle Time
10
—
12
—
15
—
ns
tCW
Chip Enable to End of Write
7
—
8
—
10
—
ns
tAS
Address Setup Time
0
—
0
—
0
—
ns
tAW
Address Valid to End of Write
7
—
8
—
10
—
ns
tWP
Write Pulse Width
7
—
8
—
10
—
ns
tWR
Write Recovery Time
0
—
0
—
0
—
ns
tWHZ
Write to Output High-Z
0
5
0
6
0
7
ns
tWLZ
Write to Output Low Z
3
—
3
—
5
—
ns
tDW
Data Setup to End of Write
5
—
6
—
7
—
ns
tDH
Data Hold from End of Write
0
—
0
—
0
—
ns
tBW
UBE, LBE to End of Write
7
—
8
—
10
—
ns
V61C51161024 Rev. 1.0 July 1998
5
V61C51161024
MOSEL VITELIC
Switching Waveforms (Read Cycle)
Read Cycle 1(1, 2)
tRC
ADDRESS
tAA
OE
tOE
tOLZ
tOHZ(5)
tBHZ
tBLZ
UBE, LBE
tBA
I/O
51161024-07
Read Cycle 2(1, 2, 4)
tRC
ADDRESS
tOH
tAA
tOH
I/O
51161024-08
Read Cycle 3(1, 3, 4)
ADDRESS
tACS
CE
tCLZ(5)
tCHZ(5)
I/O
51161024-09
NOTES:
1. WE = VIH.
2. CE1 = VIL.
3. Address valid prior to or coincident with CE transition LOW.
4. OE = VIL.
5. Transition is measured ±500mV from steady state with CL = 5pF. This parameter is guaranteed and not 100% tested.
6. UBE = VIL, LBE = VIL.
V61C51161024 Rev. 1.0 July 1998
6
V61C51161024
MOSEL VITELIC
Switching Waveforms (Write Cycle)
Write Cycle 1 (WE Controlled)(4)
tWC
ADDRESS
tWR(2)
tCW(6)
CE
tAW
tAS
WE
tBW
UBE, LBE
tWP(1)
OUTPUT
tWHZ(3)
tDW
tDH
INPUT
51161024-10
Write Cycle 2 (CE Controlled)(4)
tWC
ADDRESS
tAS
tWR(2)
tCW(6)
CE
tAW
WE
tBW
UBE, LBE
OUTPUT
Hi-Z
tDW
tDH
(5)
INPUT
51161024-11
NOTES:
1. The internal write time of the memory is defined by the overlap of CE active and WE low. All signals must be active to initiate and
any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second
transition edge of the signal that terminates the write.
2. tWR is measured from the earlier of CE or WE going high.
3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the outputs must not be applied.
4. OE = VIL or VIH. However it is recommended to keep OE at VIH during write cycle to avoid bus contention.
5. If CE is LOW during this period, I/O pins are in the output state. Then the data input signals of opposite phase to the outputs must
not be applied to them.
6. tCW is measured from CE going low to the end of write.
V61C51161024 Rev. 1.0 July 1998
7
V61C51161024
MOSEL VITELIC
Package Diagrams
44-pin 400 mil TSOP-II
+0.004
0.006 -0.002
+0.01
0.15 -0.05
23
1
22
0.020 ± 0.006
[0.50 ± .019]
0.400
[10.16]
0.463 ± 0.008
[11.76 ± 0.20]
44
0¡–5¡
0.741[18.81] MAX
0.725 ± 0.004
[18.41 ± 0.10]
0.047 [1.20] MAX
0.004 MAX
Unit in inches [mm]
0.032
[0.80]
V61C51161024 Rev. 1.0 July 1998
0.031
[0.80]
0.014 ± 0.004
[0.35 ± 0.10]
0.000 [0.0] MIN
8
V61C51161024
MOSEL VITELIC
Package Diagrams
44-pin 400 mil SOJ (450 mil pin-to-pin)
1.131+0.008 28.73 +0.2
-0.014
-0.36
22
0.31 [0.8] MIN
+.008
–.007
[2.3±0.2]
0.091
0.102 [2.6]
+.006
–.007
[1.03 ± 0.15]
0.041
0.029
[0.74]
0.138 ± 0.008
[3.5 ± 0.2]
1
0.400 [10.16]
23
0.440 ± 0.008
[11.18 ± 0.20]
Unit in inches [mm]
44
+0.004
-0.002
0.20 +0.10
-0.05
0.008
0.050
[1.27]
0.004 [0.10]
V61C51161024 Rev. 1.0 July 1998
0.005 [0.12] M
0.016+0.004
–0.005
[0.40 ± 0.10]
9
0.370 ± 0.008
[9.4 ± 0.20]
0.033
[0.85]
MOSEL VITELIC
WORLDWIDE OFFICES
V61C51161024
U.S.A.
TAIWAN
JAPAN
3910 NORTH FIRST STREET
SAN JOSE, CA 95134
PHONE: 408-433-6000
FAX: 408-433-0185
7F, NO. 102
MIN-CHUAN E. ROAD, SEC. 3
TAIPEI
PHONE: 886-2-2545-1213
FAX: 886-2-2545-1209
WBG MARINE WEST 25F
6, NAKASE 2-CHOME
MIHAMA-KU, CHIBA-SHI
CHIBA 261-71
PHONE: 81-43-299-6000
FAX: 81-43-299-6555
HONG KONG
19 DAI FU STREET
TAIPO INDUSTRIAL ESTATE
TAIPO, NT, HONG KONG
PHONE: 852-2665-4883
FAX: 852-2664-7535
1 CREATION ROAD I
SCIENCE BASED IND. PARK
HSIN CHU, TAIWAN, R.O.C.
PHONE: 886-3-578-3344
FAX: 886-3-579-2838
GERMANY
(CONTINENTAL
EUROPE & ISRAEL )
71083 HERRENBERG
BENZSTR. 32
GERMANY
PHONE: +49 7032 2796-0
FAX: +49 7032 2796 22
IRELAND & UK
BLOCK A UNIT 2
BROOMFIELD BUSINESS PARK
MALAHIDE
CO. DUBLIN, IRELAND
PHONE: +353 1 8038020
FAX: +353 1 8038049
U.S. SALES OFFICES
NORTHWESTERN
SOUTHWESTERN
CENTRAL & SOUTHEASTERN
3910 NORTH FIRST STREET
SAN JOSE, CA 95134
PHONE: 408-433-6000
FAX: 408-433-0185
SUITE 200
5150 E. PACIFIC COAST HWY.
LONG BEACH, CA 90804
PHONE: 562-498-3314
FAX: 562-597-2174
604 FIELDWOOD CIRCLE
RICHARDSON, TX 75081
PHONE: 972-690-1402
FAX: 972-690-0341
NORTHEASTERN
SUITE 436
20 TRAFALGAR SQUARE
NASHUA, NH 03063
PHONE: 603-889-4393
FAX: 603-889-9347
© Copyright 1997, MOSEL VITELIC Inc.
The information in this document is subject to change without
notice.
MOSEL VITELIC makes no commitment to update or keep current the information contained in this document. No part of this
document may be copied or reproduced in any form or by any
means without the prior written consent of MOSEL-VITELIC.
MOSEL VITELIC
7/98
Printed in U.S.A.
MOSEL VITELIC subjects its products to normal quality control
sampling techniques which are intended to provide an assurance
of high quality products suitable for usual commercial applications. MOSEL VITELIC does not do testing appropriate to provide
100% product quality assurance and does not assume any liability for consequential or incidental arising from any use of its products. If such products are to be used in applications in which
personal injury might occur from failure, purchaser must do its
own quality assurance testing appropriate to such applications.
3910 N. First Street, San Jose, CA 95134-1501 Ph: (408) 433-6000 Fax: (408) 433-0952 Tlx: 371-9461