PRELIMINARY V62C5181024 128K X 8 STATIC RAM MOSEL VITELIC ■ Packages – 32-pin TSOP (Standard) – 32-pin 600 mil PDIP – 32-pin 440 mil SOP (525 mil pin-to-pin) Features ■ High-speed: 35, 70 ns ■ Ultra low DC operating current of 5mA (max.) TTL Standby: 5 mA (Max.) CMOS Standby: 60 µA (Max.) ■ Fully static operation ■ All inputs and outputs directly compatible ■ Three state outputs ■ Ultra low data retention current (VCC = 2V) ■ Single 5V ± 10% Power Supply Description The V62C5181024 is a 1,048,576-bit static random-access memory organized as 131,072 words by 8 bits. It is built with MOSEL VITELIC’s high performance CMOS process. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures. Functional Block Diagram A0 VCC Row Decoder GND 1024 x 1024 Memory Array A9 I/O0 Column I/O Input Data Circuit Column Decoder I/O7 A10 CE1 CE2 OE WE A16 Control Circuit 5181024 01 Device Usage Chart Operating Temperature Range T W P 35 70 L LL Temperature Mark 0°C to 70 °C • • • • • • • Blank –40°C to +85°C • • • • • • • I V62C5181024 Rev. 2.2 February 2000 Package Outline Access Time (ns) 1 Power V62C5181024 MOSEL VITELIC Pin Descriptions WE Write Enable Input An active LOW input, WE input controls read and write operations. When CE and WE inputs are both LOW, the data present on the I/O pins will be written into the selected memory location. A0–A16 Address Inputs These 17 address inputs select one of the 128K x 8 bit segments in the RAM. CE1, CE2 Chip Enable Inputs CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active to read from or write to the device. If either chip enable is not active, the device is deselected and is in a standby power mode. The I/O pins will be in the high-impedance state when deselected. I/O0–I/O7 Data Input and Data Output Ports These 8 bidirectional ports are used to read data from and write data into the RAM. VCC Power Supply GND Ground Output Enable Input OE The Output Enable input is active LOW. When OE is LOW with CE LOW and WE HIGH, data of the selected memory location will be available on the I/O pins. When OE is HIGH, the I/O pins will be in the high impedance state. Pin Configurations (Top View) 32-Pin DIP/SOP 32-Pin TSOP (Standard) NC 1 32 A16 2 31 A15 A14 3 30 CE2 A12 4 29 WE A7 5 28 A13 A6 6 27 A8 A5 7 26 A9 A4 8 25 A11 A3 9 24 OE A2 10 23 A10 A1 11 22 CE1 A0 12 21 I/O7 I/O0 13 20 I/O6 I/O1 14 19 I/O5 I/O2 15 18 I/O4 GND 16 17 I/O3 A11 A9 A8 A13 WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 VCC 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 5181024 03 5181024 02 V62C5181024 Rev. 2.2 February 2000 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 2 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3 V62C5181024 MOSEL VITELIC Part Number Information V MOSEL-VITELIC MANUFACTURED 62 C 51 8 1024 – TEMP. SRAM FAMILY OPERATING VOLTAGE PKG DENSITY PWR. 1024K 62 = STANDARD BLANK = 0°C to 70°C I = -40°C to +85°C SPEED 35 ns 70 ns C = CMOS PROCESS 51 = 5V T = TSOP STANDARD P = 600 mil PDIP W = 440 mil SOP (525 mil pin-to-pin) ORGANIZATION 5181024 05 L = LOW POWER LL = LOW LOW POWER 8 = 8-bit Absolute Maximum Ratings (1) Symbol Parameter Commercial Industrial Units VCC Supply Voltage -0.5 to +7 -0.5 to +7 V VN Input Voltage -0.5 to +7 -0.5 to +7 V VDQ Input/Output Voltage Applied VCC + 0.5 VCC + 0.5 V TBIAS Temperature Under Bias -10 to +125 -65 to +135 °C TSTG Storage Temperature -55 to +125 -65 to +150 °C NOTE: 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Capacitance* Truth Table TA = 25°C, f = 1.0MHz Symbol Parameter CIN Input Capacitance COUT Output Capacitance Max. Unit Mode CE1 CE2 OE WE I/O Operation VIN = 0V 6 pF Standby H X X X High Z VI/O = 0V 8 pF Standby X L X X High Z Output Disable L H H H High Z Read L H L H DOUT Write L H X L DIN Conditions NOTE: 1. This parameter is guaranteed and not tested. NOTE: X = Don’t Care, L = LOW, H = HIGH V62C5181024 Rev. 2.2 February 2000 3 V62C5181024 MOSEL VITELIC DC Electrical Characteristics (over all temperature ranges, VCC = 5V ± 10%) Symbol Min. Typ. Max. Units VIL Input LOW Voltage(1,2) -0.5 — 0.8 V VIH Input HIGH Voltage(1) 2.2 — 6 V IIL Input Leakage Current VCC = Max, VIN = 0V to VCC -5 — 5 µA IOL Output Leakage Current VCC = Max, CE1 = VIH, VOUT = 0V to VCC -5 — 5 µA VOL Output LOW Voltage VCC = Min, IOL = 2.1mA — — 0.4 V VOH Output HIGH Voltage VCC = Min, IOH = -1mA 2.4 — — V Power Com.(4) Ind.(4) Units L 4 6 mA LL 3 5 L 30 35 LL 25 30 35ns 80 90 70ns 75 85 L 4 6 LL 3 5 L 60 80 LL 50 60 Symbol ICC Parameter Test Conditions Parameter Operating Power Supply Current, CE1 = VIL, CE2 = VIH, Output Open, VCC = Max., f = 0 Read Write ICC1 Average Operating Current, CE1 = VIL, CE2 = VIH, Output Open, VCC = Max., f = fMAX(3) ISB TTL Standby Current CE1 ≥ VIH, CE2 ≤ VIL, VCC = Max. CMOS Standby Current, CE1 ≥ VCC – 0.2V, CE2 ≤ 0.2V, VIN ≥ VCC – 0.2V or VIN ≤ 0.2V, VCC = Max. ISB1 NOTES: 1. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included. 2. VIL (Min.) = -3.0V for pulse width < 20ns. 3. fMAX = 1/tRC. 4. Maximum values. AC Test Conditions Key to Switching Waveforms Input Pulse Levels 0 to 3V Input Rise and Fall Times 5 ns Timing Reference Levels 1.5V Output Load WAVEFORM see below INPUTS OUTPUTS MUST BE STEADY WILL BE STEADY MAY CHANGE FROM H TO L WILL BE CHANGING FROM H TO L MAY CHANGE FROM L TO H WILL BE CHANGING FROM L TO H DON'T CARE: ANY CHANGE PERMITTED CHANGING: STATE UNKNOWN DOES NOT APPLY CENTER LINE IS HIGH IMPEDANCE “OFF” STATE AC Test Loads and Waveforms +5V 1800 Ω I/O Pins 990 Ω CL = 30 pF* * Includes scope and jig capacitance 5181024 06 V62C5181024 Rev. 2.2 February 2000 4 mA mA µA V62C5181024 MOSEL VITELIC Data Retention Characteristics Symbol VDR ICCDR Parameter VCC for Data Retention tR Typ.(2) Max. Units 2.0 — 5.5 V L — 2 50 µA LL — 2 40 L — — 100 LL — 4 60 0 — — ns tRC(1) — — ns CE1 ≥ VCC – 0.2V, CE2 ≤ 0.2V, VIN ≥ VCC – 0.2V, or VIN ≤ 0.2V Data Retention Current CE1 ≥ VDR –0.2V, CE2 ≤ 0.2V, VIN ≥ VCC – 0.2V, or VIN ≤ 0.2V Com’l Ind. tCDR Min. Power Chip Deselect to Data Retention Time Operation Recovery Time (see Retention Waveform) NOTES: 1. tRC = Read Cycle Time 2. TA = +25°C. Low VCC Data Retention Waveform (1) (CE1 Controlled) Data Retention Mode VCC 4.5V VDR ≥ 2V tCDR CE1 2.2V CE1 ≥ VCC – 0.2V 4.5V tR 2.2V 5181024 07 Low VCC Data Retention Waveform (2) (CE2 Controlled) Data Retention Mode VCC 4.5V VDR ≥ 2V tCDR CE2 V62C5181024 Rev. 2.2 February 2000 2.2V 4.5V tR CE2 ≤ 0.2V 5 2.2V 5181024 08 V62C5181024 MOSEL VITELIC AC Electrical Characteristics (over all temperature ranges) Read Cycle Parameter Name -35 Parameter -45 -55 -70 Min. Max. Min. Max. Min. Max. Min. Max. Unit tRC Read Cycle Time 35 — 45 — 55 — 70 — ns tAA Address Access Time — 35 — 45 — 55 — 70 ns tACS1 Chip Enable Access Time — 35 — 45 — 55 — 70 ns tACS2 Chip Enable Access Time — 35 — 45 — 55 — 70 ns Output Enable to Output Valid — 10 — 20 — 25 — 35 ns tCLZ1 Chip Enable to Output in Low Z 3 — 5 — 7 — 10 — ns tCLZ2 Chip Enable to Output in Low Z 3 — 5 — 7 — 10 — ns tOLZ Output Enable to Output in Low Z 5 — 5 — 5 — 5 — ns tCHZ Chip Disable to Output in High Z 0 10 0 15 0 20 0 25 ns tOHZ Output Disable to Output in High Z 0 10 0 15 0 20 0 25 ns tOH Output Hold from Address Change 3 — 3 — 3 — 3 — ns tOE Write Cycle Parameter Name -35 Parameter -45 -55 -70 Min. Max. Min. Max. Min. Max. Min. Max. Unit tWC Write Cycle Time 35 — 45 — 55 — 70 — ns tCW1 Chip Enable to End of Write 25 — 35 — 50 — 60 — ns tCW2 Chip Enable to End of Write 25 — 35 — 50 — 60 — ns tAS Address Setup Time 0 — 0 — 0 — 0 — ns tAW Address Valid to End of Write 25 — 35 — 45 — 60 — ns tWP Write Pulse Width 25 — 35 — 40 — 50 — ns tWR Write Recovery Time 0 — 0 — 0 — 0 — ns tWHZ Write to Output High-Z 0 10 0 15 0 20 0 25 ns tWLZ Write to Output Low Z 3 — 5 — 5 — 5 — ns tDW Data Setup to End of Write 20 — 25 — 25 — 30 — ns tDH Data Hold from End of Write 0 — 0 — 0 — 0 — ns V62C5181024 Rev. 2.2 February 2000 6 V62C5181024 MOSEL VITELIC Switching Waveforms (Read Cycle) Read Cycle 1(1, 2) tRC ADDRESS tAA OE tOE tOLZ tOH tOHZ(5) I/O 5181024 09 Read Cycle 2(1, 2, 4) tRC ADDRESS tAA tOH tOH I/O 5181024 10 Read Cycle 3(1, 3, 4) ADDRESS CE1 tACS1 CE2 I/O tACS2 tCHZ(5) tCLZ1(5) tCLZ2(5) 5181024 11 NOTES: 1. WE = VIH. 2. CE1 = VIL and CE2 = VIH. 3. Address valid prior to or coincident with CE1 transition LOW and/or CE2 transition HIGH. 4. OE = VIL. 5. Transition is measured ±500mV from steady state with CL = 5pF. This parameter is guaranteed and not 100% tested. V62C5181024 Rev. 2.2 February 2000 7 V62C5181024 MOSEL VITELIC Switching Waveforms (Write Cycle) Write Cycle 1 (WE Controlled)(4) tWC ADDRESS tWR(2) (6) tCW CE1 tAW CE2 tCW(6) tAS WE tWP(1) OUTPUT tDW tWHZ tDH INPUT 5181024 12 Write Cycle 2 (CE Controlled)(4) tWC ADDRESS tWR(2) tCW(6) (4) CE1 tAW tCW(6) CE2 tAS WE OUTPUT High-Z tDW tDH (5) INPUT 5181024 13 NOTES: 1. The internal write time of the memory is defined by the overlap of CE1 and CE2 active and WE low. All signals must be active to initiate and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 2. tWR is measured from the earlier of CE1 or WE going high, or CE2 going LOW at the end of the write cycle. 3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 4. OE = VIL or VIH. However it is recommended to keep OE at VIH during write cycle to avoid bus contention. 5. If CE1 is LOW and CE2 is HIGH during this period, I/O pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 6. tCW is measured from CE1 going low or CE2 going HIGH to the end of write. V62C5181024 Rev. 2.2 February 2000 8 V62C5181024 MOSEL VITELIC Package Diagrams 32-Pin 600 mil Plastic DIP 1.660 MAX. [42.16 MAX.] 15° MAX INDEX-1 EJECTOR MARK 0.545–0.555 [13.84–14.10] 0.600 TYP [15.24 TYP] INDEX-2 +0.004 –0.0004 0.254 +0.102 –0.010 0.010 0.010 [0.254] MIN 0.050 [1.27] MAX 0.210 [5.33] MAX 0.120 [3.05] MIN 0.100 [2.54] TYP +0.012 .047 –0 +0.305 1.19 –0 +0.006 0.018 –0.002 +0.152 0.457 –0.051 Units in inches [mm] +0.012 –0 +0.305 0.813 –0 0.032 32-Pin 440 mil SOP (525 mil pin-to-pin) Units in inches [mm] 0–8° 0.822 [20.88] MAX. 0.556 ±0.012 [14.12 ± 0.305] 0.450 ±0.008 [11.43 ± 0.203] 0.525 [13.34] MAX. 0.031 ±0.008 [0.787 ±0.203] 0.018 ± 0.004 [0.457 ± 0.102] 0.050 [1.27] 0.008 0.108 ±0.008 [2.74 ± 0.203] 0.806 ±0.008 [20.47 ± 0.203] 0.098 [2.50] MAX 0.118 [3.00] MAX. 0.10 [2.54] MAX. 0.028 [0.711] V62C5181024 Rev. 2.2 February 2000 0.002 [0.051] MAX. 9 +0.004 –0.002 0.004 [0.102] MAX. V62C5181024 MOSEL VITELIC Package Diagrams (Cont’d) 32-Pin TSOP (Standard) Units in inches [mm] 0.787 ± 0.008 [19.99 ± 0.203] Detail “A” 0.315 TYP. (0.319 MAX.) 0.010 [.254] 8.00 TYP. (8.10 MAX.) 0.024 ± 0.004 [0.610 ± 0.102] 0.724 TYP. (0.728 MAX.) [18.39 TYP. (18.49 MAX)] 0.035 ± 0.002 [0.889 ± 0.051] SEATING PLANE See Detail “A” 0.032 [0.813] TYP. 0.020 [0.508] MAX. 0.020 [0.508] SBC 0.005 MIN. 0.007 MAX. 0.003 [0.076] MAX. 0.127 MIN. 0.178 MAX. V62C5181024 Rev. 2.2 February 2000 0.047 [1.19] MAX. 10 0.009 ± 0.002 [0.229 ± 0.051] V62C5181024 MOSEL VITELIC Notes V62C5181024 Rev. 2.2 February 2000 11 MOSEL VITELIC WORLDWIDE OFFICES V62C5181024 U.S.A. TAIWAN SINGAPORE UK & IRELAND 3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0952 7F, NO. 102 MIN-CHUAN E. ROAD, SEC. 3 TAIPEI PHONE: 886-2-2545-1213 FAX: 886-2-2545-1209 10 ANSON ROAD #23-13 INTERNATIONAL PLAZA SINGAPORE 079903 PHONE: 65-3231801 FAX: 65-3237013 NO 19 LI HSIN RD. SCIENCE BASED IND. PARK HSIN CHU, TAIWAN, R.O.C. PHONE: 886-3-579-5888 FAX: 886-3-566-5888 JAPAN SUITE 50, GROVEWOOD BUSINESS CENTRE STRATHCLYDE BUSINESS PARK BELLSHILL, LANARKSHIRE, SCOTLAND, ML4 3NQ PHONE: 01698-748515 FAX: 01698-748516 HONG KONG 19 DAI FU STREET TAIPO INDUSTRIAL ESTATE TAIPO, NT, HONG KONG PHONE: 852-2666-3307 FAX: 852-2770-8011 WBG MARIVE WEST 25F 6, NAKASE 2-CHOME MIHAMA-KU, CHIBA-SHI CHIBA 261-7125 PHONE: 81-43-299-6000 FAX: 81-43-299-6555 GERMANY (CONTINENTAL EUROPE & ISRAEL) 71083 HERRENBERG BENZSTR. 32 GERMANY PHONE: +49 7032 2796-0 FAX: +49 7032 2796 22 U.S. SALES OFFICES NORTHWESTERN SOUTHWESTERN 3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0952 302 N. EL CAMINO REAL #200 SAN CLEMENTE, CA 92672 PHONE: 949-361-7873 FAX: 949-361-7807 © Copyright 2000, MOSEL VITELIC Inc. The information in this document is subject to change without notice. MOSEL VITELIC makes no commitment to update or keep current the information contained in this document. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of MOSEL-VITELIC. MOSEL VITELIC CENTRAL, NORTHEASTERN & SOUTHEASTERN 604 FIELDWOOD CIRCLE RICHARDSON, TX 75081 PHONE: 972-690-1402 FAX: 972-690-0341 2/00 Printed in U.S.A. MOSEL VITELIC subjects its products to normal quality control sampling techniques which are intended to provide an assurance of high quality products suitable for usual commercial applications. MOSEL VITELIC does not do testing appropriate to provide 100% product quality assurance and does not assume any liability for consequential or incidental arising from any use of its products. If such products are to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications. 3910 N. First Street, San Jose, CA 95134-1501 Ph: (408) 433-6000 Fax: (408) 433-0952 Tlx: 371-9461