SN54AC10, SN74AC10 TRIPLE 3-INPUT POSITIVE-NAND GATES SCAS529B – AUGUST 1995 – REVISED SEPTEMBER 1996 D D EPIC (Enhanced-Performance Implanted CMOS) 1-µm Process Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages, Ceramic Chip Carriers (FK) and Flatpacks (W), and Standard Plastic (N) and Ceramic (J) DIPS SN54AC10 . . . J OR W PACKAGE SN74AC10 . . . D, DB, N, OR PW PACKAGE (TOP VIEW) 1A 1B 2A 2B 2C 2Y GND description The ’AC10 contain three independent 3-input NAND gates. The devices perform the Boolean function Y = A • B • C or Y = A + B + C in positive logic. C H H H L L X X H X L X H X X L H 1B 1C 2A 2B 2C 3A 3B 3C 1 12 4 11 5 10 6 9 7 8 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 1Y NC 3A NC 3B NC – No internal connection logic symbol† 1A 3 VCC 1C 1Y 3A 3B 3C 3Y 2Y GND NC 3Y 3C OUTPUT Y B 13 1B 1A NC VCC 1C 2A NC 2B NC 2C FUNCTION TABLE (each gate) A 14 2 SN54AC10 . . . FK PACKAGE (TOP VIEW) The SN54AC10 is characterized for operation over the full military temperature range of – 55°C to 125°C. The SN74AC10 is characterized for operation from – 40°C to 85°C. INPUTS 1 logic diagram, each gate (positive logic) & 12 2 1Y 13 3 6 4 2Y 1A 1B 1C 2A 2B 2C 5 8 11 3Y 10 3A 3B 3C 1 2 13 12 3 4 5 6 11 10 9 8 1Y 2Y 3Y 9 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, DB, J, N, PW, and W packages. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments Incorporated. Copyright 1996, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54AC10, SN74AC10 TRIPLE 3-INPUT POSITIVE-NAND GATES SCAS529B – AUGUST 1995 – REVISED SEPTEMBER 1996 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 200 mA Maximum power dissipation at TA = 55°C (in still air) (see Note 2): D package . . . . . . . . . . . . . . . . . . . 1.25 W DB package . . . . . . . . . . . . . . . . . . . 0.5 W N package . . . . . . . . . . . . . . . . . . . . 1.1 W PW package . . . . . . . . . . . . . . . . . . . 0.5 W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils, except for the N package, which has a trace length of zero. recommended operating conditions (see Note 3) VCC Supply voltage VIH High-level input voltage VCC = 3 V VCC = 4.5 V VCC = 5.5 V VCC = 3 V SN54AC10 SN74AC10 MIN MAX MIN MAX 2 6 2 6 2.1 2.1 3.15 3.15 3.85 3.85 VIL Low-level input voltage VI VO Input voltage 0 Output voltage 0 IOH High-level output current IOL ∆t /∆v VCC = 4.5 V VCC = 5.5 V Low-level output current 0 VCC VCC – 12 – 24 – 24 VCC = 5.5 V VCC = 3 V – 24 – 24 12 12 VCC = 4.5 V VCC = 5.5 V 24 24 24 24 • DALLAS, TEXAS 75265 V 1.65 0 – 12 Input transition rise or fall rate POST OFFICE BOX 655303 0.9 1.35 VCC = 3 V VCC = 4.5 V TA Operating free-air temperature NOTE 3: Unused inputs must be held high or low to prevent them from floating. 2 0.9 1.65 V V 1.35 VCC VCC UNIT V V mA mA 0 8 0 8 ns / V – 55 125 – 40 85 °C SN54AC10, SN74AC10 TRIPLE 3-INPUT POSITIVE-NAND GATES SCAS529B – AUGUST 1995 – REVISED SEPTEMBER 1996 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC IOH = – 50 µA IOH = – 24 mA IOH = – 50 mA† IOH = – 75 mA† SN54AC10 SN74AC10 MIN MIN MAX 2.9 2.99 2.9 2.9 4.5 V 4.4 4.99 4.4 4.4 5.5 V 5.4 5.49 5.4 5.4 3V 2.56 2.4 2.46 4.5 V 3.86 3.7 3.76 5.5 V 4.86 4.7 4.76 5.5 V 3.85 0.002 0.1 0.1 0.1 4.5 V 0.001 0.1 0.1 0.1 5.5 V 0.001 0.1 0.1 0.1 3V 0.36 0.5 0.44 4.5 V 0.36 0.5 0.44 5.5 V 0.36 0.5 0.44 IOL = 50 mA† IOL = 75 mA† 5.5 V II ICC VI = VCC or GND VI = VCC or GND, 5.5 V Ci VI = VCC or GND V 1.65 5.5 V IO = 0 UNIT V 3V IOL = 12 mA IOL = 24 mA MAX 3.85 5.5 V IOL = 50 µA VOL TA = 25°C TYP MAX 3V IOH = – 12 mA VOH MIN 1.65 5.5 V 5V ±0.1 ±1 ±1 µA 2 80 20 µA 2.6 pF † Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms. " switching characteristics over recommended operating free-air temperature range, VCC = 3.3 V 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) tPLH tPHL Any Y MIN TA = 25°C TYP MAX SN54AC10 SN74AC10 MIN MAX MIN MAX 1.5 6 9.5 1 11 1 10.5 1.5 5.5 8.5 1 10 1 10 UNIT ns " switching characteristics over recommended operating free-air temperature range, VCC = 5 V 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) tPLH tPHL Any Y MIN TA = 25°C TYP MAX SN54AC10 SN74AC10 MIN MAX MIN MAX 1.5 4.5 7 1 8.5 1 8 1.5 4 6 1 7 1 6.5 UNIT ns operating characteristics, VCC = 5 V, TA = 25°C PARAMETER Cpd Power dissipation capacitance POST OFFICE BOX 655303 TEST CONDITIONS TYP UNIT CL = 50 pF, f = 1 MHz 25 pF • DALLAS, TEXAS 75265 3 SN54AC10, SN74AC10 TRIPLE 3-INPUT POSITIVE-NAND GATES SCAS529B – AUGUST 1995 – REVISED SEPTEMBER 1996 PARAMETER MEASUREMENT INFORMATION TEST S1 tPLH/tPHL Open CL = 50 pF (see Note A) 500 Ω S1 Open 50% VCC 50 % VCC In-Phase Output 50% VCC Out-of-Phase Output LOAD CIRCUIT 50% VCC VOH 50% VCC VOL VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr C. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms 4 VOH 50% VCC VOL tPLH tPHL 500 Ω 0V tPHL tPLH 2 × VCC From Output Under Test VCC Input (see Note B) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 v 2.5 ns, tf v 2.5 ns. IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. 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