NEC MC-45D32CC721KFA-C80

PRELIMINARY DATA SHEET
MOS INTEGRATED CIRCUIT
MC-45D32CC721
32 M-WORD BY 72-BIT DDR SYNCHRONOUS DYNAMIC RAM MODULE
UNBUFFERED TYPE
Description
The MC-45D32CC721 is a 33,554,432 words by 72 bits DDR synchronous dynamic RAM module on which 18
pieces of 128M DDR SDRAM: µPD45D128842 are assembled.
These modules provide high density and large quantities of memory in a small space without utilizing the surfacemounting technology on the printed circuit board.
Decoupling capacitors are mounted on power supply line for noise reduction.
Features
• 33,554,432 words by 72 bits organization (ECC type)
• Clock frequency
Part number
/CAS latency
Clock frequency
Module type
(MAX.)
MC-45D32CC721KFA-C75
MC-45D32CC721KFA-C80
CL = 2.5
133 MHz
DDR SDRAM
CL = 2
100 MHz
Unbuffered DIMM
CL = 2.5
125 MHz
Design specification
CL = 2
100 MHz
Rev.0.9 compliant
• Fully Synchronous Dynamic RAM with all signals except DM, DQS and DQ referenced to a positive clock edge
• Double Data Rate interface
Differential CLK (/CLK) input
Data inputs and DM are synchronized with both edges of DQS
Data outputs and DQS are synchronized with a cross point of CLK and /CLK
• Quad internal banks operation
• Possible to assert random column address in every clock cycle
• Programmable Mode register set
/CAS latency (2, 2.5)
Burst length (2, 4, 8)
Wrap sequence (Sequential / Interleave)
• Automatic precharge and controlled precharge
• CBR (Auto) refresh and self refresh
• 2.5 V ± 0.2 V Power supply for VDD
• 2.5 V ± 0.2 V Power supply for VDDQ
• SSTL_2 compatible with all signals
• 4,096 refresh cycles / 64 ms
• Burst termination by Precharge command and Burst stop command
• 184-pin dual in-line memory module (Pin pitch = 1.27 mm)
• Unbuffered type
• Serial PD
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. M14900EJ1V0DS00 (1st edition)
Date Published June 2000 NS CP(K)
Printed in Japan
©
2000
MC-45D32CC721
Ordering Information
Part number
Clock frequency
(MAX.)
MC-45D32CC721KFA-C75
133 MHz
Package
184-pin Dual In-line Memory Module 18 pieces of µPD45D128842G5 (Rev. K)
(Socket Type)
MC-45D32CC721KFA-C80
125 MHz
Edge connector: Gold plated
31.75 mm height
2
Mounted devices
Preliminary Data Sheet M14900EJ1V0DS00
(10.16 mm (400) TSOP (II))
MC-45D32CC721
Pin Configuration
184-pin Dual In-line Memory Module Socket Type (Edge connector: Gold plated)
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
VSS
DQ4
DQ5
VDDQ
DM0/DQS9
DQ6
DQ7
VSS
NC
NC
NC
VDDQ
DQ12
DQ13
DM1/DQS10
VDD
DQ14
DQ15
NC
VDDQ
NC
DQ20
NC
VSS
DQ21
A11
DM2/DQS11
VDD
DQ22
A8
DQ23
VSS
A6
DQ28
DQ29
VDDQ
DM3/DQS12
A3
DQ30
VSS
DQ31
CB4
CB5
VDDQ
CK0
/CK0
VSS
DM8/DQS17
A10
CB6
VDDQ
CB7
VREF
DQ0
VSS
DQ1
DQS0
DQ2
VDD
DQ3
NC
/RESET
VSS
DQ8
DQ9
DQS1
VDDQ
CK1
/CK1
VSS
DQ10
DQ11
CKE0
VDDQ
DQ16
DQ17
DQS2
VSS
A9
DQ18
A7
VDDQ
DQ19
A5
DQ24
VSS
DQ25
DQS3
A4
VDD
DQ26
DQ27
A2
VSS
A1
CB0
CB1
VDD
DQS8
A0
CB2
VSS
CB3
BA1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
VSS
DQ36
DQ37
VDD
DM4/DQS13
DQ38
DQ39
VSS
DQ44
/RAS
DQ45
VDDQ
/S0
/S1
DM5/DQS14
VSS
DQ46
DQ47
NC
VDDQ
DQ52
DQ53
NC
VDD
DM6/DQS15
DQ54
DQ55
VDDQ
NC
DQ60
DQ61
VSS
DM7/DQS16
DQ62
DQ63
VDDQ
SA0
SA1
SA2
VDDSPD
DQ32
VDDQ
DQ33
DQS4
DQ34
VSS
BA0
DQ35
DQ40
VDDQ
/WE
DQ41
/CAS
VSS
DQS5
DQ42
DQ43
VDD
NC
DQ48
DQ49
VSS
CK2
/CK2
VDDQ
DQS6
DQ50
DQ51
VSS
VDDID
DQ56
DQ57
VDD
DQS7
DQ58
DQ59
VSS
NC
SDA
SCL
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
/xxx indicates active low signal.
A0 - A11
: Address Inputs
[Row: A0 - A11, Column: A0 - A9]
BA0, BA1
: SDRAM Bank Select
DQ0 - DQ63, CB0 - CB7 : Data Inputs/Outputs
CK0 - CK2
: Clock Input
(positive line of differential pair)
/CK0 - /CK2
: Clock Input
(negative line of differential pair)
CKE0
: Clock Enable Input
/S0, /S1
: Chip Select Input
/RAS
: Row Address Strobe
/CAS
: Column Address Strobe
/WE
: Write Enable
DQS0 - DQS8
: Low Data Strobe
DM(0 - 8) / DQS(9 - 17) : Low Data Masks /
High Data Strobe
SA0 - SA2
: Address Input for EEPROM
SDA
: Serial Data I/O for PD
SCL
: Clock Input for PD
VDD
: Power Supply
VSS
: Ground
VDDID
: VDD Identification Flag
VDDQ
: Power Supply for DQ and DQS
VREF
: Input Reference
VDDSPD
: Power supply for EEPROM
NC
: No Connection
/RESET
: Reset Input
Preliminary Data Sheet M14900EJ1V0DS00
3
MC-45D32CC721
Block Diagram
/S1
/S0
DQS0
DM0/DQS9
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
DQS4
DM4/DQS13
DQ 7 DM /S
DQ 6
D0
DQ 1
DQ 0
DQ 5
DQ 4
DQ 3
DQ 2
DQS
DQ 0 DM /S
DQ 1
D9
DQ 6
DQ 7
DQ 2
DQ 3
DQ 4
DQ 5
DQS
DQ 36
DQ 37
DQ 38
DQ 39
DQS1
DM1/DQS10
DQ 8
DQ 9
DQ 10
DQ 11
DQ 12
DQ 13
DQ 14
DQ 15
DQ 20
DQ 21
DQ 22
DQ 23
DQ 7 DM /S
DQ 6
D1
DQ 1
DQ 0
DQ 5
DQ 4
DQ 3
DQ 2
DQS
DQ 0 DM /S
DQ 1
D10
DQ 6
DQ 7
DQ 2
DQ 3
DQ 4
DQ 5
DQS
DQ 28
DQ 29
DQ 30
DQ 31
DQ 40
DQ 41
DQ 42
DQ 43
DQ 44
DQ 45
DQ 46
DQ 47
DQS
DQ 0 DM /S
DQ 1
D13
DQ 6
DQ 7
DQ 2
DQ 3
DQ 4
DQ 5
DQS
DQ 7 DM /S
DQ 6
D5
DQ 1
DQ 0
DQ 5
DQ 4
DQ 3
DQ 2
DQS
DQ 0 DM /S
DQ 1
D14
DQ 6
DQ 7
DQ 2
DQ 3
DQ 4
DQ 5
DQS
DQ 7 DM /S
DQ 6
D6
DQ 1
DQ 0
DQ 5
DQ 4
DQ 3
DQ 2
DQS
DQ 0 DM /S
DQ 1
D15
DQ 6
DQ 7
DQ 2
DQ 3
DQ 4
DQ 5
DQS
DQ 7 DM /S
DQ 6
D7
DQ 1
DQ 0
DQ 5
DQ 4
DQ 3
DQ 2
DQS
DQ 0 DM /S
DQ 1
D16
DQ 6
DQ 7
DQ 2
DQ 3
DQ 4
DQ 5
DQS
DQS6
DM6/DQS15
DQ 7 DM /S
DQ 6
D2
DQ 1
DQ 0
DQ 5
DQ 4
DQ 3
DQ 2
DQS
DQ 0 DM /S
DQ 1
D11
DQ 6
DQ 7
DQ 2
DQ 3
DQ 4
DQ 5
DQS
DQ 48
DQ 49
DQ 50
DQ 51
DQ 52
DQ 53
DQ 54
DQ 55
DQS3
DM3/DQS12
DQ 24
DQ 25
DQ 26
DQ 27
DQ 7 DM /S
DQ 6
D4
DQ 1
DQ 0
DQ 5
DQ 4
DQ 3
DQ 2
DQS5
DM5/DQS14
DQS2
DM2/DQS11
DQ 16
DQ 17
DQ 18
DQ 19
DQ 32
DQ 33
DQ 34
DQ 35
DQS7
DM7/DQS16
DQ 7 DM /S
DQ 6
D3
DQ 1
DQ 0
DQ 5
DQ 4
DQ 3
DQ 2
DQS
DQ 7 DM /S
DQ 6
D8
DQ 1
DQ 0
DQ 5
DQ 4
DQ 3
DQ 2
DQS
DQ 0 DM /S
DQ 1
D12
DQ 6
DQ 7
DQ 2
DQ 3
DQ 4
DQ 5
DQS
DQ 0 DM /S
DQ 1
D17
DQ 6
DQ 7
DQ 2
DQ 3
DQ 4
DQ 5
DQS
DQ 56
DQ 57
DQ 58
DQ 59
DQ 60
DQ 61
DQ 62
DQ 63
DQS8
DM8/DQS17
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
SERIAL PD
BA0, BA1
BA0, BA1 : SDRAMs D0 - D17
A0 - A11
A0 - A11
: SDRAMs D0 - D17
/RAS
/RAS
: SDRAMs D0 - D17
/CAS
/CAS
: SDRAMs D0 - D17
SDA
SCL
A0
A2
SA0 SA1 SA2
VDDQ
D0 - D17
VDD
D0 - D17
V REF
D0 - D17
D0 - D17
CKE0
CKE0
: SDRAMs D0 - D17
VSS
/WE
/WE
: SDRAMs D0 - D17
VDDID
CK0, /CK0
CK, /CK
: SDRAMs D3, D4, D8, D12, D13, D17
CK1, /CK1
CK, /CK
: SDRAMs D0, D1, D2, D9, D10, D11
CK2, /CK2
CK, /CK
: SDRAMs D5, D6, D7, D14, D15, D16
Remarks 1. The value of all resistors of DQs, DQSs, DM/DQSs is 22 Ω.
2. D0 – D17: µPD45D128842 (4M words × 8 bits × 4 banks)
4
A1
Preliminary Data Sheet M14900EJ1V0DS00
MC-45D32CC721
Electrical Specifications
• All voltages are referenced to VSS (GND).
• After power up, wait more than 1 ms and then, execute Power on sequence and CBR (auto) refresh before
proper device operation is achieved.
Absolute Maximum Ratings
Parameter
Rating
Unit
VDD, VDDQ
–0.5 to +3.6
V
Voltage on input pin relative to VSS
VT
–0.5 to +3.6
V
Short circuit output current
IO
50
mA
Power dissipation
PD
12
W
Storage temperature
Tstg
–55 to +125
°C
Voltage on power supply pin relative to VSS
Caution
Symbol
Condition
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
MIN.
TYP.
MAX.
Unit
VDD
2.3
2.5
2.7
V
Supply voltage for DQ, DQS
VDDQ
2.3
2.5
2.7
V
Input reference voltage
VREF
0.49 × VDDQ
0.51 × VDDQ
V
Termination voltage
VTT
VREF − 0.04
VREF + 0.04
V
High level dc input voltage
VIH (DC)
VREF + 0.15
VDD + 0.3
V
Low level dc input voltage
VIL (DC)
−0.3
VREF − 0.15
V
Input differential voltage (CLK and /CLK)
VID (DC)
0.36
VDDQ + 0.6
V
Input crossing point voltage (CLK and /CLK)
VIX
0.5 × VDDQ–0.2
0.5 × VDDQ+0.2
V
Operating ambient temperature
TA
0
70
°C
Supply voltage
Symbol
Condition
VREF
Capacitance (TA = 25 °C, f = 100 MHz)
Parameter
Input capacitance
Data input/output capacitance
Symbol
Test condition
MIN.
TYP.
MAX.
Unit
pF
CI1
A0 - A11, BA0, BA1, /RAS,
/CAS, /WE
TBD
TBD
CI2
CK0 - CK2, /CK0 - /CK2
TBD
TBD
CI3
CKE0
TBD
TBD
CI4
/S0, /S1
TBD
TBD
DM(0-8)/DQS(9-17),
TBD
TBD
TBD
TBD
CI/O1
pF
DQS0 - DQS8
CI/O2
DQ0 - DQ63, CB0 - CB7
Preliminary Data Sheet M14900EJ1V0DS00
5
MC-45D32CC721
DC Characteristics 1 (Recommended Operating Conditions unless otherwise noted)
Parameter
Symbol
Operating current
(ACT-PRE)
IDD0
Operating current
IDD1
(ACT-READ-PRE)
Test condition
/CAS Grade
latency
tRC = tRC(MIN.), tCK = tCK (MIN.), One bank,
Active-precharge, DQ, DM and DQS
inputs changing twice per clock cycle,
Address and control inputs changing
once per clock cycle
tRC = tRC(MIN.), tCK = tCK (MIN.), One CL = 2
bank, Active-read-precharge,
IO = 0 mA, Burst length = 2,
CL = 2.5
Address and control inputs
changing once per clock cycle
MIN.
MAX.
Unit
-C75
TBD
mA
-C80
TBD
-C75
TBD
-C80
TBD
-C75
TBD
-C80
TBD
mA
Notes
1
Precharge power down
standby current
IDD2P
CKE ≤ VIL(MAX.), tCK = tCK(MIN.),
All banks idle, Power down mode
Idle standby current
IDD2N
CKE ≥ VIH(MIN.), tCK = tCK(MIN.), /CS ≥ VIH(MIN.),
All banks idle, Address and other control inputs
changing once per clock cycle
TBD
mA
Active power down
standby current
IDD3P
CKE ≤ VIL(MAX.), tCK = tCK(MIN.), One bank active,
Power down mode
TBD
mA
Active standby current
IDD3N
/CS ≥ VIH(MIN.), CKE ≥ VIH(MIN.), tCK = tCK(MIN.), tRC =
tRAS(MAX.), One bank, Active-precharge, DQ, DM
and DQS inputs changing twice per clock
cycle, Address and other control inputs
changing once per clock cycle
TBD
mA
Operating current
IDD4R
tCK = tCK(MIN.), Continuous burst
read, Burst length = 2, IO =
0mA, One bank active,
Address and control inputs
changing once per clock cycle
-C75
TBD
mA
2
-C80
TBD
mA
2
(Burst read)
Operating current
IDD4W
(Burst write)
CBR (auto) refresh current
Self refresh current
IDD5
IDD6
tCK = tCK(MIN.), Continuous burst
write, Burst length = 2, One
bank active, Address and
control inputs changing once
per clock cycle
CL = 2
TBD
mA
CL = 2.5 -C75
TBD
-C80
TBD
-C75
TBD
CL = 2
-C80
TBD
CL = 2.5 -C75
TBD
-C80
TBD
-C75
TBD
-C80
TBD
tRFC = tRFC(MIN.)
CKE ≤ 0.2 V
TBD
mA
mA
Notes 1. IDD1 depends on output loading and cycle rates. Specified values are obtained with the output open.
2. IDD4R and IDD4W depend on output loading and cycle rates. Specified values are obtained with the output
open.
DC Characteristics 2 (Recommended Operating Conditions unless otherwise noted)
Parameter
Symbol
Test condition
MIN.
MAX.
Unit Notes
Input leakage current
II(L)
VI = 0 to 3.6 V, all other pins not under test = 0 V
TBD
TBD
µA
Output leakage current
IO(L)
DOUT is disabled, VO = 0 to VDDQ + 0.3 V
TBD
TBD
µA
Output high current
IOH
VOUT = VDDQ − 0.43 V
TBD
mA
Output low current
IOL
VOUT = 0.35 V
TBD
mA
6
Preliminary Data Sheet M14900EJ1V0DS00
MC-45D32CC721
AC Characteristics (Recommended Operating Conditions unless otherwise noted)
Test Conditions
Parameter
Symbol
Value
Unit
Input Reference voltage (Input timing measurement reference level)
VREF
VDDQ x 0.5
V
Termination voltage (Output timing measurement reference level)
VTT
VREF
V
High level ac input voltage
VIH(ac)
VREF + 0.31
V
Low level ac input voltage
VIL(ac)
VREF − 0.31
V
Input differential voltage (CK0 - CK2 and /CK0 - /CK2)
VID(ac)
0.7
V
Input signal slew rate
SLEW
1
V/ns
Notes
1
2
Notes 1. Output waveform timing is measured where the output signal crosses through the VTT level.
2. Slew rate is to be maintained in the VIL (ac) to VIH(ac) range of the input signal swing. SLEW = (VIH(ac)VIL(ac))/ ∆t
VTT
RT = 50 Ω
Output
CLOAD = 30 pF
Preliminary Data Sheet M14900EJ1V0DS00
7
MC-45D32CC721
Synchronous Characteristics
Parameter
Clock cycle time
Symbol
CL = 2.5
tCK
CL = 2
-C75 (PC266B)
-C80 (PC200)
MIN.
MAX.
MIN.
MAX.
7.5
15
8
15
10
15
10
15
Unit
ns
CLK high-level width
tCH
0.45
0.55
0.45
0.55
tCK
CLK low-level width
tCL
0.45
0.55
0.45
0.55
tCK
DQ output access time from CLK, /CLK
tAC
–0.75
0.75
–0.8
0.8
ns
DQS output access time from CLK, /CLK
tDQSCK
–0.75
0.75
–0.8
0.8
ns
DQS-DQ skew (for DQS and associated DQ
signals)
tDQSQ
–0.5
0.5
–0.6
0.6
ns
DQS-DQ skew (for DQS and all DQ signals)
tDQSQA
–0.5
0.5
–0.6
0.6
ns
Data out low-impedance time from CLK, /CLK
tLZ
–0.75
0.75
–0.8
0.8
ns
Data out high-impedance time from CLK, /CLK
tHZ
–0.75
0.75
–0.8
0.8
ns
Half clock period
tHP
tCH, tCL
DQS read preamble
tRPRE
0.9
1.1
0.9
1.1
tCK
DQS read postamble
tRPST
0.4
0.6
0.4
0.6
tCK
DQ-DQS hold, DQS to first DQ to go non-valid,
per access
tQH
tHP – 0.75
tHP – 1
ns
DQ and DM input setup time
tDS
0.5
0.6
ns
DQ and DM input hold time
tDH
0.5
0.6
ns
tDIPW
1.75
2
ns
DQS write preamble setup time
tWPRES
0
0
ns
DQS write preamble
tWPRE
0.25
0.25
tCK
Write postamble
tWPST
0.4
0.6
0.4
0.6
tCK
Write command to first DQS latching transition
tDQSS
0.75
1.25
0.75
1.25
tCK
DQS input high pulse width
tDQSH
0.35
0.35
tCK
DQS input low pulse width
tDQSL
0.35
0.35
tCK
DQS falling edge to CLK setup time
tDSS
0.2
0.2
tCK
DQS falling edge hold time from CLK
tDSH
0.2
0.2
tCK
Address and control input setup time
tIS
0.9
1.1
ns
Address and control input hold time
tIH
0.9
1.1
ns
Address and control input pulse width
tIPW
2.2
2.5
ns
Internal write to read command delay
tWTR
1
1
tCK
DQ and DM input pulse width (for each input)
tCH, tCL
Remark These specifications are applied to the monolithic device.
8
Preliminary Data Sheet M14900EJ1V0DS00
ns
Note
MC-45D32CC721
Asynchronous Characteristics
Parameter
Symbol
-C75(PC266B)
MIN.
MAX.
-C80(PC200)
MIN.
Unit
MAX.
ACT to REF/ACT command period (operation)
tRC
65
70
ns
REF to REF/ACT command period (refresh)
tRFC
75
80
ns
ACT to PRE command period
tRAS
45
PRE to ACT command period
tRP
20
20
ns
ACT to READ/WRITE delay
tRCD
20
20
ns
ACT(one) to ACT(another) command period
tRRD
15
15
ns
Write recovery time
tWR
15
15
ns
Auto precharge write recovery time + precharge time
tDAL
35
35
ns
Mode register set command cycle time
tMRD
15
15
ns
Exit self refresh to command
tXSNR
75
Refresh time (4,096 refresh cycles)
tREF
120,000
50
120,000
80
64
Preliminary Data Sheet M14900EJ1V0DS00
ns
ns
64
ms
9
MC-45D32CC721
Serial PD
Byte No.
(1/2)
Function Described
Hex
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
80H
1
0
0
0
0
0
0
0
Notes
0
Defines the number of bytes written into
serial PD memory
1
Total number of bytes of serial PD memory
08H
0
0
0
0
1
0
0
0
256 bytes
2
Fundamental memory type
07H
0
0
0
0
0
1
1
1
DDR SDRAM
3
Number of rows
0CH
0
0
0
0
1
1
0
0
12 rows
4
Number of columns
0AH
0
0
0
0
1
0
1
0
10 columns
5
Number of banks
02H
0
0
0
0
0
0
1
0
2 banks
6
Data width
48H
0
1
0
0
1
0
0
0
72 bits
7
Data width (continued)
00H
0
0
0
0
0
0
0
0
0
8
Voltage interface
04H
0
0
0
0
0
1
0
0
SSTL2
9
CL = 2.5 Cycle time
-C75
75H
0
1
1
1
0
1
0
1
7.5 ns
-C80
80H
1
0
0
0
0
0
0
0
8 ns
-C75
75H
0
1
1
1
0
1
0
1
0.75 ns
-C80
80H
1
0
0
0
0
0
0
0
0.8 ns
02H
0
0
0
0
0
0
1
0
ECC
10
CL = 2.5 Access time
128 bytes
11
DIMM configuration type
12
Refresh rate/type
80H
1
0
0
0
0
0
0
0
Normal
13
SDRAM width
08H
0
0
0
0
1
0
0
0
x8
14
Error checking SDRAM width
08H
0
0
0
0
1
0
0
0
x8
15
Minimum clock delay
01H
0
0
0
0
0
0
0
1
1 clock
16
Burst length supported
0EH
0
0
0
0
1
1
1
0
2, 4, 8
17
Number of banks on each SDRAM
04H
0
0
0
0
0
1
0
0
4 banks
18
/CAS latency supported
0CH
0
0
0
0
1
1
0
0
2, 2.5
19
/CS latency supported
01H
0
0
0
0
0
0
0
1
0
20
/WE latency supported
02H
0
0
0
0
0
0
1
0
1
21
SDRAM module attributes
20H
0
0
1
0
0
0
0
0
Differential Clock
22
SDRAM device attributes : General
00H
0
0
0
0
0
0
0
0
VDD ± 0.2 V
23
CL = 2 Cycle time
-C75
A0H
1
0
1
0
0
0
0
0
10 ns
-C80
A0H
1
0
1
0
0
0
0
0
10 ns
-C75
75H
0
1
1
1
0
1
0
1
0.75 ns
-C80
80H
1
0
0
0
0
0
0
0
0.8 ns
-C75
50H
0
1
0
1
0
0
0
0
20 ns
-C80
50H
0
1
0
1
0
0
0
0
20 ns
-C75
3CH
0
0
1
1
1
1
0
0
15 ns
-C80
3CH
0
0
1
1
1
1
0
0
15 ns
-C75
50H
0
1
0
1
0
0
0
0
20 ns
-C80
50H
0
1
0
1
0
0
0
0
20 ns
-C75
2DH
0
0
1
0
1
1
0
1
45 ns
-C80
32H
0
0
1
1
0
0
1
0
50 ns
20H
0
0
1
0
0
0
0
0
128M bytes
24
CL = 2 Access time
25-26
27
28
tRRD(MIN.)
29
tRCD(MIN.)
30
31
10
tRP(MIN.)
tRAS(MIN.)
Module bank density
Preliminary Data Sheet M14900EJ1V0DS00
MC-45D32CC721
(2/2)
Byte No.
Function Described
Hex
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Notes
32
Command and address signal input
setup time
C0H
1
1
0
0
0
0
0
0
1.2 ns
33
Command and address signal input
hold time
C0H
1
1
0
0
0
0
0
0
1.2 ns
34
Data signal input setup time
60H
0
1
1
0
0
0
0
0
0.6 ns
35
Data signal input hold time
60H
0
1
1
0
0
0
0
0
0.6 ns
62
SPD revision
00H
0
0
0
0
0
0
0
0
63
Checksum for bytes 0 - 62
-C75
2FH
0
0
1
0
1
1
1
1
-C80
55H
0
1
0
1
0
1
0
1
00H
0
0
0
0
0
0
0
0
36-61
64-71
72
73-90
91
Manufacture’s JEDEC ID code
Manufacturing location
Manufacture’s P/N
Revision Code
93-94
Manufacturing date
95-99
Assembly serial number
100-127 Mfg specific
Timing Chart
Refer to the µPD45D128442, 45D128842, 45D128164 Data sheet (M13852E).
Preliminary Data Sheet M14900EJ1V0DS00
11
MC-45D32CC721
Package Drawing
184-PIN DUAL IN-LINE MODULE (SOCKET TYPE)
A (AREA B)
U
J1 (AREA B)
K
M
M
J
I
A
E
H
J2 (AREA A)
N
P
(OPTIONAL HOLES)
D
B
G
Q
C
A1 (AREA A)
ITEM
detail of A part
S
C2
133.35
A1
133.35±0.13
B
64.77
C
6.35
C1
1.80
C2
3.80
D
49.53
E
G
1.27 (T.P.)
6.35
H
10.00
17.80
31.75±0.13
I
J
R
C1
T
J1
23.38
J2
19.80
K
4.0 MAX.
M
4.0
N
φ 2.50
P
1.27±0.1
4.0 MIN.
Q
R
12
Preliminary Data Sheet M14900EJ1V0DS00
MILLIMETERS
A
S
0.2±0.15
1.0±0.05
T
U
2.50±0.15
3.0 MIN.
MC-45D32CC721
[MEMO]
Preliminary Data Sheet M14900EJ1V0DS00
13
MC-45D32CC721
[MEMO]
14
Preliminary Data Sheet M14900EJ1V0DS00
MC-45D32CC721
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Preliminary Data Sheet M14900EJ1V0DS00
15
MC-45D32CC721
CAUTION FOR HANDLING MEMORY MODULES
When handling or inserting memory modules, be sure not to touch any components on the modules, such as
the memory IC, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these
components to prevent damaging them.
When re-packing memory modules, be sure the modules are NOT touching each other. Modules in contact
with other modules may cause excessive mechanical stress, which may damage the modules.
• The information in this document is current as of June, 2000. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data
books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products
and/or types are available in every country. Please check with an NEC sales representative for
availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
• NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
• Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
• While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
• NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness
to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
M8E 00. 4