PRELIMINARY PRODUCT INFORMATION MOS INTEGRATED CIRCUIT µPD789322,789324,789326,789327 8-BIT SINGLE-CHIP MICROCONTROLLER The µPD789322, 789324, 789326, and 789327 are µPD789327 Subseries (designed for remote controller with onchip LCD) product in the 78K/0S Series. In addition to an 8-bit CPU, they have on-chip hardware for a remote controller with on-chip LCD, Including a LCD controller/driver, a serial interface, a key return signal detection circuit, and timers with carrier generator that can easily output waveforms for infrared remote control. The µPD78F9328, a product with on-chip flash memory which can operate on the same supply voltage as for masked ROM products and various development tools are also under development. Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before designing. µPD789327, 789467 Subseries User’s Manual: To be prepared 78K/0S Series User’s Manual Instructions: U11047E FEATURES • ROM and RAM size Item Data Memory Program memory (ROM) Part Number Internal High-Speed Packege LCD display RAM RAM µPD789322 4 K bytes µPD789324 8 K bytes µPD789326 16 K bytes µPD789327 24 K bytes 256 bytes 24 bytes 52-pin plastic LQFP (10×10 mm) 512 bytes • Variable minimum instruction execution time: High speed (0.4 µs: @5.0-MHz operation with main system clock), low speed (1.6 µs: @5.0-MHz operation with main system clock), and ultra low speed (122 µs: @32.768-kHz operation with subsystem clock) • I/O ports: 21 • Serial interface (3-wire serial I/O mode): 1 channel • LCD controller/driver Segment signals: 24 Common signals: 4 • Timer: 4 channels • Supply voltage: VDD = 1.8 to 5.5 V APPLICATIONS Remote-control devices, healthcare equipment, etc. The information contained in this document is being issued in advance of the production cycle for the device. The parameters for the device may change before final production or NEC Corporation, at its own discretion, may withdraw the device prior to its production. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. U14673EJ1V0PM00 (1st edition) Date Published March 2000 NS CP(K) Printed in Japan 2000 µPD789322,789324,789326,789327 ORDERING INFORMATION Part Number Package µPD789322GB-xxx-8ET 52-pin plastic LQFP (10×10 mm) µPD789324GB-xxx-8ET 52-pin plastic LQFP (10×10 mm) µPD789326GB-xxx-8ET 52-pin plastic LQFP (10×10 mm) µPD789327GB-xxx-8ET 52-pin plastic LQFP (10×10 mm) Remark xxx Indicates ROM code suffix. 2 Preliminary Product Information U14673EJ1V0PM00 µPD789322,789324,789326,789327 78K/0S SERIES LINEUP The products in the 78K/0S Series are listed below. The names enclosed in boxes are subseries names. Products under mass production Products under development Y subseries supports SMB. Small, general-purpose 44 pins 42/44 pins 28 pins µ PD789026 with subsystem clock added µ PD789014 with timer reinforced and ROM and RAM expanded µ PD789046 µ PD789026 µ PD789014 UART. Low-voltage (1.8-V) operation Small, general-purpose + A/D µ PD789177 µ PD789167 µ PD789156 µ PD789146 µ PD789134A µ PD789124A µ PD789114A µ PD789104A 44 pins 44 pins 30 pins 30 pins 30 pins 30 pins 30 pins 30 pins µ PD789177Y µ PD789167Y µ PD789167 with improved A/D µ PD789104A with improved timer µ PD789146 with improved A/D µ PD789104A with EEPROM added µ PD789124A with improved A/D RC oscillation model of µ PD789104A µ PD789104A with improved A/D µ PD789026 with A/D and multiplier added For inverter control µ PD789842 44 pins 78K/0S series Internal inverter control circuit and UART For driving LCD 80 pins 80 pins 64 pins 64 pins 64 pins 64 pins 64 pins 64 pins µ PD789417A µ PD789407A µ PD789456 µ PD789446 µ PD789436 µ PD789426 µ PD789316 µ PD789306 µ PD789407A with improved A/D µ PD789456 with improved I/O µ PD789446 with improved A/D µ PD789426 with improved display output µ PD789426 with improved A/D µ PD789306 with A/D added RC oscillation model of µ PD789306 Basic subseries for driving LCD For driving Dot LCD 144 pins 88 pins µ PD789835 µ PD789830 Segment/common output: 96 pins Segment: 40 pins, common: 16 pins For ASSP 52 pins 52 pins 44 pins 44 pins 20 pins 20 pins µ PD789467 µ PD789327 µ PD789800 µ PD789840 µ PD789861 µ PD789860 µ PD789327 with A/D added For remote controller. Internal LCD controller/driver For PC keyboard. Internal USB function For key pad. Internal POC RC oscillation model of µPD789860 For keyless entry. Internal POC and key return circuit Preliminary Product Information U14673EJ1V0PM00 3 µPD789322,789324,789326,789327 The major differences between subseries are shown below. Function Subseries Name ROM Capacity Small, µPD789046 16 K generalµPD789026 4 K-16 K purpose µPD789014 2 K-4 K Small, µPD789177 16 K-24 K generalµPD789167 purpose µPD789156 8 K-16 K + A/D Timer 8-bit 1 ch 16-bit 1 ch Watch WDT 1 ch 1 ch 8-bit A/D 10-bit A/D Serial Interface I/O VDD MIN Value Remark − − 1 ch (UART:1 ch) 34 pins 1.8 V − 1.8 V − − 2 ch − 3 ch 1 ch 22 pins 1 ch 1 ch − 1 ch µPD789146 − 8 ch 8 ch − − 4 ch 4 ch − µPD789134A 2 K-8 K 20 pins Internal EEPROM 4 ch RC oscillation version µPD789124A 4 ch − µPD789114A − 4 ch µPD789104A 4 ch − 8 ch − 1 ch (UART: 1 ch) 30 pins 4.0 V − 7 ch 1 ch (UART: 1 ch) 43 pins 1.8 V − µPD789842 8 K-16 K 3 ch Note 1 ch 1 ch For LCD µPD789417A 12 K-24 K driving µPD789407A 3 ch 1 ch 1 ch 1 ch µPD789456 12 K-16 K 2 ch For inverter control 1 ch (UART: 1 ch) 31 pins 7 ch − − 6 ch µPD789446 6 ch − µPD789436 − 6 ch µPD789426 6 ch − µPD789316 8 K to 16K − − 30 pins 40 pins 2 ch (UART: 1 ch) 23 pins RC oscillation version µPD789306 − For Dot LCD driving µPD789835 24 K-60 K 6 ch − µPD789830 24 K 1 ch 1 ch ASSP µPD789467 4 K-24 K 2 ch − 1 ch 1 ch 2 ch 1 ch µPD789840 µPD789861 4 K 1 ch 1 ch − 1 ch 1 ch 1 ch 27 pins 1.8 V 1 ch (UART: 1 ch) 30 pins 2.7 V − − 1.8 V 1 ch 21 pins − 2 ch (USB: 1 ch) 31 pins 4.0 V 1 ch 29 pins 2.8 V 14 pins 1.8 V − µPD789860 − − Internal LCD − RC oscillation version, Internal EEPROM Internal EEPROM Note 10-bit timer: 1 channel 4 18 pins − 4 ch − − − µPD789327 µPD789800 8 K 2 ch Preliminary Product Information U14673EJ1V0PM00 µPD789322,789324,789326,789327 OVERVIEW OF FUNCTIONS µPD789322 Item Internal memory ROM 4 Kbytes High-speed RAM 256 bytes LCD display RAM 24 bytes µPD789324 8 Kbytes µPD789326 16 Kbytes µPD789327 24 Kbytes 512 bytes Main system clock (oscillation frequency) Ceramic/crystal resonator (1.0 to 5.0 MHz) Subsystem clock (oscillation frequency) Crystal resonator (32.768 kHz) Minimum instruction execution time 0.4 µs/1.6 µs (@5.0-MHz operation with main system clock) 122 µs (@32.768-kHz operation with subsystem clock) General-purpose registers 8 bits × 8 registers Instruction set • 16-bit operations • Bit manipulation (set, reset, test) etc. I/O ports Total: CMOS I/O: Timers 2 channels • 8-bit timer: 1 channel • Watch timer: • Watchdog timer: 1 channel Timer outputs 1 Serial interface 3-wire serial I/O mode: 1 channel LCD controller/driver • Segment signal outputs: 24 • Common signal outputs: 4 Vectored interrupt sources 21 21 Maskable Internal: 6, External: 2 Non-maskable Internal: 1 Reset • Reset by RESET signal input • Internal reset by watchdog timer • Reset via power-on-clear circuit Supply voltage VDD = 1.8 to 5.5 V Operating ambient temperature TA = −40 to +85°C Package 52-pin plastic LQFP (10×10 mm) Preliminary Product Information U14673EJ1V0PM00 5 µPD789322,789324,789326,789327 CONTENTS 1. PIN CONFIGURATION (TOP VIEW).....................................................................................................8 2. BLOCK DIAGRAM .................................................................................................................................9 3. PIN 3.1 3.2 3.3 FUNCTIONS ..................................................................................................................................10 Port Pins.......................................................................................................................................10 Non-Port Pins...............................................................................................................................11 Pin I/O Circuits and Recommended Connection of Unused Pins ..........................................12 4. CPU 4.1 4.2 4.3 ARCHITECTURE .........................................................................................................................14 Memory Space .............................................................................................................................14 Data Memory Addressing ...........................................................................................................15 Processor Registers....................................................................................................................16 5. PERIPHERAL HARDWARE FUNCTIONS..........................................................................................20 5.1 Ports .............................................................................................................................................20 5.2 Clock Generator...........................................................................................................................26 5.3 8-Bit Timer 30, 40.........................................................................................................................31 5.4 Watch Timer .................................................................................................................................41 5.5 Watchdog Timer ..........................................................................................................................44 5.6 Serial Interface 10........................................................................................................................46 5.7 LCD Controller/Driver..................................................................................................................50 6. INTERRUPT FUNCTION ......................................................................................................................56 6.1 Interrupt Types ............................................................................................................................56 6.2 Interrupt Sources and Configuration ........................................................................................56 6.3 Interrupt Function Control Registers ........................................................................................59 7. STANDBY FUNCTION .........................................................................................................................65 7.1 Standby Function ........................................................................................................................65 7.2 Standby Function Control Register...........................................................................................67 8. RESET FUNCTION...............................................................................................................................68 8.1 Reset Function.............................................................................................................................68 8.2 Power Failure Detection Function .............................................................................................70 9. MASK OPTION ......................................................................................................................................71 10. INSTRUCTION SET OVERVIEW ......................................................................................................72 10.1 Conventions...............................................................................................................................72 10.2 Operations..................................................................................................................................74 11. ELECTRICAL SPECIFICATIONS ......................................................................................................79 12. PACKAGE DRAWING.........................................................................................................................90 6 Preliminary Product Information U14673EJ1V0PM00 µPD789322,789324,789326,789327 APPENDIX A. DEVELOPMENT TOOLS ................................................................................................ 91 APPENDIX B. RELATED DOCUMENTS................................................................................................ 93 Preliminary Product Information U14673EJ1V0PM00 7 µPD789322,789324,789326,789327 1. PIN CONFIGURATION (TOP VIEW) 52-pin plastic LQFP (10× ×10 mm) P80/S22 S23 VLC0 P22/SI10 µPD789326GB-xxx-8ET P21/SO10 P20/SCK10 IC0 XT1 XT2 VSS VDD X2 µPD789324GB-xxx-8ET X1 µPD789322GB-xxx-8ET µPD789327GB-xxx-8ET P84/S18 35 P85/S17 P40/KR00 6 34 S16 P03 7 33 S15 P02 8 32 S14 P01 9 31 S13 P00 10 30 S12 INT/P61 11 29 S11 P11 12 28 S10 P10 27 13 14 15 16 17 18 19 20 21 21 23 24 25 26 S9 S8 S7 36 5 S6 4 P41/KR01 S5 P42/KR02 S4 P83/S19 S3 P82/S20 37 S2 38 3 S1 2 P43/KR03 S0 P60/TO40 COM3 P81/S21 COM2 52 51 50 49 48 47 46 45 44 43 42 41 40 39 COM1 1 COM0 RESET Caution Connect the IC0 (Internally Connected) pin directly to VSS. COM0 to COM3: Common Output RESET: Reset IC0: Internally connected S0 to S23: Segment Output INT: Interrupt from Peripherals SCK10: Serial Clock Input/Output KR00 to KR03: Key Return SI10: Serial Data Input P00 to P03: Port 0 SO10: Serial Data Output P10, P11: Port 1 VDD: Power Supply P20 to P22: Port 2 VLC0: Power Supply for LCD P40 to P43: Port 4 VSS: Ground P60, P61: Port 6 X1, X2: Crystal (Main system clock) P80 to P85: Port 8 XT1, XT2: Crystal (Sabsystem clock) TO40: Timer Output 8 Preliminary Product Information U14673EJ1V0PM00 µPD789322,789324,789326,789327 2. BLOCK DIAGRAM TO40/P60 8-bit timer 30 Cascaded 16-bit 8-bit timer timer 40 Watch timer 78K/0S CPU core ROM Port 0 P00 to P03 Port 1 P10, P11 Port 2 P20 to P22 Port 4 P40 to P43 Port 6 P60, P61 Port 8 P80 to P85 Watchdog timer SCK10/P20 SO10/P21 SI10/P22 Serial interface 10 RAM RAM space for LCD data S0 to S23 COM0 to COM3 System control LCD controller/driver VLC0 RESET X1 X2 XT1 XT2 INT/P61 Interrupt control Power-on clear VDD VSS KR00/P40 to KR03/P43 IC0 Remark The Internal ROM and RAM capacities differ depending on the product. Preliminary Product Information U14673EJ1V0PM00 9 µPD789322,789324,789326,789327 3. PIN FUNCTIONS 3.1 Port Pins Pin Name I/O Function After Reset Alternate Function P00 to P03 I/O Port 0. This is a 4-bit I/O port. Input/output can be specified in 1-bit units. When used as an input port, on-chip pull-up resistors can be specified for the whole port using pull-up resistor option register 0 (PU0). Input − P10, P11 I/O Port 1. This is a 2-bit I/O port. Input/output can be specified in 1-bit units. When used as an input port, on-chip pull-up resistors can be specified for the whole port using pull-up resistor option register 0 (PU0). Input − P20 I/O Port 2. This is a 3-bit I/O port. Input/output can be specified in 1-bit units. When used as an input port, on-chip pull-up resistors can be specified in 1-bit units using pull-up resistor option register 2 (PUB2). Input P21 P22 SCK10 SO10 SI10 P40 to P43 I/O Port 4. This is a 4-bit I/O port. Input/output can be specified in 1-bit units. When used as an input port, on-chip pull-up resistors can be specified for the whole port using pull-up resistor option register 0 (PU0), or key return mode register 00 (KRM00). Input KR00 to KR03 P60 I/O Port 6. This is a 2-bit I/O port. Input/output can be specified in 1-bit units. Input TO40 Port 8. This is a 6-bit I/O port. Input/output can be specified in 1-bit units. Low-level output P61 P80 to P85 10 I/O Preliminary Product Information U14673EJ1V0PM00 INT S22 to S17 µPD789322,789324,789326,789327 3.2 Non-Port Pins Pin Name I/O Function After Reset Alternate Function INT Input External interrupt input for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. Input P61 KR00 to KR03 Input Key return signal detection Input P40 to P43 TO40 Output 8-bit timer 40 output Input P60 SCK10 I/O Serial clock input/output of serial interface 10 Input P20 SI10 Input Serial data input of serial interface 10 Input P22 SO10 Output Serial data output of serial interface 10 Input P21 S0 to S16 Output LCD controller/driver segment signal outputs Low-level output S17 to S22 VLC0 Output − X1 Input X2 − XT1 Input XT2 − RESET P85 to P80 − S23 COM0 to COM3 − Input LCD controller/driver common signal outputs Low-level output − LCD drive voltage − − Connecting crystal resonator for main system clock oscillation − − − − − − − − Connecting crystal resonator for subsystem clock oscillation System reset input − Input VDD − Positive power supply − − VSS − Ground potential − − IC0 − Internally connected. Connect to VSS directly. − − Preliminary Product Information U14673EJ1V0PM00 11 µPD789322,789324,789326,789327 3.3 Pin I/O Circuits and Recommended Connection of Unused Pins The I/O circuit type of each pin and recommended connection of unused pins is shown in Table 3-1. For the input/output circuit configuration of each type, refer to Figure 3-1. Table 3-1. Types of Pin I/O Circuits and Recommended Connection of Unused Pins Pin Name P00 to P03 I/O Circuit Type 5-A I/O I/O Input: Independently connect to VDD or VSS via a resistor. Output: Leave open. P10, P11 P20/SCK10 8-A P21/SO10 5-A P22/SI10 8-A Recommend Connection of Unused Pins P40/KR00 to P43/KR03 P60/TO40 5 P61/INT 8 P80/S22 to P85/S17 17-G S0 to S16, S23 17-D COM0 to COM3 18-B − VLC0 Input: Independently connect to VSS via a resistor. Output: Leave open. Input: Independently connect to VDD or VSS via a resistor. Output: Leave open. Output Leave open. − XT1 Input XT2 − RESET 2 Input IC0 − − Connect to VSS. Leave open. − Connect directly to VSS directly. Figure 3-1. I/O Circuit Type (1/2) Type 2 Type 5 VDD Data P-ch IN IN/OUT Output disable Schmitt-triggered input with hysteresis characteristics. 12 Input enable Preliminary Product Information U14673EJ1V0PM00 N-ch VSS µPD789322,789324,789326,789327 Figure 3-1. I/O Circuit Type (2/2) Type 5-A Type 8 VDD Pull-up enable VDD P-ch Data VDD P-ch IN/OUT Data P-ch IN/OUT Output disable Output disable N-ch VSS N-ch VSS Input enable Type 8-A Type 17-D VDD VLC0 P-ch Pull-up enable P-ch VLC1 P-ch N-ch VDD Data P-ch SEG data P-ch OUT N-ch IN/OUT Output disable P-ch N-ch VLC2 N-ch N-ch VSS VSS Type 17-G Type 18-B VDD Data P-ch IN/OUT Output disable N-ch VSS VLC0 Input enable VLC1 P-ch P-ch N-ch P-ch N-ch VLC0 P-ch VLC1 OUT COM data P-ch N-ch P-ch N-ch P-ch P-ch N-ch VLC2 N-ch SEG data N-ch VSS P-ch N-ch VLC2 N-ch VSS Remark VLC1: VLC0 × 2/3, VLC2: VLC0/3 Preliminary Product Information U14673EJ1V0PM00 13 µPD789322,789324,789326,789327 4. CPU ARCHITECTURE 4.1 Memory Space The µPD789322, 789324, 789326, and 789327 are provided with 64 Kbytes of accessible memory space. Figure 4-1 shows the memory map. Figure 4-1. Memory Map FFFFH Special function registers 256 × 8 bits FF00H FEFFH Note Internal high-speed RAM mmmmH mmmmH−1 Reserved FA18H FA17H Data memory space FA00H F9FFH n n n n H+1 nnnnH LCD display RAM 24 × 8 bits nnnnH Reserved Program area Program memory space Internal ROM Note 0080H 007FH CALLT table area 0040H 003FH Program area 0014H 0013H 0000H 0000H Vector table area Note The internal ROM capacity and internal high-speed RAM capacity depend on the products (see the next table). Relevant Product Name 14 Internal ROM Last Address Internal High-Speed RAM Start Address nnnnH mmmmH µPD789322 0FFFH FE00H µPD789324 1FFFH µPD789326 3FFFH µPD789327 5FFFH Preliminary Product Information U14673EJ1V0PM00 FD00H µPD789322,789324,789326,789327 4.2 Data Memory Addressing The µPD789322, 789324, 789326, and 789327 are provided with a variety of addressing modes to improve the operability of the memory. In the area that incorporates data memory (FD00H to FFFFH) in particular, specific addressing modes that correspond to the particular functions of an area, such as the special function registers (SFRs), are available. Figure 4-2 shows the data memory addressing modes. Figure 4-2. Data Memory Addressing Modes FFFFH Special function registers (SFRs) 256 × 8 bits SFR addressing FF20H FF1FH FF00H FEFFH Internal high-speed RAM Short direct addressing Note FE20H FE1FH mmmmH mmmmH−1 Direct addressing Reserved Register indirect addressing FA18H FA17H Based addressing LCD display RAM 24 × 8 bits FA00H F9FFH Reserved n n n n H+1 nnnnH Internal ROM Note 0000H Note The internal ROM capacity and internal high-speed RAM capacity depend on the products (see the next table). Relevant Product Name Internal ROM Last Address Internal High-Speed RAM Start Address nnnnH mmmmH µPD789322 0FFFH FE00H µPD789324 1FFFH µPD789326 3FFFH µPD789327 5FFFH Preliminary Product Information U14673EJ1V0PM00 FD00H 15 µPD789322,789324,789326,789327 4.3 Processor Registers 4.3.1 Control registers (1) Program counter (PC) The PC is a 16-bit register that holds the address information of the next program to be executed. Figure 4-3. Program Counter Configuration 15 0 PC PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 (2) Program status word (PSW) The PSW is an 8-bit register that indicates the status of the CPU according to the results of instruction execution. Figure 4-4. Program Status Word Configuration 7 IE 0 Z 0 AC 0 0 1 CY (a) Interrupt enable flag (IE) This flag controls the interrupt request acknowledgement of the CPU. (b) Zero flag (Z) This flag is set (1) if the result of an operation is zero; otherwise it is reset (0). (c) Auxiliary carry flag (AC) AC is set (1) if the result of the operation has a carry from bit 3 or a borrow at bit 3; otherwise it is reset (0). (d) Carry flag (CY) CY is used to indicate whether an overflow or underflow has occurred during the execution of a subtract or add instruction. (3) Stack pointer (SP) The SP is a 16-bit register that holds the start address of the stack area. Only the internal RAM area (FD00H to FEFFH) can be specified as the stack area. Figure 4-5. Stack Pointer Configuration 15 0 SP SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 Caution RESET input makes the SP contents undefined, so be sure to initialize the SP before instruction execution. 16 Preliminary Product Information U14673EJ1V0PM00 µPD789322,789324,789326,789327 4.3.2 General-purpose registers The µPD789322, 789324, 789326, and 789327 have eight 8-bit general-purpose registers (X, A, C, B, E, D, L, and H). These registers can be used either singly as 8-bit registers or in pairs as 16-bit registers (AX, BC, DE, and HL), and can be described in terms of function names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL) and absolute names (R0 to R7 and RP0 to RP3). Figure 4-6. General-Purpose Register Configuration (a) Absolute register names 16-bit processing 8-bit processing R7 RP3 R6 R5 RP2 R4 R3 RP1 R2 R1 RP0 R0 15 0 7 0 (b) Functional register names 8-bit processing 16-bit processing H HL L D DE E B BC C A AX X 15 0 7 Preliminary Product Information U14673EJ1V0PM00 0 17 µPD789322,789324,789326,789327 4.3.3 Special function registers (SFRs) Special function registers are used as peripheral hardware mode registers and control registers, and are mapped in the 256-byte space from FF00H to FFFFH. Note that the bit number of a bit name that is a reserved word in the RA78K0S and defined under the header file “sfrbit.h” in the CC78K0S appears enclosed in a circle in the register formats. Refer to the register formats in 5. PERIPHERAL HARDWARE FUNCTIONS. Table 4-1. Special Function Registers (1/2) Address Special Function Register (SFR) Name Symbol R/W R/W Bit Unit for Manipulation 1 Bit 8 Bits 16 Bits √ √ − After Reset FF00H Port 0 P0 FF01H Port 1 P1 √ √ − FF02H Port 2 P2 √ √ − FF03H port 4 P4 √ √ − FF05H Port 6 P6 √ √ − FF08H Port 8 P8 √ √ − FF20H Port mode register 0 PM0 √ √ − FF21H Port mode register 1 PM1 √ √ − FF22H Port mode register 2 PM2 √ √ − FF24H Port mode register 4 PM4 √ √ − FF26H Port mode register 6 PM6 √ √ − FF28H Port mode register 8 PM8 √ √ − FF32H Pull-up resistor option register B2 PUB2 √ √ − FF4AH Watch timer mode control register WTM √ √ − FF58H Port function register 8 PF8 √ √ − FF63H 8-bit compare register 30 CR30 W − √ − Undefined FF64H 8-bit timer counter 30 TM30 R − √ − 00H FF65H 8-bit timer mode control register 30 TMC30 R/W √ √ − FF66H 8-bit compare register 40 CR40 W − √ − FF67H 8-bit H width compare register 40 − √ − FF68H 8-bit timer counter 40 FF69H CRH40 00H FFH 00H Undefined TM40 R − √ − 8-bit timer mode control register 40 TMC40 R/W √ √ − FF6AH Carrier generator output control register 40 TCA40 W − √ − FF72H Serial operation mode register 10 CSIM10 R/W √ √ − FF74H Transmission/reception shift register 10 SIO10 √ √ − Undefined FFB0H LCD display mode register 0 LCDM0 √ √ − 00H FFB2H LCD clock control register 0 LCDC0 √ √ − POCF1 √ √ − FFDDH Power-on-clear register 1 Note This value is 04H only after a power-on-clear reset. 18 Preliminary Product Information U14673EJ1V0PM00 00H Note 00H µPD789322,789324,789326,789327 Table 4-1. Special Function Registers (2/2) Address Special Function Register (SFR) Name Symbol R/W Bit Unit for Manipulation After Reset 1 Bit 8 Bits 16 Bits √ √ − 00H MK0 √ √ − FFH FFECH External interrupt mode register 0 INTM0 − √ − 00H FFF0H Subclock oscillation mode register SCKM √ √ − FFF2H Subclock control register CSS √ √ − FFF5H Key return mode register 00 KRM00 √ √ − FFF7H Pull-up resistor option register 0 PU0 √ √ − FFF9H Watchdog timer mode register WDTM √ √ − OSTS − √ − 04H PCC √ √ − 02H FFE0H Interrupt request flag register 0 FFE4H Interrupt mask flag register 0 IF0 FFFAH Oscillation stabilization time selection register FFFBH Processor clock control register R/W Preliminary Product Information U14673EJ1V0PM00 19 µPD789322,789324,789326,789327 5. PERIPHERAL HARDWARE FUNCTIONS 5.1 Ports 5.1.1 Port functions Various kinds of control operations are possible using the ports provided in the µPD789322, 789324, 789326, and 789327. These ports are illustrated in Figure 5-1 and their functions are listed in Table 5-1. A number of alternate functions are also provided, except for those ports functioning as digital I/O ports. Refer to 3. PIN FUNCTIONS for details of the alternate function pins. Figure 5-1. Ports P40 P00 Port 4 Port 6 Port 0 P43 P03 P60 P61 P10 P11 P80 P20 Port 1 Port 2 P22 Port 8 P85 20 Preliminary Product Information U14673EJ1V0PM00 µPD789322,789324,789326,789327 Table 5-1. Port Functions Port Name Pin Name Function Port 0 P00 to P03 This is an I/O port for which input and output can be specified in 1-bit units. When used as an input port, on-chip pull-up resistors can be specified using pull-up resistor option register 0 (PU0). Port 1 P10, P11 This is an I/O port for which input and output can be specified in 1-bit units. When used as an input port, on-chip pull-up resistors can be specified using pull-up resistor option register 0 (PU0). Port 2 P20 to P22 This is an I/O port for which input and output can be specified in 1-bit units. When used as an input port, on-chip pull-up resistors can be specified using pull-up resistor option register B2 (PUB2). Port 4 P40 to P43 This is an I/O port for which input and output can be specified in 1-bit units. When used as an input port, on-chip pull-up resistors can be specified using pull-up resistor option register 0 (PU0), or key return mode register 00 (KRM00). Port 6 P60, P61 This is an I/O port for which input and output can be specified in 1-bit units. Port 8 P80 to P85 This is an I/O port for which input and output can be specified in 1-bit units. Preliminary Product Information U14673EJ1V0PM00 21 µPD789322,789324,789326,789327 5.1.2 Port configuration The ports consist of the following hardware. Table 5-2. Port Configuration Item Configuration Control registers Port mode registers (PMm: m = 0 to 2, 4, 6, 8) Pull-up resistor option registers (PU0, PUB2) Port function register 8 (PF8) Ports Total: 21 (CMOS I/O: 21) Pull-up resistors Total: 13 (software control: 13) Figure 5-2. Basic Configuration of CMOS Port VDD WRPUm PU× P-ch Internal bus Selector WRPORTm WRPORTm Output latch Pmn Pmn WRPMm PMmn Caution Figure 5-2 shows the basic configuration of a CMOS I/O port. This configuration differs depending on the functions of alternate function pins. Also, an on-chip pull-up resistor can be connected to port 4 by means of a setting in key return mode register 00 (KRM00). Remark PU×: Pull-up resistor option register (× = 0, B2) PMmn: Bit n of port mode register m (m = 0 to 2, 4, 6, 8 n = 0 to 5) 22 Pmn: Bit n of port m RD: Port read signal WR: Port write signal Preliminary Product Information U14673EJ1V0PM00 µPD789322,789324,789326,789327 5.1.3 Port function control registers The ports are controlled by the following three types of registers. • Port mode registers (PM0 to PM2, PM4, PM6, PM8) • Pull-up resistor option registers (PU0, PUB2) • Port function register 8 (PF8) (1) Port mode registers (PM0 to PM2, PM4, PM6, PM8) Input and output can be specified in 1-bit units. These registers can be set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets these registers to FFH. When using the port pins as their alternate functions, set the port mode register and the output latch as shown in Table 5-3. Caution Because P61 functions alternately as an external interrupt input, when the output level changes after the output mode of the port function is specified, the interrupt request flag will be inadvertently set. Therefore, be sure to preset the interrupt mask flag (PMK0) before using the port in output mode. Figure 5-3. Port Mode Register Format Symbol 7 6 5 4 3 2 1 0 Address After reset R/W PM0 1 1 1 1 PM03 PM02 PM01 PM00 FF20H FFH R/W PM1 1 1 1 1 1 1 PM11 PM10 FF21H FFH R/W PM2 1 1 1 1 1 PM22 PM21 PM20 FF22H FFH R/W PM4 1 1 1 1 PM43 PM42 PM41 PM40 FF24H FFH R/W PM6 1 1 1 1 1 1 PM61 PM60 FF26H FFH R/W PM8 1 1 PM85 PM84 PM83 PM82 PM81 PM80 FF28H FFH R/W PMmn Pmn pin input/output mode selection (m = 0 to 2, 4, 6, 8 n = 0 to 5) 0 Output mode (output buffer on) 1 Input mode (output buffer off) Preliminary Product Information U14673EJ1V0PM00 23 µPD789322,789324,789326,789327 Table 5-3. Port Mode Registers and Output Latch Settings When Using Alternate Functions Pin Name Alternate Function PM×× P×× Input 1 × Output 0 1 Name P20 I/O SCK10 P21 SO10 Output 0 1 P22 SI10 Input 1 × P40 to P43 KR00 to KR03 Input 1 × P60 TO40 Output 0 0 P61 INT Input 1 × Output × × Note S22 to S17 P80 to P85 Note When using P80 to P85 pins as S22 to S17, set port function register 8 (PF8) to 3FH. Remark ×: don’t care PM××: Port mode register P××: Port output latch (2) Pull-up resistor option register 0 (PU0) This register sets whether to use on-chip pull-up resistors for ports 0, 1, and 4 on a port by port basis. An onchip pull-up resistor can be used only for those bits set to the input mode of a port for which the use of the onchip pull-up resistor has been specified using PU0. For those bits set to the output mode, on-chip pull-up resistors cannot be used, regardless of the setting of PU0. This also applies to alternate-function pins used as output pins. PU0 is set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 00H. Figure 5-4. Format of Pull-Up Resistor Option Register 0 Symbol 7 6 5 <4> 3 2 <1> <0> Address After reset R/W PU0 0 0 0 PU04 0 0 PU01 PU00 FFF7H 00H R/W PU0m Port m on-chip pull-up resistor selection (m = 0, 1, 4) 0 An on-chip pull-up resistor is not connected 1 An on-chip pull-up resistor is connected Caution Always set bits 2, 3, and 5 to 7 to 0. 24 Preliminary Product Information U14673EJ1V0PM00 µPD789322,789324,789326,789327 (3) Pull-up resistor option register B2 (PUB2) This register sets whether to use on-chip pull-up resistors for P20 to P22 in bit units. An on-chip pull-up resistor can be used only for those bits set to the input mode of a port for which the use of the on-chip pull-up resistor has been specified using PUB2. For those bits set to the output mode, on-chip pull-up resistors cannot be used, regardless of the setting of PUB2. This also applies to alternate-function pins used as output pins. PUB2 is set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 00H. Figure 5-5. Format of Pull-Up Resistor Option Register B2 Symbol 7 6 5 4 3 <2> <1> <0> Address After reset R/W PUB2 0 0 0 0 0 PUB22 PUB21 PUB20 FF32H 00H R/W PUB2n P2n on-chip pull-up resistor selection (n = 0 to 2) 0 An on-chip pull-up resistor is not connected 1 An on-chip pull-up resistor is connected Caution Always set bits 3 to 7 to 0. (4) Port function register 8 (PF8) This register sets the port function of port 8 in 1-bit units. The pins of port 8 are selected as either LCD segment signal outputs or general-purpose port pins according to the setting of PF8. PF8 can be set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 00H. Figure 5-6. Format of Port Function Register 8 Symbol 7 6 5 4 3 2 1 0 Address After reset R/W PF8 0 0 PF85 PF84 PF83 PF82 PF81 PF80 FF58H 00H R/W PF8n P8n port function (n = 0 to 5) 0 Operates as a general-purpose port 1 Operates as an LCD segment signal output Preliminary Product Information U14673EJ1V0PM00 25 µPD789322,789324,789326,789327 5.2 Clock Generator 5.2.1 Clock generator function The clock generator generates the clock pulse to be supplied to the CPU and peripheral hardware. There are two types of system clock oscillators: • Main system clock oscillator (ceramic/crystal resonator) This circuit generates a frequency of 1.0 to 5.0 MHz. Oscillation can be stopped by executing the STOP instruction or by means of a processor clock control register (PCC) setting. • Subsystem clock oscillator This circuit generates a frequency of 32.768 kHz. Oscillation can be stopped using the subclock oscillation mode register (SCKM). 5.2.2 Clock generator configuration The clock generator consists of the following hardware. Table 5-4. Clock Generator Configuration Item Configuration Control registers Processor clock control register (PCC) Subclock oscillation mode register (SCKM) Subclock control register (CSS) Oscillators Main system clock oscillator Subsystem clock oscillator 26 Preliminary Product Information U14673EJ1V0PM00 µPD789322,789324,789326,789327 Figure 5-7. Clock Generator Block Diagram Internal bus Subclock oscillation mode register (SCKM) FRC SCC XT1 XT2 Subsystem clock oscillatior fXT Watch timer LCD controller/driver 1/2 X2 Main system fX clock oscillator Prescaler fXT 2 Clock to peripheral hardware fX 22 Standby control circuit Selector X1 STOP Wait control circuit CPU clock (fCPU) CLS CSS0 MCC PCC1 Processor clock control register (PCC) Subclock control register (CSS) Internal bus Preliminary Product Information U14673EJ1V0PM00 27 µPD789322,789324,789326,789327 5.2.3 Clock generator control registers The clock generator is controlled by the following three registers. • Processor clock control register (PCC) • Subclock oscillation mode register (SCKM) • Subclock control register (CSS) (1) Processor clock control register (PCC) This register is used to select the CPU clock and set the frequency division ratio. PCC is set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 02H. Figure 5-8. Format of Processor Clock Control Register Symbol <7> 6 5 4 3 2 1 0 Address After reset R/W PCC MCC 0 0 0 0 0 PCC1 0 FFFBH 02H R/W MCC Main system clock oscillator operation control 0 Operation enabled 1 Operation stopped CSS0 PCC1 0 0 CPU clock (fCPU) selection fX 2 Note Minimum instruction execution time: 2fCPU (0.2 µs) 0.4 µs 0 1 fX/2 (0.8 µs) 1.6 µs 1 × fXT/2 (61 µs) 122 µs Note The CPU clock is selected by a combination of flag settings in the PCC and CSS registers. (Refer to 5.2.3 (3) Subclock control register (CSS).) Cautions 1. Always set bits 0 and 2 to 6 to 0. 2. MCC can be set only when the subsystem clock is selected as the CPU clock. Setting MCC to 1 while the main system clock is operating is invalid. Remarks 1. fX: Main system clock oscillation frequency 2. fXT: Subsystem clock oscillation frequency 3. The parenthesized values apply to operation at fX = 5.0 MHz or fXT = 32.768 kHz. 28 Preliminary Product Information U14673EJ1V0PM00 µPD789322,789324,789326,789327 (2) Subclock oscillation mode register (SCKM) This register is used to select a feedback resistor for the subsystem clock and control the oscillation of the clock. SCKM is set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 00H. Figure 5-9. Format of Subclock Oscillation Mode Register Symbol 7 6 5 4 3 2 1 <0> Address After reset R/W SCKM 0 0 0 0 0 0 FRC SCC FFF0H 00H R/W FRC Feedback resistor selection 0 An on-chip feedback resistor is used 1 An on-chip feedback resistor is not used SCC Control of subsystem clock oscillator operation 0 Operation enabled 1 Operation stopped Caution Always set bits 2 to 7 to 0. Preliminary Product Information U14673EJ1V0PM00 29 µPD789322,789324,789326,789327 (3) Subclock control register (CSS) This register is used to specify whether the main system or subsystem clock oscillator is selected and to indicate the operating status of the CPU clock. CSS is set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 00H. Figure 5-10. Format of Subclock Control Register Symbol 7 6 5 4 3 2 1 0 Address After reset R/W CSS 0 0 CLS CSS0 0 0 0 0 FFF2H 00H R/W CLS CPU clock operating status 0 Operating on the output of the (divided) main system clock 1 Operating on the output of the subsystem clock CSS0 Selection of main system clock or subsystem clock oscillator 0 Main system clock oscillator (divided) output 1 Subsystem clock oscillator output Note Bit 5 is read-only. Caution Always set bits 0 to 3, 6, and 7 to 0. 30 Preliminary Product Information U14673EJ1V0PM00 Note µPD789322,789324,789326,789327 5.3 8-Bit Timer 30, 40 5.3.1 Functions of 8-bit timer 30, 40 The 8-bit timer in the µPD789322, 789324, 789326, and 789327 have 2 channels (timer 30 and timer 40). The operation modes in the following table are possible by means of mode register settings. Table 5-5. List of Modes Channel Timer 30 Timer 40 √ √ Mode 8-bit timer counter mode (discrete mode) 16-bit timer counter mode (cascade connection mode) √ Carrier generator mode √ PWM output mode – √ (1) 8-bit timer counter mode (discrete mode) The timer can be used for the following functions in this mode. • 8-bit resolution interval timer • 8-bit resolution square wave output (timer 40 only) (2) 16-bit timer counter mode (cascade connection mode) These timers can be used for 16-bit timer operations via a cascade connection. The timer can be used for the following functions in this mode. • 16-bit resolution interval timer • 16-bit resolution square wave output (3) Carrier generator mode In this mode the carrier clock generated by timer 40 is output in the cycle set by timer 30. (4) PWM output mode In this mode, a pulse with an arbitrary duty ratio, which is set by timer 40, is output. Preliminary Product Information U14673EJ1V0PM00 31 µPD789322,789324,789326,789327 5.3.2 Configuration of 8-bit timer 30, 40 8-bit timers 30 and 40 consist of the following hardware. Table 5-6. Configuration of 8-Bit Timer 30, 40 Item Configuration Timer counter 8 bits × 2 (TM30, TM40) Registers Compare registers: 8 bits × 3 (CR30, CR40, CRH40) Timer outputs 1 (TO40) Control registers 8-bit timer mode control register 30 (TMC30) 8-bit timer mode control register 40 (TMC40) Carrier generator output control register 40 (TCA40) Port mode register 6 (PM6) 32 Preliminary Product Information U14673EJ1V0PM00 Figure 5-11. Block Diagram of Timer 30 Internal bus 8-bit timer mode control registedr 30 (TMC30) TCE30 TCL301 TCL300 TMD300 Selector To Figure 5-12 (G) Timer 30 match signal (in carrier generator mode) Match (from Figure 5-12 (B)) Carrier clock (in carrier generator mode) or timer 40 output signal (in other than carrier generator mode) (from Figure 5-12 (C)) Selector fX/26 fX/28 Timer 40 interrupt request signal Selector Bit 7 of TM40 (from Figure 5-12 (A)) 8-bit timer counter 30 (TM30) OVF Clear Internal reset signal From Figure 5-12 (D) Count operation start signal (for cascade connection) Selector Cascade connection mode INTTM30 From Figure 5-12 (E) Timer 40 match signal (in cascade connection mode) To Figure 5-12 (F) 33 Timer 30 match signal (in cascade connection mode) µPD789322,789324,789326,789327 Preliminary Product Information U14673EJ1V0PM00 8-bit compare register 30 (CR30) Decoder 34 Figure 5-12. Block Diagram of Timer 40 Internal bus Carrier generator output control register 40 (TCA40) 8-bit timer mode control register 40 (TMC40) 8-bit H width compare register 40 (CRH40) TCE40 TCL402 TCL401 TCL400 TMD401 TMD400 TOE40 8-bit compare register 40 (CR40) RMC40 NRZB40 NRZ40 Decoder From Figure 5-11 (G) Timer counter match signal from timer 30 (in carrier generator mode) Selector To Figure 5-11 (C) Carrier clock (in carrier generator mode) or timer 40 output signal (in other than carrier generator mode) 8-bit timer counter 40 (TM40) Prescaler 2 fX/2 fX/23 Clear Selector fX/22 fX/2 TO40/P60 OVF Carrier generator mode PWM mode Reset 4 fX/2 Cascade connection mode To Figure 5-11 (A) Bit 7 of TM40 (in cascade connection mode) Internal reset signal INTTM40 To Figure 5-11 (D) Count operation start signal to timer 30 (in cascade connection mode) To Figure 5-11 (E) TM40 timer counter match signal (in cascade connection mode) To Figure 5-11 (F) TM30 match signal (in cascade connection mode) Note Refer to Figure 5-13 for details. To Figure 5-11 (B) Timer 40 interrupt request signal count clock input signal to TM30 µPD789322,789324,789326,789327 Preliminary Product Information U14673EJ1V0PM00 fX Output control circuitNote F/F Match µPD789322,789324,789326,789327 Figure 5-13. Block Diagram of Output Control Circuit (Timer 40) TOE40 RMC40 NRZ40 P60 PM60 Selector output latch F/F TO40/P60 Carrier clock (in carrier generator mode) or timer 40 output signal (in other than carrier generator mode) Carrier generator mode (1) 8-bit compare register 30 (CR30) A value specified in CR30 is compared with the count value in 8-bit timer counter 30 (TM30), and if they match, an interrupt request (INTTM30) is generated. CR30 is set using an 8-bit memory manipulation instruction. RESET input makes this register undefined. Caution CR30 cannot be used in carrier generator mode or PWM output mode. (2) 8-bit compare register 40 (CR40) A value specified in CR40 is compared with the count value in 8-bit timer counter 40 (TM40), and if they match, an interrupt request (INTTM40) is generated. When operating as a 16-bit timer in cascade connection with TM30, an interrupt request (INTTM40) is only generated if both CR30 and TM30, and CR40 and TM40 match simultaneously (INTTM30 is not issued). CR40 is set using an 8-bit memory manipulation instruction. RESET input makes this register undefined. (3) 8-bit H width compare register (CRH40) In carrier generator mode or PWM output mode, a timer output high-level width can be set by writing a value to CRH40. CRH40 is set using an 8-bit memory manipulation instruction. RESET input makes this register undefined. Preliminary Product Information U14673EJ1V0PM00 35 µPD789322,789324,789326,789327 (4) 8-bit timer counter 30, 40 (TM30, TM40) This is an 8-bit register for counting the count pulses. TM30 and TM40 can be read with a 1-bit or 8-bit memory manipulation instruction. RESET input sets these registers to 00H. The conditions under which TM30 and TM40 are cleared to 00H are listed below. (a) Discrete mode (i) TM30 • Upon a reset • When TCE30 (bit 7 of 8-bit timer mode control register 30 (TMC30)) is cleared to 0 • Upon a match between TM30 and CR30 • If the TM30 count value overflows (ii) TM40 • Upon a reset • When TCE40 (bit 7 of 8-bit timer mode control register 40 (TMC40)) is cleared to 0 • Upon a match between TM40 and CR40 • If the TM40 count value overflows (b) Cascade connection mode (TM30 and TM40 cleared to 00H simultaneously) • Upon a reset • When the TCE40 flag is cleared to 0 • Upon a simultaneous match between TM30 and CR30, and TM40 and CR40 • If the TM30 and TM40 count values overflow simultaneously (c) Carrier generator/PWM output mode (TM40 only) • Upon a reset • When the TCE40 flag is cleared to 0 • Upon a match between TM40 and CR40 • Upon a match between TM40 and CRH40 • If the TM40 count value overflows 36 Preliminary Product Information U14673EJ1V0PM00 µPD789322,789324,789326,789327 5.3.3 8-bit timer 30, 40 control registers 8-bit timers 30 and 40 are controlled by the following 4 registers. • 8-bit timer mode control register 30 (TMC30) • 8-bit timer mode control register 40 (TMC40) • Carrier generator output control register 40 (TCA40) • Port mode register 6 (PM6) Preliminary Product Information U14673EJ1V0PM00 37 µPD789322,789324,789326,789327 (1) 8-bit timer mode control register 30 (TMC30) This register is used to control the timer 30 count clock and operation mode settings. TMC30 is set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 00H. Figure 5-14. Format of 8-Bit Timer Mode Control Register 30 Symbol <7> 6 5 4 3 2 1 0 Address After reset R/W TMC30 TCE30 0 0 TCL301 TCL300 0 TMD300 0 FF65H 00H R/W TM30 count control operation TCE30 0 TM30 count value cleared and operation stopped 1 Count operation starts TCL301 0 TCL300 0 Note 1 Timer 30 count clock selection 6 fX/2 8 (78.1 kHz) 0 1 fX/2 1 0 Timer 40 match signal 1 1 Carrier clock (in carrier generator mode) or timer 40 output signal (in other than carrier generator mode) TMD300 TMD401 TMD400 0 0 0 Discrete mode 1 0 1 Cascade connection mode 0 1 1 Carrier generator mode 0 1 0 PWM output mode Other than above (19.5 kHz) Note 2 Timer 30, timer 40 operation mode selection Setting prohibited Notes 1. The TCE30 setting will be ignored in cascade mode because in this case the count operation is controlled by TCE40 (bit 7 of TMC40). 2. The operation mode selection is made using a combination of TMC30 and TMC40 register settings. Caution In cascade connection mode, the timer 40 output signal is forcibly selected for the count clock. Remarks 1. fX: Main system clock oscillation frequency 2. The parenthesized values apply to operation at fX = 5.0 MHz 38 Preliminary Product Information U14673EJ1V0PM00 µPD789322,789324,789326,789327 (2) 8-bit timer mode control register 40 (TMC40) This register is used to control the timer 40 count clock and operation mode settings. TMC40 is set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 00H. Figure 5-15. Format of 8-Bit Timer Mode Control Register 40 Symbol <7> 6 5 4 3 2 1 <0> Address After reset R/W TMC40 TCE40 0 TCL402 TCL401 TCL400 TMD401 TMD400 TOE40 FF69H 00H R/W Note 1 TCE40 TM40 count control operation 0 TM40 count value cleared and operation stopped (in cascade connection mode, the count value of TM30 is cleared at the same time) 1 Count operation starts (in cascade connection mode, the count operation of TM30 starts at the same time) TCL402 TCL401 TCL400 0 0 0 fX (5 MHz) 0 0 1 fX/2 (1.25 MHz) 0 1 0 fX/2 (2.5 MHz) 0 1 1 fX/2 (1.25 MHz) 1 0 0 fX/2 (625 kHz) 1 0 1 fX/2 (313 kHz) Other than above Timer 40 count clock selection 2 2 3 4 Setting prohibited Note 2 Timer 30, timer 40 operation mode selection TMD300 TMD401 TMD400 0 0 0 Discrete mode 1 0 1 Cascade connection mode 0 1 1 Carrier generator mode 0 1 0 PWM output mode Other than above Setting prohibited TOE40 Timer output control 0 Output disabled (port mode) 1 Output enabled Notes 1. The TCE30 setting will be ignored in cascade mode because in this case the count operation is controlled by TCE40 (bit 7 of TMC40). 2. The operation mode selection is made using a combination of TMC30 and TMC40 register settings. Remarks 1. fX: Main system clock oscillation frequency 2. The parenthesized values apply to operation at fX = 5.0 MHz Preliminary Product Information U14673EJ1V0PM00 39 µPD789322,789324,789326,789327 (3) Carrier generator output control register 40 (TCA40) This register is used to set the timer output data in the carrier generator mode. TCA40 is set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 00H. Figure 5-16. Format of Carrier Generator Output Control Register 40 Symbol 7 6 5 4 3 <2> <1> <0> Address After reset R/W TCA40 0 0 0 0 0 RMC40 NRZB40 NRZ40 FF6AH 00H W RMC40 Remote controller output control 0 When NRZ40 = 1, a carrier pulse is output to the TO40/P60 pin 1 When NRZ40 = 1, a high level is output to the TO40/P60 pin NRZB40 This bit stores the data that NRZ40 will output next. Data is transferred to NRZ40 upon the generation of a timer 30 match signal. NRZ40 No return, zero data 0 A low level is output (the carrier clock is stopped) 1 A carrier pulse is output Caution TCA40 cannot be set with a 1-bit memory manipulation instruction. Be sure to set it with an 8-bit memory manipulation instruction. (4) Port mode register 6 (PM6) This register is used to set port 6 to input or output in 1-bit units. When the TO40/P60 pin is used as a timer output, set the PM60 and P60 output latches to 0. PM6 is set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to FFH. Figure 5-17. Format of Port Mode Register 6 Symbol 7 6 5 4 3 2 1 0 Address After reset R/W PM6 1 1 1 1 1 1 PM61 PM60 FF26H FFH R/W PM6n 40 Input/output mode of pin P6n (n = 0, 1) 0 Output mode (output buffer on) 1 Input mode (output buffer off) Preliminary Product Information U14673EJ1V0PM00 µPD789322,789324,789326,789327 5.4 Watch Timer 5.4.1 Watch timer functions The watch timer has the following functions. • Watch timer • Interval timer The watch and interval timers can be used at the same time. Figure 5-18 shows a block diagram of the watch timer. Figure 5-18. Watch Timer Block Diagram fXT 5-bit counter 9-bit prescaler fW fW 24 fW 25 fW 26 fW 27 fW 28 fW 29 INTWT Clear Selector fX/2 Selector Clear 7 INTWTI WTM7 WTM6 WTM5 WTM4 WTM1 WTM0 Watch timer mode control register (WTM) Internal bus Preliminary Product Information U14673EJ1V0PM00 41 µPD789322,789324,789326,789327 (1) Watch timer An interrupt request (INTWT) is generated at 0.5-second intervals using the 4.19-MHz main system clock or 32.768-kHz subsystem clock. Caution When the main system clock is operating at 5.0 MHz, it cannot be used to generate a 0.5-second interval. In this case, the subsystem clock, which operates at 32.768 kHz, should be used instead. (2) Interval timer The interval timer is used to generate an interrupt request (INTWTI) at preset intervals. Table 5-7. Interval Time of Interval Timer Interval Time 4 5 2 × 1/fW 2 × 1/fW 6 2 × 1/fW 7 2 × 1/fW 8 2 × 1/fW 9 2 × 1/fW At fX = 5.0 MHz Operation At fX = 4.19 MHz Operation At fXT = 32.768 kHz Operation 409.6 µs 488 µs 488 µs 819.2 µs 977 µs 977 µs 1.64 ms 1.95 ms 1.95 ms 3.28 ms 3.91 ms 3.91 ms 6.55 ms 7.81 ms 7.81 ms 13.1 ms 15.6 ms 15.6 ms 7 Remarks 1. fW: Watch timer clock frequency (fX/2 or fXT) 2. fX: Main system clock oscillation frequency 3. fXT: Subsystem clock oscillation frequency 5.4.2 Watch timer configuration The watch timer consists of the following hardware. Table 5-8. Watch Timer Configuration Item Configuration Counter 5 bits × 1 Prescaler 9 bits × 1 Control register Watch timer mode control register (WTM) 42 Preliminary Product Information U14673EJ1V0PM00 µPD789322,789324,789326,789327 5.4.3 Watch timer control register The following register controls the watch timer. • Watch timer mode control register (WTM) (1) Watch timer mode control register (WTM) This register is used to enable/disable the count clock and operation of the watch timer and set the interval time of the prescaler and operation control of the 5-bit counter. WTM is set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 00H. Figure 5-19. Format of Watch Timer Mode Control Register Symbol 7 6 5 4 3 2 <1> <0> Address After reset R/W WTM WTM7 WTM6 WTM5 WTM4 0 0 WTM1 WTM0 FF4AH 00H R/W WTM7 Watch timer count clock (fW) selection 7 0 fX/2 (39.1 kHz) 1 fXT WTM6 (32.768 kHz) WTM5 WTM4 Prescaler interval time selection 4 0 0 0 2 /fW 0 0 1 2 /fW 0 1 0 2 /fW 0 1 1 2 /fW 1 0 0 2 /fW 1 0 1 2 /fW Other than above 5 6 7 8 9 Setting prohibited WTM1 5-bit counter operation control 0 Cleared after operation stopped 1 Start WTM0 Watch timer operation enable 0 Operation stopped (both prescaler and timer cleared) 1 Operation enabled 7 Remarks 1. fW: Watch timer clock frequency (fX/2 or fXT) 2. fX: Main system clock oscillation frequency 3. fXT: Subsystem clock oscillation frequency 4. The parenthesized values apply to operation at fX = 5.0 MHz or fXT = 32.768 kHz. Preliminary Product Information U14673EJ1V0PM00 43 µPD789322,789324,789326,789327 5.5 Watchdog Timer 5.5.1 Watchdog timer functions The watchdog timer has the following functions. (1) Watchdog timer The watchdog timer is used to detect a program runaway. If a runaway is detected, either a non-maskable interrupt or the RESET signal can be generated. (2) Interval timer The interval timer is used to generate interrupts at preset intervals. 5.5.2 Watchdog timer configuration The watchdog timer consists of the following hardware. Table 5-9. Watchdog Timer Configuration Item Configuration Control register Watchdog timer mode register (WDTM) Figure 5-20. Watchdog Timer Block Diagram Internal bus WDTMK 7-bit counter Clear Control circuit fX 24 WDTIF RESET INTWDT non-maskable interrupt request RUN WDTM4 WDTM3 Watchdog timer mode register (WDTM) Internal bus 44 INTWDT maskable interrupt request Preliminary Product Information U14673EJ1V0PM00 µPD789322,789324,789326,789327 5.5.3 Watchdog timer control register The watchdog timer is controlled by the following register. • Watchdog timer mode register (WDTM) (1) Watchdog timer mode register (WDTM) This register is used to set the watchdog timer operation mode and whether to enable or disable counting. WDTM is set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 00H. Figure 5-21. Format of Watchdog Timer Mode Register Symbol <7> 6 5 4 3 2 1 0 Address After reset R/W WDTM RUN 0 0 WDTM4 WDTM3 0 0 0 FFF9H 00H R/W Note 1 Watchdog timer operation selection RUN 0 Counting stopped 1 Counter cleared and counting starts Note 2 Watchdog timer operation mode selection WDTM4 WDTM3 0 0 Operation stopped 0 1 Interval timer mode (when an overflow occurs, a maskable interrupt is generated) 1 0 Watchdog timer mode 1 (when an overflow occurs, a non-maskable interrupt is generated) 1 1 Watchdog timer mode 2 (when an overflow occurs, a reset operation is activated) Note 3 Notes 1. Once the RUN bit has been set (1), it is impossible to clear it (0) by software. Consequently, once counting begins, it cannot be stopped by any means other than RESET input. 2. Once WDTM3 and WDTM4 have been set (1), it is impossible to clear them (0) by software. 3. The interval timer starts operating as soon as the RUN bit is set to 1. Cautions 1. When the RUN bit is set to 1, and the watchdog timer is cleared, the actual overflow time will be up to 0.8% shorter than the time specified by the watchdog timer clock selection register. 2. To use watchdog timer mode 1 or 2, be sure to set WDTM4 to 1 after confirming that WDTIF (bit 0 of interrupt request flag 0 (IF0)) has been set to 0. If WDTIF is 1, selecting watchdog timer mode 1 or 2 causes a non-maskable interrupt to be generated the instant rewriting ends. Preliminary Product Information U14673EJ1V0PM00 45 µPD789322,789324,789326,789327 5.6 Serial Interface 10 5.6.1 Functions of serial interface 10 Serial interface 10 has the following two modes. • Operation stopped mode • 3-wire serial I/O mode (1) Operation stopped mode This mode is used to minimize power consumption when serial transfer is not performed. (2) 3-wire serial I/O mode (switchable between MSB-first and LSB-first transmission) This mode is used to transmit 8-bit data, using three lines: a serial clock line (SCK10) and two serial data lines (SI10 and SO10). As 3-wire serial I/O mode supports simultaneous transmission and reception, the time required for data processing can be reduced. In 3-wire serial I/O mode, it is possible to select whether 8-bit data transmission begins with the MSB or LSB, allowing serial interface 10 to be connected to any device regardless of whether that device is designed for MSB-first or LSB-first transmission. 3-wire serial I/O mode is effective for connecting peripheral I/O circuits and display controllers having conventional clock synchronous serial interfaces, such as those of the 75XL, 78K, and 17K Series devices. 5.6.2 Configuration of serial interface 10 Serial interface 10 consists of the following hardware. Table 5-10. Configuration of Serial Interface 10 Item Configuration Register Transmission/reception shift register 10 (SIO10) Control register Serial operation mode register 10 (CSIM10) (1) Transmission/reception shift register 10 (SIO10) This is an 8-bit register used for parallel/serial data conversion and for serial transmission or reception in synchronization with the serial clock. SIO10 is set using an 8-bit memory manipulation instruction. RESET input makes this register undefined. 46 Preliminary Product Information U14673EJ1V0PM00 Figure 5-22. Block Diagram of Serial Interface 10 Internal bus Serial operation mode register 10 (CSIM10) CSIE10 TPS101 TPS100 DIR10 CSCK10 SI10/P22 SO10/P21 PM21 Serial clock counter Interrupt request generator PM20 F/F Selector Clock control circuit Selector SCK10/P20 fX/22 fX/23 TPS101 TPS100 INTCSI10 47 µPD789322,789324,789326,789327 Preliminary Product Information U14673EJ1V0PM00 Transmission/reception shift register 10 (SIO10) µPD789322,789324,789326,789327 5.6.3 Control register for serial interface 10 Serial interface 10 is controlled by the following register. • Serial operation mode register 10 (CSIM10) Figure 5-23. Format of Serial Operation Mode Register 10 Symbol <7> 6 5 4 3 2 1 0 Address After reset R/W CSIM10 CSIE10 0 TPS101 TPS100 0 DIR10 CSCK10 0 FF72H 00H R/W CSIE10 3-wire serial I/O mode operation control 0 Operation stopped 1 Operation enabled TPS101 TPS100 Selection of count clock when internal clock selected 2 0 0 fX/2 (1.25 MHz) 0 1 fX/2 (625 kHz) Other than above 3 Setting prohibited DIR10 First-bit specification 0 MSB 1 LSB CSCK10 SIO10 clock selection 0 External clock pulse input to the SCK10 pin 1 Internal clock selected with TPS100, TPS101 Cautions 1. Bits 0, 3 and 6 must be fixed to 0. 2. Be sure to switch to operation mode after stopping the serial transmission/reception operation. Remarks 1. fX: Main system clock oscillation frequency 2. The parenthesized values apply to operation at fX = 5.0 MHz. 48 Preliminary Product Information U14673EJ1V0PM00 µPD789322,789324,789326,789327 Table 5-11. Operation Mode Settings for Serial Interface 10 (1) Operation stopped mode CSIM10 CSIE10 0 PM22 P22 PM21 P21 PM20 P20 First Bit Shift Clock P22/SI10 Pin Function P21/SO10 Pin Function P20/SCK10 Pin Function DIR10 CSCK10 × × ×Note 1 ×Note 1 ×Note 1 ×Note 1 ×Note 1 ×Note 1 Other than above − − P22 P21 P20 Setting prohibited (2) 3-wire serial I/O mode CSIM10 CSIE10 1 PM22 P22 PM21 P21 PM20 P20 First Bit Shift Clock P22/SI10 Pin Function P21/SO10 Pin Function P20/SCK10 Pin Function DIR10 CSCK10 0 1 1 × 1 0 1 0 1 × 1 0 1 0 1Note 2 ×Note 2 0 1 Other than above MSB External clock LSB SI10Note 2 SO10 (CMOS output) SCK10 input Internal clock SCK10 output External clock SCK10 input Internal clock SCK10 output Setting prohibited Notes 1. Can be used freely as a port 2. Can be used as P22 (CMOS I/O) only when transmitting Remark ×: don’t care Preliminary Product Information U14673EJ1V0PM00 49 µPD789322,789324,789326,789327 5.7 LCD Controller/Driver 5.7.1 LCD controller/driver functions The LCD controller/driver incorporated in the µPD789322, 789324, 789326, and 789327 has the following features. (1) Segment and common signals based on the automatic reading of the display data memory can be automatically output (2) Four types of frame frequencies are selectable (3) 24 segment signal outputs (S0 to S23), 4 common signal outputs (COM0 to COM3) (4) Operation with a subsystem clock is possible The maximum number of displayable pixels is shown in Table 5-12 below. Table 5-12. Maximum Number of Display Pixels Bias Method Time Division 1/3 4 Common Signals Used COM0 to COM3 Note The LCD panel of the figure Maximum Number of Display Pixels 96 (24 segments × 4 commons) consists of 12 rows with 2 segments per row. 5.7.2 LCD controller/driver configuration The LCD controller/driver consists of the following hardware. Table 5-13. Configuration of LCD Controller/Driver Item Configuration Display outputs Segment signals: 24 Common signals: 4 Control registers LCD display mode register 0 (LCDM0) LCD clock control register 0 (LCDC0) Port function register 8 (PF8) 50 Preliminary Product Information U14673EJ1V0PM00 µPD789322,789324,789326,789327 The correspondence with the LCD display RAM is shown in Figure 5-24 below. Figure 5-24. Correspondence with LCD Display RAM Address Bit Segment 7 6 5 4 3 FA17H 0 0 0 0 → S23 FA16H 0 0 0 0 → S22 FA15H 0 0 0 0 → S21 FA14H 0 0 0 0 → S20 FA13H 0 0 0 0 → S19 FA12H 0 0 0 0 → S18 FA11H 0 0 0 0 → S17 FA10H 0 0 0 0 → S16 FA0FH 0 0 0 0 → S15 FA0EH 0 0 0 0 → S14 FA0DH 0 0 0 0 → S13 FA0CH 0 0 0 0 → S12 FA0BH 0 0 0 0 → S11 FA0AH 0 0 0 0 → S10 FA09H 0 0 0 0 → S9 FA08H 0 0 0 0 → S8 FA07H 0 0 0 0 → S7 FA06H 0 0 0 0 → S6 FA05H 0 0 0 0 → S5 FA04H 0 0 0 0 → S4 FA03H 0 0 0 0 → S3 FA02H 0 0 0 0 → S2 FA01H 0 0 0 0 → S1 FA00H 0 0 0 0 → S0 ↑ Common COM3 2 1 0 ↑ ↑ ↑ COM2 COM1 COM0 Remark Bits 4 to 7 are fixed to 0. Preliminary Product Information U14673EJ1V0PM00 51 52 Figure 5-25. LCD Controller/Driver Block Diagram Internal bus LCD display mode register 0 (LCDM0) Display data memory LCDON0 VAON0 LIPS0 LCDC03 LCDC02 LCDC01 LCDC00 FA00H 76543210 FA11H FA16H 76543210 . . . 76543210 FA17H 6543210 2 2 fX/2 fX/26 fX/27 fXT Selector PF85 PF84 PF83 PF82 PF81 PF80 5 fCLK fCLK 26 Prescaker fCLK 27 fCLK 28 fCLK 29 LCD clock fLCD selection circuit 3210 Selector 3210 Selector Timing controller 3210 Selector LCDON0 LCDON0 Segment driver LCDON0 Segment driver Segment driver PF85 LCD drive voltage control circuit RLCD RLCD VSS 1 VLC0 3 3210 Selector LCDON0 Segment driver PF80 . . . . . Common driver RLCD 2 VLC0 3 VLC0 COM0 COM1 COM2 COM3 S0 . . . . . . . . . . S17/P85 . . . . . S22/P80 S23 µPD789322,789324,789326,789327 Preliminary Product Information U14673EJ1V0PM00 Port function register 8 (PF8) . . . . LCD clock control register 0 (LCDC0) µPD789322,789324,789326,789327 5.7.3 LCD controller/driver control registers The LCD controller/driver is controlled by the following three registers. • LCD display mode register 0 (LCDM0) • LCD clock control register 0 (LCDC0) • Port function register 8 (PF8) (1) LCD display mode register 0 (LCDM0) This register is used to enable/disable operation, and set the operation mode and the supply of power for LCD drive. LCDM0 is set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 00H. Figure 5-26. Format of LCD Display Mode Register 0 Symbol <7> LCDM0 LCDON0 <6> 5 <4> 3 2 1 0 Address After reset R/W VAON0 0 LIPS0 0 0 0 0 FFB0H 00H R/W LCDON0 LCD display enable/disable 0 Display off (all segment outputs are unselected for signal output) 1 Display on Note LCD controller/driver operation mode VAON0 0 No internal booster (for 2.7- to 5.5-V display) 1 Internal booster enabled (for 1.8- to 5.5-V display) Supply of power for LCD drive LIPS0 0 Power not supplied for LCD drive 1 Power supplied for LCD drive Note Note To reduce power consumption when the LCD display is not being used, set VAON0 and LIPS0 to 0. Cautions 1. Always set bits 0 to 3 and 5 to 0. 2. When manipulating VAON0, observe following procedure. A. When internal booster is stopped after changing to the display off condition from the display on condition 1) Set the display off condition by setting LCDON0 = 0. 2) Set all segment buffers and common buffers to output disabled by setting LIPS0 = 0. 3) Stop the booster by setting VAON0 = 0. B. When the booster is stopped in the display on condition This is prohibited. Be sure to stop the booster after changing to the display off condition. C. When the display is turned on from the booster-stoped condition 1) Wait about 500 ms after starting the booster by setting VAON0 = 1. 2) Set all segment buffers and common buffers to signal output unselected by setting LIPS0 = 1. 3) Set the display on condition by setting LCDON0 = 1. Preliminary Product Information U14673EJ1V0PM00 53 µPD789322,789324,789326,789327 (2) LCD clock control register (LCDC0) This register is used to set the internal and LCD clocks. The frame frequency is determined by the number of LCD clock time divisions. LCDC0 is set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 00H. Figure 5-27. Format of LCD Clock Control Register 0 Symbol 7 6 5 4 3 2 1 0 Address After reset R/W LCDC0 0 0 0 0 LCDC03 LCDC02 LCDC01 LCDC00 FFB2H 00H R/W LCDC03 LCDC02 0 0 0 Internal clock (fCLK) selection fXT 1 fX/2 1 LCDC01 LCDC00 (156.3 kHz) 6 fX/2 0 1 (32.768 kHz) 5 1 Note (78.1 kHz) 7 fX/2 (39.1 kHz) LCD clock (fLCD) selection 6 0 0 fCLK/2 0 1 fCLK/2 1 0 fCLK/2 1 1 fCLK/2 7 8 9 Note Select fX so that a clock of at least 32 kHz is set for the internal clock fCLK. Remarks 1. fX: Main system clock oscillation frequency 2. fXT: Subsystem clock oscillation frequency 3. The parenthesized values apply to operation at fX = 5.0 MHz or fXT = 32.768 kHz Caution Always set bits 4 to 7 to 0. Examples of the frame frequencies when the internal clock is fXT (32.768 kHz) are shown in Table 5-14 below. Table 5-14. Frame Frequency (Hz) LCD Clock (fLCD) Time Division 4 54 9 8 7 6 fXT/2 fXT/2 fXT/2 fXT/2 (64 Hz) (128 Hz) (256 Hz) (512 Hz) 16 32 64 128 Preliminary Product Information U14673EJ1V0PM00 µPD789322,789324,789326,789327 (3) Port function register 8 (PF8) This register is used to select whether S17/P85 to S22/P80 are used as LCD segment signal outputs or general-purpose ports. PF8 is set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 00H. Figure 5-28. Format of Port Function Register 8 Symbol 7 6 5 4 3 2 1 0 Address After reset R/W PF8 0 0 PF85 PF84 PF83 PF82 PF81 PF80 FF58H 00H R/W PF8n Port function of P8n (n = 0 to 5) 0 Operates as a general-purpose port 1 Operates as an LCD segment signal output Preliminary Product Information U14673EJ1V0PM00 55 µPD789322,789324,789326,789327 6. INTERRUPT FUNCTION 6.1 Interrupt Types Two types of interrupts are supported. (1) Non-maskable interrupts Non-maskable interrupt requests are acknowledged unconditionally, i.e. even when interrupts are disabled. These interrupts take precedence over all other interrupts and are not subject to interrupt priority control. A non-maskable interrupt causes the generation of the standby release signal. An interrupt from the watchdog timer is the only non-maskable interrupt source supported in the µPD789322, 789324, 789326, and 789327. (2) Maskable interrupts Maskable interrupts are subject to mask control. If two or more maskable interrupts occur simultaneously, the default priority listed in Table 6-1 applies. A maskable interrupt causes the generation of the standby release signal. Maskable interrupts from 2 external and 6 internal sources are supported in the µPD789322, 789324, 789326, and 789327. 6.2 Interrupt Sources and Configuration The µPD789322, 789324, 789326, and 789327 support a total of 9 maskable and non-maskable interrupt sources (see Table 6-1). 56 Preliminary Product Information U14673EJ1V0PM00 µPD789322,789324,789326,789327 Table 6-1. Interrupt Sources Interrupt Type Default Note 1 Priority Interrupt Source Name Trigger Internal/ External Vector Table Address Basic Configuration Note 2 Type 0004H (A) Non-maskable − INTWDT Watchdog timer overflow (with watchdog timer mode 1 selected) Maskable 0 INTWDT Watchdog timer overflow (with interval timer mode selected) 1 INTP0 Pin input edge detection External 0006H (C) 2 INTCSI10 End of serial interface 10 3-wire SIO transfer reception Internal 0008H (B) 3 INTWT Watch timer interrupt 000AH 4 INTTM30 Generation of 8-bit timer 30 matching signal 000CH 5 INTTM40 Generation of 8-bit timer 40 matching signal 000EH 6 INTKR00 Key return signal detection External 0010H (C) 7 INTWTI Watch timer interval timer interrupt Internal 0012H (B) Internal (B) Notes 1. Default priority is the priority order when more than one maskable interrupt request is generated at the same time. 0 is the highest priority and 7 is the lowest. 2. Basic configuration types (A), (B), and (C) correspond to (A), (B), and (C) in Figure 6-1. Remark Only one of the two watchdog timer interrupt sources, non-maskable or maskable (internal), can be selected. Preliminary Product Information U14673EJ1V0PM00 57 µPD789322,789324,789326,789327 Figure 6-1. Basic Configuration of Interrupt Function (A) Internal non-maskable interrupt Internal bus Vector table address generator Interrupt request Standby release signal (B) Internal maskable interrupt Internal bus MK Interrupt request IE Vector table address generator IF Standby release signal (C) External maskable interrupt Internal bus INTM0, KRM00 Interrupt request MK Edge detection circuit IE IF Vector table address generator Standby release signal INTM0: External interrupt mode register 0 KRM00: Key return mode register 00 58 IF: Interrupt request flag IE: Interrupt enable flag MK: Interrupt mask flag Preliminary Product Information U14673EJ1V0PM00 µPD789322,789324,789326,789327 6.3 Interrupt Function Control Registers Interrupts are controlled by the following five registers. • Interrupt request flag register 0 (IF0) • Interrupt mask flag register 0 (MK0) • External interrupt mode register 0 (INTM0) • Program status word (PSW) • Key return mode register 00 (KRM00) Table 6-2 lists the interrupt requests and the corresponding interrupt request and interrupt mask flags. Table 6-2. Interrupt Request Signals and Corresponding Flags Interrupt Request Signal INTWDT INTP0 INTCSI0 INTWT INTTM30 INTTM40 INTKR00 INTWTI Interrupt Request Flag WDTIF PIF0 CSIIF0 WTIF TMIF30 TMIF40 KRIF00 WTIIF Preliminary Product Information U14673EJ1V0PM00 Interrupt Mask Flag WDTMK PMK0 CSIMK0 WTMK TMMK30 TMMK40 KRMK00 WTIMK 59 µPD789322,789324,789326,789327 (1) Interrupt request flag register 0 (IF0) An interrupt request flag is set (1) when the corresponding interrupt request is generated, or when an instruction is executed. It is cleared (0) when the interrupt request is acknowledged, when the RESET signal is input, or when an instruction is executed. IF0 is set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 00H. Figure 6-2. Format of Interrupt Request Flag Register 0 Symbol <7> <6> <5> <4> <3> <2> <1> <0> Address After reset R/W IF0 WTIIF KRIF00 TMIF40 TMIF30 WTIF CSIIF0 PIF0 WDTIF FFE0H 00H R/W Interrupt request flag ××IF× 0 No interrupt request signal generated 1 An interrupt request signal is generated and an interrupt request made Cautions 1. The WDTIF flag can be read/written only when the watchdog timer is being used as an interval timer. It must be cleared to 0 if the watchdog timer is used in watchdog timer mode 1 or 2. 2. Because P61 functions alternately as an external interrupt, when the output level changes after the output mode of the port function is specified, the interrupt request flag will be inadvertently set. Therefore, be sure to preset the interrupt mask flag (PMK0) before using the port in output mode. 60 Preliminary Product Information U14673EJ1V0PM00 µPD789322,789324,789326,789327 (2) Interrupt mask flag register 0 (MK0) Interrupt mask flags are used to enable and disable the corresponding maskable interrupts. MK0 is set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to FFH. Figure 6-3. Format of Interrupt Mask Flag Register 0 Symbol <7> MK0 WTIMK <6> <5> <4> KRMK00 TMMK40 TMMK30 <3> <2> <1> <0> Address After reset R/W WTMK CSIMK0 PMK0 WDTMK FFE4H FFH R/W Interrupt servicing control ××MK 0 Interrupt servicing enabled 1 Interrupt servicing disabled Cautions 1. When the watchdog timer is being used in watchdog timer mode 1 or 2, any attempt to read the WDTMK flag results in an undefined value being detected. 2. Because P61 functions alternately as an external interrupt, when the output level changes after the output mode of the port function is specified, the interrupt request flag will be inadvertently set. Therefore, be sure to preset the interrupt mask flag (PMK0) before using the port in output mode. Preliminary Product Information U14673EJ1V0PM00 61 µPD789322,789324,789326,789327 (3) External interrupt mode register 0 (INTM0) This register is used to specify the valid edge for INTP0. INTM0 is set using an 8-bit memory manipulation instruction. RESET input sets this register to 00H. Figure 6-4. Format of External Interrupt Mode Register 0 Symbol 7 6 5 4 3 2 1 0 Address After reset R/W INTM0 0 0 0 0 ES01 ES00 0 0 FFECH 00H R/W ES01 ES00 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both rising and falling edges INTP0 valid edge selection Cautions 1. Always set bits 0, 1, and 4 to 7 to 0. 2. Before setting INTM0, set (1) the interrupt mask flag (PMK0) to disable interrupts. To enable interrupts, clear (0) the interrupt request flag (PIF0), then clear (0) the interrupt mask flag (PMK0). 62 Preliminary Product Information U14673EJ1V0PM00 µPD789322,789324,789326,789327 (4) Program status word (PSW) The program status word is used to hold the instruction execution results and the current status of the interrupt requests. The IE flag, used to enable and disable maskable interrupts, is mapped to the PSW. The PSW can be read and written in 8-bit units, as well as in 1-bit units by using bit manipulation instructions and dedicated instructions (EI and DI). When a vector interrupt is acknowledged, the PSW is automatically saved to the stack, and the IE flag is reset (0). RESET input sets the PSW to 02H. Figure 6-5. Program Status Word Configuration Symbol 7 6 5 4 3 2 1 0 After reset PSW IE Z 0 AC 0 0 1 CY 02H Used in the execution of ordinary instructions IE Interrupt acknowledgement enable/disable 0 Disabled 1 Enabled Preliminary Product Information U14673EJ1V0PM00 63 µPD789322,789324,789326,789327 (5) Key return mode register 00 (KRM00) This register is used to set the pin that is to detect the key return signal (rising edge of port 4). KRM00 is set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 00H. Figure 6-6. Format of Key Return Mode Register 00 Symbol 7 6 5 4 3 2 1 0 Address After reset R/W KRM00 0 0 0 0 0 0 0 KRM000 FFF5H 00H R/W KRM000 Key return signal detection control 0 Key return signal not detected 1 Key return signal detected (port 4 falling edge detection) Cautions 1. Always set bits 1 to 7 to 0. 2. Before setting KRM00, set (1) bit 6 (KRMK00) of MK0 to disable interrupts. To enable interrupts, clear (0) KRMK00 after clearing (0) bit 6 (KRIF00) of IF0. 3. On-chip pull-up resistors are automatically connected in input mode to the pins specified for key return signal detection (P40 to P43). Although these resistors are disconnected when the mode changes to output, key return signal detection continues unchanged. Figure 6-7. Block Diagram of Falling Edge Detection Circuit Key return mode register 00 (KRM00) P40/KR00 P41/KR01 P42/KR02 P43/KR03 Selector Note Falling edge detection circuit KRIF00 setting signal Standby release signal KRMK00 Note For selecting the pin to be used as falling edge input. 64 Preliminary Product Information U14673EJ1V0PM00 µPD789322,789324,789326,789327 7. STANDBY FUNCTION 7.1 Standby Function A standby function is incorporated to minimize the system’s power consumption. There are two standby modes: HALT and STOP. The HALT and STOP modes are selected using the HALT and STOP instructions. (1) HALT mode In this mode, the CPU operating clock is stopped. The average current consumption can be reduced by intermittent operation combining this mode with the normal operation mode. (2) STOP mode In this mode, main system clock oscillation is stopped. All operations performed with the main system clock are suspended, thus minimizing power consumption. Caution When shifting to STOP mode, execute the STOP instruction after first stopping the operation of the hardware. Preliminary Product Information U14673EJ1V0PM00 65 µPD789322,789324,789326,789327 Table 7-1. Operation Statuses in HALT Mode Item HALT Mode Operation Status During Main System Clock Operation Subsystem Clock Operating Subsystem Clock Stopped Main system clock Can be oscillated CPU Operation stopped Ports (output latches) Status before HALT mode setting retained 8-bit timer 30, 40 Operable Watch timer Operable Watchdog timer Operable Power-on-clear circuit Operable Key return circuit Operable Serial interface 10 Operable LCD controller/driver Operable External interrupts Operable HALT Mode Operation Status During Subsystem Clock Operation Main System Clock Operating Main System Clock Stopped Oscillation stopped Operation stopped Note 1 Operable Note 2 Operable Operable Operation stopped Note 3 Operable Note 4 Notes 1, 4 Operable Note 4 Operable Notes 2, 4 Operable Note 5 Notes 1. Operation is enabled when the main system clock is selected 2. Operation is enabled when the subsystem clock is selected 3. Operation is enabled only when an external clock is selected 4. The HALT instruction can be set after display instruction execution 5. Operation is enabled only for a maskable interrupt that is not masked Table 7-2. Operation Statuses in STOP Mode Item STOP Mode Operation Status During Main System Clock Operation Subsystem Clock Operating Main system clock Oscillation stopped CPU Operation stopped Ports (output latches) Status before STOP mode setting retained 8-bit timer 30, 40 Operation stopped Watch timer Operable Watchdog timer Operation stopped Power-on-clear circuit Operable Key return circuit Operable Serial interface 10 Operable LCD controller/driver Operable External interrupts Note 1 Subsystem Clock Stopped Operation stopped Note 2 Note 1 Operation stopped Note 3 Operable Notes 1. Operation is enabled when the subsystem clock is selected. 2. Operation is enabled only when an external clock is selected. 3. Operation is enabled only for a maskable interrupt that is not masked 66 Preliminary Product Information U14673EJ1V0PM00 µPD789322,789324,789326,789327 7.2 Standby Function Control Register The oscillation stabilization time selection register (OSTS) is used to control the wait time from the time STOP mode is released by an interrupt request until oscillation stabilizes. OSTS is set using an 8-bit memory manipulation instruction. RESET input sets this register to 04H. Note that the time required for oscillation to stabilize after RESET input or the release of STOP mode by POC will be taken as the time selected by mask option (215/fX, or 217/fX) (refer to 9. MASK OPTION for mask option details) . Figure 7-1. Format of Oscillation Stabilization Time Selection Register Symbol 7 6 5 4 3 2 1 0 Address After reset R/W OSTS 0 0 0 0 0 OSTS2 OSTS1 OSTS0 FFFAH 04H R/W OSTS2 OSTS1 OSTS0 0 0 0 2 /fX (819 µs) 0 1 0 2 /fX (6.55 ms) 1 0 0 2 /fX (26.2 ms) Other than above Caution Oscillation stabilization time selection 12 15 17 Setting prohibited The wait time required after releasing STOP mode does not include the time (“a” in the following figure) required for the clock oscillation to restart after STOP mode is released, regardless of whether STOP mode is released by RESET input or interrupt. STOP mode release X1 pin voltage waveform a VSS Remarks 1. fX: Main system clock oscillation frequency 2. The parenthesized values apply to operation at fX = 5.0 MHz. Preliminary Product Information U14673EJ1V0PM00 67 µPD789322,789324,789326,789327 8. RESET FUNCTION 8.1 Reset Function The µPD789322, 789324, 789326, and 789327 can be reset using the following three signals. (1) External reset signal input via RESET pin (2) Internal reset by watchdog timer runaway time detection (3) Internal reset using power-on-clear circuit (POC) The external and internal reset signals are functionally equivalent. When RESET is input, program execution begins from the addresses written at addresses 0000H and 0001H. If a low-level signal is applied to the RESET pin, or if the watchdog timer overflows, a reset occurs, causing each item of the hardware to enter the states listed in Table 8-1. While a reset is being applied, or while the oscillation frequency is stabilizing immediately after the end of a reset sequence, each pin remains in the high-impedance state. If a high-level signal is applied to the RESET pin, the reset sequence is terminated, and program execution begins once the oscillation stabilization time has elapsed. A reset sequence caused by a watchdog timer overflow is terminated automatically and again program execution begins upon the elapse of the oscillation stabilization time. Reset by power-ON clear is cleared if the supply voltage rises beyond a specific level, and the program execution is started after the oscillation stabilization time has elapsed. Cautions 1. To use an external reset sequence, input a low-level signal to the RESET pin for at least 10 µs. 2. When a reset is used to release STOP mode, the data of when STOP mode was entered is retained during the reset sequence, except for the port pins, which are in the high-impedance state. 3. The oscillation stabilization time after RESET input or the release of STOP mode by POC can 15 17 be selected from 2 /fX or 2 /fX by mask option (refer to 9. MASK OPTION). Figure 8-1. Reset Function Block Diagram Power-on-clear circuit RESET Count clock VDD Reset control circuit Watchdog timer Reset signal Overflow Stop 68 Preliminary Product Information U14673EJ1V0PM00 Interrupt function µPD789322,789324,789326,789327 Table 8-1. Status of Hardware After Reset Hardware Program counter (PC) Note 1 Status After Reset Contents of reset vector table (0000H, 0001H) set Stack pointer (SP) Undefined Program status word (PSW) 02H RAM Data memory Undefined General-purpose registers Undefined Note 2 Note 2 Ports (P0 to P2, P4, P6, P8) (output latches) 00H Port mode registers (PM0 to PM2, PM4, PM6, PM8) FFH Port function register 8 (PF8) 00H Pull-up resistor option registers (PU0, PUB2) 00H Processor clock control register (PCC) 02H Subclock oscillation mode register (SCKM) 00H Subclock control register (CSS) 00H Oscillation stabilization time selection register (OSTS) 04H 8-bit timer 30, 40 Timer counters (TM30, TM40) 00H Compare registers (CR30, CR40, CRH40) Undefined Mode control registers (TMC30, TMC40) 00H Carrier generator output control register (TCA40) 00H Watch timer Mode control register (WTM) 00H Watchdog timer Mode register (WDTM) 00H Serial interface 10 Serial operation mode register 10 (CSIM10) 00H Transmission/reception shift register 10 (SIO10) Undefined Display mode register 0 (LCDM0) 00H Clock control register 0 (LCDC0) 00H Power-on-clear circuit Power-on-clear register 1 (POCF1) 00H Interrupts Request flag register 0 (IF0) 00H Mask flag register 0 (MK0) FFH External interrupt mode register 0 (INTM0) 00H Key return mode register 00 (KRM00) 00H LCD controller/driver Note 3 Notes 1. While a reset signal is being input, and during the oscillation stabilization period, only the contents of the PC will be undefined; the remainder of the hardware will be the same state as after reset. 2. In standby mode, RAM enters the hold state after reset. 3. The value is 04H only after a power-on-clear reset. Preliminary Product Information U14673EJ1V0PM00 69 µPD789322,789324,789326,789327 8.2 Power Failure Detection Function When a reset is generated via the power-on-clear circuit, bit 2 (POCOF1) of the power-on-clear register (POCF1) is set (1). This bit is then cleared (0) by an instruction written to POCF1. After a power-on-clear reset (i.e. after program execution has started from address 0000H), a power failure can be detected by detecting POCOF1. Figure 8-2. Format of Power-on-Clear Register 1 Symbol POCF1 7 0 6 0 5 0 4 0 POCOF1 3 0 2 POCOF1 1 0 0 Power-on-clear generation status detection 0 Power-on-clear not generated, or cleared by write operation 1 Power-on-clear reset generated Note The value is 04H only after a power-on-clear reset. 70 0 Preliminary Product Information U14673EJ1V0PM00 Address FFDDH After reset Note 00H R/W R/W µPD789322,789324,789326,789327 9. MASK OPTION The µPD789322, 789324, 789326, and 789327 have the following mask option. • Oscillation stabilization wait time The oscillation stabilization wait time after the release of STOP mode by RESET or POC can be selected. <1> 215/fX <2> 217/fX Preliminary Product Information U14673EJ1V0PM00 71 µPD789322,789324,789326,789327 10. INSTRUCTION SET OVERVIEW The instruction set for the µPD789322, 789324, 789326, and 789327 are listed in this section. 10.1 Conventions 10.1.1 Operand formats and descriptions The description made in the operand field of each instruction conforms to the operand format for the instructions listed below (the details conform to the assembly specification). If more than one operand format is listed for an instruction, one is selected. Uppercase letters, #, !, $, and brackets [ ] are used to specify keywords, which must be written exactly as they appear. The meanings of these special characters are as follows: • #: Immediate data specification • $: Relative address specification • !: Absolute address specification • [ ]: Indirect address specification Immediate data should be described using appropriate values or labels. The specification of values and labels must be accompanied by #, !, $, or [ ]. Operand registers, expressed as r or rp in the formats, can be described using both functional names (X, A, C, etc.) and absolute names (R0, R1, R2, and other names listed in Table 5-1 below). Table 10-1. Operand Formats and Descriptions Format Description r rp sfr X (R0), A (R1), C (R2), B (R3), E (R4), D (R5), L (R6), H (R7) AX (RP0), BC (RP1), DE (RP2), HL (RP3) Special function register symbol saddr saddrp FE20H to FF1FH FE20H to FF1FH addr16 addr5 0000H to FFFFH Immediate data or label (only even addresses for 16-bit data transfer instructions) 0040H to 007FH Immediate data or label (even addresses only) word byte bit 16-bit immediate data or label 8-bit immediate data or label 3-bit immediate data or label Immediate data or label Immediate data or label (even addresses only) Remark For details concerning special function register symbols, refer to Table 4-1 Registers. 72 Preliminary Product Information U14673EJ1V0PM00 Special Function µPD789322,789324,789326,789327 10.1.2 Operation field definitions A: A register (8-bit accumulator) X: X register B: B register C: C register D: D register E: E register H: H register L: L register AX: AX register pair (16-bit accumulator) BC: BC register pair DE: DE register pair HL: HL register pair PC: Program counter SP: Stack pointer PSW: Program status word CY: Carry flag AC: Auxiliary carry flag Z: Zero flag IE: Interrupt request enable flag NMIS: Flag to indicate that a non-maskable interrupt is being processed (): Contents of a memory location indicated by a parenthesized address or register name XH, XL: Higher and lower 8 bits of a 16-bit register ∧: Logical product (AND) ∨: Logical sum (OR) ∀: Exclusive OR : Inverted data addr16: 16-bit immediate data or label jdisp8: Signed 8-bit data (displacement value) 10.1.3 Flag operation field definitions (Blank): No change 0: Clear to 0 1: Set to 1 ×: Set or clear according to the result R: Restore to the previous value Preliminary Product Information U14673EJ1V0PM00 73 µPD789322,789324,789326,789327 10.2 Operations Mnemonic Operand Byte Clock Operation Flag Z AC CY MOV r, #byte 3 6 r ← byte saddr , #byte 3 6 (saddr) ← byte 3 6 sfr ← byte 2 4 A←r 2 4 r←A A, saddr 2 4 A ← (saddr) saddr, A 2 4 (saddr) ← A A, sfr 2 4 A ← sfr sfr, A 2 4 sfr ← A A, !addr16 3 8 A ← (addr16) !addr16, A 3 8 (addr16) ← A PSW, #byte 3 6 PSW ← byte A, PSW 2 4 A ← PSW PSW, A 2 4 PSW ← A A, [DE] 1 6 A ← (DE) sfr, #byte A, r r, A XCH Note 1 [DE], A 1 6 (DE) ← A A, [HL] 1 6 A ← (HL) [HL], A 1 6 (HL) ← A A, [HL + byte] 2 6 A ← (HL + byte) [HL + byte], A 2 6 (HL + byte) ← A A, X 1 4 A↔X 2 6 A↔r A, saddr 2 6 A ↔ (saddr) A, sfr 2 6 A ↔ (sfr) A, r MOVW Note 1 Note 2 A, [DE] 1 8 A ↔ (DE) A, [HL] 1 8 A ↔ (HL) A, [HL + byte] 2 8 A ↔ (HL + byte) rp, #word 3 6 rp ← word AX, saddrp 2 6 AX ← (saddrp) 2 8 (saddrp) ← AX 1 4 AX ← rp 1 4 rp ← AX 1 8 AX ↔ rp saddrp, AX AX, rp rp, AX XCHW AX, rp Note 3 Note 3 Note 3 × × × × × × Notes 1. Except when r = A. 2. Except when r = A or X. 3. Only when rp = BC, DE, or HL. Remark The instruction clock cycle is based on the CPU clock (fCPU) specified by the processor clock control register (PCC). 74 Preliminary Product Information U14673EJ1V0PM00 µPD789322,789324,789326,789327 Mnemonic Operand Byte Clock Operation Flag A, #byte 2 4 A, CY ← A + byte × × × saddr, #byte 3 6 (saddr), CY ← (saddr) + byte × × × A, r 2 4 A, CY ← A + r × × × A, saddr 2 4 A, CY ← A + (saddr) × × × A, !addr16 3 8 A, CY ← A + (addr16) × × × A, [HL] 1 6 A, CY ← A + (HL) × × × A, [HL + byte] 2 6 A, CY ← A + (HL + byte) × × × A, #byte 2 4 A, CY ← A + byte + CY × × × saddr, #byte 3 6 (saddr), CY ← (saddr) + byte + CY × × × A, r 2 4 A, CY ← A + r + CY × × × A, saddr 2 4 A, CY ← A + (saddr) + CY × × × A, !addr16 3 8 A, CY ← A + (addr16) + CY × × × A, [HL] 1 6 A, CY ← A + (HL) + CY × × × A, [HL + byte] 2 6 A, CY ← A + (HL + byte) + CY × × × A, #byte 2 4 A, CY ← A − byte × × × saddr, #byte 3 6 (saddr), CY ← (saddr) − byte × × × A, r 2 4 A, CY ← A − r × × × A, saddr 2 4 A, CY ← A − (saddr) × × × A, !addr16 3 8 A, CY ← A − (addr16) × × × A, [HL] 1 6 A, CY ← A − (HL) × × × A, [HL + byte] 2 6 A, CY ← A − (HL + byte) × × × A, #byte 2 4 A, CY ← A − byte − CY × × × saddr, #byte 3 6 (saddr), CY ← (saddr) − byte − CY × × × A, r 2 4 A, CY ← A − r − CY × × × A, saddr 2 4 A, CY ← A − (saddr) − CY × × × A, !addr16 3 8 A, CY ← A − (addr16) − CY × × × A, [HL] 1 6 A, CY ← A − (HL) − CY × × × A, [HL + byte] 2 6 A, CY ← A − (HL + byte) − CY × × × A, #byte 2 4 A ← A ∧ byte × saddr, #byte 3 6 (saddr) ← (saddr) ∧ byte × A, r 2 4 A←A∧r × A, saddr 2 4 A ← A ∧ (saddr) × A, !addr16 3 8 A ← A ∧ (addr16) × A, [HL] 1 6 A ← A ∧ (HL) × A, [HL + byte] 2 6 A ← A ∧ (HL + byte) × Z AC CY ADD ADDC SUB SUBC AND Remark The instruction clock cycle is based on the CPU clock (fCPU) specified by the processor clock control register (PCC). Preliminary Product Information U14673EJ1V0PM00 75 µPD789322,789324,789326,789327 Mnemonic Operand Byte Clock Operation Flag A, #byte 2 4 A ← A ∨ byte saddr, #byte 3 6 (saddr) ← (saddr) ∨ byte × A, r 2 4 A←A∨r × A, saddr 2 4 A ← A ∨ (saddr) × A, !addr16 3 8 A ← A ∨ (addr16) × A, [HL] 1 6 A ← A ∨ (HL) × A, [HL + byte] 2 6 A ← A ∨ (HL + byte) × A, #byte 2 4 A ← A ∀ byte × saddr, #byte 3 6 (saddr) ← (saddr) ∀ byte × A, r 2 4 A←A∀r × A, saddr 2 4 A ← A ∀ (saddr) × A, !addr16 3 8 A ← A ∀ (addr16) × A, [HL] 1 6 A ← A ∀ (HL) × A, [HL + byte] 2 6 A ← A ∀ (HL + byte) × A, #byte 2 4 A − byte × × × saddr, #byte 3 6 (saddr) − byte × × × A, r 2 4 A−r × × × A, saddr 2 4 A − (saddr) × × × A, !addr16 3 8 A − (addr16) × × × A, [HL] 1 6 A − (HL) × × × Z AC CY OR XOR CMP × A, [HL + byte] 2 6 A − (HL + byte) × × × ADDW AX, #word 3 6 AX, CY ← AX + word × × × SUBW AX, #word 3 6 AX, CY ← AX − word × × × CMPW AX, #word 3 6 AX − word × × × INC r 2 4 r←r+1 × × saddr 2 4 (saddr) ← (saddr) + 1 × × r 2 4 r←r−1 × × saddr 2 4 (saddr) ← (saddr) − 1 × × rp 1 4 rp ← rp + 1 DEC INCW DECW rp 1 4 rp ← rp − 1 ROR A, 1 1 2 (CY, A7 ← A0, Am−1 ← Am) × 1 × ROL A, 1 1 2 (CY, A0 ← A7, Am+1 ← Am) × 1 × RORC A, 1 1 2 (CY ← A0, A7 ← CY, Am−1 ← Am) × 1 × ROLC A, 1 1 2 (CY ← A7, A0 ← CY, Am+1 ← Am) × 1 × Remark The instruction clock cycle is based on the CPU clock (fCPU) specified by the processor clock control register (PCC). 76 Preliminary Product Information U14673EJ1V0PM00 µPD789322,789324,789326,789327 Mnemonic Operand Byte Clock Operation saddr.bit 3 6 (saddr.bit) ← 1 sfr.bit 3 6 sfr.bit ← 1 A.bit 2 4 A.bit ← 1 PSW.bit 3 6 PSW bit ← 1 [HL].bit 2 10 (HL).bit ← 1 saddr.bit 3 6 (saddr.bit) ← 0 sfr.bit 3 6 sfr.bit ← 0 A.bit 2 4 A.bit ← 0 Flag Z AC CY SET1 CLR1 × × × × × × PSW.bit 3 6 PSW.bit ← 0 [HL].bit 2 10 (HL).bit ← 0 SET1 CY 1 2 CY ← 1 CLR1 CY 1 2 CY ← 0 0 NOT1 CY 1 2 CY ← CY × CALL !addr16 3 6 (SP − 1) ← (PC + 3)H, (SP − 2) ← (PC + 3)L, PC ← addr16, SP ← SP − 2 CALLT [addr5] 1 8 (SP − 1) ← (PC + 1)H, (SP − 2) ← (PC + 1)L, PCH ← (00000000, addr5 + 1), PCL ← (00000000, addr5), SP ← SP − 2 RET 1 6 PCH ← (SP + 1), PCL ← (SP), SP ← SP + 2 RETI 1 8 PCH ← (SP + 1), PCL ← (SP), PSW ← (SP + 2), SP ← SP + 3, NMIS ← 0 PSW 1 2 (SP − 1) ← PSW, SP ← SP − 1 rp 1 4 (SP − 1) ← rpH, (SP − 2) ← rpL, SP ← SP − 2 PSW 1 4 PSW ← (SP), SP ← SP + 1 rp 1 6 rpH ← (SP + 1), rpL ← (SP), SP ← SP + 2 SP, AX 2 8 SP ← AX PUSH POP MOVW BR AX, SP 2 6 AX ← SP !addr16 3 6 PC ← addr16 $addr16 2 6 PC ← PC + 2 + jdisp8 AX 1 6 PCH ← A, PCL ← X 1 R R R R R R Remark The instruction clock cycle is based on the CPU clock (fCPU) specified by the processor clock control register (PCC). Preliminary Product Information U14673EJ1V0PM00 77 µPD789322,789324,789326,789327 Mnemonic Operand Byte Clock Operation Flag Z AC CY BC $addr16 2 6 PC ← PC + 2 + jdisp8 if CY = 1 BNC $addr16 2 6 PC ← PC + 2 + jdisp8 if CY = 0 BZ $addr16 2 6 PC ← PC + 2 + jdisp8 if Z = 1 BNZ $addr16 2 6 PC ← PC + 2 + jdisp8 if Z = 0 BT saddr.bit, $addr16 4 10 PC ← PC + 4 + jdisp8 if (saddr.bit) = 1 sfr.bit, $addr16 4 10 PC ← PC + 4 + jdisp8 if sfr.bit = 1 BF A.bit, $addr16 3 8 PC ← PC + 3 + jdisp8 if A.bit = 1 PSW.bit, $addr16 4 10 PC ← PC + 4 + jdisp8 if PSW.bit = 1 saddr.bit, $addr16 4 10 PC ← PC + 4 + jdisp8 if (saddr.bit) = 0 sfr.bit, $addr16 4 10 PC ← PC + 4 + jdisp8 if sfr.bit = 0 A.bit, $addr16 3 8 PC ← PC + 3 + jdisp8 if A.bit = 0 PSW.bit, $addr16 4 10 PC ← PC + 4 + disp8 if PSW.bit = 0 B, $addr16 2 6 B ← B − 1, then PC ← PC + 2 + jdisp8 if B ≠ 0 C, $addr16 2 6 C ← C − 1, then PC ← PC + 2 + jdisp8 if C ≠ 0 saddr, $addr16 3 8 (saddr) ← (saddr) − 1, then PC ← PC + 3 + jdisp8 if (saddr) ≠ 0 NOP 1 2 No Operation EI 3 6 IE ← 1 (Enable Interrupt) DI 3 6 IE ← 0 (Disable Interrupt) HALT 1 2 Set HALT Mode STOP 1 2 Set STOP Mode DBNZ Remark The instruction clock cycle is based on the CPU clock (fCPU) specified by the processor clock control register (PCC). 78 Preliminary Product Information U14673EJ1V0PM00 µPD789322,789324,789326,789327 11. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25°°C) Parameter Supply voltage Input voltage Symbol Conditions Ratings Unit VDD −0.3 to +6.5 V VLC0 −0.3 to +6.5 −0.3 to VDD + 0.3 VI Output voltage Output current, high Output current, low V Note Note V VO1 P00 to P03, P10, P11, P20 to P22, P40 to P43, P60, P61 −0.3 to VDD + 0.3 VO2 COM0 to COM3, S0 to S16, P80/S22 to P85/S17, S23 −0.3 to VLC0 + 0.3 IOH Pin P60/TO40 −30 mA Per pin (except P60/TO40) −10 mA Total for all pins (except P60/TO40) −30 mA Per pin 30 mA Total for all pins 80 mA IOL Note V V Operating ambient temperature TA −40 to +85 °C Storage temperature Tstg −65 to +150 °C Note 6.5 V or lower Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. Preliminary Product Information U14673EJ1V0PM00 79 µPD789322,789324,789326,789327 Main System Clock Oscillator Characteristics (TA = −40 to +85°C, VDD = 1.8 to 5.5 V) Resonator Ceramic resonator Recommended Circuit VDD X2 C2 Crystal resonator IC X2 C2 External clock X2 X1 Parameter Conditions Oscillation frequency Note 1 (fX) MIN. 1.0 Oscillation After VDD has reached the MIN. Note 2 stabilization time oscillation voltage range C1 X1 Oscillation frequency Note 1 (fX) 1.0 Oscillation Note 2 stabilization time C1 X1 TYP. MAX. Unit 5.0 MHz 4 ms 5.0 MHz 30 ms X1 input frequency Note 1 (fX) 1.0 5.0 MHz X1 input high-/lowlevel width (tXH, tXL) 85 500 ns Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. 2. Time required to stabilize oscillation after reset or STOP mode release. Cautions 1. When using the main system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. • Keep the wiring length as short as possible. • Do not cross the wiring with other signal lines. • Do not route the wiring near a signal line through which a high fluctuating current flows. • Always make the ground point of the oscillator capacitor the same potential as VSS. • Do not ground the capacitor to a ground pattern through which a high current flows. • Do not fetch signals from the oscillator. 2. When the main system clock is stopped and the device is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock. Remark For the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. 80 Preliminary Product Information U14673EJ1V0PM00 µPD789322,789324,789326,789327 Subsystem Clock Oscillator Characteristics (TA = −40 to +85°C, VDD = 1.8 to 5.5 V) Resonator Crystal resonator Recommended Circuit IC XT1 C3 External clock XT2 R XT1 C4 XT2 Parameter Conditions MIN. TYP. MAX. Unit 32 32.768 35 kHz 1.2 2 s Oscillation frequency Note 1 (fXT) Oscillation VDD = 4.5 to 5.5 V Note 2 stabilization time 10 XT1 input frequency Note 1 (fXT) 32 35 kHz XT1 input high-/lowlevel width (tXTH, tXTL) 14.3 15.6 µs Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. 2. The time required for oscillation to stabilize after VDD reaches the MIN. oscillation voltage range. Use a resonator to stabilize oscillation during the oscillation wait time. Cautions 1. When using the subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. • Keep the wiring length as short as possible. • Do not cross the wiring with the other signal lines. • Do not route the wiring near a signal line through which a high fluctuating current flows. • Always make the ground point of the oscillator capacitor the same potential as VSS. • Do not ground the capacitor to a ground pattern through which a high current flows. • Do not fetch signals from the oscillator. 2. The subsystem clock oscillator is designed as a low-amplitude circuit for reducing current consumption, and is more prone to malfunction due to noise than the main system clock oscillator. Particular care is therefore required with the wiring method when the subsystem clock is used. Remark For the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. Preliminary Product Information U14673EJ1V0PM00 81 µPD789322,789324,789326,789327 DC Characteristics (TA = −40 to +85°C, VDD = 1.8 to 5.5 V) (1/2) Parameter Output current, low Output current, high Symbol IOL IOH Conditions MAX. Unit Per pin 10 mA Total for all pins 80 mA Per pin (except P60/TO40) −1 mA −24 mA −15 mA 0.7 VDD VDD V 0.9 VDD VDD V 0.8 VDD VDD V 0.9 VDD VDD V P60/TO40 VDD = 3.0 V, VOH = 1.0 V MIN. −7 Total for all pins (except P60/TO40) Input voltage, high VIH1 VIH2 Input voltage, low VDD = 2.7 to 5.5 V RESET, P20, P40 to P43, P61 VDD = 2.7 to 5.5 V X1, X2 VDD − 0.1 VDD V VIH4 XT1, XT2 VDD − 0.1 VDD V VIL1 P00 to P03, P10, P11, P21, P22, P60 VDD = 2.7 to 5.5 V 0 0.3 VDD V 0 0.1 VDD V RESET, P20, P40 to P43, P61 VDD = 2.7 to 5.5 V 0 0.2 VDD V 0 0.1 VDD V VIL3 X1, X2 0 0.1 V VIL4 XT1, XT2 0 0.1 V VOH11 VOH12 VOH21 P00 to P03, P10, P11, P20 to P22, P40 to P43, P61 P60/TO40 VOH22 VOH31 P80/S22 to P85/S17 VOH32 Output voltage, low −15 VIH3 VIL2 Output voltage, high P00 to P03, P10, P11, P21, P22, P60 TYP. VOL11 VOL12 VOL21 VOL22 P00 to P03, P10, P11, P20 to P22, P40 to P43, P60, P61 P80/S22 to P85/S17 1.8 ≤ VDD ≤ 5.5 V, IOH = −100 µA VDD − 0.5 V 1.8 ≤ VDD ≤ 5.5 V, IOH = −500 µA VDD − 0.7 V 1.8 ≤ VDD ≤ 5.5 V, IOH = −400 µA VDD − 0.5 V 1.8 ≤ VDD ≤ 5.5 V, IOH = −2 mA VDD − 0.7 V 1.8 ≤ VDD ≤ 5.5 V, IOH = −100 µA VLC0 − 0.5 V 1.8 ≤ VDD ≤ 5.5 V, IOH = −500 µA VLC0 − 0.7 V 1.8 ≤ VDD ≤ 5.5 V, IOL = 400 µA 0.5 V 1.8 ≤ VDD ≤ 5.5 V, IOL = 2 mA 0.7 V 1.8 ≤ VLC0 ≤ 5.5 V, IOL = 400 µA 0.5 V 1.8 ≤ VLC0 ≤ 5.5 V, IOL = 2 mA 0.7 V Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. 82 Preliminary Product Information U14673EJ1V0PM00 µPD789322,789324,789326,789327 DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V) (2/2) Parameter Input leakage current, high Symbol ILIH1 Conditions VIN = VDD ILIH2 Input leakage current, low ILIL1 VIN = 0 V ILIL2 MIN. TYP. MAX. Unit P00 to P03, P10, P11, P20 to P22, P40 to P43, P60, P61, RESET 3 µA X1, X2, XT1, XT2 20 µA P00 to P03, P10, P11, P20 to P22, P40 to P43, P60, P61, RESET −3 µA X1, X2, XT1, XT2 −20 µA Output leakage current, high ILOH VOUT = VDD 3 µA Output leakage current, low ILOL VOUT = 0 V −3 µA Software pull-up resistors R1 VIN = 0 V P00 to P03, P10, P11, P20 to P22, P40 to P43 100 200 kΩ IDD1 5.0-MHz crystal oscillation operating mode VDD = 5.5 V 2.0 4.0 mA VDD = 3.3 V 0.6 1.2 mA 5.0-MHz crystal oscillation HALT mode VDD = 5.5 V 1.1 2.2 mA VDD = 3.3 V 0.4 0.8 mA 32.768-kHz crystal VDD = 5.5 V Note 4 oscillation HALT mode VDD = 3.3 V 25 55 µA 5 25 µA STOP mode VDD = 5.5 V 1 10 µA VDD = 3.3 V 1 5 µA Supply current Note 1 Ceramic/crystal oscillation IDD2 IDD3 IDD4 Note 2 Note 3 50 Notes 1. Current flowing through ports (including current flowing through on-chip pull-up resistors) is not included. 2. High-speed operation (when the processor clock control register (PCC) is set to 00H). 3. Low-speed operation (when PCC is set to 02H) 4. When the main system clock is stopped. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. Preliminary Product Information U14673EJ1V0PM00 83 µPD789322,789324,789326,789327 AC Characteristics (1) Basic operation (TA = −40 to +85°C, VDD = 1.8 to 5.5 V) Parameter Symbol Conditions MIN. Cycle time (Min. instruction execution time) TCY Interrupt input high-/low-level width tINTH, tINTL INT 10 µs Key return pin low-level width tKRIL KR00 to KR03 10 µs RESET low-level width tRSL 10 µs VDD = 2.7 to 5.5 V TCY vs. VDD (Main System Clock) 60 20 Cycle time TCY [ µ s] 10 Guaranteed operation range 2.0 1.0 0.5 0.4 0.1 1 2 3 4 5 6 Supply voltage VDD (V) 84 Preliminary Product Information U14673EJ1V0PM00 TYP. MAX. Unit 0.4 8.0 µs 1.6 8.0 µs µPD789322,789324,789326,789327 (2) Serial interface 10 (TA = –40 to +85°C, VDD = 1.8 to 5.5 V) (a) 3-wire serial I/O mode (Internal clock output) Parameter SCK10 cycle time Symbol tKCY1 Conditions VDD = 2.7 to 5.5 V SCK10 high-/low-level width tKH1, tKL1 VDD = 2.7 to 5.5 V SI10 setup time (to SCK10 ↑) tSIK1 VDD = 2.7 to 5.5 V SI10 hold time (from SCK10 ↑) tKSI1 SO10 output delay time from SCK10 ↓ tKSO1 MIN. R = 1 kΩ, C = 100 pF MAX. Unit 800 ns 3,200 ns tKCY1/2 − 50 ns tKCY1/2 − 150 ns 150 ns 500 ns 400 ns 800 ns VDD = 2.7 to 5.5 V Note TYP. VDD = 2.7 to 5.5 V 0 250 ns 250 1,000 ns MAX. Unit Note R and C are the load resistance and load capacitance of the SO10 output line. (b) 3-wire serial I/O mode (External clock input) Parameter SCK10 cycle time Symbol tKCY2 Conditions VDD = 2.7 to 5.5 V SCK10 high-/low-level width tKH2, tKL2 VDD = 2.7 to 5.5 V SI10 setup time (to SCK10 ↑) tSIK2 VDD = 2.7 to 5.5 V SI10 hold time (from SCK10 ↑) tKSI2 SO10 output delay time from SCK10 ↓ tKSO2 VDD = 2.7 to 5.5 V R = 1 kΩ, C = 100 pF Note VDD = 2.7 to 5.5 V MIN. TYP. 900 ns 3,500 ns 400 ns 1,600 ns 100 ns 150 ns 400 ns 600 ns 0 300 ns 250 1,000 ns Note R and C are the load resistance and load capacitance of the SO10 output line. Preliminary Product Information U14673EJ1V0PM00 85 µPD789322,789324,789326,789327 AC Timing Measurement Point (excluding X1, XT1 input) 0.8 VDD 0.8 VDD Test points 0.2 VDD 0.2 VDD Clock Timing 1/fX tXL tXH VIH3 (MIN.) X1 input VIL3 (MAX.) 1/fXT tXTL tXTH VIH4 (MIN.) XT1 input VIL4 (MAX.) Interrupt Input Timing tINTL tINTH INT Key Return Input Timing tKRIL KR00 to KR03 RESET Input Timing tRSL RESET 86 Preliminary Product Information U14673EJ1V0PM00 µPD789322,789324,789326,789327 Serial Transfer Timing 3-wire serial I/O mode: tKCYn tKLn tKHn SCK10 tSIKn SI10 tKSIn Input data tKSOn SO10 Output data Remark n = 1, 2 Preliminary Product Information U14673EJ1V0PM00 87 µPD789322,789324,789326,789327 LCD Characteristics (TA = −40 to +85°C, VDD = 1.8 to 5.5 V) Parameter Symbol LCD drive voltage VLC0 Conditions Note 1 VAON0 Note 1 VAON0 LCD division resistance LCD output voltage differential TYP. MAX. Unit =1 1.8 5.5 V =0 2.7 5.5 V 200 kΩ RLCD Note 2 MIN. 50 100 VODC IO = ±5 µA 1/3 bias 0 ±0.2 V VODS IO = ±1 µA 1/3 bias 0 ±0.2 V (common) Note 2 LCD output voltage differential (segment) Notes 1. Bit 6 of LCD display mode register 0 (LCDM0) 2. The voltage differential is the difference between the output voltage and the ideal value of the segment and common signal outputs. Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = −40 to +85°C, VDD = 1.8 to 5.5 V) Parameter Symbol Data retention supply voltage Conditions VDDDR Low voltage detection (POC) voltage Power supply rise time VPOC tPth Release signal set time Note 2 Oscillation stabilization wait time MIN. TYP. 1.8 Response time: 2 ms Note 1 VDD: 0 V → 1.8 V 1.8 1.9 0.01 MAX. Unit 3.6 V 2.0 V 100 ms µs tSREL STOP cancelled by RESET 10 tWAIT Cancelled by RESET Note 3 s Cancelled by interrupt request Note 4 s Notes 1. The response time is the time until the output is inverted following detection of voltage by POC, or the time until operation stabilizes after the shift from the operation stopped state to the operating state. 2. The oscillation stabilization time is the amount of time the CPU operation is stopped in order to avoid unstable operation at the start of oscillation. Program operation does not start until both the oscillation stabilization time and the time until oscillation starts have elapsed. 15 17 3. 2 /fX or 2 /fX can be selected using the mask option (refer to 9. MASK OPTION). 12 15 17 4. 2 /fX, 2 /fX, or 2 /fX can be selected using bits 0 to 2 (OSTS0 to OSTS2) of the oscillation stabilization time selection register (OSTS) (refer to 7.2 Standby Function Control Register). Remark fX: Main system clock oscillation frequency 88 Preliminary Product Information U14673EJ1V0PM00 µPD789322,789324,789326,789327 Data Retention Timing Internal reset operation HALT mode STOP mode Operating mode Data retention mode VDD VDDDR tSREL STOP instruction execution RESET tWAIT HALT mode STOP mode Operating mode Data retention mode VDD VDDDR tSREL STOP instruction execution Standby release signal (interrupt request) tWAIT Preliminary Product Information U14673EJ1V0PM00 89 µPD789322,789324,789326,789327 12. PACKAGE DRAWING 52-PIN PLASTIC LQFP (10x10) A B detail of lead end 28 27 41 42 S P C T D R 52 1 L 14 13 U Q F J G I H M K M ITEM A B N S S MILLIMETERS 12.0±0.2 10.0±0.2 C 10.0±0.2 D 12.0±0.2 F 1.1 G 1.1 H I 0.32±0.06 0.13 J 0.65 (T.P.) K 1.0±0.2 L 0.5 M 0.17 +0.03 −0.05 N 0.10 P 1.4 Q 0.1±0.05 R 3° +4° −3° S 1.5±0.1 T U 0.25 0.6±0.15 S52GB-65-8ET-1 90 Preliminary Product Information U14673EJ1V0PM00 µPD789322,789324,789326,789327 APPENDIX A. DEVELOPMENT TOOLS The following development tools are available for system development using the µPD789322, 789324, 789326, and 789327. Language Processing Software RA78K0S Notes 1, 2, 3 CC78K0S Assembler package common to 78K/0S Series Notes 1, 2 ,3 DF789328 C compiler package common to 78K/0S Series Notes 1, 2, 3, 5 Notes 1, 2, 3 CC78K/0S–L Device file for µPD789327 Subseries C compiler library source file common to 78K/0S Series Flash Memory Writing Tools Flashpro III Note 4 (Part number: FL-PR3 , PG-FP3) FA-52GB Notes 4, 5 Dedicated flash memory programmer Adapter for writing to flash memory designed for 52-pin plastic LQFP (GB-8ET type) Debugging Tools IE-78K0S-NS In-circuit emulator In-circuit emulator to debug hardware or software when application systems using the 78K/0S Series are developed. The IE-78K0S-NS supports an integrated debugger (ID78K0S-NS). The IE-78K0S-NS is used in combination with an interface adapter for connection to an AC adapter, emulation probe, or host machine. IE-70000-MC-PS-B AC adapter AC adapter to supply power from a 100- to 240-V AC outlet. IE-70000-98-IF-C Interface adapter Interface adapter required when using a PC-9800 Series computer (except notebook type) as the host machine for the IE-78K0S-NS (C bus supported). IE-70000-CD-IF-A PC card interface PC card and interface cable required when a notebook PC is used as the host machine for the IE-78K0S-NS (PCMCIA socket supported). IE-70000-PC-IF-C Interface adapter Interface adapter required when using an IBM PC/AT™ or compatible as the host machine for the IE-78K0S-NS (ISA bus supported). IE-70000-PCI-IF Interface adapter Interface adapter required when using a PC incorporating a PCI bus as the host machine for the IE-78K0S-NS. IE-789328-NS-EM1 Emulation board NP-52GB Note 5 Notes 4, 5 SM78K0S Notes 1, 2 ID78K0S-NS DF789328 Notes 1, 2 Notes 1, 2, 5 Emulation board to emulate the peripheral hardware specific to the device. The IE789328-NS-EM1 is used in combination with the in-circuit emulator. Board to connect an in-circuit emulator to the target system. This board is dedicated for a 52-pin plastic LQFP (GB-8ET type). System simulator common to 78K/0S Series Integrated debugger common to 78K/0S Series Device file for µPD789327 Subseries Notes 1. Based on the PC-9800 series (Japanese Windows™) 2. Based on IBM PC/AT or compatibles (Japanese/English Windows) 3. Based on the HP9000 series 700™ (HP-UX™), SPARCstation™ (SunOS™, Solaris™), and NEWS™ (NEWS-OS™) 4. Manufactured by Naito Densei Machida Mfg. Co, Ltd. (+81-44-822-3813). 5. Under development Remark The RA78K0S, CC78K0S, and SM78K0S are used in combination with the DF789328 device file. Preliminary Product Information U14673EJ1V0PM00 91 µPD789322,789324,789326,789327 Real-Time OS MX78K0S Notes 1, 2 OS for 78K/0S Series Notes 1. Based on the PC-9800 series (Japanese Windows) 2. Based on IBM PC/AT or compatibles (Japanese/English Windows) 92 Preliminary Product Information U14673EJ1V0PM00 µPD789322,789324,789326,789327 APPENDIX B. RELATED DOCUMENTS Documents Related to Devices Document Name Document No. Japanese English µPD789322, 789324, 789326, 789327 Preliminary Product Information U14673J This document µPD78F9328 Preliminary Product Information U14411J U14411E µPD789327, 789467 Subseries User’s Manual To be prepared To be prepared 78K/0S Series User’s Manual Instructions U11047J U11047E Documents Related to Development Tools (User’s Manual) Document Name Document No. Japanese RA78K0S Assembler Package English Operation U11622J U11622E Assembly Language U11599J U11599E Structured Assembly Language U11623J U11623E Operation U11816J U11816E Language U11817J U11817E SM78K0S System Simulator Windows Based Reference U11489J U11489E SM78K Series System Simulator External Part User Open Interface Specifications U10092J U10092E ID78K0S-NS Integrated Debugger Windows Based Reference U12901J U12901E IE-78K0S-NS In-circuit Emulator U13549J U13549E IE-789328-NS-EM1 Emulation Board To be prepared To be prepared CC78K0S C Compiler Documents Related to Embedded Software (User’s Manual) Document Name Document No. Japanese 78K/0S Series OS MX78K0S Fundamental U12938J English U12938E Other Documents Document Name Document No. English Japanese SEMICONDUCTORS SELECTION GUIDE Products & Packages (CD-ROM) X13769X Semiconductor Device Mounting Technology Manual C10535J C10535E Quality Grades on NEC Semiconductor Devices C11531J C11531E NEC Semiconductor Device Reliability/Quality Control System C10983J C10983E Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892J C11892E Guide to Microcontroller-Related Products by Third Parties U11416J − Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing. Preliminary Product Information U14673EJ1V0PM00 93 µPD789322,789324,789326,789327 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. EEPROM is a trademark of NEC Corporation. Windows is either a registered trademark or a trademark of Microsoft Corporation in the United States and/or other countries. PC/AT is a trademark of International Business Machines Corporation. HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. Solaris and SunOS are trademarks of Sun Microsystems, Inc. NEWS and NEWS-OS are trademarks of Sony Corporation. 94 Preliminary Product Information U14673EJ1V0PM00 µPD789322,789324,789326,789327 Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • Ordering information • Product release schedule • Availability of related technical literature • Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) • Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) NEC Electronics (Germany) GmbH NEC Electronics Hong Kong Ltd. Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288 Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics (France) S.A. Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (France) S.A. NEC Electronics Singapore Pte. Ltd. Spain Office Madrid, Spain Tel: 91-504-2787 Fax: 91-504-2860 United Square, Singapore 1130 Tel: 65-253-8311 Fax: 65-250-3583 NEC Electronics Hong Kong Ltd. NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics (UK) Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 NEC Electronics Taiwan Ltd. NEC Electronics Italiana s.r.l. NEC Electronics (Germany) GmbH Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951 NEC do Brasil S.A. Electron Devices Division Rodovia Presidente Dutra, Km 214 07210-902-Guarulhos-SP Brasil Tel: 55-11-6465-6810 Fax: 55-11-6465-6829 J99.1 Preliminary Product Information U14673EJ1V0PM00 95 µPD789322,789324,789326,789327 The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. • The information contained in this document is being issued in advance of the production cycle for the device. The parameters for the device may change before final production or NEC Corporation, at its own discretion, may withdraw the device prior to its production. • No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. • NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. • Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. • While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. • NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. M5 98. 8