DATA SHEET MOS INTEGRATED CIRCUIT µ PD753036, 753036(A) 4-BIT SINGLE-CHIP MICROCONTROLLER DESCRIPTION The µPD753036 is one of the 75XL series 4-bit single-chip microcontroller chips and has a data processing capability comparable to that of an 8-bit microcontroller. It has an on-chip LCD controller/driver with a larger ROM capacity and extended CPU functions compared with the conventional µPD75336, and can provide high-speed operation at a low supply voltage of 1.8 V. It can be supplied in a small plastic TQFP package (12 × 12 mm) and is suitable for small sets using LCD panels. A stricter quality assurance program applies the µPD753036(A) compared to the µPD753036 (standard model). (In terms of NEC’s quality grading, this is a “special” grade product.) For details of functions refer to the following User’s Manual. µPD753036 User’s Manual: U10201E FEATURES • Internal programmable LCD controller/driver • Internal A/D converter which can be operated at a low • Low voltage operation VDD = 1.8 to 5.5 V • Can be driven by two 1.5 V batteries • On-chip memory voltage • 8-bit resolution × 8 channels (successive approxi- • Program memory (ROM): 16384 × 8 bits • Data memory (RAM): 768 × 4 bits mation type) • Capable of high-speed operation and variable instruction execution time for power saving • 0.95, 1.91, 3.81, 15.3 µs (@ 4.19 MHz) • Small plastic TQFP (12 × 12 mm) • Suitable for small sets such as cameras • One-time PROM: µ PD75P3036 • 0.67, 1.33, 2.67, 10.7 µs (@ 6.0 MHz) • 122 µs (@ 32.768 kHz) APPLICATION Radio transmitter/receiver, compact disc player, rice cooker, home bakery, etc. ORDERING INFORMATION Part number Package Quality grade µPD753036GC-×××-3B9 80-pin plastic QFP (14 × 14 mm, 0.65 mm pitch) Standard µPD753036GK-×××-BE9 80-pin plastic TQFP (fine pitch) (12 × 12 mm, 0.5 mm pitch) Standard µPD753036GC(A)-×××-3B9 80-pin plastic QFP (14 × 14 mm, 0.65 mm pitch) Special Remark ××× indicates ROM code suffix. Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications. Unless otherwise specified, the µPD753036 is treated as the representative model throughout this document. The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. U11353EJ4V0DS00 (4th edition) Date Published June 2000 N CP(K) Printed in Japan The mark shows major revised points. © 1996, 2000 µPD753036, 753036(A) Functional Outline Parameter Function • 0.95, 1.91, 3.81, 15.3 µs (main system clock: @4.19 MHz operation) • 0.67, 1.33, 2.67, 10.7 µs (main system clock: @6.0 MHz operation) • 122 µs (subsystem clock: @32.768 kHz operation) Minimum instruction execution time On-chip memory ROM 16384 × 8 bits RAM 768 × 4 bits General purpose register • 4-bit operation: 8 × 4 banks • 8-bit operation: 4 × 4 banks Input/ output port CMOS input 8 CMOS input/output 20 Bit port output 8 Also used for segment pins N-ch open-drain input/output pins 8 On-chip pull-up resistors can be specified by using mask option 13 V withstand voltage Total 44 LCD controller/driver On-chip pull-up resistors can be specified by using software: 27 • Segment selection: • Display mode selection: 12/16/20 segments (can be changed to bit port output in unit of 4; max. 8) Static 1/2 duty (1/2 bias) 1/3 duty (1/2 bias) 1/3 duty (1/3 bias) 1/4 duty (1/3 bias) On-chip split resistor for LCD drive can be specified by using mask option Timer 5 channels • 8-bit timer/event counter: 3 channels (16-bit timer/event counter, career generator, timer with gate) • Basic interval/watchdog timer: 1 channel • Watch timer: 1 channel Serial interface • 3-wire serial I/O mode ... MSB or LSB can be selected for transferring first bit • 2-wire serial I/O mode • SBI mode A/D converter 8-bit resolution × 8 channels (1.8 V ≤ AV REF ≤ V DD) Bit sequential buffer (BSB) 16 bits Clock output (PCL) • Φ, 524, 262, 65.5 kHz (main system clock: @4.19 MHz operation) • Φ, 750, 375, 93.8 kHz (main system clock: @6.0 MHz operation) Buzzer output (BUZ) • 2, 4, 32 kHz (main system clock: @4.19 MHz operation or subsystem clock: @32.768 kHz operation) • 2.93, 5.86, 46.9 kHz (main system clock: @6.0 MHz operation) Vectored interrupts External: 3, Internal: 5 Test input External: 1, Internal: 1 System clock oscillator • Ceramic or crystal oscillator for main system clock oscillation • Crystal oscillator for subsystem clock oscillation Standby function STOP/HALT mode Power supply voltage VDD = 1.8 to 5.5 V Package • 80-pin plastic QFP (14 × 14 mm, 0.65 mm pitch) • 80-pin plastic TQFP (fine pitch) (12 × 12 mm, 0.5 mm pitch) 2 Data Sheet U11353EJ4V0DS00 µPD753036, 753036(A) CONTENTS 1. PIN CONFIGURATION (TOP VIEW) ................................................................................................... 5 2. BLOCK DIAGRAM ............................................................................................................................... 7 3. PIN 3.1 3.2 3.3 3.4 FUNCTION ...................................................................................................................................... 8 Port Pins ...................................................................................................................................... 8 Non-Port Pins ...........................................................................................................................10 Pin Input/Output Circuits ........................................................................................................12 Recommended Connections for Unused Pins .....................................................................15 4. SWITCHING FUNCTION BETWEEN Mk I MODE AND Mk II MODE ............................................. 16 4.1 Difference between Mk I and Mk II ..........................................................................................16 4.2 Setting Method of Stack Bank Select Register (SBS).......................................................... 17 5. MEMORY CONFIGURATION ............................................................................................................18 6. PERIPHERAL HARDWARE FUNCTIONS .......................................................................................21 6.1 Digital I/O Port ..........................................................................................................................21 6.2 Clock Generator .......................................................................................................................22 6.3 Subsystem Clock Oscillator Control Functions ..................................................................23 6.4 Clock Output Circuit ................................................................................................................24 6.5 Basic Interval Timer/Watchdog Timer ...................................................................................25 6.6 Watch Timer ..............................................................................................................................26 6.7 Timer/Event Counter ................................................................................................................27 6.8 Serial Interface .........................................................................................................................31 6.9 LCD Controller/Driver ..............................................................................................................33 6.10 A/D Converter ..........................................................................................................................35 6.11 Bit Sequential Buffer ..............................................................................................................36 7. INTERRUPT FUNCTION AND TEST FUNCTION ............................................................................ 37 8. STANDBY FUNCTION .......................................................................................................................39 9. RESET FUNCTION ............................................................................................................................40 10. MASK OPTION ...................................................................................................................................43 11. INSTRUCTION SETS .........................................................................................................................44 12. ELECTRICAL CHARACTERISTICS .................................................................................................54 13. CHARACTERISTIC CURVE (reference) ..........................................................................................69 14. PACKAGE DRAWINGS .....................................................................................................................73 Data Sheet U11353EJ4V0DS00 3 µPD753036, 753036(A) 15. RECOMMENDED SOLDERING CONDITIONS ................................................................................75 APPENDIX A. µPD75336, 753036, 75P3036 FUNCTION LIST ...........................................................76 APPENDIX B. DEVELOPMENT TOOLS ................................................................................................78 APPENDIX C. RELATED DOCUMENTS ...............................................................................................82 4 Data Sheet U11353EJ4V0DS00 µPD753036, 753036(A) 1. PIN CONFIGURATION (TOP VIEW) • 80-pin plastic QFP (14 × 14 mm, 0.65 mm pitch) µPD753036GC-×××-3B9, 753036GC(A)-×××-3B9 • 80-pin plastic TQFP (fine pitch) (12 × 12 mm, 0.5 mm pitch) XT1 VDD AVREF AVSS AN5 AN4 AN3 AN2 AN1 AN0 P83/AN7 P82/AN6 P81/TI2 P80/TI1 P33 P32 P31/SYNC P30/LCDCL P23/BUZ P22/PCL/PTO2 P21/PTO1 P20/PTO0 P13/TI0 P12/INT2 P11/INT1 P10/INT0 P03/SI/SB1 P50 P51 P52 P53 P00/INT4 P01/SCK P02/SO/SB0 COM1 COM2 COM3 BIAS VLC0 VLC1 VLC2 P40 P41 P42 P43 VSS 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 1 59 2 58 3 57 4 56 5 55 6 54 7 53 8 52 9 51 10 50 11 49 12 48 13 47 14 46 15 45 16 44 17 43 18 42 19 41 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 COM0 S31/BP7 S30/BP6 S29/BP5 S28/BP4 S27/BP3 S26/BP2 S25/BP1 S24/BP0 S23 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 P72/KR6 P71/KR5 P70/KR4 P63/KR3 P62/KR2 P61/KR1 P60/KR0 RESET X2 X1 Note IC XT2 P73/KR7 µPD753036GK-×××-BE9 Note Connect the IC (Internally Connected) pin directly to VDD. Data Sheet U11353EJ4V0DS00 5 µPD753036, 753036(A) 6 P00-P03 : Port 0 VLC0-VLC2 : LCD Power Supply 0-2 P10-P13 : Port 1 BIAS : LCD Power Supply Bias Control P20-P23 : Port 2 LCDCL : LCD Clock P30-P33 : Port 3 SYNC : LCD Synchronization P40-P43 : Port 4 TI0-TI2 : Timer Input 0-2 P50-P53 : Port 5 PTO0-PTO2 : Programmable Timer Output 0-2 P60-P63 : Port 6 BUZ : Buzzer Clock P70-P73 : Port 7 PCL : Programmable Clock P80-P83 : Port 8 AVREF : Analog Reference BP0-BP7 : Bit Port 0-7 AVSS : Analog Ground KR0-KR7 : Key Return 0-7 AN0-AN7 : Analog Input 0-7 SCK : Serial Clock INT0, INT1, INT4 : External Vectored Interrupt 0, 1, 4 SI : Serial Input INT2 : External Test Input 2 SO : Serial Output X1, X2 : Main System Clock Oscillation 1, 2 SB0, SB1 : Serial Data Bus 0, 1 XT1, XT2 : Subsystem Clock Oscillation 1, 2 RESET : Reset VDD : Positive Power Supply S12-S31 : Segment Output 12-31 VSS : Ground COM0-COM3 : Common Output 0-3 IC : Internally Connected Data Sheet U11353EJ4V0DS00 µPD753036, 753036(A) 2. BLOCK DIAGRAM TI0/P13 PTO0/P20 AN0-AN5 AN6/P82 AN7/P83 8 AVREF AVSS 8-bit timer/event counter #0 INTT0 TOUT0 A/D converter Basic interval timer/ watchdog timer SP (8) Program counter (14) ALU CY INTBT INTT1 TI1/P80 PTO1/P21 TI2/P81 PTO2/PCL/P22 8-bit timer/event counter #1 8-bit timer/event counter #2 Cascaded 16-bit timer/ event timer INTT2 Watch timer INTW fLCD BUZ/P23 SI/SB1/P03 S0/SB0/P02 SCK/P01 SBS Bank General reg. Program memory (ROM) 16384 × 8 bits Decode and control Data memory (RAM) 768 × 4 bits Clocked serial interface Interrupt control 8 Bit seq. buffer (16) 4 P00-P03 Port1 4 P10-P13 Port2 4 P20-P23 Port3 4 P30-P33 Port4 4 P40-P43 Port5 4 P50-P53 Port6 4 P60-P63 Port7 4 P70-P73 Port8 4 P80-P83 12 S12-S23 LCD controller/ driver INTCSI TOUT0 INT0/P10 INT1/P11 INT4/P00 INT2/P12 KR0/P60KR7/P73 Port0 CPU clock φ fx/2N Clock output control Clock divider fLCD System clock generator Sub Stand by Main control 8 4 S24/BP0S31/BP7 COM0-COM3 VLC0 VLC1 VLC2 BIAS LCDCL/P30 SYNC/P31 IC VDD VSS RESET PCL/P22 XT1XT2 X1 X2 Data Sheet U11353EJ4V0DS00 7 µPD753036, 753036(A) 3. PIN FUNCTION 3.1 Port Pins (1/2) Pin Name P00 Input/Output Alternate Function Input INT4 P01 SCK P02 SO/SB0 P03 SI/SB1 P10 Input INT0 P11 INT1 P12 INT2 P13 TI0 P20 Input/Output PTO0 P21 PTO1 P22 PCL/PTO2 P23 BUZ P30 Input/Output LCDCL Function 4-bit input port (PORT0). For P01 to P03, connections of on-chip pull-up resistors can be specified by software in 3-bit units. 8-bit Access State after Reset I/O Circuit Type Note 1 No Input B F -A F -B M -C 4-bit input port (PORT1) Connections of on-chip pull-up resistors can be specified by software in 4-bit units. P10/INT0 can select noise eliminating circuit. No Input B -C 4-bit input/output port (PORT2) Connections of on-chip pull-up resistors can be specified by software in 4-bit units. No Input E-B Programmable 4-bit input/output port (PORT3). No Input E-B P31 SYNC P32 – P33 – P40-P43 Note 2 Input/Output – N-ch open-drain 4-bit input/output port Yes (PORT4). A pull-up resistor can be contained bit-wise (mask option). In the open-drain mode, withstands up to 13 V. High level (when pullup resistors are contained) or high impedance M-D P50-P53 Note 2 Input/Output – N-ch open-drain 4-bit input/output port (PORT5). A pull-up resistor can be contained bit-wise (mask option). In the open-drain mode, withstands up to 13 V. High level (when pullup resistors are provided) or high impedance M-D Notes 1. 2. This port can be specified input/output in bit units. Connections of on-chip pull-up resistor can be specified by software in 4-bit units. Circled characters indicate the Schmitt-trigger input. If on-chip pull-up resistors are not specified by mask option (when used as N-ch open-drain input port), low level input leakage current increases when input or bit manipulation instruction is executed. 8 Data Sheet U11353EJ4V0DS00 µPD753036, 753036(A) 3.1 Port Pins (2/2) Pin Name P60 Input/Output Alternate Function Input/Output KR0 P61 KR1 P62 KR2 P63 KR3 P70 Input/Output KR4 P71 KR5 P72 KR6 P73 KR7 P80 Input/Output TI1 P81 TI2 P82 AN6 P83 AN7 BP0 Output S24 BP1 S25 BP2 S26 BP3 S27 BP4 Output S29 BP6 S30 BP7 S31 2. 8-bit Access State after Reset I/O Circuit Type Note 1 Yes Input F -A Input F -A Input E -E Programmable 4-bit input/output port (PORT6). This port can be specified for input/output bit-wise. Connections of on-chip pull-up resistors can be specified by software in 4-bit units. 4-bit input/output port (PORT7). Connections of on-chip pull-up resistors can be specified by software in 4-bit units. No 4-bit input/output port (PORT8). Connections of on-chip pull-up resistors can be specified by software in 4-bit units. Y-B No 1-bit output port (BIT PORT) Also used for segment output pins. Note 2 H-A S28 BP5 Notes 1. Function Circled characters indicate the Schmitt-trigger input. BP0 through BP7 select VLC1 as an input source. However, the output levels change depending on the external circuit of BP0 through BP7 and VLC1. Example Because BP0 through BP7 are mutually connected inside the µPD753036, the output levels of BP0 through BP7 are determined by R1, R2, and R 3. VDD µ PD753036 R2 BP0 ON VLC1 BP1 R1 ON R3 Data Sheet U11353EJ4V0DS00 9 µPD753036, 753036(A) 3.2 Non-Port Pins (1/2) Pin Name TI0 Input/Output Alternate Function Input P13 TI1 P80 TI2 P81 PTO0 Output P20 PTO1 P21 PTO2 P22 PCL State after Reset I/O Circuit Type Note 1 Inputs external event pulses to the timer/event counter. Input B -C Timer/event counter output Input E-B Input F -A Function E -E Clock output BUZ P23 Optional frequency output (for buzzer output or system clock trimming) P01 Serial clock input/output SO/SB0 P02 Serial data output Serial data bus input/output F -B SI/SB1 P03 Serial data input Serial data bus input/output M -C SCK Input/Output INT4 Input P00 Edge detection vectored interrupt input (both rising edge and falling edge detection) Input B INT0 Input P10 Noise eliminator/ asynch selectable Input B -C P11 Edge detection vectored interrupt input (detection edge can be selected) INT0/P10 can select noise eliminator. Edge-detection-testable input Asynchronous Input B -C Input Y INT1 INT2 Input P12 AN0-AN5 Input – AN6 P82 AN7 P83 Asynchronous Analog signal input for A/D converter Y-B AV REF – – A/D converter reference voltage input – Z-N AV SS – – A/D converter reference GND – Z-N KR0-KR3 Input P60-P63 Falling edge detection testable input Input F -A KR4-KR7 Input P70-P73 Falling edge detection testable input Input F -A S12-S23 Output – Segment signal output Note 2 G-A S24-S31 Output BP0-BP7 Segment signal output Note 2 H-A COM0-COM3 Output – Common signal output Note 2 G-B – – LCD drive power On-chip split resistor is enable (mask option). – – Output – Output for external split resistor disconnect Note 3 – V LC0 -VLC2 BIAS Notes 1. 2. Circled characters indicate the Schmitt trigger input. Each display output selects the following VLCX as input source. S12-S31: VLC1, COM0-COM2: VLC2, COM3: VLC0. 3. When a split resistor is contained ....... Low level When no split resistor is contained ...... High-impedance 10 Data Sheet U11353EJ4V0DS00 µPD753036, 753036(A) 3.2 Non-Port Pins (2/2) Pin Name Input/Output Alternate Function State after Reset I/O Circuit Type Note 1 LCDCL Note 2 Output P30 Clock output for externally expanded driver Input E-B SYNC Note 2 Output P31 Clock output for externally expanded driver sync Input E-B X1 X2 Input – – Crystal/ceramic connection pin for the main system clock oscillator. When inputting the external clock, input the external clock to pin X1, and the reverse phase of the external clock to pin X2. – – XT1 Input – – – Crystal connection pin for the subsystem clock oscillator. When the external clock is used, input the external clock to pin XT1 and the reverse phase of the external clock to pin XT2. Pin XT1 can be used as a 1-bit input (test) pin. – XT2 Input – System reset input (low level active) – B IC – – Internally connected. Connect directly to VDD. – – V DD – – Positive power supply – – V SS – – GND – – RESET Function Notes 1. Circled characters indicate the Schmitt-trigger input. 2. These pins are provided for future system expansion. At present, these pins are used only as pins P30 and P31. Data Sheet U11353EJ4V0DS00 11 µPD753036, 753036(A) 3.3 Pin Input/Output Circuits The µPD753036 pin input/output circuits are shown schematically. (1/3) TYPE A TYPE D VDD VDD Data P-ch OUT P-ch IN N-ch Output disable N-ch Push-pull output that can be placed in output high impedance (both P-ch, N-ch off). CMOS specification input buffer. TYPE E-B TYPE B VDD P.U.R. P.U.R. enable IN P-ch Data IN/OUT Type D Output disable Type A Schmitt trigger input having hysteresis characteristic. P.U.R. : Pull-Up Resistor TYPE E-E TYPE B-C VDO VDD P.U.R P.U.R. P-ch P.U.R. enable P.U.R. enable P-ch Data Output disable IN IN/OUT Type D Type A Type B P.U.R. : Pull-Up Resistor 12 Data Sheet U11353EJ4V0DS00 µPD753036, 753036(A) (2/3) TYPE F-A TYPE G-B VDD P.U.R. enable VLC1 P-ch P-ch N-ch P-ch N-ch Data Output disable P-ch N-ch VLC0 P.U.R. IN/OUT Type D OUT COM data Type B P-ch N-ch VLC2 N-ch P-ch N-ch P.U.R. : Pull-Up Resistor TYPE F-B TYPE H-A VDD P.U.R. P.U.R. enable Output disable (P) P-ch VDD SEG data P-ch Data Output disable Type G-A OUT IN/OUT Bit port data Output disable N-ch Output disable (N) Type D P.U.R. : Pull-Up Resistor TYPE G-A TYPE M-C VDD VLC0 P.U.R. P-ch N-ch P.U.R. enable P-ch VLC1 IN/OUT P-ch N-ch SEG data VLC2 Data OUT N-ch Output disable N-ch P-ch N-ch N-ch P.U.R. : Pull-Up Resistor Data Sheet U11353EJ4V0DS00 13 µPD753036, 753036(A) (3/3) TYPE M-D TYPE Y-B VDD VDD P.U.R. (Mask Option) IN/OUT Data Output disable P.U.R. enable N-ch (+13 V withstand voltage) VDD P-ch Data IN/OUT Type D P-ch Input instruction Output disable P.U.R.Note Type A Voltage limitation circuit (+13 V withstand voltage) Note This pull-up resistor operates only when an input instruction is executed without a pull-up resistor connected using the mask option (current flows from VDD to the pin when the pin is low). TYPE Y Port inputNote 2 Type Y P.U.R. : Pull-Up Resistor TYPE Z-N AVREF VDD P-ch IN VDD + N-ch Sampling C – Reference voltage AVSS AVSS Input enable Reference voltage (From voltage tap of series resistor string) ADEN N-ch AVSS 14 Data Sheet U11353EJ4V0DS00 µPD753036, 753036(A) 3.4 Recommended Connections for Unused Pins Table 3-1. List of Recommended Connections for Unused Pins Pin Recommended Connection P00/INT4 Connect to VSS or V DD P01/SCK Connect to VSS or V DD individually via resistor P02/SO/SB0 P03/SI/SB1 Connect to VSS P10/INT0-P12/INT2 Connect to VSS or V DD P13/TI0 P20/PTO0 Input: Individually connect to VSS or VDD via resistor P21/PTO1 Output: Leave unconnected P22/PCL/PTO2 P23/BUZ P30/LCDCL P31/SYNC P32 P33 P40-P43 Input: Connect to VSS. P50-P53 Output: Connect to VSS. (Do not connect a pull-up resistor using the mask option.) P60/KR0-P63/KR3 Input: Individually connect to VSS or V DD via resistor P70/KR4-P73/KR7 Output: Leave unconnected P80/TI1, P81/TI2 P82/AN6, P83/AN7 S12-S23 Leave unconnected S24/BP0-S31/BP7 COM0-COM3 VLC0-VLC2 Connect to VSS BIAS Only if all of VLC0-VLC2 are unused, connect to VSS. In other cases, no connection required. XT1 Note Connect to VSS XT2 Note Leave unconnected AN0-AN5 Connect to VSS or V DD AV REF Connect to VSS AV SS IC Note Connect to VDD directly When the subsystem clock is not used, set SOS. 0 to 1 (so as not to use the internal feedback resistor). Data Sheet U11353EJ4V0DS00 15 µPD753036, 753036(A) 4. SWITCHING FUNCTION BETWEEN Mk I MODE AND Mk II MODE 4.1 Difference between Mk I and Mk II The CPU of µPD753036 has the following two modes: Mk I and Mk II, either of which can be selected. The mode can be switched by the bit 3 of the Stack Bank Select register (SBS). • Mk I mode: Upward compatible with µ PD75336. Can be used in the 75XL CPU with a ROM capacity of up to 16K bytes. • Mk II mode: Incompatible with µPD75336. Can be used in all the 75XL CPU’s including those products whose ROM capacity is more than 16 Kbytes. Table 4-1. Differences between Mk I Mode and Mk II Mode Mk I Mode Mk II Mode Program memory (bytes) 16384 Number of stack bytes for subroutine instructions 2 bytes 3 bytes BRA !addr1 instruction Not available Available CALL !addr instruction 3-machine cycles 4-machine cycles CALLF !faddr instruction 2-machine cycles 3-machine cycles CALLA !addr1 instruction Caution Mk II supports a program area exceeding 16K bytes in the 75X and 75XL series. Therefore, this mode is useful for enhancing software compatibility with products exceeding 16K bytes. When Mk II mode is selected, the number of stack bytes used can be increased by 1 byte per stack compared with Mk I mode. When the CALL !addr instruction and CALLF !faddr instruction are used, the number of machine cycles becomes greater by 1. Therefore, use Mk I mode if the RAM efficiency and processing capability is more important than software compatibility. 16 Data Sheet U11353EJ4V0DS00 µPD753036, 753036(A) 4.2 Setting Method of Stack Bank Select Register (SBS) Switching between the Mk I mode and Mk II mode can be done by the SBS. Figure 4-1 shows the format. The SBS is set by a 4-bit memory manipulation instruction. When using the Mk I mode, the SBS must be initialized to 10××B Note at the beginning of a program. When using the Mk II mode, it must be initialized to 00××B Note. Note The desired numbers must be set in the ×× positions. Figure 4-1. Stack Bank Select Register Format Address 3 F84H SBS3 2 1 SBS2 SBS1 0 Symbol SBS0 SBS Stack area specification 0 0 Memory bank 0 0 1 Memory bank 1 1 0 Memory bank 2 1 1 Prohibited 0 Be sure to set bit 2 to 0. Mode switching specification 0 Mk II mode 1 Mk I mode Caution Since SBS. 3 is set to “1” after a RESET signal is generated, the CPU operates in the Mk I mode. When executing an instruction in the Mk II mode, set SBS. 3 to “0” to select the Mk II mode. Data Sheet U11353EJ4V0DS00 17 µPD753036, 753036(A) 5. MEMORY CONFIGURATION • Program memory (ROM) ······ 16384 × 8 bits • Addresses 0000H and 0001H Vector table wherein the program start address and the values set for the RBE and MBE at the time a RESET signal is generated are written. Reset and start are possible at an arbitrary address. • Addresses 0002H-000DH Vector table wherein the program start address and values set for the RBE and MBE by the vectored interrupts are written. Interrupt execution can start at an arbitrary address. • Addresses 0020H-007FH Table area referenced by the GETI instruction Note. Note The GETI instruction realizes a 1-byte instruction on behalf of an arbitrary 2-byte instruction, 3-byte instruction, or two 1-byte instructions. It is used to decrease the program steps. • Data memory (RAM) • Data area ··· 768 words × 4 bits (000H-2FFH) • Peripheral hardware area ··· 128 words × 4 bits (F80H-FFFH) 18 Data Sheet U11353EJ4V0DS00 µPD753036, 753036(A) Figure 5-1. Program Memory Map 0000H 7 6 MBE RBE 5 0 Internal reset start address (high-order 6 bits) ” 0002H MBE RBE INTBT/INT4 start address ” 0004H MBE RBE INT0 start address ” 0006H MBE RBE INT1 start address ” 0008H MBE RBE INTCSI start address ” 000AH MBE RBE INTT0 start address ” 000CH MBE RBE (Iow-order 8 bits) (high-order 6 bits) (Iow-order 8 bits) (high-order 6 bits) (Iow-order 8 bits) CALLF !faddr instruction entry address (high-order 6 bits) (Iow-order 8 bits) Branch address of BR BCXA, BR BCDE, BR !addr, BRA !addr1Note or CALLA !addr1Note instruction BRCB !caddr instruction branch address (high-order 6 bits) (Iow-order 8 bits) CALL !addr instruction subroutine entry address (high-order 6 bits) (Iow-order 8 bits) INTT1,INTT2 start address (high-order 6 bits) ” (Iow-order 8 bits) BR $addr instruction relative branch address (–15 to –1, +2 to +16) 0020H GETI instruction reference table 007FH 0080H Branch destination address and subroutine entry address when GETI instruction is executed 07FFH 0800H 0FFFH 1000H BRCB !caddr instruction branch address 1FFFH 2000H BRCB !caddr instruction branch address 2FFFH 3000H BRCB !caddr instruction branch address 3FFFH Note Can be performed only in the Mk II mode. Remark In addition to the above, a branch can be taken to the address indicated by changing only the low-order 8 bits of PC by executing the BR PCDE, BR PCXA instruction. Data Sheet U11353EJ4V0DS00 19 µPD753036, 753036(A) Figure 5-2. Data Memory Map Data memory Memory bank 000H (32 × 4) General purpose register area 01FH 020H 0 256 × 4 (224 × 4) 0FFH 100H 256 × 4 (236 × 4) 1EBH 1ECH (20 × 4) Display data memory Stack areaNote 1 1FFH 200H Data area static RAM (768 × 4) 256 × 4 2 2FFH Not incorporated F80H Peripheral hardware area 128 × 4 FFFH Note For stack area, one memory bank can be selected among memory bank 0-2. 20 Data Sheet U11353EJ4V0DS00 15 µPD753036, 753036(A) 6. PERIPHERAL HARDWARE FUNCTIONS 6.1 Digital I/O Port The following four types of I/O ports are available: • CMOS input (PORT0 and 1) : 8 pins • CMOS I/O (PORT2, 3, 6, 7, and 8) : 20 pins • N-ch open-drain I/O (PORT4 and 5) : 8 pins • Bit port output (BP0 through BP7) 8 pins Total : : 44 pins Table 6-1. Types and Features of Digital Ports Port Name PORT0 Function 4-bit input Also used as the INT4, SCK, SO/SB0, SI/SB1 pins. 4-bit input port Also used as the INT0INT2 and TI0 pins. Can be set to input mode or output mode in 4-bit units. Also used as the PTO0PTO2, PCL, BUZ pins. Can be set to input mode or output mode in 1-bit units. Also used as the LCDCL, SYNC pins. 4-bit I/O (N-channel open-drain, 13 V withstand voltage) Can be set to input mode or output mode in 4-bit units. Ports 4 and 5 are paired and data can be input/ output in 8-bit units. On-chip pull-up resistor can be specified bit-wise by mask option. 4-bit I/O Can be set to input mode or output mode in 1-bit units. Ports 6 and 7 are paired and data can be input/ output in 8-bit units. Also used as the KR0-KR3 pins. 4-bit I/O PORT3 PORT4 PORT5 PORT6 Remarks When using serial interface function, the dual function pin can function as the output port depending on the operation mode. PORT1 PORT2 Operation & Features PORT7 Can be set to input mode or output mode in 4-bit units. Also used as the KR4-KR7 pins. PORT8 Can be set to input mode or output mode in 4-bit units Also used as the TI1, TI2, AN6, AN7 pins. BP0-BP7 1-bit output Outputs data bit-wise. Can be switched to LCD drive segment output S24-S31 by software. Data Sheet U11353EJ4V0DS00 — 21 µPD753036, 753036(A) 6.2 Clock Generator The clock generator provides the clock signals to the CPU and peripheral hardware and its configuration is shown in Figure 6-1. The operation of the clock generation circuit is determined by the processor clock control register (PCC) and system clock control register (SCC). Two types of system clocks are available: main system clock and subsystem clock. Furthermore, the instruction execution time can be changed. • 0.95, 1.91, 3.81, 15.3 µs (main system clock: at 4.19 MHz operation) • 0.67, 1.33, 2.67, 10.7 µs (main system clock: at 6.0 MHz operation) • 122 µs (subsystem clock: at 32.768 kHz operation) Figure 6-1. Clock Generator Block Diagram · Basic interval timer (BT) · Timer/event counter · Serial interface · Watch timer · LCD controller/driver · A/D converter · INT0 noise eliminator · Clock output circuit XT1 VDD XT2 Subsystems clock oscillator fXT Main system clock oscillator fX LCD controller/driver Watch timer X1 VDD X2 1/1~1/4096 Divider 1/2 1/4 1/16 Selector WM.3 SCC Oscillation stop SCC3 Divider Selector 1/4 Internal bus SCC0 Φ · CPU · INT0 noise eliminator · Clock output circuit PCC PCC0 PCC1 4 HALT F/F PCC2 S HALTNote STOPNote PCC3 R PCC2, PCC3 Clear STOP F/F Q Q Wait release signal from BT S RESET signal R Standby release signal from interrupt control circuit Note Instruction execution 22 Data Sheet U11353EJ4V0DS00 µPD753036, 753036(A) Remarks 1. fX = Main system clock frequency 2. fXT = Subsystem clock frequency 3. Φ = CPU clock 4. PCC: Processor Clock Control Register 5. SCC: System Clock Control Register 6. One Clock cycle (tCY) of the CPU clock equal to one machine cycle of the instruction. 6.3 Subsystem Clock Oscillator Control Functions The µPD753036 subsystem clock oscillator has the following two control functions. • Selects by software whether an on-chip feedback resistor is to be used or notNote. • Reduces current consumption by decreasing the drive current of the on-chip inverter when the supply voltage is high (VDD ≥ 2.7 V). Note When the subsystem clock is not used, set SOS.0 to 1 (so as not to use the internal feedback resistor), connect the XT1 pin to VSS, and open the XT2 pin to lower the supply current that is consumed in the subsystem clock oscillator. The above functions can be used by switching the bits 0 and 1 of the sub-oscillator control register (SOS). (Refer to Figure 6-2.) Figure 6-2. Subsystem Clock Oscillator SOS.0 Feedback resistor Inverter SOS.1 XT1 XT2 VDD Data Sheet U11353EJ4V0DS00 23 µPD753036, 753036(A) 6.4 Clock Output Circuit The clock output circuit is provided to output the clock pulses from the P22/PCL/PTO2 pin, and used to apply to the remote control waveform outputs and to supply clock pulses to the peripheral LSIs. • Clock output (PCL): Φ, 524, 262, 65.5 kHz (main system clock: at 4.19 MHz operation) Φ, 750, 375, 93.8 kHz (main system clock: at 6.0 MHz operation) Figure 6-3. Clock Output Circuit Block Diagram From clock generator From timer/event counter (channel 2) Φ Output buffer fX/23 Selector Selector fX/24 PCL/P22PTO2 fX/26 PORT2.2 CLOM3 0 CLOM1 CLOM0 CLOM P22 output latch Bit 2 of PMGB Port 2 I/O mode specification bit 4 Internal bus Remark Special care has been taken in designing the chip so that small-width pulses may not be output when switching clock output enable/disable. 24 Data Sheet U11353EJ4V0DS00 µPD753036, 753036(A) 6.5 Basic Interval Timer/Watchdog Timer The basic interval timer/watchdog timer has the following functions. • • • • Interval timer operation to generate a reference time interrupt Watchdog timer operation to detect a runaway of program and reset the CPU Selects and counts the wait time when the standby mode is released Reads the contents of counting Figure 6-4 Basic Interval Timer/Watchdog Timer Block Diagram From clock generator Clear Clear fX/25 fX/27 MPX Basic interval timer (8-bit frequency divider) Set fX/29 BT fX/212 3 Wait release signal when standby is released. BTM3 BTM2 BTM1 BTM0 BTM SET1Note 4 BT interrupt request flag Vectored interrupt IRQBT request signal Internal reset signal WDTM SET1Note 8 1 Internal bus Note Instruction execution Data Sheet U11353EJ4V0DS00 25 µPD753036, 753036(A) 6.6 Watch Timer The µPD753036 has one channel of watch timer. The functions of the watch timer are as follows: • Sets the test flag (IRQM) with 0.5 sec interval. The standby mode can be released by the IRQM. • 0.5 sec interval can be created by both the main system clock (4.19 MHz) and subsystem clock (32.768 kHz). • Convenient for program debugging and checking as interval becomes 128 times shorter (3.91 ms) with the fast feed mode. • Outputs the frequencies (2.048, 4.096, 32.768 kHz) to the BUZ pin (P23), usable for buzzer and trimming of system clock frequencies. • Clears the frequency divider to make the clock start with zero seconds. Figure 6-5. Watch Timer Block Diagram fW (512 Hz : 1.95 ms) 26 fW (256 Hz : 3.91 ms) 27 fX 128 From clock generator (32.768 kHz) Selector fW (32.768 kHz) fXT (32.768 kHz) Divider fW 214 fLCD Selector INTW IRQW set signal 2 Hz 0.5 sec 4 kHz 2 kHz fW fW 23 24 Clear Selector Output buffer P23/BUZ WM WM7 PORT2.3 0 WM5 WM4 WM3 8 WM2 WM1 WM0 P23 output latch PMGB bit 2 Port 2 input/ output mode Bit test instruction Internal bus The values enclosed in parentheses are applied when fX = 4.19 MHz and fXT = 32.768 kHz. 26 Data Sheet U11353EJ4V0DS00 µPD753036, 753036(A) 6.7 Timer/Event Counter The µPD753036 has three channels of timer/event counters. The configuration is shown in Figures 6-6 through 6-8. The functions of the timer/event counter are as follows: • • • • Programmable interval timer operation Square wave output of any frequency to the PTOn pin. (n = 0-2) Event counter operation Divides the frequency of signal input via the TIn pin to 1-Nth of the original signal and outputs the divided frequency to the PTOn pin (frequency division operation). • Supplies the serial shift clock to the serial interface circuit. • Reads the counting value. The timer/event counter operates in the following four modes as set by the mode register. Table 6-2. Operation Modes of Timer/Event Counter Channel Channel 0 Channel 1 Channel 2 Yes Yes Yes NoNote No Yes PWM pulse generator mode No No Yes 16-bit timer/event counter mode No Yes NoNote Yes No Yes Mode 8-bit timer/event counter mode Gate control function Gate control function Carrier generator mode Note Used for gate control signal generation Data Sheet U11353EJ4V0DS00 27 28 Figure 6-6. Timer/Event Counter Block Diagram (channel 0) Internal bus 8 SET1Note 8 8 – TM06 TM05 TM04 TM03 TM02 0 TOE0 TMOD0 TM0 T0 enable flag Modulo register (8) 0 PORT2.0 PGMB bit 2 Port 2 P20 input/output output latch mode To serial interface 8 PORT1.3 TOUT0 Match Comparator (8) TOUT F/F Output buffer 8 Data Sheet U11353EJ4V0DS00 Input buffer Reset T0 TI0/P13 From clock generator P20/PTO0 fx/24 fx/26 fx/28 fx/210 INTT0 IRQT0 set signal Count register (8) MPX CP Clear Timer operation start RESET IRQT0 clear signal To timer/event counter (channel 2) Caution When setting TM0, be sure to set bits 0 and 1 to 0. µPD753036, 753036(A) Note Instruction execution Figure 6-7. Timer/Event Counter Block Diagram (channel 1) Internal bus 8 Note SET1 TOE1 TM1 – 8 TM16 TM15 TM14 TM13 TM12 TM11 TM10 T1 enable flag TMOD1 Decoder PORT1.2 PORT2.1 P21 output latch PMGB.2 Port 2 input/output mode Modulo register (8) 8 TI1/P80 Data Sheet U11353EJ4V0DS00 Timer/event counter output (channel 2) fx/2 fx/26 fx/28 fx/210 fx/212 MPX CP TOUT F/F P21/PTO1 Output buffer Reset 8 5 From clock generator Match Comparator (8) Input buffer T1 Count register (8) Clear RESET Timer operation start 16 bit timer/event counter mode IRQT1 set signal Selector Timer/event counter reload signal (channel 2) Timer/event counter comparator (channel 2) (When 16-bit timer/event counter mode) Note Instruction execution 29 µPD753036, 753036(A) Timer/event counter match signal (channel 2) (When 16-bit timer/event counter mode) INTT1 IRQT1 set signal 30 Figure 6-8. Timer/Event Counter Block Diagram (channel 2) Internal bus 8 8 Decoder MPX (8) 8 TI2/P81 TC2 TGCE Reload TOUT F/F Reset 8 Data Sheet U11353EJ4V0DS00 MPX CP TOE2REMC NRZB NRZ Match Comparator (8) Input buffer fx fx/2 From clock fx/24 generator fx/26 fx/28 fx/210 TMOD2 Modulo register (8) 8 Modulo register for high level period setup TM26 TM25 TM24 TM23 TM22 TM21 TM20 PORT1.2 PORT2.2 PMGB.2 P22 Port 2 output latch input/output 8 TMOD2H T2 Count register (8) P22/PCL/PTO2 Output buffer Selector 8 TM2 Selector SET1 Selector 8 Note Overflow Timer/event counter clock input (channel 1) Carrier generator mode Clear INTT2 IRQT2 set signal 16-bit timer/event counter mode IRQT2 clear signal Timer operation start RESET Timer event counter TOUT F/F (channel 0) Timer/event counter clear signal (channel 1) (When 16-bit timer/event counter mode) Timer/event counter match signal (channel 1) (When 16-bit timer/event counter mode) Timer/event counter match signal (channel 1) (When carrier generator mode) µPD753036, 753036(A) Note Instruction execution From clock generator µPD753036, 753036(A) 6.8 Serial Interface The µPD753036 incorporates a clock-synchronous 8-bit serial interface and can be used in the following four modes. • • • • Operation stop mode 3-wire serial I/O mode 2-wire serial I/O mode SBI mode Data Sheet U11353EJ4V0DS00 31 32 Figure 6-9. Serial Interface Block Diagram Internal bus 8/4 Bit test 8 8 CSIM 8 Bit manipulation Bit test Slave address register (SVA) (8) SBIC Match signal RELT CMDT Address comparator (8) P03/SI/SB1 SO latch SET CLR Selector Shift register (SIO) D Q BSYE P02/SO/SB0 ACKE ACKT Data Sheet U11353EJ4V0DS00 (8) Busy/ acknowledge output circuit Selector Bus release/ command/ acknowledge detection circuit RELD CMDD ACKD INTCSI P01/SCK Serial clock counter Serial clock control circuit IRQCSI set signal Serial clock selector External SCK fX/23 fX/24 fX/26 TOUT0 (from timer/event counter (channel 0)) µPD753036, 753036(A) P01 output Iatch INTCSI control circuit µPD753036, 753036(A) 6.9 LCD Controller/Driver The µPD753036 incorporates a display controller which generates segment and common signals according to the display data memory contents and incorporates segment and common drivers which can drive the panel directly. The µPD753036 LCD controller/driver functions are as follows: • Display data memory is read automatically by DMA operation and segment and common signals are generated. • Display mode can be selected from among the following five: (1) Static (2) 1/2 duty (time multiplexing by 2), 1/2 bias (3) 1/3 duty (time multiplexing by 3), 1/2 bias (4) 1/3 duty (time multiplexing by 3), 1/3 bias (5) 1/4 duty (time multiplexing by 4), 1/3 bias • A frame frequency can be selected from among four in each display mode. • A maximum of 20 segment signal output pins (S12-S31) and four common signal bit port output (COM0COM3). • The segment signal output pins (S24-S27 and S28-S31) can be changed to the bit port output in 4-pin units. • Split-resistor can be incorporated to supply LCD drive power. (Mask option) • Various bias methods and LCD drive voltages can be applicable. • When display is off, current flow to the split resistor is cut. • Display data memory not used for display can be used for normal data memory. • It can also operate by using the subsystem clock. Data Sheet U11353EJ4V0DS00 33 34 Figure 6-10. LCD Controller/Driver Block Diagram Internal bus 4 Display data memory Data Sheet U11353EJ4V0DS00 1FFH 3 2 1 0 1FEH 3 2 1 0 1F9H 3 2 1 0 1F8H 3 2 1 0 1ECH 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 8 4 4 8 Display mode register Display control register Port 3 output latch 1 0 Port mode register group A Timing controller 1 0 fLCD Multiplexer S31/BP7 S30/BP6 S24/BP0 Common driver S23 S12 COM3 COM2 COM1 COM0 LCD drive voltage control VLC2 VLC1 VLC0 P31/ P30/ SYNC LCDCL µPD753036, 753036(A) Segment driver LCD drive mode changer Selector µPD753036, 753036(A) 6.10 A/D Converter µPD753036 incorporates an 8-bit resolution A/D converter with an analog input (AN0-AN7). It uses the successive approximation method. Figure 6-11. A/D Converter Block Diagram Internal bus 8 ADEN ADM6 ADM5 ADM4 SOC EOC 0 0 8 AN0 Control circuit AN1 Sample hold circuit AN2 + AN3 Multiplexer SA register (8) – AN4 Comparator AN5 AN6/P82 8 AN7/P83 Tap decoder AVREF R/2 R R R R/2 Series resistor string AVSS ADEN Data Sheet U11353EJ4V0DS00 35 µPD753036, 753036(A) 6.11 Bit Sequential Buffer ....... 16 Bits The bit sequential buffer (BSB) is a special data memory for bit manipulation and the bit manipulation can be easily performed by changing the address specification and bit specification in sequence, therefore it is useful when processing a long data bit-wise. Figure 6-12. Bit Sequential Buffer Format Address Bit FC3H 3 Symbol L register 2 1 FC2H 0 3 2 BSB3 L = FH 1 FC1H 0 3 BSB2 L = CH L = BH 2 1 FC0H 0 3 BSB1 L = 8H L = 7H L = 4H L = 3H DECS L 2 1 0 BSB0 L = 0H INCS L Remarks 1. 2. 36 In the pmem.@L addressing, the specified bit moves corresponding to the L register. In the pmem.@L addressing, the BSB can be manipulated regardless of MBE/MBS specification. Data Sheet U11353EJ4V0DS00 µPD753036, 753036(A) 7. INTERRUPT FUNCTION AND TEST FUNCTION The µPD753036 has eight interrupt sources and two test sources. Of the test sources, INT2 has two types of edge-detected testable inputs. The interrupt control circuit of the µPD753036 has the following functions: (1) Interrupt function ● Vectored interrupt function for hardware control, enabling/disabling the interrupt acceptance by the interrupt enable flag (IE×××) and interrupt master enable flag (IME). ● Can set any interrupt start address. ● Nesting wherein the order of priority can be specified by the interrupt priority select register (IPS). ● Test function of interrupt request flag (IRQ×××). An interrupt generated can be checked by software. ● Release the standby mode. A release interrupt can be selected by the interrupt enable flag. (2) Test function ● Test request flag (IRQ×××) generation can be checked by software. ● Release the standby mode. The test source to be released can be selected by the test enable Data Sheet U11353EJ4V0DS00 37 38 Figure 7-1. Interrupt Control Circuit Block Diagram Internal bus 2 1 4 IME IPS IM2 IM1 IST1 IST0 Interruput enable flag (IE×××) IM0 Decoder INTBT INT4/P00 INT0/P10 Note Data Sheet U11353EJ4V0DS00 INT1/P11 Selector Both edge detector Edge detector Edge detector INT2/P12 KR0/P60 IRQ0 IRQCS1 INTT0 IRQT0 INTT1 IRQT1 INTT2 IRQT2 INTW IRQW Selector IRQ2 Priority control circuit Vector table address generator Standby release signal Falling edge detector IM2 Note Noise eliminator (Standby release is disable when noise eliminator is selected.) µPD753036, 753036(A) KR3/P63 VRQn IRQ4 IRQ1 INTCS1 Rising edge detector IRQBT µPD753036, 753036(A) 8. STANDBY FUNCTION In order to save power consumption while a program is in a standby mode, two types of standby modes (STOP mode and HALT mode) are provided for the µPD753036. Table 8-1. Operation Status in Standby Mode STOP Mode HALT Mode Set instruction STOP instruction HALT instruction System clock when set Settable only when the main system clock is used. Settable both by the main system clock and subsystem clock. Operation status Clock generator The main system clock stops oscillation. Only the CPU Φ halts (oscillation continues). Basic interval timer Operation stops Operation. (The IRQBT is set in the reference interval) Note 1. Serial interface Operable only when an external SCK input is selected as the serial clock. Operable Note 1 Timer/event counter Operable only when a signal input to the T10-T12 pins is specified as the count clock. Operable Note 1 Watch timer Operable when fXT is selected as the count clock. Operable LCD driver controller Operable only when fXT is selected as the LCDCL. Operable External interrupt The INT1, 2, and 4 are operable. Only the INT0 is not operated. Note 2 CPU The operation stops. Release signal Notes 1. 2. • Interrupt request signal sent from the operable hardware enabled by the interrupt enable flag. • Test request signal sent from the test source enabled by the test enable flag • RESET signal Cannot operate only when the main system clock stops. Can operate only when the noise eliminator is not used (IM02 = 1) by bit 2 of the edge detection mode register(IM0). Data Sheet U11353EJ4V0DS00 39 µPD753036, 753036(A) 9. RESET FUNCTION There are two reset inputs: external RESET signal and reset signal sent from the basic interval timer/watchdog timer. When either one of the reset signals are input, an internal reset signal is generated. Figure 9-1 shows the circuit diagram of the above two inputs. Figure 9-1. Configuration of Reset Function RESET Internal reset signal Reset signal sent from the basic interval timer/watchdog timer WDTM Internal bus By the RESET signal generation, each device is initialized as listed in Table 9-1. Figure 9-2 shows the timing chart of the reset operation. Figure 9-2. Reset Operation by RESET Signal Generation Wait Note RESET signal generated Operating mode or standby mode HALT mode Operating mode Internal reset operation Note The following two times can be selected by the mask option. 2 17/fX (21.8 ms : at 6.0 MHz operation, 31.3 ms : at 4.19 MHz operation) 2 15/fX (5.46 ms : at 6.0 MHz operation, 7.81 ms : at 4.19 MHz operation) 40 Data Sheet U11353EJ4V0DS00 µPD753036, 753036(A) Table 9-1. Status of Each Device After Reset (1/2) RESET Signal Generation in the Standby Mode RESET Signal Generation in Operation Sets the low-order 6 bits of program memory’s address 0000H to the PC13-PC8 and the contents of address 0001H to the PC7-PC0. Sets the low-order 6 bits of program memory’s address 0000H to the PC13-PC8 and the contents of address 0001H to the PC7-PC0. Held Undefined Skip flag (SK0-SK2) 0 0 Interrupt status flag (IST0, 1) 0 0 Bank enable flag (MBE, RBE) Sets the bit 6 of program memory’s address 0000H to the RBE and bit 7 to the MBE. Sets the bit 6 of program memory’s address 0000H to the RBE and bit 7 to the MBE. Undefined Undefined 1000B 1000B Data memory (RAM) Held Undefined General-purpose register (X, A, H, L, D, E, B, C) Held Undefined Bank select register (MBS, RBS) 0, 0 0, 0 Undefined Undefined Hardware Program counter (PC) PSW Carry flag (CY) Stack pointer (SP) Stack bank select register (SBS) Basic interval Counter (BT) timer/watch- Mode register (BTM) 0 0 dog timer Watchdog timer enable flag (WDTM) 0 0 Timer/event Counter (T0) 0 0 counter (T0) Modulo register (TMOD0) FFH FFH 0 0 0, 0 0, 0 0 0 FFH FFH 0 0 0, 0 0, 0 0 0 Mode register (TM0) TOE0, TOUT F/F Timer/event Counter (T1) counter (T1) Modulo register (TMOD1) Mode register (TM1) TOE1, TOUT F/F Timer/event Counter (T2) counter (T2) Modulo register (TMOD2) FFH FFH High level period setting modulo register (TMOD2H) FFH FFH 0 0 0, 0 0, 0 0, 0, 0 0, 0, 0 TGCE 0 0 Mode register (WM) 0 0 Mode register (TM2) TOE2, TOUT F/F REMC, NRZ, NRZB Watch timer Data Sheet U11353EJ4V0DS00 41 µPD753036, 753036(A) Table 9-1. Status of Each Device After Reset (2/2) Serial interface Hardware RESET Signal Generation in the Standby Mode RESET Signal Generation in Operation Shift register (SIO) Held Undefined Operating mode register (CSIM) 0 0 SBI control register (SBIC) 0 0 Held Undefined Slave address register (SVA) Clock generator, Processor clock control register (PCC) 0 0 clock output System clock control register (SCC) 0 0 circuit Clock output mode register (CLOM) 0 0 Sub-oscillator control register (SOS) 0 0 LCD controller/ Display mode register (LCDM) 0 0 driver Display control register (LCDC) 0 0 Interrupt Interrupt request flag (IRQ×××) Reset (0) Reset (0) function Interrupt enable flag (IE×××) 0 0 Interrupt master enable flag (IME) 0 0 0, 0, 0 0, 0, 0 0 0 Output buffer Off Off Output latch Cleared (0) Cleared (0) I/O mode registers (PMGA, PMGB, BMGC) 0 0 Pull-up resistor setting register (POGA, POGB) 0 0 Held Undefined INT0, 1, 2 mode registers (IM0, IM1, IM2) Interrupt priority selection register (IPS) Digital port Bit sequential buffer (BSB0-BSB3) 42 Data Sheet U11353EJ4V0DS00 µPD753036, 753036(A) 10. MASK OPTION The µPD753036 has the following mask options. • P40-P43, P50-P53 mask options On-chip pull-up resistors can be connected. (1) On-chip pull-up resistors are specifiable bit-wise. (2) On-chip pull-up resistors are not specifiable. • VLC0-VLC2 pin, BIAS pin mask option On-chip dividing resistor for LCD drive can be connected. (1) Dividing resistor is not connected. (2) Four 10 kΩ (TYP.) dividing resistors are connected at the same time. (3) Four 100 kΩ (TYP.) dividing resistors are connected at the same time. • Standby function mask option Wait times can be selected by a RESET signal. (1) 217/fX (21.8ms : at fX = 6.0 MHz, 31.3ms : at fX = 4.19MHz) (2) 215/fX (5.46ms : at fX = 6.0 MHz, 7.81ms : at fX = 4.19MHz) • Subsystem clock mask option Use of the internal feedback resistor can be selected. (1) Internal feedback resistor can be used. (Switched ON/OFF via software) (2) Internal feedback resistor cannot be used. (Switched out in hardware) Data Sheet U11353EJ4V0DS00 43 µPD753036, 753036(A) 11. INSTRUCTION SETS (1) Expression formats and specification methods of operands The operand is written in the operand column of each instruction in accordance with the specification method for the operand expression format of the instruction. For details, refer to RA75X Assembler Package User’s Manual – Language (U12385E). If there are several elements, one of them is selected. Capital letters and the + and – symbols are key words and are written as they are. For immediate data, appropriate numbers and labels are written. Instead of the labels such as mem, fmem, pmem, and bit, the symbols of the registers can be specified. However, there are restrictions in the labels that can be written for fmem and pmem. For details, refer to User’s Manual. Representation format Specification Method reg reg1 X, A, B, C, D, E, H, L X, B, C, D, E, H, L rp XA, BC, DE, HL rp1 rp2 rp' rp'1 BC, BC, XA, BC, rpa rpa1 HL, HL+, HL–, DE, DL DE, DL n4 n8 4-bit immediate data or label 8-bit immediate data or label mem bit 8-bit immediate data or label 2-bit immediate data or label fmem pmem FB0H-FBFH, FF0H-FFFH immediate data or label FC0H-FFFH immediate data or label addr addr1 caddr faddr 0000H-3FFFH immediate data or label 0000H-3FFFH immediate data or label (Mk II mode only) 12-bit immediate data or label 11-bit immediate data or label taddr 20H-7FH immediate data (where bit 0 = 0) or label PORTn IE××× RBn MBn PORT0-PORT8 IEBT, IET0-IET2, IE0-IE2, IE4, IECSI, IEW RB0-RB3 MB0, MB1, MB2, MB15 DE, HL DE BC, DE, HL, XA', BC', DE', HL' DE, HL, XA', BC', DE', HL' Note Note mem can be only used even address in 8-bit data processing. 44 Data Sheet U11353EJ4V0DS00 µPD753036, 753036(A) (2) Legend in explanation of operation A : A register, 4-bit accumulator B : B register C : C register D : D register E : E register H : H register L : L register X : X register XA : XA register pair; 8-bit accumulator BC : BC register pair DE : DE register pair HL : HL register pair XA’ : XA’ expanded register pair BC’ : BC’ expanded register pair DE’ : DE’ expanded register pair HL’ : HL’ expanded register pair PC : Program counter SP : Stack pointer CY : Carry flag, bit accumulator PSW : Program status word MBE : Memory bank enable flag RBE : Register bank enable flag PORTn : Port n (n = 0-8) IME : Interrupt master enable flag IPS : Interrupt priority selection register IE××× : Interrupt enable flag RBS : Register bank selection register MBS : Memory bank selection register PCC : Processor clock control register . : Separation between address and bit (××) : The contents addressed by ×× ××H : Hexadecimal data Data Sheet U11353EJ4V0DS00 45 µPD753036, 753036(A) (3) Explanation of symbols under addressing area column *1 MB = MBE•MBS (MBS = 0-2, 15) *2 MB = 0 *3 MBE = 0 : MB = 0 (000H-07FH) MB = 15 (F80H-FFFH) MBE = 1 : MB = MBS (MBS = 0-2, 15) *4 MB = 15, fmem = FB0H-FBFH, FF0H-FFFH *5 MB = 15, pmem = FC0H-FFFH *6 addr = 0000H-3FFFH *7 addr, addr1 = (Current PC) – 15 to (Current PC) – 1 (Current PC) + 2 to (Current PC) + 16 *8 caddr = 0000H-0FFFH 1000H-1FFFH 2000H-2FFFH 3000H-3FFFH *9 faddr = 0000H-07FFH *10 taddr = 0020H-007FH *11 addr1 = 0000H-3FFFH Remarks 1. (PC13, 12 (PC13, 12 (PC13, 12 (PC13, 12 = = = = 00B) or 01B) or 10B) or 11B) Data memory addressing Program memory addressing MB indicates memory bank that can be accessed. 2. In *2, MB = 0 independently of how MBE and MBS are set. 3. In *4 and *5, MB = 15 independently of how MBE and MBS are set. 4. *6 to *11 indicate the areas that can be addressed. (4) Explanation of number of machine cycles column S denotes the number of machine cycles required by skip operation when a skip instruction is executed. The value of S varies as follows. • When no skip is made: S = 0 • When the skipped instruction is a 1- or 2-byte instruction: S = 1 • When the skipped instruction is a 3-byte instructionNote: S = 2 Note 3-byte instruction: BR !addr, BRA !addr1, CALL !addr or CALLA !addr1 instruction Caution The GETI instruction is skipped in one machine cycle. One machine cycle is equal to one cycle of CPU clock (= tCY); time can be selected from among four types by setting PCC. 46 Data Sheet U11353EJ4V0DS00 µPD753036, 753036(A) Instruction Group Transfer Mnemonic MOV XCH Number of Bytes Number of Machine Cycles A, #n4 1 1 A ← n4 reg1, #n4 2 2 reg1 ← n4 XA, #n8 2 2 XA ← n8 String effect A HL, #n8 2 2 HL ← n8 String effect B rp2, #n8 2 2 rp2 ← n8 A, @HL 1 1 A ← (HL) *1 A, @HL+ 1 2+S A ← (HL), then L ← L+1 *1 L=0 A, @HL– 1 2+S A ← (HL), then L ← L–1 *1 L = FH A, @rpa1 1 1 A ← (rpa1) *2 XA, @HL 2 2 XA ← (HL) *1 @HL, A 1 1 (HL) ← A *1 @HL, XA 2 2 (HL) ← XA *1 A, mem 2 2 A ← (mem) *3 XA, mem 2 2 XA ← (mem) *3 mem, A 2 2 (mem) ← A *3 mem, XA 2 2 (mem) ← XA *3 A, reg1 2 2 A ← reg1 XA, rp' 2 2 XA ← rp' reg1, A 2 2 reg1 ← A rp'1, XA 2 2 rp'1 ← XA A, @HL 1 1 A ↔ (HL) *1 A, @HL+ 1 2+S A ↔ (HL), then L ← L+1 *1 L=0 A, @HL– 1 2+S A ↔ (HL), then L ← L–1 *1 L = FH A, @rpa1 1 1 A ↔ (rpa1) *2 XA, @HL 2 2 XA ↔ (HL) *1 A, mem 2 2 A ↔ (mem) *3 XA, mem 2 2 XA ↔ (mem) *3 A, reg1 1 1 A ↔ reg1 XA, rp' 2 2 XA ↔ rp' Operand Operation Data Sheet U11353EJ4V0DS00 Addressing Area Skip Condition String effect A 47 µPD753036, 753036(A) Instruction Group Table reference Bit transfer Operation Mnemonic MOVT MOV1 ADDS ADDC SUBS SUBC Note 48 Number of Bytes Number of Machine Cycles XA, @PCDE 1 3 XA ← (PC13–8+DE)ROM XA, @PCXA 1 3 XA ← (PC13–8+XA)ROM XA, @BCDENote 1 3 XA ← (B1,0+CDE)ROM *6 XA, @BCXANote 1 3 XA ← (B1,0+CXA)ROM *6 CY, fmem.bit 2 2 CY ← (fmem.bit) *4 CY, pmem.@L 2 2 CY ← (pmem7–2+L3–2.bit(L1–0)) *5 CY, @H+mem.bit 2 2 CY ← (H+mem3–0.bit) *1 fmem.bit, CY 2 2 (fmem.bit) ← CY *4 pmem.@L, CY 2 2 (pmem7–2+L3–2.bit(L1–0)) ← CY *5 @H+mem.bit, CY 2 2 (H+mem3–0.bit) ← CY *1 A, #n4 1 1+S A ← A+n4 carry XA, #n8 2 2+S XA ← XA+n8 carry A, @HL 1 1+S A ← A+(HL) XA, rp' 2 2+S XA ← XA+rp' carry rp'1, XA 2 2+S rp'1 ← rp'1+XA carry A, @HL 1 1 A, CY ← A+(HL)+CY XA, rp' 2 2 XA, CY ← XA+rp'+CY rp'1, XA 2 2 rp'1, CY ← rp'1+XA+CY A, @HL 1 1+S A ← A–(HL) XA, rp' 2 2+S XA ← XA–rp' borrow rp'1, XA 2 2+S rp'1 ← rp'1–XA borrow A, @HL 1 1 A, CY ← A–(HL)–CY XA, rp' 2 2 XA, CY ← XA–rp'–CY rp'1, XA 2 2 rp'1, CY ← rp'1–XA–CY Operand Operation Only the low-order 2-bits are valid for the B register. Data Sheet U11353EJ4V0DS00 Addressing Area *1 Skip Condition carry *1 *1 *1 borrow µPD753036, 753036(A) Instruction Group Operation Number of Bytes Number of Machine Cycles A, #n4 2 2 A ← A ∧ n4 A, @HL 1 1 A ← A ∧ (HL) XA, rp' 2 2 XA ← XA ∧ rp' rp'1, XA 2 2 rp'1 ← rp'1 ∧ XA A, #n4 2 2 A ← A ∨ n4 A, @HL 1 1 A ← A ∨ (HL) XA, rp' 2 2 XA ← XA ∨ rp' rp'1, XA 2 2 rp'1 ← rp'1 ∨ XA A, #n4 2 2 A ← A v n4 A, @HL 1 1 A ← A v (HL) XA, rp' 2 2 XA ← XA v rp' rp'1, XA 2 2 rp'1 ← rp'1 v XA RORC A 1 1 CY ← A0, A3 ← CY, An–1 ← An NOT A 2 2 A←A INCS reg 1 1+S reg ← reg+1 reg=0 rp1 1 1+S rp1 ← rp1+1 rp1=00H @HL 2 2+S (HL) ← (HL)+1 *1 (HL)=0 mem 2 2+S (mem) ← (mem)+1 *3 (mem)=0 reg 1 1+S reg ← reg–1 reg=FH rp' 2 2+S rp' ← rp'–1 rp'=FFH reg, #n4 2 2+S Skip if reg = n4 reg=n4 @HL, #n4 2 2+S Skip if (HL) = n4 *1 (HL) = n4 A, @HL 1 1+S Skip if A = (HL) *1 A = (HL) XA, @HL 2 2+S Skip if XA = (HL) *1 XA = (HL) A, reg 2 2+S Skip if A = reg A=reg XA, rp' 2 2+S Skip if XA = rp' XA=rp' SET1 CY 1 1 CY ← 1 CLR1 CY 1 1 CY ← 0 SKT CY 1 1+S NOT1 CY 1 1 Mnemonic AND OR XOR Accumulator manipulation Increment and Decrement DECS Comparison Carry flag manipulation SKE Operand Operation Skip if CY = 1 Addressing Area Skip Condition *1 *1 *1 CY=1 CY ← CY Data Sheet U11353EJ4V0DS00 49 µPD753036, 753036(A) Instruction Group Memory bit manipulation Mnemonic SET1 CLR1 SKT SKF SKTCLR AND1 OR1 XOR1 50 Number of Bytes Number of Machine Cycles mem.bit 2 2 (mem.bit) ← 1 *3 fmem.bit 2 2 (fmem.bit) ← 1 *4 pmem.@L 2 2 (pmem7–2+L3–2.bit(L1–0)) ← 1 *5 @H+mem.bit 2 2 (H+mem3–0.bit) ← 1 *1 mem.bit 2 2 (mem.bit) ← 0 *3 fmem.bit 2 2 (fmem.bit) ← 0 *4 pmem.@L 2 2 (pmem7–2+L3–2.bit(L1–0)) ← 0 *5 @H+mem.bit 2 2 (H+mem3–0.bit) ← 0 *1 mem.bit 2 2+S Skip if (mem.bit)=1 *3 (mem.bit)=1 fmem.bit 2 2+S Skip if (fmem.bit)=1 *4 (fmem.bit)=1 pmem.@L 2 2+S Skip if (pmem7–2+L3–2.bit(L1–0))=1 *5 (pmem.@L)=1 @H+mem.bit 2 2+S Skip if (H+mem3–0.bit)=1 *1 (@H+mem.bit)=1 mem.bit 2 2+S Skip if (mem.bit)=0 *3 (mem.bit)=0 fmem.bit 2 2+S Skip if (fmem.bit)=0 *4 (fmem.bit)=0 pmem.@L 2 2+S Skip if (pmem7–2+L3–2.bit(L1–0))=0 *5 (pmem.@L)=0 @H+mem.bit 2 2+S Skip if (H+mem3–0.bit)=0 *1 (@H+mem.bit)=0 fmem.bit 2 2+S Skip if (fmem.bit)=1 and clear *4 (fmem.bit)=1 pmem.@L 2 2+S Skip if (pmem7–2+L3–2.bit(L1–0))=1 and clear *5 (pmem.@L)=1 @H+mem.bit 2 2+S Skip if (H+mem3–0.bit)=1 and clear *1 (@H+mem.bit)=1 CY, fmem.bit 2 2 CY ← CY ∧ (fmem.bit) *4 CY, pmem.@L 2 2 CY ← CY ∧ (pmem7–2+L3–2.bit(L1–0)) *5 CY, @H+mem.bit 2 2 CY ← CY ∧ (H+mem3–0.bit) *1 CY, fmem.bit 2 2 CY ← CY ∨ (fmem.bit) *4 CY, pmem.@L 2 2 CY ← CY ∨ (pmem7–2+L3–2.bit(L1–0)) *5 CY, @H+mem.bit 2 2 CY ← CY ∨ (H+mem3–0.bit) *1 CY, fmem.bit 2 2 CY ← CY v (fmem.bit) *4 CY, pmem.@L 2 2 CY ← CY v (pmem7–2+L3–2.bit(L1–0)) *5 CY, @H+mem.bit 2 2 CY ← CY v (H+mem3–0.bit) *1 Operand Operation Data Sheet U11353EJ4V0DS00 Addressing Area Skip Condition µPD753036, 753036(A) Instruction Group Number of Bytes Number of Machine Cycles addr – – PC13–0 ← addr Select appropriate instruction from among BR !addr, BRCB !caddr, and BR $addr according to the assembler being used. BR !addr BRCB !caddr BR $addr *6 addr1 – – PC13–0 ← addr1 Select appropriate instruction from the following according to the assembler being used. BR !addr BRA !addr1 BRCB !caddr BR $sddr1 *11 !addr 3 3 PC13–0 ← addr *6 $addr 1 2 PC13–0 ← addr *7 $addr1 1 2 PC13–0 ← addr1 PCDE 2 3 PC13–0 ← PC13–8+DE PCXA 2 3 PC13–0 ← PC13–8+XA BCDENote 2 2 3 PC13–0 ← B1,0+CDE *6 BCXANote 2 2 3 PC13–0 ← B1,0+CXA *6 BRANote 1 !addr1 3 3 PC13–0 ← addr1 *11 BRCB !caddr 2 2 PC13–0 ← PC13,12+caddr11-0 *8 CALLANote 1 !addr1 3 3 (SP–5)(SP–6)(SP–3)(SP–4) ← 0, 0, PC13–0 (SP–2) ← ×, ×, MBE, RBE PC13–0 ← addr1, SP ← SP–6 *11 CALLNote 1 3 3 (SP–4)(SP–1)(SP–2) ← PC11–0 (SP–3) ← MBE, RBE, PC13, PC12 PC13–0 ← addr, SP ← SP–4 *6 4 (SP–5)(SP–6)(SP–3)(SP–4) ← 0, 0, PC13–0 (SP–2) ← ×, ×, MBE, RBE PC13–0 ← addr, SP ← SP–6 2 (SP–4)(SP–1)(SP–2) ← PC11–0 (SP–3) ← MBE, RBE, PC13, PC12 PC13–0 ← 000+faddr, SP ← SP–4 3 (SP–5)(SP–6)(SP–3)(SP–4) ← 0, 0, PC13–0 (SP–2) ← ×, ×, MBE, RBE PC13–0 ← 000+faddr, SP ← SP–6 Mnemonic BRNote1 Branch Subroutine stack control Operand !addr CALLFNote 1 !faddr Notes 1. 2 Operation Addressing Area Skip Condition *9 The above operations in the shaded boxes can be performed only in the Mk II mode. The other operations can be performed only in the Mk I mode. 2. Only the low-order 2 bits are valid for the B register. Data Sheet U11353EJ4V0DS00 51 µPD753036, 753036(A) Instruction Group Subroutine stack control Mnemonic Operand RETNote 1 Number of Bytes Number of Machine Cycles 1 3 Addressing Area Operation Skip Condition MBE, RBE, PC13, PC12 ← (SP+1) PC11–0 ← (SP)(SP+3)(SP+2), SP ← SP+4 ×, ×, MBE, RBE ← (SP+4) 0, 0, PC13, PC12 ← (SP+1) PC11–0 ← (SP)(SP+3)(SP+2), SP ← SP+6 RETSNote 1 1 3+S MBE, RBE, PC13, PC12 ← (SP+1) PC11–0 ← (SP)(SP+3)(SP+2), SP ← SP+4 then skip unconditionally Unconditional ×, ×, MBE, RBE ← (SP+4) 0, 0, PC13, PC12 ← (SP+1) PC11–0 ← (SP)(SP+3)(SP+2), SP ← SP+6 then skip unconditionally RETINote 1 1 3 MBE, RBE, PC13, PC12 ← (SP+1) PC11–0 ← (SP)(SP+3)(SP+2) PSW ← (SP+4)(SP+5), SP ← SP+6 0, 0, PC13, PC12 ← (SP+1) PC11–0 ← (SP)(SP+3)(SP+2) PSW ← (SP+4)(SP+5), SP ← SP+6 rp 1 1 (SP–1)(SP–2) ← rp, SP ← SP–2 BS 2 2 (SP–1) ← MBS, (SP–2) ← RBS, SP ← SP–2 rp 1 1 rp ← (SP+1)(SP), SP ← SP+2 BS 2 2 MBS ← (SP+1), RBS ← (SP), SP ← SP+2 2 2 IME(IPS.3) ← 1 2 2 IE××× ← 1 2 2 IME(IPS.3) ← 0 IE××× 2 2 IE××× ← 0 A, PORTn 2 2 A ← PORTn (n = 0-8) XA, PORTn 2 2 XA ← PORTn+1, PORTn (n = 4, 6) PORTn, A 2 2 PORTn ← A (n = 2-8) PORTn, XA 2 2 PORTn+1, PORTn ← XA (n = 4, 6) HALT 2 2 Set HALT Mode (PCC.2 ← 1) STOP 2 2 Set STOP Mode (PCC.3 ← 1) NOP 1 1 No Operation PUSH POP Interrupt control EI IE××× DI Input/output INNote 2 OUTNote 2 CPU control Notes 1. The above operations in the shaded boxes can be performed only in the Mk II mode. The other operations can be performed only in the Mk I mode. 2. While the IN instruction and OUT instruction are being executed, the MBE must be set to 0 or 1 and MBS must be set to 15. 52 Data Sheet U11353EJ4V0DS00 µPD753036, 753036(A) Instruction Group Special Number of Bytes Number of Machine Cycles RBn 2 2 RBS ← n (n = 0-3) MBn 2 2 MBS ← n (n = 0-2, 15) GETINotes 1, 2 taddr 1 3 • When TBR instruction PC13–0 ← (taddr)5–0+(taddr+1) Mnemonic SEL Operand Operation –––––––––––––––––––––––––––––––––– Addressing Area Skip Condition *10 –––––––––––– • When TCALL instruction (SP–4)(SP–1)(SP–2) ← PC11–0 (SP–3) ← MBE, RBE, PC13, PC12 PC13–0 ← (taddr)5–0+(taddr+1) SP ← SP–4 –––––––––––––––––––––––––––––––––– • When instruction other than TBR and TCALL instructions (taddr) (taddr+1) instruction is executed 1 3 ––––––––––––– • When TCALL instruction (SP–5)(SP–6)(SP–3)(SP–4) ← 0, 0, PC13–0 (SP–2) ← ×, ×, MBE, RBE PC13–0 ← (taddr)5–0+(taddr+1) SP ← SP–6 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –– – – – – 3 Depending on the reference instruction • When TBR instruction PC13–0 ← (taddr)5–0+(taddr+1) PC14 ← 0 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –– – – – – 4 –––––––––––– • When instruction other than TBR and TCALL instructions (taddr) (taddr+1) instruction is executed ––––––––––––– Depending on the reference instruction Notes 1. The shaded box is applicable only to the Mk II mode. The other area is applicable only to Mk I mode. 2. The TBR and TCALL instructions are the table definition assembler pseudo instructions of the GETI instruction. Data Sheet U11353EJ4V0DS00 53 µPD753036, 753036(A) 12. ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings (TA = 25°C) Parameter Symbol Conditions Supply voltage V DD Input voltage V I1 Other than ports 4, 5 V I2 Ports 4, 5 Pull-up resistor provided N-ch open drain Ratings Unit –0.3 to +7.0 V –0.3 to VDD + 0.3 V –0.3 to VDD + 0.3 V –0.3 to +14 V Output voltage VO High-level output current IOH –0.3 to VDD + 0.3 V Per pin –10 mA Low-level output current IOL Total of all pins –30 mA Per pin 30 mA Ambient operating temperature TA 200 mA –40 to +85Note °C Storage temperature Tstg –65 to +150 °C Total of all pins Note To drive LCD in the normal mode, TA = –10 to +85°C Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Capacitance (TA = 25 °C, VDD = 0 V) Parameter Input capacitance Symbol Conditions CIN f = 1 MHz Output capacitance COUT Pins other than tested pins: 0 V I/O capacitance CIO 54 Data Sheet U11353EJ4V0DS00 MIN. TYP. MAX. Unit 15 pF 15 pF 15 pF µPD753036, 753036(A) Main System Clock Oscillator Characteristics (TA = –40 to +85°C, V DD = 1.8 to 5.5 V) Oscillator Recommended Circuit Ceramic oscillator Parameter Conditions Oscillation frequency (f X) Note 1 X1 1.0 TYP. MAX. Unit 6.0 Note 2 MHz 4 ms X2 C1 C2 Oscillation stabilization timeNote 3 VDD Crystal resonator After VDD has reached MIN. value of oscillation voltage range Oscillation frequency (f X) Note 1 X1 MIN. 1.0 6.0Note 2 MHz X2 C1 C2 Oscillation stabilization timeNote 3 VDD = 4.5 to 5.5 V 10 VDD External clock 30 X1 input frequency (f X) Note 1 X1 ms 1.0 6.0 Note 2 MHz X2 X1 input high-, low-level widths (t XH, tXL) 83.3 500 ns Notes 1. The oscillation frequency and X1 input frequency shown above indicate characteristics of the oscillator 2. If the oscillation frequency is 4.19 MHz < fX < 6.0 MHz at 1.8 V ≤ VDD < 2.7 V, do not select the processor only. For the instruction execution time, refer to AC Characteristics. clock control register (PCC) = 0011. If PCC = 0011, one machine cycle is less than 0.95 µs, falling short of the rated value of 0.95 µs. 3. The oscillation stabilization time is the time required for oscillation to be stabilized after VDD has been applied or STOP mode has been released. Caution When using the main system clock oscillator, wire the portion enclosed in the dotted line in the above figure as follows to prevent adverse influences due to wiring capacitance: • Keep the wiring length as short as possible. • Do not cross the wiring with other signal lines. • Do not route the wiring in the vicinity of a line through which a high alternating current flows. • Always keep the ground point of the capacitor of the oscillator at the same potential as VDD . • Do not ground to a power supply pattern through which a high current flows. • Do not extract signals from the oscillator. Data Sheet U11353EJ4V0DS00 55 µPD753036, 753036(A) Subsystem Clock Oscillator Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V) Oscillator Recommended Circuit Crystal resonator Parameter Conditions Oscillation frequency (f XT)Note 1 XT1 MIN. TYP. MAX. Unit 32 32.768 35 kHz 1.0 2 s XT2 R C3 C4 Oscillation stabilization timeNote 2 VDD = 4.5 to 5.5 V VDD External clock XT1 Notes 1. 10 XT1 input frequency (f XT)Note 1 32 100 kHz XT1 input high-, low-level widths (t XTH, t XTL) 5 15 µs XT2 The oscillation frequency shown above indicate characteristics of the oscillator only. For the instruction execution time, refer to AC Characteristics. 2. The oscillation stabilization time is the time required for oscillation to be stabilized after VDD has been applied. Caution When using the subsystem clock oscillator, wire the portion enclosed in the dotted line in the above figure as follows to prevent adverse influences due to wiring capacitance: • Keep the wiring length as short as possible. • Do not cross the wiring with other signal lines. • Do not route the wiring in the vicinity of a line through which a high alternating current flows. • Always keep the ground point of the capacitor of the oscillator at the same potential as VDD . • Do not ground to a power supply pattern through which a high current flows. • Do not extract signals from the oscillator. The subsystem clock oscillator has a low amplification factor to reduce current consumption and is more susceptible to noise than the main system clock oscillator. Therefore, exercise utmost care in wiring the subsystem clock oscillator. 56 Data Sheet U11353EJ4V0DS00 µPD753036, 753036(A) Recommended Oscillator Constants Ceramic resonator (TA = –20 to +80°C) Manufacturer TDK Corp. Part Number Frequency (MHz) Oscillator Constant (pF) C1 C2 CCR1000K2 1.0 100 100 CCR4.19MC3 4.19 – – CCR5.0MC3 5.0 Oscillation Voltage Range (V DD) MIN. (V) MAX. (V) 2.4 5.5 6.0 FCR4.19MC5 4.19 FCR5.0MC5 5.0 FCR6.0MC5 6.0 Murata Mfg. CSB1000JNote 1.0 100 100 2.0 5.5 Co., Ltd. CSA2.00MG040 2.0 100 100 2.0 5.5 – – 4.19 30 30 2.0 5.5 CSA4.19MG CST4.19MGW – – CSA4.19MGU 30 30 CST4.19MGWU CSA6.00MG 6.0 – 30 CST6.00MGW – – CSA6.00MGU 30 30 CST6.00MGWU Kyocera Corp. – 30 Rd = 2.2 kΩ – Capacitor-contained model – Capacitor-contained model 1.8 – Capacitor-contained model 2.7 5.5 – Capacitor-contained model 2.4 – – – KBR-1000F/Y 1.0 100 100 1.8 5.5 KBR-2.0MS 2.0 68 68 2.0 5.5 KBR-4.19MKC 4.19 – – 1.9 5.5 33 33 – – – – 33 33 – – KBR-4.19MSB – Capacitor-contained model CCR6.0MC3 CST2.00MG040 Remark Capacitor-contained model – Capacitor-contained model – PBRC 4.19A PBRC 4.19B KBR-6.0MKC KBR-6.0MSB 6.0 Capacitor-contained model 1.9 5.5 Capacitor-contained model – PBRC 6.00A PBRC 6.00B Data Sheet U11353EJ4V0DS00 Capacitor-contained model 57 µPD753036, 753036(A) Note When using the CSB1000J (1.0 MHz) by Murata Mfg. Co., Ltd. as a ceramic resonator, a limiting resistor (Rd = 2.2 kΩ) is necessary (refer to the figure below). The resistor is not necessary when using the other recommended resonators. X1 X2 CSB1000J C1 Rd C2 VDD Caution The oscillator constants and oscillation voltage range indicate conditions for stable oscillation but do not guarantee accuracy of the oscillation frequency. If the application circuit requires accuracy of the oscillation frequency, it is necessary to set the oscillation frequency of the resonator in the application circuit. For this, it is necessary to directly contact the manufacturer of the resonator being used. 58 Data Sheet U11353EJ4V0DS00 µPD753036, 753036(A) DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V) Parameter Low-level output Symbol IOL current High-level input VIH1 Conditions MAX. Unit Per pin 15 mA Total of all pins 120 mA 2.7 V ≤ V DD ≤ 5.5 V Ports 2, 3 voltage VIH2 VIH3 Ports 0, 1, 6-8, RESET Ports 4, 5 MIN. 0.7 V DD VDD V 1.8 V ≤ V DD < 2.7 V 0.9 VDD VDD V 2.7 V ≤ V DD ≤ 5.5 V 0.8 V DD VDD V 1.8 V ≤ V DD < 2.7 V 0.9 VDD VDD V Pull-up resistor 2.7 V ≤ V DD ≤ 5.5 V 0.7 V DD VDD V provided 1.8 V ≤ V DD < 2.7 V 0.9 VDD VDD V 2.7 V ≤ V DD ≤ 5.5 V 0.7 V DD 13 V 1.8 V ≤ V DD < 2.7 V 0.9 VDD 13 V N-ch open drain VIH4 X1, XT1 VIL1 Ports 2-5 VIL2 Ports 0, 1, 6-8, RESET VIL3 X1, XT1 High-level output voltage VOH SCK, SO, ports 2, 3, 6-8, BP0-BP7 IOH = –1.0 mA Low-level output VOL1 SCK, SO, ports 2-8, IOL = 15 mA BP0-BP7 VDD = 4.5 to 5.5 V Low-level input voltage voltage TYP. V DD – 0.1 VDD V 2.7 ≤ VDD ≤ 5.5 V 0 0.3 VDD V 1.8 V ≤ V DD < 2.7 V 0 0.1 VDD V 2.7 ≤ VDD ≤ 5.5 V 0 0.2 VDD V 1.8 V ≤ V DD < 2.7 V 0 0.1 VDD V 0 0.1 V V DD – 0.5 V 0.2 IOL = 1.6 mA VOL2 SB0, SB1 ILIH1 VIN = V DD 2.0 V 0.4 V 0.2 VDD V Pins other than X1, XT1 3 µA X1, XT1 20 µA Ports 4, 5 (N-ch open drain) 20 µA N-ch open drain Pull-up resistor ≥ 1 kΩ High-level input leakage current ILIH2 ILIH3 VIN = 13 V Low-level input ILIL1 VIN = 0 V leakage current ILIL2 X1, XT1 ILIL3 Ports 4, 5 (N-ch open drain) Pins other than ports 4, 5, X1, XT1 –3 µA –20 µA –3 µA When input instruction is not executed Port 4, 5 (N-ch open drain) When input instruction is executed High-level output –30 µA VDD = 5.0 V –10 –20 µA VDD = 3.0 V –3 –6 µA 3 µA 20 µA –3 µA ILOH1 VOUT = VDD SCK, SO/SB0, SB1, ports 2, 3, 6-8 ILOH2 VOUT = 13 V Ports 4, 5 (N-ch open drain) ILOL VOUT = 0 V Internal pull-up RL1 VIN = 0 V resistor R L2 leakage current Low-level output Ports 4, 5 (Pull-up resistor provided) leakage current Ports 0-3, 6-8 (except pin P00) 50 100 200 kΩ Ports 4, 5 (when mask option selected) 15 30 60 kΩ Data Sheet U11353EJ4V0DS00 59 µPD753036, 753036(A) DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V) Parameter LCD drive voltage Symbol VLCD Conditions VAC0 = 0 MAX. Unit T A = –40 to +85°C MIN. 2.7 VDD V T A = –10 to 85°C 2.2 VDD V 1.8 VDD V VAC0 = 1 VAC currentNote 1 IVAC LCD divider RLCD1 resistorNote 2 RLCD2 LCD output voltage VODC deviation 1 4 µA 50 100 200 kΩ 5 10 VAC0 = 1, V DD = 2.0 V ±10% IO = ±1.0 µA VLCD0 = VLCD TYP. 20 kΩ 0 ±0.2 V 0 ±0.2 V 7.5 mA VLCD1 = VLCD × 2/3 Note 3 VLCD2 = VLCD × 1/3 (common) LCD output voltage VODS IO = ±0.5 µA 1.8 V ≤ VLCD ≤ VDD IDD1 6.00 MHzNote 5 crystal oscillation C1 = C2 = 22 pF VDD = 5.0 V ±10%Note 6 deviationNote 3 (segment) Supply currentNote 4 IDD2 IDD1 IDD2 IDD3 4.19 MHzNote 5 crystal oscillation C1 = C2 = 22 pF VDD = 3.0 V ±10% 0.6 1.8 mA HALT VDD = 5.0 V ±10% 0.9 2.7 mA mode VDD = 3.0 V ±10% 0.5 1.0 mA VDD = 5.0 V ±10%Note 6 1.7 4.5 mA ±10%Note 7 VDD = 3.0 V 0.33 1.0 mA HALT VDD = 5.0 V ±10% 0.7 2.0 mA mode VDD = 3.0 V ±10% 0.3 0.9 mA 32.768 Low- VDD = 3.0 V ±10% 12 35 µA kHzNote 8 voltage VDD = 2.0 V ±10% 5.5 16 µA crystal modeNote 9 VDD = 3.0 V, TA = 25°C 12 24 µA VDD = 3.0 V ±10% 9.2 27 µA VDD = 3.0 V, TA = 25°C 9.2 18 µA oscillation IDD4 Low current consumption mode Note 10 HALT Low- VDD = 3.0 V ±10% 8.5 25 µA mode voltage VDD = 2.0 V ±10% 3.0 12.0 µA V DD = 3.0 V, TA = 25° C 8.5 17 µA VDD = 3.0 V ±10% 4.6 13.8 µA mode Note 9 Low power consumption mode Note 10 IDD5 XT1 = 0V Note 11 V DD = 3.0 V, TA = 25° C VDD = 5.0 V ±10% VDD = 3.0 V ±10% STOP mode Notes 1. 2.5 Note 7 TA = 25°C 4.6 9.2 µA 0.05 10 µA 0.02 5.0 µA 0.02 3.0 µA Clear VAC0 to 0 in the low-current mode and STOP mode. When VAC0 is set to 1, the current increases by about 1 µA. 2. Either RLCD1 or RLCD2 can be selected by mask option. 3. Voltage deviation is the difference between the ideal values (VLCDn; n = 0, 1, 2) of the segment and common outputs and the output voltage. 4. The current flowing through the internal pull-up resistor and the LCD divider resistor is not included. 5. Including the case when the subsystem clock oscillates. 6. When the device operates in high-speed mode with the processor clock control register (PCC) set to 0011. 7. When the device operates in low-speed mode with PCC set to 0000. 8. When the device operates on the subsystem clock, with the system clock control register (SCC) set to 1001 and oscillation of the main system clock stopped. 9. When the sub-oscillator control register (SOS) is set to 0000. 10. When SOS is set to 0010. 11. When SOS is set to 00×1 and the sub-oscillator feedback resistor is not used (×: don’t care). 60 Data Sheet U11353EJ4V0DS00 µPD753036, 753036(A) AC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit 0.67 64 µs (minimum instruction main system clock 0.95 64 µs execution time = 1 Operates with subsystem clock 114 125 µs 0 1.0 MHz 0 275 kHz CPU clock cycle timeNote 1 tCY Operates with VDD = 2.7 to 5.5 V 122 machine cycle) TI0, TI1, TI2 input frequency TI0, TI1, TI2 input high-, fTI tTIH, t TIL VDD = 2.7 to 5.5 V 0.48 µs 1.8 µs IM02 = 0 Note 2 µs IM02 = 1 10 µs INT1, 2, 4 10 µs KR0-KR7 10 µs 10 µs VDD = 2.7 to 5.5 V low-level widths Interrupt input high-, tINTH, t INTL INT0 low-level widths RESET low-level width Notes 1. tRSL The cycle time (minimum instruction tCY vs VDD execution time) of the CPU clock (Φ) (with main system clock) is determined by the oscillation fre64 60 quency of the connected resonator (and external clock), the system clock control register (SCC), and processor 6 clock control register (PCC). 5 Operation guaranteed range ply voltage VDD vs. cycle time tCY characteristics when the device operates with the main system clock. 2. 2t CY or 128/fX depending on the setting of the interrupt mode register (IM0). Cycle time tCY [ µ s] The figure on the right shows the sup- 4 3 2 1 0.5 0 1 2 3 4 5 6 Supply voltage VDD [V] Data Sheet U11353EJ4V0DS00 61 µPD753036, 753036(A) Serial transfer operation 2-wire and 3-wire serial I/O modes (SCK ··· internal clock output): (TA = –40 to +85°C, VDD = 1.8 to 5.5 V) Parameter SCK cycle time SCK high-, low-level widths Symbol tKCY1 tKL1, Conditions VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V tKH1 SI Note 1 setup time (vs. SCK ↑) tSIK1 SI Note 1 hold time (vs. SCK ↑) SCK ↓ → SO Note 1 output tKSI1 tKSO1 delay time Notes 1. VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V RL = 1 kΩ Note 2 VDD = 2.7 to 5.5 V CL = 100 pF MIN. TYP. MAX. Unit 1300 ns 3800 ns tKCY1/2–50 ns tKCY1/2–150 ns 150 ns 500 ns 400 ns 600 ns 0 250 ns 0 1000 ns Read as SB0 or SB1 when using the 2-wire serial I/O mode. RL and CL respectively indicate the load resistance and load capacitance of the SO output line. 2. 2-wire and 3-wire serial I/O modes (SCK ··· external clock input): (TA = –40 to +85°C, VDD = 1.8 to 5.5 V) Parameter Symbol Conditions SCK cycle time tKCY2 VDD = 2.7 to 5.5 V SCK high-, low-level widths tKL2, VDD = 2.7 to 5.5 V tKH2 SI Note 1 setup time (vs. SCK ↑) tSIK2 VDD = 2.7 to 5.5 V SI Note 1 hold time (vs. SCK ↑) tKSI2 VDD = 2.7 to 5.5 V SCK ↓ → SONote 1 output tKSO2 RL = 1 kΩ MIN. TYP. MAX. ns 3200 ns 400 ns 1600 ns 100 ns 150 ns 400 ns 600 delay time Notes 1. 2. 62 Note 2 VDD = 2.7 to 5.5 V CL = 100 pF Unit 800 ns 0 300 ns 0 1000 ns Read as SB0 or SB1 when using the 2-wire serial I/O mode. RL and CL respectively indicate the load resistance and load capacitance of the SO output line. Data Sheet U11353EJ4V0DS00 µPD753036, 753036(A) SBI mode (SCK ··· internal clock output (master)): (TA = –40 to +85°C, VDD = 1.8 to 5.5 V) Parameter SCK cycle time SCK high-, low-level widths Symbol tKCY3 tKL3, Conditions VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V tKH3 SB0, 1 setup time tSIK3 VDD = 2.7 to 5.5 V (vs. SCK ↑) SB0, 1 hold time (vs. SCK ↑) tKSI3 SCK ↓ → SB0, 1 output tKSO3 delay time MIN. TYP. MAX. 1300 ns 3800 ns tKCY3/2–50 ns tKCY3/2–150 ns 150 ns 500 ns t KCY3/2 RL = 1 kΩ Note VDD = 2.7 to 5.5 V CL = 100 pF Unit ns 0 250 0 1000 ns ns SCK ↑ → SB0, 1 ↓ tKSB tKCY3 ns SB0, 1 ↓ → SCK ↓ tSBK tKCY3 ns SB0, 1 low-level width tSBL tKCY3 ns SB0, 1 high-level width tSBH tKCY3 ns Note RL and CL respectively indicate the load resistance and load capacitance of the SB0 and 1 output lines. SBI mode (SCK ··· external clock input (slave)): (TA = –40 to +85°C, VDD = 1.8 to 5.5 V) Parameter Symbol Conditions SCK cycle time tKCY4 VDD = 2.7 to 5.5 V SCK high-, low-level widths tKL4, VDD = 2.7 to 5.5 V tKH4 SB0, 1 setup time tSIK4 VDD = 2.7 to 5.5 V (vs. SCK ↑) SB0, 1 hold time (vs. SCK ↑) SCK ↓ → SB0, 1 output tKSI4 tKSO4 delay time RL = 1 kΩ Note VDD = 2.7 to 5.5 V CL = 100 pF MIN. TYP. MAX. Unit 800 ns 3200 ns 400 ns 1600 ns 100 ns 150 ns t KCY4/2 ns 0 300 ns 0 1000 ns SCK ↑ → SB0, 1 ↓ tKSB tKCY4 ns SB0, 1 ↓ → SCK ↓ tSBK tKCY4 ns SB0, 1 low-level width tSBL tKCY4 ns SB0, 1 high-level width tSBH tKCY4 ns Note RL and CL respectively indicate the load resistance and load capacitance of the SB0 and 1 output lines. Data Sheet U11353EJ4V0DS00 63 µPD753036, 753036(A) A/D Converter Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V, 1.8 V ≤ AVREF ≤ V DD, AVSS = VSS) Parameter Symbol Conditions Resolution Absolute accuracyNote 1 VDD = AVREF MIN. TYP. MAX. Unit 8 8 8 bit 1.5 LSB 3 LSB 2.7 V ≤ VDD 1.8 V ≤ VDD < 2.7 V VDD ≠ AVREF Conversion time tCONV Note 2 Sampling time tSAMP Note 3 Analog input voltage VIAN AV SS Analog input impedance RAN 1000 AV REF current IREF 0.25 Notes 1. 2. 3 LSB 168/f X µs 44/fX µs AVREF V MΩ 2.0 mA Absolute accuracy excluding quantization error (±1/2LSB) Time until end of conversion (EOC = 1) after execution of conversion start instruction (40.1 µs: fX = 4.19 MHz). 3. 64 Time until end of sampling after execution of conversion start instruction (10.5 µs: f X = 4.19 MHz). Data Sheet U11353EJ4V0DS00 µPD753036, 753036(A) AC timing test points (except X1 and XT1 inputs) VIH (MIN.) VIH (MIN.) VIL (MAX.) VIL (MAX.) VOH (MIN.) VOH (MIN.) VOL (MAX.) VOL (MAX.) Clock timing 1/fX tXL tXH VDD – 0.1 V X1 input 0.1 V 1/fXT tXTL tXTH VDD – 0.1 V XT1 input 0.1 V TI0, TI1, TI2 timing 1/fTI tTIL tTIH TI0, TI1, TI2 Data Sheet U11353EJ4V0DS00 65 µPD753036, 753036(A) Serial transfer timing 3-wire serial I/O mode tKCY1, 2 tKL1, 2 tKH1, 2 SCK tSIK1, 2 tKSI1, 2 Input data SI tKSO1, 2 Output data SO 2-wire serial I/O mode tKCY1, 2 tKL1, 2 tKH1, 2 SCK tSIK1, 2 tKSI1, 2 SB0, 1 tKSO1, 2 66 Data Sheet U11353EJ4V0DS00 µPD753036, 753036(A) Serial transfer timing Bus release signal transfer tKCY3, 4 tKL3, 4 tKH3, 4 SCK tKSB tSBL tSBH tSIK3, 4 tSBK tKSI3, 4 SB0, 1 tKSO3, 4 Command signal transfer tKCY3, 4 tKL3, 4 tKH3, 4 SCK tKSB tSIK3, 4 tSBK tKSI3, 4 SB0, 1 tKSO3, 4 Interrupt input timing tINTL tINTH INT0, 1, 2, 4 KR0-7 RESET input timing tRSL RESET Data Sheet U11353EJ4V0DS00 67 µPD753036, 753036(A) Data retention characteristics of data memory in STOP mode and at low supply voltage (TA = –40 to +85°C) Parameter Symbol Conditions MIN. Data retention power supply current VDDDR 1.8 Release signal setup time tSREL 0 Oscillation stabilization tWAIT wait timeNote 1 Notes 1. TYP. MAX. Unit 5.5 V µs Released by RESET Note 2 ms Released by interrupt request Note 3 ms The oscillation stabilization wait time is the time during which the CPU stops operating to prevent unstable operation when oscillation is started. 2. Either 217/fX or 215/fX can be selected by mask option. 3. Set by the basic interval timer mode register (BTM). (Refer to the table below.) Wait Time BTM3 BTM2 BTM1 BTM0 – 0 0 0 220/f x (approx. 250 ms) 220/f x (approx. 175 ms) – 0 1 1 217/f x (approx. 31.3 ms) 217/f x (approx. 21.8 ms) – 1 0 1 215/f x (approx. 7.81 ms) 215/f x (approx. 5.46 ms) 1 213/f x 213/f x (approx. 1.37 ms) fx = 4.19 MHz – 1 1 f x = 6.0 MHz (approx. 1.95 ms) Data retention timing (when STOP mode released by RESET) Internal reset operation HALT mode STOP mode Operation mode Data retention mode VDD tSREL STOP instruction execution RESET tWAIT Data retention timing (standby release signal: when STOP mode released by interrupt signal) HALT mode STOP mode Operation mode Data retention mode tSREL VDD STOP instruction execution Standby release signal (interrupt request) tWAIT 68 Data Sheet U11353EJ4V0DS00 µPD753036, 753036(A) 13. CHARACTERISTIC CURVE (reference) IDD vs. VDD (main system clock: 6.0 MHz crystal resonator) (TA = 25 °C) 10 5.0 PCC = 0011 PCC = 0010 PCC = 0001 PCC = 0000 Main system clock HALT mode + 32 kHz oscillation 1.0 Supply current IDD (mA) 0.5 0.1 0.05 Subsystem clock operation mode (SOS.1 = 0) Subsystem clock HALT mode (SOS.1 = 0) Main system clock STOP mode + 32 kHz oscillation (SOS.1 = 0) Subsystem clock HALT mode (SOS.1 = 1) Main system clock STOP mode + 32 kHz oscillation (SOS.1 = 1) 0.01 0.005 ×1 ×2 ×T1 ×T2 Crystal resonator Crystal resonator 32.768 kHz 330 kΩ 6.0 MHz 22 pF 22 pF 22 pF VDD VDD 22 pF 0.001 0 1 2 3 4 5 6 7 8 Supply voltage VDD (V) Data Sheet U11353EJ4V0DS00 69 µPD753036, 753036(A) IDD vs. VDD (main system clock: 4.19 MHz crystal resonator) (TA = 25 °C) 10 5.0 PCC = 0011 PCC = 0010 1.0 PCC = 0001 PCC = 0000 Main system clock HALT mode + 32 kHz oscillation Supply current IDD (mA) 0.5 0.1 0.05 Subsystem clock operation mode (SOS.1 = 0) Subsystem clock HALT mode (SOS.1 = 0) Main system clock STOP mode + 32 kHz oscillation (SOS.1 = 0) Subsystem clock HALT mode (SOS.1 = 1) Main system clock STOP mode + 32 kHz oscillation (SOS.1 = 1) 0.01 0.005 ×1 ×2 ×T1 ×T2 Crystal resonator Crystal resonator 32.768 kHz 330 kΩ 4.19 MHz 22 pF 22 pF 22 pF VDD VDD 22 pF 0.001 0 1 2 3 4 Supply voltage VDD (V) 70 Data Sheet U11353EJ4V0DS00 5 6 7 8 µPD753036, 753036(A) IOH vs. VDD – V OH (ports 2, 3, 6-8) (TA = 25 °C) 15 VDD = 5 V VDD = 4 V VDD = 5.5 V VDD = 3 V VDD = 2.2 V 10 5 VDD = 1.8 V 0 0 0.5 1.0 1.5 2.0 2.5 3.0 VDD – VOH [V] Data Sheet U11353EJ4V0DS00 71 µPD753036, 753036(A) IOL vs. VOL (ports 2, 3, 6-8) (TA = 25°C) 40 VDD = 5 V VDD = 4 V VDD = 3 V 30 VDD = 5.5 V IOL [mA] VDD = 2.2 V 20 VDD = 1.8 V 10 0 0 0.5 1.0 VOL [V] 72 Data Sheet U11353EJ4V0DS00 1.5 2.0 µPD753036, 753036(A) 14. PACKAGE DRAWINGS 80-PIN PLASTIC QFP (14x14) A B 60 61 41 40 detail of lead end S C D Q R 21 20 80 1 F G J I H M K P S N S L M NOTE ITEM Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition. MILLIMETERS A 17.2±0.4 B 14.0±0.2 C 14.0±0.2 D 17.2±0.4 F 0.825 G 0.825 H I 0.30±0.10 0.13 J 0.65 (T.P.) K 1.6±0.2 0.8±0.2 L M 0.15 +0.10 −0.05 N 0.10 P 2.7±0.1 Q 0.1±0.1 R 5°±5° S 3.0 MAX. S80GC-65-3B9-6 Data Sheet U11353EJ4V0DS00 73 µPD753036, 753036(A) 80 PIN PLASTIC TQFP (FINE PITCH) (12x12) A B 60 41 61 40 detail of lead end S C D Q R 21 80 1 20 F G H I J M K P M N S L NOTE Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition. S ITEM MILLIMETERS A 14.00±0.20 B 12.00±0.20 C 12.00±0.20 D F 14.00±0.20 1.25 G 1.25 H 0.22 +0.05 –0.04 I 0.10 J 0.50 (T.P.) K 1.00±0.20 L 0.50±0.20 M 0.145 +0.055 –0.045 N 0.10 P 1.05±0.07 Q 0.10±0.05 R 5°±5° S 1.27 MAX. P80GK-50-BE9-6 74 Data Sheet U11353EJ4V0DS00 µPD753036, 753036(A) 15. RECOMMENDED SOLDERING CONDITIONS Solder the µPD753036 under the following recommended conditions. For the details on the recommended soldering conditions, refer to Information Document Semiconductor Device Mounting Technology Manual (C10535E). For the soldering methods and conditions other than those recommended, consult NEC. Table 15-1. Soldering Conditions of Surface Mount Type (1) µPD753036GC-×××-3B9: 80-pin plastic QFP (14 × 14 mm, 0.65 mm pitch) µPD753036GC(A)-×××-3B9: 80-pin plastic QFP (14 × 14 mm, 0.65 mm pitch) Soldering Method Soldering Conditions Symbol of Recommended Condition Infrared reflow Package peak temperature: 235°C, Time: 30 seconds max. (210°C min.), Number of times: 3 max. IR35-00-3 VPS Package peak temperature: 215°C, Time: 40 seconds max. (200°C min.), Number of times: 3 max. VP15-00-3 Wave soldering Soldering bath temperature: 260°C max., Time: 10 seconds max., Number of times: 1 WS60-00-1 Preheating temperature: 120°C max. (package surface temperature) Partial heating Pin temperature: 300°C max., Time: 3 seconds max. (per side of device) – (2) µPD753036GK-×××-BE9: 80-pin plastic TQFP (fine pitch) (12 × 12 mm, 0.5 mm pitch) Soldering Method Soldering Conditions Symbol of Recommended Condition Infrared reflow Package peak temperature: 235°C, Time: 30 seconds max. (210°C min.), Number of times: 2 max., Exposure limit: 7 daysNote (after that, prebake at 125°C for 10 hours) IR35-107-2 VPS Package peak temperature: 215°C, Time: 40 seconds max. (200°C min.), Number of times: 2 max., Exposure limit: 7 daysNote (after that, prebake at 125°C for 10 hours) VP15-107-2 Partial heating Pin temperature: 300°C max., Time: 3 seconds max. (per side of device) Note – After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period. Caution Do not use different soldering methods together (except for partial heating). Data Sheet U11353EJ4V0DS00 75 µPD753036, 753036(A) APPENDIX A. µPD75336, 753036, 75P3036 FUNCTION LIST µPD75336 µPD753036 µPD75P3036 Mask ROM 0000H-3F7FH (16256 × 8 bits) Mask ROM 0000H-3FFFH (16384 × 8 bits) One-time PROM 0000H-3FFFH (16384 × 8 bits) Parameter Program memory Data memory CPU Instruction execution time 75X High-End 75XL CPU When main system clock is selected 0.95, 1.91, 15.3 µs (at 4.19 MHz operation) • 0.95, 1.91, 3.81, 15.3 µs (at 4.19 MHz operation) • 0.67, 1.33, 2.67, 10.7 µs (at 6.0 MHz operation) When subsystem clock is selected 122 µs (at 32.768 kHz operation) Pin 48 connection 50-53 Stack Instruction 000H-2FFH (768 × 4 bits) P22/PCL P30-P33 76 P30/MD0-P33/MD3 55 P81 P81/T12 57 IC SBS register None SBS.3 = 1: Mk I mode selection SBS.3 = 0: Mk II mode selection Stack area 000H-0FFH n00H-nFFH (n = 0-2) Subroutine call instruction stack operation 2-byte stack When Mk I mode: 2-byte stack When Mk II mode: 3-byte stack BRA !addr1 CALLA !addr1 Unavailable When Mk I mode: unavailable When Mk II mode: available VPP MOVT XA, @BCDE MOVT XA, @BCXA BR BCDE BR BCXA Timer P22/PCL/PTO2 Available CALL !addr 3 machine cycles Mk I mode: 3 machine cycles, Mk II mode: 4 machine cycles CALLF !faddr 2 machine cycles Mk I mode: 2 machine cycles, Mk II mode: 3 machine cycles 4 channels • Basic interval timer: 1 channel • 8-bit timer/event counter: 2 channels • Watch timer: 1 channel 5 channels • Basic interval timer/watchdog timer: 1 channel • 8-bit timer/event counter: 3 channels (can be used as 16-bit timer/event counter, career generator, timer with gate) • Watch timer: 1 channel Data Sheet U11353EJ4V0DS00 µPD753036, 753036(A) µPD75336 Parameter µPD753036 µPD75P3036 Clock output (PCL) • Φ, 524, 262, 65.5 kHz (Main system clock: at 4.19 MHz operation) • Φ, 524, 262, 65.5 kHz (Main system clock: at 4.19 MHz operation) • Φ, 750, 375, 93.8 kHz (Main system clock: at 6.0 MHz operation) BUZ output (BUZ) 2, 4, 32 kHz (Main system clock: at 4.19 MHz operation, or subsystem clock: at 32.762 kHz operation) • 2, 4, 32 kHz (Main system clock: during 4.19 MHz operation or subsystem clock: at 32.768 kHz operation) • 2.93, 5.86, 46.9 kHz (Main system clock: at 6.0 MHz operation) Serial interface 3 modes are available • 3-wire serial I/O mode ... MSB/LSB can be selected for transfer first bit • 2-wire serial I/O mode • SBI mode SOS register Feedback resistor cut flag (SOS.0) None Contained Sub-oscillator current cut flag (SOS.1) None Contained Register bank selection register (RBS) Yes Standby release by INT0 No Yes Vectored interrupt External: 3, internal: 4 External: 3, internal: 5 Operating supply voltage VDD = 2.7 to 6.0 V VDD = 1.8 to 5.5 V Operating ambient temperature TA = –40 to +85°C Package • 80-pin plastic TQFP (fine pitch) (12 × 12 mm, 0.5 mm pitch) • 80-pin plastic QFP (14 × 14 mm, 0.65 mm pitch) Data Sheet U11353EJ4V0DS00 77 µPD753036, 753036(A) APPENDIX B. DEVELOPMENT TOOLS The following development tools are provided for system development using the µPD753036. In 75XL series, relocatable assemblers common to the entire series are used in combination with the device file for each product type. Language processor RA75X relocatable assembler Host machine OS PC-9800 series Distribution media MS-DOSTM Part number (product name) 3.5-inch 2HD µS5A13RA75X 3.5-inch 2HC µS7B13RA75X Ver. 3.30 to Ver. 6.2 IBM PC/ATTM compatible machines Device file Note Refer to “OS for IBM PC” Host machine OS PC-9800 series Distribution media MS-DOS Part number (product name) 3.5-inch 2HD µS5A13DF753036 3.5-inch 2HC µS7B13DF753036 Ver. 3.30 to Ver. 6.2 IBM PC/AT compatible machines Note Note Refer to “OS for IBM PC” Ver.5.00 and the upper versions of Ver.5.00 have the task swap function, but it cannot be used for this software. Remark The operation of the assembler and the device file is guaranteed only on the above host machines and OSs. 78 Data Sheet U11353EJ4V0DS00 µPD753036, 753036(A) PROM write tools Hardware PG-1500 PA-75P328GC PG-1500 is a PROM programmer which enables you to program single chip microcontrollers containing PROM by stand-alone or host machine operation by connecting an attached board and optional programmer adapter to PG-1500. It also enables you to program typical PROM devices of 256 Kbits to 4 Mbits. PROM programmer adapter for the µPD75P3036GC. Connect the programmer adapter to PG-1500 for use. Software PA-75P316GK PROM programmer adapter for the µPD75P3036GK. Connect the programmer adapter to PG-1500 for use. PA-75P3036KK-T PROM programmer adapter for the µPD75P3036KK-T. Connect the programmer adapter to PG-1500 for use. PG-1500 controller PG-1500 and a host machine are connected by serial and parallel interfaces and PG-1500 is controlled on the host machine. Host machine OS PC-9800 series MS-DOS Distribution media Part number (product name) 3.5-inch 2HD µS5A13PG1500 3.5-inch 2HD µS7B13PG1500 Ver. 3.30 to Ver. 6.2 Note IBM PC/AT compatible machines Note Refer to “OS for IBM PC” Ver.5.00 and the upper versions of Ver.5.00 have the task swap function, but it cannot be used for this software. Remark The operation of the PG-1500 controller is guaranteed only on the above host machines and OSs. Data Sheet U11353EJ4V0DS00 79 µPD753036, 753036(A) Debugging tool The in-circuit emulators (IE-75000-R and IE-75001-R) are available as the program debugging tool for the µPD753036. The system configurations are described as follows. Hardware IE-75000-RNote 1 In-circuit emulator for debugging the hardware and software when developing the application systems that use the 75X series and 75XL series. When developing a µPD753036 subseries, the emulation board IE-75300-R-EM and emulation probe EP-75336GC-R or EP-75336GK-R that are sold separately must be used with the IE-75000-R. By connecting with the host machine and the PROM programmer, efficient debugging can be made. It contains the emulation board IE-75000-R-EM which is connected. IE-75001-R In-circuit emulator for debugging the hardware and software when developing the application systems that use the 75X series and 75XL series. When developing a µPD753036 sub-series, the emulation board IE-75300-R-EM and emulation probe EP-75336GC-R or EP-75336GK-R which are sold separately must be used with the IE-75001-R. It can debug the system efficiently by connecting the host machine and PROM programmer. IE-75300-R-EM Emulation board for evaluating the application systems that use the µPD753036 subseries. It must be used with the IE-75000-R or IE-75001-R. EP-75336GC-R Emulation probe for the µPD753036GC. It must be connected to IE-75000-R (or IE-75001-R) and IE-75300-R-EM. It is supplied with the 80-pin conversion socket EV-9200GC-80 which facilitates connection to a target system. EV-9200GC-80 EP-75336GK-R TGK-080SDWNote 2 Software IE control program Emulation probe for the µPD753036GK. It must be connected to the IE-75000-R (or IE-75001-R) and IE-75300-R-EM. It is supplied with the 80-pin conversion adapter TGK-080SDW which facilitates connection to a target system. Connects the IE-75000-R or IE-75001-R to a host machine via RS-232C and Centronics I/F and controls the above hardware on a host machine. Host machine OS PC-9800 series MS-DOS Ver. 3.30 to Distribution media Part number (product name) 3.5-inch 2HD µS5A13IE75X 5-inch 2HD µS5A10IE75X 3.5-inch 2HC µS7B13IE75X 5-inch 2HC µS7B10IE75X Ver. 6.2 Note 3 IBM PC/AT compatible machines Notes 1. 2. Refer to “OS for IBM PC” Maintenance parts This is a product of Tokyo Eletech Corp. For further information, contact: Daimaru Kogyo, Ltd. Tokyo Electronics Department (TEL +81-3-3820-7112) Osaka Electronics 2nd Department (TEL +81-6-6244-6672) 3. Ver.5.00 and the upper versions of Ver.5.00 have the task swap function, but it cannot be used for this software. Remarks 1. 2. 80 The operation of the IE control program is guaranteed only on the above host machines and OSs. The µPD753036 subseries consists of the µPD753036 and 75P3036. Data Sheet U11353EJ4V0DS00 µPD753036, 753036(A) OS for IBM PC The following IBM PC OS’s are supported. OS Version PC DOSTM Ver. 5.02 to Ver. 6.3 J6.1/VNote to J6.3/VNote MS-DOS Ver. 5.0 to Ver. 6.22 5.0/VNote to 6.2/VNote IBM DOSTM J5.02/VNote Note Only English version is supported. Caution Ver.5.00 and the upper versions of Ver.5.0 have the task swap function, but it cannot be used for this software. Data Sheet U11353EJ4V0DS00 81 µPD753036, 753036(A) APPENDIX C. RELATED DOCUMENTS Some of the following related documents are preliminary. Device Related Documents Document No. Document Name Japanese English µPD753036 Data Sheet U11353J U11353E (this document) µPD75P3036 Data Sheet U11575J U11575E µPD753036 User’s Manual U10201J U10201E 75XL Series Selection Guide U10453J U10453E Development Tool Related Documents Document No. Document Name Hardware Japanese English IE-75000 R/IE-75001-R User’s Manual EEU-846 EEU-1416 IE-75300-R-EM User’s Manual U11354J U11354E EP-75336GC/GK-R User’s Manual U10644J U10644E PG-1500 User’s Manual U11940J U11940E RA75X Assembler Package Operation U12622J U12622E User’s Manual Language U12385J U12385E Structured Assembler Preprocessor U12598J U12598E PC-9800 Series (MS-DOS) Base EEU-704 EEU-1291 IBM PC Series (PC DOS) Base EEU-5008 U10540E Software PG-1500 Controller User’s Manual Other Documents Document No. Document Name Japanese English SEMICONDUCTOR SELECTION GUIDE Products & Packages (CD-ROM) X13769X Semiconductor Device Mounting Technology Manual C10535J C10535E Quality Grades on NEC Semiconductor Devices C11531J C11531E NEC Semiconductor Device Reliability/Quality Control System C10983J C10983E Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892J C11892E Guide to Microcontroller-Related Products by Third Parties U11416J – Caution The above related documents are subject to change without notice. For design purpose, etc., be sure to use the latest documents. 82 Data Sheet U11353EJ4V0DS00 µPD753036, 753036(A) [MEMO] Data Sheet U11353EJ4V0DS00 83 µPD753036, 753036(A) [MEMO] 84 Data Sheet U11353EJ4V0DS00 µPD753036, 753036(A) [MEMO] Data Sheet U11353EJ4V0DS00 85 µPD753036, 753036(A) NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 86 Data Sheet U11353EJ4V0DS00 µPD753036, 753036(A) Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • Ordering information • Product release schedule • Availability of related technical literature • Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) • Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) NEC Electronics (Germany) GmbH NEC Electronics Hong Kong Ltd. Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288 Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics Hong Kong Ltd. Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (France) S.A. NEC Electronics Singapore Pte. Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Spain Office Madrid, Spain Tel: 91-504-2787 Fax: 91-504-2860 United Square, Singapore 1130 Tel: 65-253-8311 Fax: 65-250-3583 NEC Electronics Italiana s.r.l. NEC Electronics (Germany) GmbH Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 NEC Electronics (France) S.A. NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics (UK) Ltd. NEC Electronics Taiwan Ltd. Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951 NEC do Brasil S.A. Electron Devices Division Rodovia Presidente Dutra, Km 214 07210-902-Guarulhos-SP Brasil Tel: 55-11-6465-6810 Fax: 55-11-6465-6829 J99.1 Data Sheet U11353EJ4V0DS00 87 µPD753036, 753036(A) [MEMO] MS-DOS is either a registered trademark or a trademark of Microsoft Corporation in the United States and/or other countries. IBM DOS, PC/AT, and PC DOS are trademarks of IBM Corporation. The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. • The information in this document is current as of June, 2000. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. • No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. • NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. • Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. • While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. • NEC semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above). M8E 00. 4