DATA SHEET MOS INTEGRATED CIRCUIT µPD784035Y,784036Y,784037Y,784038Y 16-/8-BIT SINGLE-CHIP MICROCONTROLLERS DESCRIPTION The µPD784038Y is based on the µPD784038 with an I2C bus control function added, and is ideal for audio-visual applications. One-time PROM and EPROM versions, such as the µPD78P4038Y, that can operate in the same voltage range as mask ROM versions, and various development tools are provided. The functions are explained in detail in the following User’s Manual. Be sure to read this manual when designing your system. µPD784038, 784038Y Subseries User’s Manual - Hardware: U11316E 78K/IV Series User’s Manual - Instruction: U10905E FEATURES Timer/counter 16-bit timer/counter × 3 units 16-bit 78K/IV Series Pin-compatible with µPD78234 Subseries, timer × 1 unit µPD784026 Subseries, and µPD784038 PWM output: 2 outputs Subseries Standby function Higher internal memory capacity than µPD78234 HALT/STOP/IDLE mode Subseries and µPD784026 Subseries Clock division function Minimum instruction execution time: 125 ns Watchdog timer: 1 channel (@ 32-MHz operation) Clock output function I/O ports: 64 Selectable from fCLK, fCLK/2, f CLK/4, fCLK/8, and Serial interface: 3 channels fCLK/16 UART/IOE (3-wire serial I/O): 2 channels A/D converter: 8-bit resolution × 8 channels CSI (3-wire serial I/O, 2-wire serial I/O, I2C bus): D/A converter: 8-bit resolution × 2 channels 1 channel Supply voltage: VDD = 2.7 to 5.5 V APPLICATION FIELDS Cellular phones, cordless phones, audio-visual systems, etc. Unless contextually excluded, references in this document to the µPD784038Y mean µPD784035Y, µPD784036Y, and µPD784037Y. The information in this document is subject to change without notice. Document No. U10741EJ1V0DS00 (1st edition) Date Published July 1997 N Printed in Japan The mark ★ shows major revised points. © 1996 µPD784035Y, 784036Y, 784037Y, 784038Y ORDERING INFORMATION Part Number Package Internal ROM (Bytes) Internal RAM (Bytes) µPD784035YGC-×××-3B9 80-pin plastic QFP (14 × 14 mm, 2.7-mm thick) 48 K 2048 µPD784035YGC-×××-8BT 80-pin plastic QFP (14 × 14 mm, 1.4-mm thick) 48 K 2048 µPD784035YGK-×××-BE9Note 80-pin plastic TQFP (fine pitch) (12 × 12 mm) 48 K 2048 µPD784036YGC-×××-3B9 80-pin plastic QFP (14 × 14 mm, 2.7-mm thick) 64 K 2048 µPD784036YGC-×××-8BT 80-pin plastic QFP (14 × 14 mm, 1.4-mm thick) 64 K 2048 64 K 2048 µPD784036YGK-×××-BE9Note 80-pin plastic TQFP (fine pitch) (12 × 12 mm) µPD784037YGC-×××-3B9 80-pin plastic QFP (14 × 14 mm, 2.7-mm thick) 96 K 3584 µPD784037YGC-×××-8BT 80-pin plastic QFP (14 × 14 mm, 1.4-mm thick) 96 K 3584 µPD784037YGK-×××-BE9 80-pin plastic TQFP (fine pitch) (12 × 12 mm) 96 K 3584 µPD784038YGC-×××-3B9 80-pin plastic QFP (14 × 14 mm, 2.7-mm thick) 128 K 4352 µPD784038YGC-×××-8BT 80-pin plastic QFP (14 × 14 mm, 1.4-mm thick) 128 K 4352 µPD784038YGK-×××-BE9 80-pin plastic TQFP (fine pitch) (12 × 12 mm) 128 K 4352 Note Under development Remark ××× indicates the ROM code suffix. 2 µPD784035Y, 784036Y, 784037Y, 784038Y 78K/IV Series Product Development : Under mass production : Under development I2C bus supported µ PD784038Y µ PD784038 Standard models µ PD784026 A/D, 16-bit timer, enhanced power management Enhanced internal memory capacity Pin-compatible with the µ PD784026 Multi-master I2C bus supported µ PD784225Y µ PD784225 80-pin, ROM collection added Multi-master I2C bus supported Multi-master I2C bus supported µ PD784216Y µPD784218Y µ PD784216 100-pin, enhanced I/O and internal memory capacity µPD784218 Enhanced internal memory capacity, ROM collection added µ PD784054 µPD784046 ASSP models On-chip 10-bit A/D µPD784908 On-chip IEBusTM controller µ PD78F4943 56-Kbyte flash memory for CD-ROM µPD784915 Software servo control On-chip analog circuit for VCRs Enhanced timer Multi-master I2C bus supported µ PD784928Y µ PD784928 Enhanced functions of the µ PD784915 3 µPD784035Y, 784036Y, 784037Y, 784038Y FUNCTIONS µPD784035Y Part Number µPD784036Y µPD784037Y µPD784038Y Item Number of basic instructions (mnemonics) 113 General-purpose register 8 bits × 16 registers × 8 banks, or 16 bits × 8 registers × 8 banks (memory mapping) Minimum instruction execution time 125 ns/250 ns/500 ns/1000 ns (@ 32-MHz operation) Internal memory 48 KBytes ROM RAM Memory space I/O port Pins with ancillary functionNote 64 KBytes 2048 Bytes 96 KBytes 128 KBytes 3584 Bytes 4352 Bytes 1 MByte with program and data spaces combined Total 64 Input 8 I/O 56 Pins with pullup resistor 54 LEDs direct drive output 24 Transistor direct drive 8 Real-time output port 4 bits × 2 or 8 bits × 1 Timer/counter Timer/counter 0: Timer register × 1 (16 bits) Capture register × 1 Compare register × 2 Pulse output • Toggle output • PWM/PPG output • One-shot pulse output Timer/counter 1: Timer register × 1 (8/16 bits) Capture register × 1 Capture/compare register × 1 Compare register × 1 Pulse output • Real-time output (4 bits × 2) Timer/counter 2: Timer register × 1 (8/16 bits) Capture register × 1 Capture/compare register × 1 Compare register × 1 Pulse output • Toggle output • PWM/PPG output Timer 3: (8/16 bits) Timer register × 1 Compare register × 1 PWM output 12-bit resolution × 2 channels Serial interface UART/IOE (3-wire serial I/O) : 2 channels (on-chip baud rate generator) CSI (3-wire serial I/O, 2-wire serial I/O, I2C bus) : 1 channel A/D converter 8-bit resolution × 8 channels D/A converter 8-bit resolution × 2 channels Clock output Selectable from fCLK, fCLK/2, fCLK/4, fCLK/8, fCLK/16 (can also be used as 1-bit output port) Watchdog timer 1 channel Standby Interrupt HALT/STOP/IDLE mode Hardware source 24 (internal: 17, external: 7 (variable sampling clock input: 1)) Software source BRK instruction, BRKCS instruction, operand error Non-maskable Internal: 1, external: 1 Maskable Internal: 16, external: 6 • 4 programmable priority levels • 3 processing styles: vectored interrupt/macro service/context switching Supply voltage VDD = 2.7 to 5.5 V Package 80-pin plastic QFP (14 × 14 mm, 2.7-mm thick) 80-pin plastic QFP (14 × 14 mm, 1.4-mm thick) 80-pin plastic TQFP (fine pitch) (12 × 12 mm) Note The pins with ancillary function are included in the I/O pins. 4 µPD784035Y, 784036Y, 784037Y, 784038Y CONTENTS 1. DIFFERENCES AMONG MODELS IN µPD784038Y SUBSERIES ............................................. 7 2. MAJOR DIFFERENCES FROM µPD784026 SUBSERIES AND µPD78234 SUBSERIES ........ 8 3. PIN CONFIGURATION (TOP VIEW) ............................................................................................. 9 4. BLOCK DIAGRAM ......................................................................................................................... 11 5. PIN FUNCTION ............................................................................................................................... 12 6. 5.1 Port Pins ................................................................................................................................................ 12 5.2 Non-Port Pins ....................................................................................................................................... 14 5.3 Types of Pin I/O Circuits and Connections for Unused Pins ........................................................ 16 CPU ARCHITECTURE ................................................................................................................... 19 6.1 6.2 Memory Space ...................................................................................................................................... 19 CPU Registers ...................................................................................................................................... 24 6.2.1 General-purpose registers ........................................................................................................ 24 6.2.2 Control registers ........................................................................................................................ 25 6.2.3 Special function registers (SFRs) ............................................................................................. 26 7. PERIPHERAL HARDWARE FUNCTIONS ...................................................................................... 31 7.1 Ports ....................................................................................................................................................... 31 7.2 Clock Generation Circuit ..................................................................................................................... 32 7.3 Real-Time Output Port ......................................................................................................................... 34 7.4 Timer/Counter ....................................................................................................................................... 35 7.5 PWM Output (PWM0, PWM1) .............................................................................................................. 37 7.6 A/D Converter ....................................................................................................................................... 38 7.7 D/A Converter ....................................................................................................................................... 39 7.8 Serial Interface ..................................................................................................................................... 40 7.9 7.8.1 Asynchronous serial interface/3-wire serial I/O (UART/IOE) .................................................. 41 7.8.2 Clocked serial interface (CSI) .................................................................................................... 43 Clock Output Function ........................................................................................................................ 44 7.10 Edge Detection Function .................................................................................................................... 45 7.11 Watchdog Timer ................................................................................................................................... 45 8. INTERRUPT FUNCTION ................................................................................................................ 46 8.1 Interrupt Sources ................................................................................................................................. 46 8.2 Vectored Interrupt ................................................................................................................................ 48 8.3 Context Switching ................................................................................................................................ 49 8.4 Macro Service ....................................................................................................................................... 49 8.5 Application Example of Macro Service ............................................................................................. 50 5 µPD784035Y, 784036Y, 784037Y, 784038Y 9. LOCAL BUS INTERFACE ............................................................................................................. 52 9.1 Memory Expansion .............................................................................................................................. 52 9.2 Memory Space ...................................................................................................................................... 53 9.3 Programmable Wait ............................................................................................................................. 54 9.4 Pseudo Static RAM Refresh Function .............................................................................................. 54 9.5 Bus Hold Function ............................................................................................................................... 54 10. STANDBY FUNCTION ................................................................................................................... 55 11. RESET FUNCTION ......................................................................................................................... 56 12. INSTRUCTION SET ........................................................................................................................ 57 ★ 13. ELECTRICAL SPECIFICATIONS ................................................................................................. 62 14. PACKAGE DRAWINGS ................................................................................................................. 83 ★ 15. RECOMMENDED SOLDERING CONDITIONS ............................................................................ 86 APPENDIX A DEVELOPMENT TOOLS .............................................................................................. 88 APPENDIX B RELATED DOCUMENTS ............................................................................................. 90 6 µPD784035Y, 784036Y, 784037Y, 784038Y 1. DIFFERENCES AMONG MODELS IN µPD784038Y SUBSERIES The only difference among the µPD784035Y, 784036Y, 784037Y, and 784038Y lies in the internal memory capacity. The µPD78P4038Y is provided with a 128-KB one-time PROM or EPROM instead of the mask ROM of the above models. These differences are summarized in Table 1-1. Table 1-1. Differences among Models in µPD784038Y Subseries Part Number µPD784031Y µPD784035Y µPD784036Y µPD784037Y µPD784038Y µPD78P4038Y Item Internal ROM Not available 48 KBytes 64 KBytes 96 KBytes 128 KBytes 128 KBytes (mask ROM) (mask ROM) (mask ROM) (mask ROM) (one-time PROM or EPROM) Internal RAM Package 2048 Bytes 3584 Bytes 4352 Bytes 80-pin plastic QFP (14 × 14 mm, 2.7-mm thick) 80-pin plastic QFP (14 × 14 mm, 1.4-mm thick) 80-pin plastic TQFP (fine pitch) (12 × 12 mm) 80-pin ceramic WQFN (14 × 14 mm) 7 µPD784035Y, 784036Y, 784037Y, 784038Y 2. MAJOR DIFFERENCES FROM µPD784026 SUBSERIES AND µPD78234 SUBSERIES Series Name µPD784038Y Subseries Item µPD784038 Subseries Number of basic instructions 113 µPD784026 Subseries µPD78234 Subseries 65 (mnemonics) Minimum instruction execution time 125 ns 160 ns 333 ns (@ 32-MHz operation) (@ 25-MHz operation) (@ 12-MHz operation) Memory space (program/data) 1 MByte combined 64 KBytes/1 MByte Timer/counter 16-bit timer/counter × 1 16-bit timer/counter × 1 8-/16-bit timer/counter × 2 8-bit timer/counter × 2 8-/16-bit timer × 1 8-bit timer × 1 Clock output function Provided None Watchdog timer Provided None Serial interface UART/IOE (3-wire serial UART/IOE (3-wire serial UART × 1 channel I/O) × 2 channels I/O) × 2 channels CSI (3-wire serial I/O, SBI) CSI (3-wire serial I/O, CSI (3-wire serial I/O, SBI) × 1 channel 2-wire serial I/O, I2C × 1 channel busNote) × 1 channel Interrupt Context Provided None 4 levels 2 levels Standby function HALT/STOP/IDLE modes HALT/STOP modes Operating clock Selectable from fXX/2, fXX/4, fXX/8, and fXX /16 Fixed to fXX /2 None Specifies ROM-less mode switching Priority Pin function MODE pin (always high level with µPD78233 and 78237) TEST pin Device test pin None Usually, low level Package 80-pin plastic QFP 80-pin plastic QFP 80-pin plastic QFP (14 × 14 mm, 2.7-mm (14 × 14 mm, 2.7-mm (14 × 14 mm, 2.7-mm thick) thick) thick) 80-pin plastic QFP (14 × 80-pin plastic TQFP (fine 94-pin plastic QFP 14 mm, 1.4-mm thick) pitch) (12 × 12 mm): (20 × 20 mm) 80-pin plastic TQFP (fine µPD784021 only 84-pin plastic QFJ pitch) (12 × 12 mm) 80-pin ceramic WQFN (1150 × 1150 mil) 80-pin ceramic WQFN (14 × 14 mm): 94-pin ceramic WQFN (14 × 14 mm): µPD78P4026 only (20 × 20 mm): µPD78P238 µPD78P4038Y and 78P4038 only Note 8 µPD784038Y Subseries only only µPD784035Y, 784036Y, 784037Y, 784038Y 3. PIN CONFIGURATION (Top View) • 80-pin plastic QFP (14 × 14 mm, 2.7-mm thick) µPD784035YGC-×××-3B9, 784036YGC-×××-3B9, 784037YGC-×××-3B9, 784038YGC-×××-3B9 • 80-pin plastic QFP (14 × 14 mm, 1.4-mm thick) µPD784035YGC-×××-8BT, 784036YGC-×××-8BT, 784037YGC-×××-8BT, 784038YGC-×××-8BT • 80-pin plastic TQFP (fine pitch) (12 × 12 mm) P31/TxD/SO1 P30/RxD/SI1 P27/SI0 P26/INTP5 P25/INTP4/ASCK/SCK1 P24/INTP3 P23/INTP2/CI P22/INTP1 P21/INTP0 P20/NMI AVREF3 AVREF2 ANO1 ANO0 AVSS AVREF1 AVDD P77/ANI7 P76/ANI6 P75/ANI5 µPD784035YGK-×××-BE9Note 1, 784036YGK-×××-BE9Note 1, 784037YGK-×××-BE9, 784038YGK-×××-BE9 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 1 59 2 58 3 57 4 56 5 55 6 54 7 53 8 52 9 51 10 50 11 49 12 48 13 47 14 46 15 45 16 44 17 43 18 42 19 2021 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 4041 P74/ANI4 P73/ANI3 P72/ANI2 P71/ANI1 P70/ANI0 VDD0 P17 P16 P15 P14/TxD2/SO2 P13/TxD2/SI2 P12/ASCK2/SCK2 P11/PWM1 P10/PWM0 Note 2 TEST VSS0 ASTB/CLKOUT P40/AD0 P41/AD1 P42/AD2 P66/WAIT/HLDRQ P65/WR P64/RD P63/A19 P62/A18 P61/A17 P60/A16 P57/A15 P56/A14 P55/A13 P54/A12 P53/A11 P52/A10 P51/A9 P50/A8 P47/AD7 P46/AD6 P45/AD5 P44/AD4 P43/AD3 P32/SCK0/SCL P33/SO0/SDA P34/TO0 P35/TO1 P36/TO2 P37/TO3 RESET VDD1 X2 X1 VSS1 P00 P01 P02 P03 P04 P05 P06 P07 P67/REFRQ/HLDAK Notes 1. Under development 2. TEST pin should be connected to VSS0 directly. 9 µPD784035Y, 784036Y, 784037Y, 784038Y A8 to A19 : Address Bus P60 to P67 AD0 to AD7 : Address/Data Bus P70 to P77 : Port7 ANI0 to ANI7 : Analog Input PWM0, PWM1 : Pulse Width Modulation Output ANO0, ANO1 : Analog Output RD : Read Strobe ASCK, ASCK2 : Asynchronous Serial Clock REFRQ : Refresh Request ASTB : Address Strobe RESET : Reset AVDD : Analog Power Supply RxD, RxD2 : Receive Data AVREF1 to AVREF3 : Reference Voltage 10 : Port6 SCK0 to SCK2 : Serial Clock AVSS : Analog Ground SCL : Serial Clock CI : Clock Input SDA : Serial Data CLKOUT : Clock Output SI0 to SI2 : Serial Input HLDAK : Hold Acknowledge SO0 to SO2 : Serial Output HLDRQ : Hold Request TEST : Test INTP0 to INTP5 : Interrupt from Peripherals TO0 to TO3 : Timer Output NMI TxD, TxD2 : Transmit Data : Non-maskable Interrupt P00 to P07 : Port0 VDD0 to VDD1 : Power Supply P10 to P17 : Port1 VSS0 to VSS1 : Ground P20 to P27 : Port2 WAIT : Wait P30 to P37 : Port3 WR : Write Strobe P40 to P47 : Port4 X1, X2 : Crystal P50 to P57 : Port5 µPD784035Y, 784036Y, 784037Y, 784038Y 4. BLOCK DIAGRAM NMI INTP0 to INTP5 INTP3 TO0 TO1 TIMER/COUNTER0 (16 BITS) INTP0 TIMER/COUNTER1 (16 BITS) INTP1 INTP2/CI TO2 TO3 UART/IOE2 PROGRAMMABLE INTERRUPT CONTROLLER TIMER/COUNTER2 (16 BITS) BAUD-RATE GENERATOR UART/IOE1 BAUD-RATE GENERATOR CLOCKED SERIAL INTERFACE CLOCK OUTPUT 78K/IV CPU CORE RxD/SI1 TxD/SO1 ASCK/SCK1 RxD2/SI2 TxD2/SO2 ASCK2/SCK2 SCK0/SCL SO0/SDA SI0 ASTB/CLKOUT AD0 to AD7 ROM A8 to A15 TIMER3 (16 BITS) P00 to P03 P04 to P07 PWM0 REAL-TIME OUTPUT PORT PWM RAM PWM1 BUS I/F A16 to A19 RD WR WAIT/HLDRQ REFRQ/HLDAK PORT0 P00 to P07 PORT1 P10 to P17 PORT2 P20 to P27 PORT3 P30 to P37 PORT4 P40 to P47 PORT5 P50 to P57 PORT6 P60 to P67 PORT7 P70 to P77 ANO0 ANO1 AVREF2 D/A CONVERTER AVREF3 ANI0 to ANI7 AVDD AVREF1 AVSS INTP5 A/D CONVERTER WATCHDOG TIMER SYSTEM CONTROL RESET TEST X1 X2 VDD0, VDD1 VSS0, VSS1 Remark The internal ROM and RAM capacities differ depending on the model. 11 µPD784035Y, 784036Y, 784037Y, 784038Y 5. PIN FUNCTION 5.1 Port Pins Pin Name I/O Alternate function P00 to P07 I/O – Function Port 0 (P0): • 8-bit I/O port • Can be used as real-time output port (4 bits × 2). • Can be set in input or output mode bitwise. • Pins set in input mode can be connected to internal pull-up resistors by software. • Can drive transistor. P10 I/O Port 1 (P1): PWM0 • 8-bit I/O port P11 PWM1 P12 ASCK2/SCK2 P13 RxD2/SI2 • Can be set in input or output mode bitwise. P14 P20 resistors by software. TxD2/SO2 P15 to P17 • Pins set in input mode can be connected to internal pull-up • Can drive LEDs. – Input NMI P21 INTP0 P22 INTP1 P23 INTP2/CI Port 2 (P2): • 8-bit input port • P20 cannot be used as general-purpose port pin (non-maskable P24 INTP3 P25 INTP4/ASCK/SCK1 P26 INTP5 P27 SI0 P30 I/O RxD/S1 P31 TxD/SO1 P32 SCK0/SCL P33 SO0/SDA P34 to P37 TO0 to TO3 interrupt). However, its input level can be checked by interrupt routine. • P22 through P27 can be connected to internal pull-up resistors by software in 6-bit units. • P25/INTP4/ASCK/SCK1 pin can operate as SCK1 output pin if so specified by CSIM1. Port 3 (P3): • 8-bit I/O port • Can be set in input or output mode bitwise. P40 to P47 I/O AD0 to AD7 • Pins set in input mode can be connected to internal pull-up resistors by software. Port 4 (P4): • 8-bit I/O port • Can be set in input or output mode bitwise. • Pins set in input mode can be connected to internal pull-up resistors by software. • Can drive LEDs. P50 to P57 I/O A8 to A15 Port 5 (P5): • 8-bit I/O port • Can be set in input or output mode bitwise. • Pins set in input mode can be connected to internal pull-up resistors by software. • Can drive LEDs. 12 µPD784035Y, 784036Y, 784037Y, 784038Y Pin Name I/O P60 to P63 I/O Alternate function Function A16 to A19 Port6 (P6): P64 RD • 8-bit I/O port P65 WR P66 WAIT/HLDRQ P67 REFRQ/HLDAK P70 to P77 I/O AN10 to AN17 • Can be set in input or output mode bitwise. • Pins set in input mode can be connected to internal pull-up resistors by software. Port 7 (P7): • 8-bit I/O port • Can be set in input or output mode bitwise. 13 µPD784035Y, 784036Y, 784037Y, 784038Y 5.2 Non-Port Pins Pin Name I/O TO0 to TO3 Output P34 to P37 Timer output CI Input P23/INTP2 Count clock input to timer/counter 2 RxD Input P30/SI1 Serial data input (UART0) P13/SI2 Serial data input (UART2) P31/SO1 Serial data output (UART0) P14/SO2 Serial data output (UART2) RxD2 TxD Output TxD2 ASCK Input Alternate function Function P25/INTP4/SCK1 Baud rate clock input (UART0) P12/SCK2 Baud rate clock input (UART2) P33/SO0 Serial data input/output (2-wire serial I/O, I2C bus) P27 Serial data input (3-wire serial I/O0) SI1 P30/RxD Serial data input (3-wire serial I/O1) SI2 P13/RxD2 Serial data input (3-wire serial I/O2) P33/SDA Serial data output (3-wire serial I/O0) P31/TxD Serial data output (3-wire serial I/O1) ASCK2 SDA I/O SI0 Input SO0 Output SO1 SO2 P14/TxD2 Serial data output (3-wire serial I/O2) P32/SCL Serial clock input/output (3-wire serial I/O0) SCK1 P25/INTP4/ASCK Serial clock input/output (3-wire serial I/O1) SCK2 P12/ASCK2 Serial clock input/output (3-wire serial I/O2) SCL P32/SCK0 Serial clock input/output (2-wire serial I/O, I2C bus) P20 External interrupt requests SCK0 NMI I/O Input – INTP0 P21 • Count clock input to timer/counter 1 • Capture trigger signal of CR11 or CR12 INTP1 P22 • Count clock input to timer/counter 2 • Capture trigger signal of CR22 INTP2 P23/CI • Count clock input to timer/counter 2 • Capture trigger signal of CR21 INTP3 P24 • Count clock input to timer/counter 0 • Capture trigger signal of CR02 INTP4 P25/ASCK/SCK1 INTP5 P26 AD0 to AD7 – Conversion start trigger input to A/D converter I/O P40 to P47 Time-division address/data bus (for external memory connection) A8 to A15 Output P50 to P57 Higher address bus (for external memory connection) A16 to A19 Output P60 to P63 Higher address when address is extended (for external memory connection) RD Output P64 Read strobe to external memory WR Output P65 Write strobe to external memory Input P66/HLDRQ Wait insertion REFRQ Output P67/HLDAK Refresh pulse output to external pseudo static memory HLDRQ Input P66/WAIT Bus hold request input HLDAK Output P67/REFRQ Bus hold acknowledge output ASTB Output CLKOUT Latch timing output of time-division address (A0 through A7) WAIT (when accessing external memory) CLKOUT 14 Output ASTB Clock output µPD784035Y, 784036Y, 784037Y, 784038Y Pin Name I/O Alternate function Function RESET Input – Chip reset X1 Input – Crystal connection for system clock oscillation X2 – (Clock can also be input to X1). ANI0 to ANI7 Input ANO0, ANO1 Output – Analog voltage output from D/A converter – – Reference voltage to A/D converter AVREF1 P70 to P77 Analog voltage input to A/D converter AVREF2, AVREF3 Reference voltage to D/A converter AVDD A/D converter power supply AVSS A/D converter GND VDD0Note1 Positive power supply of the port block VDD1Note1 Positive power supply except for the port block VSS0Note2 GND of the port block VSS1Note2 GND except for the port block TEST Directly connect to VSS0 (IC test pin). Notes 1. The potential of the VDD0 pin must be equal to that of the VDD1 pin. 2. The potential of the VSS0 pin must be equal to that of the VSS1 pin. 15 µPD784035Y, 784036Y, 784037Y, 784038Y 5.3 Types of Pin I/O Circuits and Connections for Unused Pins Table 5-1 shows types of pin I/O circuits and the connections for unused pins. For the input/output circuit of each type, refer to Figure 5-1. Table 5-1. Types of Pin I/O Circuits and Connections for Unused Pins Pin Name P00 to P07 I/O Circuit Type 5-H I/O I/O P10/PWM0 Recommended Connection for Unused Pins Input: Connect to VDD0 Output: Open P11/PWM1 P12/ASCK2/SCK2 8-C P13/RxD2/SI2 5-H P14/TxD2/SO2 P15 to P17 P20/NMI 2 Input Connect to VDD0 or VSS0. P21/INTP0 P22/INTP1 2-C Connect to VDD0. P23/INTP2/CI P24/INTP3 P25/INTP4/ASCK/SCK1 8-C I/O Input: Connect to VDD0 Output: Open P26/INTP5 2-C Input Connect to VDD0. 5-H I/O Input: Connect to VDD0. P27/SI0 P30/RxD/SI1 P31/TxD/SO1 P32/SCK0/SCL Output: Open 10-B P33/SO0/SDA P34/TO0 to P37/TO3 5-H P40/AD0 to P47/AD7 P50/A8 to P57/A15 P60/A16 to P63/A19 P64/RD P65/WR P66/WAIT/HLDRQ P67/REFRQ/HLDAK P70/ANI0 to P77/ANI7 20-A I/O Input: Connect to VDD0 or VSS0. Output: Open ANO0, ANO1 12 ASTB/CLKOUT 4-B 16 Output Open µPD784035Y, 784036Y, 784037Y, 784038Y Pin Name I/O Circuit Type RESET 2 TEST 1-A AVREF1 to AVREF3 I/O Recommended Connection for Unused Pins Input – Directly connect to VSS0. – Connect to VSS0. AVSS AVDD Connect to VDD0. Caution Connect an I/O pin whose input/output mode is unstable to VDD0 via a resistor of several 10 kΩ (especially if the voltage on the reset input pin rises higher than the low-level input level on power application or when the mode is switched between input and output by software). Remark Because the circuit type numbers shown in the above table are commonly used with all the models in the 78K Series, these numbers of some models are not serial (because some circuits are not provided to some models). 17 µPD784035Y, 784036Y, 784037Y, 784038Y Figure 5-1. Types of Pin I/O Circuits Type 1-A Type 2-C VDD0 VDD0 P IN pullup enable P N VSS0 Type 2 IN IN Schmitt trigger input with hysteresis characteristics Type 5-H Schmitt trigger input with hysteresis characteristics Type 4-B VDD0 data VDD0 pullup enable P VDD0 P data P OUT output disable IN/OUT N output disable VSS0 Push-pull output that can go into a high-impedance state (with both P-ch and N-ch off) N VSS0 input enable Type 12 Type 8-C VDD0 pullup enable P VDD0 data P Analog output voltage P N IN/OUT output disable OUT N VSS0 Type 10-B Type 20-A VDD0 VDD0 data pullup enable P P IN/OUT VDD0 data output disable P N VSS0 IN/OUT Comparator open drain output disable – N P N AVSS AVREF (threshold voltage) VSS0 input enable 18 + µPD784035Y, 784036Y, 784037Y, 784038Y 6. CPU ARCHITECTURE 6.1 Memory Space A memory space of 1 MByte can be accessed. Mapping of the internal data area (special function registers and internal RAM) can be specified the LOCATION instruction. The LOCATION instruction must be always executed after RESET cancellation, and must not be used more than once. (1) When LOCATION 0 instruction is executed • Internal memory The internal data area and internal ROM area are mapped as follows: Part Number µPD784035Y Internal Data Area Internal ROM Area 0F700H-0FFFFH 00000H-0BFFFH µPD784036Y µPD784037Y 00000H-0F6FFH 0F100H-0FFFFH 00000H-0F0FFH 10000H-17FFFH µPD784038Y 0EE00H-0FFFFH 00000H-0FDFFH 10000H-1FFFFH Caution The following areas that overlap the internal data area of the internal ROM cannot be used when the LOCATION 0 instruction is executed. Part Number Unusable Area µPD784035Y – µPD784036Y 0F700H-0FFFFH (2304 Bytes) µPD784037Y 0F100H-0FFFFH (3840 Bytes) µPD784038Y 0EE00H-0FFFFH (4608 Bytes) • External memory The external memory is accessed in external memory expansion mode. (2) When LOCATION 0FH instruction is executed • Internal memory The internal data area and internal ROM area are mapped as follows: Part Number µPD784035Y Internal Data Area Internal ROM Area FF700H-FFFFFH 00000H-0BFFFH µPD784036Y 00000H-0FFFFH µPD784037Y FF100H-FFFFFH 00000H-17FFFH µPD784038Y FEE00H-FFFFFH 00000H-1FFFFH • External memory The external memory is accessed in external memory expansion mode. 19 20 Figure 6-1. Memory Map of µPD784035Y On execution of LOCATION 0 instruction On execution of LOCATION 0FH instruction F F F F FH F FEF FH 0 FEF FH General-purpose registers (128 Bytes) Note 1 External memory (960 KBytes) 0 FE8 0H 0 FE 7 FH 1 0 0 0 0H 0 F F F FH Special 0 F FDFH Note 1 0 F FD0H 0 FF 0 0H 0 FEF FH 0 FE3 1H function registers (SFR) F F F F F H Special F F FDFH Note 1 F F FD0H FFF 0 0H F FEF FH 0 FE0 6H (256 Bytes) (256 Bytes) Internal RAM (2048 Bytes) FFE8 0H F FE 7 FH Macro service control word area (44 Bytes) function registers (SFR) FF 7 0 0H F F 6 F FH FFE3 1H FFE0 6H Data area (512 Bytes) Internal RAM (2048 Bytes) F FD0 0H F FCF FH External memory (997120 Bytes) Program/data area (1536 Bytes) 0 F 7 0 0H 0 F 7 0 0H 0 F 6 F FH Note 1 FF 7 0 0H 0 BF F FH Note 2 External memory (14080 KBytes) Program/data area (48 KBytes) Note 1 0 1 0 0 0H 0 0 F F FH CALLF entry area (2 KB) 0C0 0 0H 0 BF F FH 0 0 8 0 0H 0 0 7 F FH 0 0 0 8 0H 0 0 0 7 FH Internal ROM (48 KBytes) 0 0 0 0 0H 0 0 0 4 0H 0 0 0 3 FH 0 0 0 0 0H 1 0 0 0 0H 0 F F F FH Note 2 0C0 0 0H 0 BF F FH CALLT table area (64 Bytes) Vector table area (64 Bytes) Internal ROM (48 KBytes) 0 0 0 0 0H Notes 1. Accessed in external memory expansion mode. 2. Base area and entry area for reset or interrupt. However, the internal RAM area is not used as a reset entry area. µPD784035Y, 784036Y, 784037Y, 784038Y 0 FD0 0H 0 FCF FH Figure 6-2. Memory Map of µPD784036Y On execution of LOCATION 0 instruction On execution of LOCATION 0FH instruction F F F F FH F FEF FH 0 FEF FH General-purpose registers (128 Bytes) Note 1 External memory (960 KBytes) 0 FE8 0H 0 FE 7 FH 0 FE3 1H function registers (SFR) 0 FE0 6H (256 Bytes) (256 Bytes) Internal RAM (2048 Bytes) FFE8 0H F FE 7 FH Macro service control word area (44 Bytes) function registers (SFR) FF 7 0 0H F F 6 F FH FFE3 1H FFE0 6H Data area (512 Bytes) 0 FD0 0H 0 FCF FH Internal RAM (2048 Bytes) F FD0 0H F FCF FH External memory (980736 Bytes) Program/data area (1536 Bytes) 0 F 7 0 0H 0 F 7 0 0H 0 F 6 F FH Note 1 FF 7 0 0H 0 F F F FH Note 2 0 F 6 F FH Note 3 Program/data area Note 4 0 1 0 0 0H 0 0 F F FH CALLF entry area (2 KBytes) Internal ROM (63232 Bytes) 0 0 8 0 0H 0 0 7 F FH 0 0 0 8 0H 0 0 0 7 FH 0 0 0 4 0H 0 0 0 3 FH 0 0 0 0 0H 0 0 0 0 0H 1 0 0 0 0H 0 F F F FH CALLT table area (64 Bytes) Vector table area (64 Bytes) Internal ROM (64 KBytes) Note 4 0 0 0 0 0H Notes 1. Accessed in external memory expansion mode. 21 2. This 2304-Byte area can be used as an internal ROM only when the LOCATION 0FH instruction is executed. 3. On execution of LOCATION 0 instruction: 63232 Bytes, on execution of LOCATION 0FH instruction: 65536 Bytes 4. Base area and entry area for reset or interrupt. However, the internal RAM area is not used as a reset entry area. µPD784035Y, 784036Y, 784037Y, 784038Y 1 0 0 0 0H 0 F F F FH Special 0 F FDFH Note 1 0 F FD0H 0 FF 0 0H 0 FEF FH F F F F F H Special F F FDFH Note 1 F F FD0H FFF 0 0H F FEF FH 22 Figure 6-3. Memory Map of µPD784037Y On execution of LOCATION 0 instruction On execution of LOCATION 0FH instruction F F F F FH Note 1 External memory (928 KBytes) 1 8 0 0 0H 1 7 F F FH F FEF FH 0 FEF FH F F F F F H Special F F FDFH Note 1 F F FD0H FFF 0 0H F FEF FH General-purpose registers (128 Bytes) (256 Bytes) Internal RAM (3584 Bytes) FFE8 0H F FE 7 FH 0 FE8 0H 0 FE 7 FH function registers (SFR) FF 1 0 0H F F 0 F FH Internal ROM (32768 Bytes) 1 0 0 0 0H 0 F F F FH Special function registers 0 F FDFH Note 1 0 F FD0H (256 Bytes) 0 FF 0 0H 0 FEF FH 0 FE3 1H (SFR) 0 FE0 6H Macro service control word area (44 Bytes) FFE3 1H FFE0 6H Data area (512 Bytes) 0 FD0 0H 0 FCF FH F FD0 0H F FCF FH External memory (946432 Bytes) Program/data area (3072 Bytes) 0 F 1 0 0H 0 F 0 F FH 0 F 1 0 0H FF 1 0 0H 1 7 F F FH 1 0 0 0 0H 1 7 F F FH Note 1 Note 2 0 F 0 F FH Note 3 Program/data area Note 4 0 1 0 0 0H 0 0 F F FH CALLF entry area (2 KBytes) Internal ROM (61696 Bytes) 0 0 8 0 0H 0 0 7 F FH 0 0 0 8 0H 0 0 0 7 FH 0 0 0 4 0H 0 0 0 3 FH 0 0 0 0 0H 0 0 0 0 0H 1 8 0 0 0H 1 7 F F FH CALLT table area (64 Bytes) Vector table area (64 Bytes) Internal ROM (96 KBytes) 0 0 0 0 0H Notes 1. Accessed in external memory expansion mode. 2. This 3840-Byte area can be used as an internal ROM only when the LOCATION 0FH instruction is executed. 3. On execution of LOCATION 0 instruction: 94464 Bytes, on execution of LOCATION 0FH instruction: 98304 Bytes 4. Base area and entry area for reset or interrupt. However, the internal RAM area is not used as a reset entry area. Note 4 µPD784035Y, 784036Y, 784037Y, 784038Y Internal RAM (3584 Bytes) Figure 6-4. Memory Map of µPD784038Y On execution of LOCATION 0 instruction On execution of LOCATION 0FH instruction F F F F FH Note 1 External memory (896 KBytes) 2 0 0 0 0H 1 F F F FH F FEF FH 0 FEF FH F F F F F H Special F F FDFH Note 1 F F FD0H FFF 0 0H F FEF FH General-purpose registers (128 Bytes) (256 Bytes) Internal RAM (4352 Bytes) FFE8 0H F FE 7 FH 0 FE8 0H 0 FE 7 FH function registers (SFR) FEE 0 0H F EDF FH Internal ROM 0 FE3 1H (SFR) 0 FE0 6H Macro service control word area (44 Bytes) FFE3 1H FFE0 6H Data area (512 Bytes) 0 FD0 0H 0 FCF FH Internal RAM (4352 Bytes) F FD0 0H F FCF FH External memory (912896 Bytes) Program/data area (3840 Bytes) 0 EE 0 0H 0 EDF FH 0 EE 0 0H FEE 0 0H 1 F F F FH 1 0 0 0 0H 1 F F F FH Note 1 Note 2 0 EDF FH Note 3 Program/data area Note 4 0 1 0 0 0H 0 0 F F FH CALLF entry area (2 KBytes) Internal ROM (60928 Bytes) 0 0 8 0 0H 0 0 7 F FH 0 0 0 8 0H 0 0 0 7 FH 0 0 0 4 0H 0 0 0 3 FH 0 0 0 0 0H 0 0 0 0 0H 2 0 0 0 0H 1 F F F FH CALLT table area (64 Bytes) Vector table area (64 Bytes) Internal ROM (128 KBytes) Note 4 0 0 0 0 0H 23 Notes 1. Accessed in external memory expansion mode. 2. This 4608-Byte area can be used as an internal ROM only when the LOCATION 0FH instruction is executed. 3. On execution of LOCATION 0 instruction: 126464 Bytes, on execution of LOCATION 0FH instruction: 131072 Bytes 4. Base area and entry area for reset or interrupt. However, the internal RAM area is not used as a reset entry area. µPD784035Y, 784036Y, 784037Y, 784038Y (65536 Bytes) 1 0 0 0 0H 0 F F F FH Special function registers 0 F FDFH Note 1 0 F FD0H (256 Bytes) 0 FF 0 0H 0 FEF FH µPD784035Y, 784036Y, 784037Y, 784038Y 6.2 CPU Registers 6.2.1 General-purpose registers Sixteen 8-bit general-purpose registers are available. Two 8-bit registers can be also used in pairs as a 16-bit register. Of the 16-bit registers, four can be used in combination with an 8-bit register for address expansion as 24bit address specification registers. Eight banks of these registers are available which can be selected by using software or the context switching function. The general-purpose registers except V, U, T, and W registers for address expansion are mapped to the internal RAM. Figure 6-5. General-Purpose Register Format A (R1) X (R0) AX (RP0) B (R3) C (R2) BC (RP1) R5 R4 RP2 R7 R6 RP3 V R9 VP (RP4) VVP (RG4) U R8 R11 R10 T UP (RP5) UUP (RG5) D (R13) E (R12) W DE (RP6) TDE (RG6) H (R15) L (R14) 8 banks WHL (RG7) Parentheses ( HL (RP7) ) indicate an absolute name. Caution Registers R4, R5, R6, R7, RP2, and RP3 can be used as X, A, C, B, AX, and BC registers, respectively, by setting the RSS bit of the PSW to 1. However, use this function only for recycling the program of the 78K/III Series. 24 µPD784035Y, 784036Y, 784037Y, 784038Y 6.2.2 Control registers (1) Program counter (PC) The program counter is a 20-bit register whose contents are automatically updated when the program is executed. Figure 6-6. Program Counter (PC) Format 19 0 PC (2) Program status word (PSW) This register holds the statuses of the CPU. Its contents are automatically updated when the program is executed. Figure 6-7. Program Status Word (PSW) Format PSWH 15 14 13 12 11 10 9 8 UF RBS2 RBS1 RBS0 – – – – 7 6 5 4 3 2 1 0 AC IE P/V 0 CY PSW PSWL Note S Z RSS Note This flag is provided to maintain compatibility with the 78K/III Series. Be sure to clear this flag to 0, except when the software for the 78K/III Series is used. (3) Stack pointer (SP) This is a 24-bit pointer that holds the first address of the stack. Be sure to write 0 to the higher 4 bits of this pointer. Figure 6-8. Stack Pointer (SP) Format 23 SP 0 20 0 0 0 0 25 µPD784035Y, 784036Y, 784037Y, 784038Y 6.2.3 Special function registers (SFRs) The special function registers, such as the mode registers and control registers of the internal peripheral hardware, are registers to which special functions are allocated. These registers are mapped to a 256-Byte space of addresses 0FF00H through 0FFFFHNote. Note On execution of the LOCATION 0 instruction. FFF00H through FFFFFH on execution of the LOCATION 0FH instruction. Caution Do not access an address in this area to which no SFR is allocated. If such an address is accessed by mistake, the µPD784038Y may be in the deadlock status. This deadlock status can be cleared only by inputting the RESET signal. Table 6-1 lists the special function registers (SFRs). The meanings of the symbols in this table are as follows: • Symbol ............................... Symbol indicating an SFR. This symbol is reserved for NEC’s assembler (RA78K4). It can be used as an sfr variable by the #pragma sfr command with the C compiler (CC78K4). • R/W .................................... Indicates whether the SFR is read-only, write-only, or read/write. R/W : Read/write R : Read-only W : Write-only • Bit units for manipulation .. Bit units in which the value of the SFR can be manipulated. SFRs that can be manipulated in 16-bit units can be described as the operand sfrp of an instruction. To specify the address of this SFR, describe an even address. SFRs that can be manipulated in 1-bit units can be described as the operand of a bit manipulation instruction. • After reset .......................... Indicates the status of the register when the RESET signal has been input. 26 µPD784035Y, 784036Y, 784037Y, 784038Y Table 6-1. Special Function Registers (SFRs) AddressNote Special Function Register (SFR) Name Symbol R/W Bit units for manipulation 1 bit 8 bits 16 bits 0FF00H Port 0 P0 0FF01H Port 1 P1 0FF02H Port 2 P2 R – 0FF03H Port 3 P3 R/W – 0FF04H Port 4 P4 – 0FF05H Port 5 P5 – 0FF06H Port 6 P6 – 00H 0FF07H Port 7 P7 – Undefined P0L – – 0FF0EH Port 0 buffer register L R/W After reset – Undefined – 0FF0FH Port 0 buffer register H P0H 0FF10H Compare register (timer/counter 0) CR00 – – 0FF12H Capture/compare register (timer/counter 0) CR01 – – 0FF14H Compare register L (timer/counter 1) CR10 CR10W – 0FF15H Compare register H (timer/counter 1) 0FF16H Capture/compare register L (timer/counter 1) 0FF17H Capture/compare register H (timer/counter 1) 0FF18H Compare register L (timer/counter 2) 0FF19H Compare register H (timer/counter 2) 0FF1AH Capture/compare register L (timer/counter 2) 0FF1BH Capture/compare register H (timer/counter 2) 0FF1CH Compare register L (timer 3) 0FF1DH Compare register H (timer 3) 0FF20H Port 0 mode register PM0 – 0FF21H Port 1 mode register PM1 – 0FF23H Port 3 mode register PM3 – 0FF24H Port 4 mode register PM4 – 0FF25H Port 5 mode register PM5 – 0FF26H Port 6 mode register PM6 – 0FF27H Port 7 mode register PM7 – 0FF2EH Real-time output port control register RTPC – 00H 0FF30H Capture/compare control register 0 CRC0 – 10H 0FF31H Timer output control register TOC – 00H 0FF32H Capture/compare control register 1 CRC1 – – 0FF33H Capture/compare control register 2 CRC2 – – Note – CR11 CR11W – CR20 CR20W – CR21 CR21W – CR30 CR30W – – – – – – – – – – – – – – – – FFH 10H When the LOCATION 0 instruction is executed. When the LOCATION 0FH instruction is executed, “F0000H” is added to this value. 27 µPD784035Y, 784036Y, 784037Y, 784038Y AddressNote 1 Special Function Register (SFR) Name Symbol R/W R Bit units for manipulation 1 bit 8 bits – – 16 bits 0FF36H Capture register (timer/counter 0) CR02 0FF38H Capture register L (timer/counter 1) CR12 CR12W 0FF39H Capture register H (timer/counter 1) 0FF3AH Capture register L (timer/counter 2) 0FF3BH Capture register H (timer/counter 2) 0FF41H Port 1 mode control register PMC1 0FF43H Port 3 mode control register PMC3 – 0FF4EH Pull-up resistor option register PUO – 0FF50H Timer register 0 TM0 Timer register 1 0FF53H 0FF54H – – CR22 CR22W 0FF55H 0FF56H – – 0FF57H – R/W R TM1 TM1W – – – – – 00H 0000H – – TM2 TM2W – – – Timer register 3 – – – Timer register 2 0000H – 0FF51H 0FF52H After reset – TM3 TM3W – – – – 0FF5CH Prescaler mode register 0 PRM0 0FF5DH Timer control register 0 TMC0 0FF5EH Prescaler mode register 1 PRM1 0FF5FH Timer control register 1 TMC1 0FF60H D/A conversion value setting register 0 DACS0 – – 0FF61H D/A conversion value setting register 1 DACS1 – – 0FF62H D/A converter mode register DAM – 03H 0FF68H A/D converter mode register ADM – 00H 0FF6AH A/D conversion result register ADCR R – Undefined 0FF70H PWM control register PWMC R/W – 05H 0FF71H PWM prescaler register PWPR – – 00H 0FF72H PWM modulo register 0 PWM0 – – 0FF74H PWM modulo register 1 PWM1 – – 0FF7DH One-shot pulse output control register OSPC – 0FF80H I2C IICC – 0FF81H Prescaler mode register for serial clock SPRM 0FF82H Clocked serial interface mode register CSIM 0FF83H bus control register Slave address register SVA R/W – – – – – R/WNote 2 Note 3 – 11H – 00H – 11H – 00H Undefined 00H – 04H – 00H – 01H Notes 1. When the LOCATION 0 instruction is executed. When the LOCATION 0FH instruction is executed, “F0000H” is added to this value. 2. Bit 0 is read-only. 3. Only bit 0 can be manipulated in bit units. 28 µPD784035Y, 784036Y, 784037Y, 784038Y AddressNote 1 Special Function Register (SFR) Name Symbol R/W Bit units for manipulation 1 bit 0FF84H Clocked serial interface mode register 1 CSIM1 0FF85H Clocked serial interface mode register 2 CSIM2 0FF86H Serial shift register SIO 0FF88H Asynchronous serial interface mode register ASIM 0FF89H Asynchronous serial interface mode register 2 ASIM2 0FF8AH Asynchronous serial interface status register ASIS 0FF8BH Asynchronous serial interface status register 2 ASIS2 0FF8CH Serial receive buffer: UART0 RXB Serial transmit shift register: UART0 TXS Serial shift register: IOE1 8 bits R/W 16 bits – 00H – – – – – R – – – – W – – SIO1 R/W – – Serial receive buffer: UART2 RXB2 R – – Serial transmit shift register: UART2 TXS2 W – – Serial shift register: IOE2 SIO2 R/W – – 0FF90H Baud rate generator control register BRGC – – 0FF91H Baud rate generator control register 2 BRGC2 – – 0FFA0H External interrupt mode register 0 INTM0 – 0FFA1H External interrupt mode register 1 INTM1 – 0FFA4H Sampling clock select register SCS0 0FFA8H In-service priority register ISPR R – 0FFAAH Interrupt mode control register IMC R/W – 0FFACH Interrupt mask register 0L MK0L MK0 0FFADH Interrupt mask register 0H MK0H 0FFAEH Interrupt mask register 1L MK1L 0FFC0H Standby control register STBC – 0FFC2H Watchdog timer mode register WDM – 0FFC4H Memory expansion mode register 0FFC5H 0FF8DH After reset – Undefined 00H – 80H FFFFH – FFH Note 2 – 30H Note 2 – 00H MM – 20H Hold mode register HLDM – 00H 0FFC6H Clock output mode register CLOM – 0FFC7H Programmable wait control register 1 PWC1 – 0FFC8H Programmable wait control register 2 PWC2 – – – AAH AAAAH Notes 1. When the LOCATION 0 instruction is executed. When the LOCATION 0FH instruction is executed, “F0000H” is added to this value. 2. Data can be written by using only a dedicated instruction such as “MOV STBC, #byte instruction” and “MOV WDM, #byte instruction”, and cannot be written with any other instructions. 29 µPD784035Y, 784036Y, 784037Y, 784038Y AddressNote Special Function Register (SFR) Name Symbol R/W Bit units for manipulation 1 bit 0FFCCH Refresh mode register RFM R/W 0FFCDH Refresh area specification register RFA 0FFCFH Oscillation stabilization time specification OSTS 8 bits After reset 16 bits – 00H – – – register 0FFD0H- External SFR area – – – 0FFDFH 0FFE0H Interrupt control register (INTP0) PIC0 – 0FFE1H Interrupt control register (INTP1) PIC1 – 0FFE2H Interrupt control register (INTP2) PIC2 – 0FFE3H Interrupt control register (INTP3) PIC3 – 0FFE4H Interrupt control register (INTC00) CIC00 – 0FFE5H Interrupt control register (INTC01) CIC01 – 0FFE6H Interrupt control register (INTC10) CIC10 – 0FFE7H Interrupt control register (INTC11) CIC11 – 0FFE8H Interrupt control register (INTC20) CIC20 – 0FFE9H Interrupt control register (INTC21) CIC21 – 0FFEAH Interrupt control register (INTC30) CIC30 – 0FFEBH Interrupt control register (INTP4) PIC4 – 0FFECH Interrupt control register (INTP5) PIC5 – 0FFEDH Interrupt control register (INTAD) ADIC – 0FFEEH Interrupt control register (INTSER) SERIC – 0FFEFH Interrupt control register (INTSR) SRIC – Interrupt control register (INTCSI1) CSIIC1 – 0FFF0H Interrupt control register (INTST) STIC – 0FFF1H Interrupt control register (INTCSI) CSIIC – 0FFF2H Interrupt control register (INTSER2) SERIC2 – 0FFF3H Interrupt control register (INTSR2) SRIC2 – Interrupt control register (INTCSI2) CSIIC2 – 0FFF4H Interrupt control register (INTST2) STIC2 – 0FFF5H Interrupt control register (INTSPC) SPCIC – Note 30 43H When the LOCATION 0 instruction is executed. When the LOCATION 0FH instruction is executed, “F0000H” is added to this value. µPD784035Y, 784036Y, 784037Y, 784038Y 7. PERIPHERAL HARDWARE FUNCTIONS 7.1 Ports The ports shown in Figure 7-1 are provided to make various control operations possible. Table 7-1 shows the function of each port. Ports 0 through 6 can be connected to internal pull-up resistors by software when inputting. Figure 7-1. Port Configuration P00 Port 0 P07 P10 Port 1 P17 P20-P27 8 Port 2 P30 Port 3 P37 P40 Port 4 P47 P50 Port 5 P57 P60 Port 6 P67 P70 Port 7 P77 31 µPD784035Y, 784036Y, 784037Y, 784038Y Table 7-1. Port Functions Port Name Pin Name Function Specification of Pull-up Resistor Connection by Software Port 0 P00 to P07 • Can be set in input or output mode in All port pins in input mode 1-bit units. • Can operate as 4-bit real-time output port (P00 through P03 and P04 through P07) • Can drive transistor. Port 1 P10 to P17 • Can be set in input or output mode in All port pins in input mode 1-bit units. • Can drive LEDs. Port 2 P20 to P27 • Input port In 6-bit units (P22 through P27) Port 3 P30 to P37 • Can be set in input or output mode in All port pins in input mode 1-bit units. Port 4 P40 to P47 • Can be set in input or output mode in All port pins in input mode 1-bit units. • Can drive LEDs. Port 5 P50 to P57 • Can be set in input or output mode in All port pins in input mode 1-bit units. • Can drive LEDs. Port 6 P60 to P67 • Can be set in input or output mode in All port pins in input mode 1-bit units. Port 7 P70 to P77 • Can be set in input or output mode in – 1-bit units. 7.2 Clock Generation Circuit An on-chip clock generation circuit necessary for operation is provided. This clock generation circuit has a divider circuit. If high-speed operation is not necessary, the internal operating frequency can be lowered by the divider circuit to reduce the current consumption. Figure 7-2. Block Diagram of Clock Generation Circuit X1 fXX 1/2 1/2 X2 fXX/2 UART/IOE INTP0 noise reduction circuit Oscillation stabilization timer Remark fXX : oscillation frequency or external clock input fCLK: internal operating frequency 32 1/2 1/2 Selector Oscillation circuit fCLK CPU Peripheral circuit µPD784035Y, 784036Y, 784037Y, 784038Y Figure 7-3. Example of Using Oscillation Circuit (1) Crystal/ceramic oscillation µ PD784038Y VSS1 X1 X2 (2) External clock • EXTC bit of OSTS = 1 µ PD74HC04, etc. • EXTC bit of OSTS = 0 µ PD784038Y µ PD784038Y X1 X1 X2 Open X2 Caution When using the clock oscillation circuit, wire the dotted portion in the above figure as follows to avoid adverse influences of wiring capacitance. • Keep the wiring length as short as possible. • Do not cross the wiring with other signal lines. • Do not route the wiring in the vicinity of lines through which a high alternating current flows. • Always keep the potential at the ground point of the capacitor in the oscillation circuit the same as VSS1. Do not ground to a ground pattern through which a high current flows. • Do not extract signals from the oscillation circuit. 33 µPD784035Y, 784036Y, 784037Y, 784038Y 7.3 Real-Time Output Port The real-time output port outputs data stored in a buffer in synchronization with the coincidence interrupt generated by timer/counter 1 or with an external interrupt. As a result, pulses without jitter can be output. The real-time output port is therefore ideal for applications where arbitrary patterns must be output at specific intervals (such as open loop control of a stepping motor). The real-time output port mainly consists of port 0 and port 0 buffer registers (P0H and P0L) as shown in Figure 7-4. Figure 7-4. Block Diagram of Real-Time Output Port Internal bus 8 4 Buffer register Real-time output port control register (RTPC) 8 INTP0 (from external source) INTC10 (from timer/counter 1) INTC11 (from timer/counter 1) 4 Output trigger control circuit P0H P0L 4 4 Output latch (P0) P07 34 P00 µPD784035Y, 784036Y, 784037Y, 784038Y 7.4 Timer/Counter Three units of timers/counters and one unit of timer are provided. Because a total of seven interrupt requests are supported, these timers/counters and timer can be used as seven units of timers/counters. Table 7-2. Operations of Timers/Counters Name Timer/Counter 0 Timer/Counter 1 Timer/Counter 2 Timer 3 2ch 2ch 1ch Item Count width 8 bits – 16 bits Operation mode Interval timer External event counter One-shot timer Function Timer output – – – 2ch – – 2ch – Toggle output – – PWM/PPG output – – One-shot pulse outputNote – Real-time output Pulse width measurement Number of interrupt requests Note 2ch – – – – – 1 input 1 input 2 inputs – 2 2 2 1 The one-shot pulse output function makes a pulse output level active by software and inactive by hardware (interrupt request signal). This function is different in nature from the one-shot timer function of timer/counter 2. 35 µPD784035Y, 784036Y, 784037Y, 784038Y Figure 7-5. Block Diagram of Timers/Counters Timer/counter 0 Timer register 0 (TM0) OVF Compare register (CR00) Match Compare register (CR01) Match Capture register (CR02) Edge detection INTP3 Software trigger TO0 Pulse output control Prescaler fXX/8 Selector Clear control TO1 INTC00 INTP3 INTC01 Timer/counter 1 Prescaler fXX/8 Selector Clear control Event input Timer register 1 (TM1/TM1W) OVF Compare register (CR10/CR10W) Match Capture/Compare register (CR11/CR11W) Match INTC10 To real-time output port Edge detection INTP0 INTC11 INTP0 Capture register (CR12/CR12W) Timer/counter 2 Edge detection INTP2/CI INTP2 INTP1 Timer register 2 (TM2/TM2W) OVF Compare register (CR20/CR20W) Match Capture/Compare register (CR21/CR21W) Match Pulse output control Prescaler fXX/8 Selector Clear control Capture register (CR22/CR22W) Edge detection INTC20 INTP1 INTC21 Timer 3 fXX/8 Prescaler Timer register 3 (TM3/TM3W) Clear Capture register (CR30/CR30W) match CSI INTC30 Remark OVF: overflow flag 36 TO2 TO3 µPD784035Y, 784036Y, 784037Y, 784038Y 7.5 PWM Output (PWM0, PWM1) Two channels of PWM (pulse width modulation) output circuits with a resolution of 12 bits and a repeat frequency of 62.5 kHz (fCLK = 16 MHz) are provided. Both these PWM output channels can select a high or low level as the active level. These outputs are ideal for controlling the speed of a DC motor. Figure 7-6. Block Diagram of PWM Output Unit Internal bus 16 8 PWM modulo register PWMn 15 8 7 8 4 3 0 PWM control register (PWMC) 4 Reload control fCLK Prescaler 8-bit down counter Pulse control circuit Output control PWMn (output pin) 4-bit counter 1/256 Remark n = 0 or 1 37 µPD784035Y, 784036Y, 784037Y, 784038Y 7.6 A/D Converter An analog-to-digital (A/D) converter with eight multiplexed inputs (ANI0 through ANI7) is provided. This A/D converter is of successive approximation type. The result of conversion is retained by an 8-bit A/D conversion result register (ADCR). Therefore, high-speed, high-accuracy conversion can be performed (conversion time: approx. 7.5 µs at fCLK = 16 MHz). A/D conversion can be started in either of the following two modes: • Hardware start: Conversion is started by trigger input (INTP5). • Software start: Conversion is started by setting a bit of the A/D converter mode register (ADM). After started, the A/D converter operates in the following modes: • Scan mode: Two or more analog inputs are sequentially selected, and data to be converted are obtained from all the input pins. • Select mode: Only one analog input pin is used to continuously obtain converted values. These operation modes and whether starting or stopping the A/D converter are specified by the ADM. When the result of conversion is transferred to the ADCR, interrupt request INTAD is generated. By using this request and macro service, the converted values can be successively transferred to the memory. Figure 7-7. Block Diagram of A/D Converter Series resistor string Sample & hold circuit Input selector AVREF1 R/2 Voltage comparator R Successive approximation register (SAR) INTP5 Edge detection circuit Conversion trigger INTAD Control Circuit Tap selector ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 R/2 AVSS Trigger enable 8 A/D converter mode register (ADM) A/D conversion result register (ADCR) 8 8 Internal bus 38 µPD784035Y, 784036Y, 784037Y, 784038Y 7.7 D/A Converter Two circuits of digital-to-analog (D/A) converters are provided. These D/A converters are of voltage output type and have a resolution of 8 bits. The conversion method is of R-2R resistor ladder type. By writing a value to be output to an 8-bit D/A conversion value setting register (DACSn: n = 0 or 1), an analog value is output to the ANOn (n = 0 or 1) pin. The output voltage range is determined by the voltage applied across the AVREF2 and AVREF3 pins. Because the output impedance is high, no current can be extracted from the output. If the impedance of the load is low, insert a buffer amplifier between the load and output pin. The ANOn pin goes into a high-impedance state while the RESET signal is low. When the RESET signal is deasserted, DACSn is cleared to 0. Figure 7-8. Block Diagram of D/A Converter ANOn 2R AVREF2 R 2R Selector R 2R AVREF3 R 2R DACSn DACEn Internal bus Remark n = 0 or 1 39 µPD784035Y, 784036Y, 784037Y, 784038Y 7.8 Serial Interface Three independent serial interface channels are provided. • Asynchronous serial interface (UART)/3-wire serial I/O (IOE) × 2 • Clocked serial interface (CSI) × 1 • 3-wire serial I/O (IOE) • 2-wire serial I/O (IOE) • I2C bus interface (I2C) Therefore, communication with an external system and local communication within the system can be simultaneously executed (refer to Figure 7-9). Figure 7-9. Example of Serial Interface (a) UART + I2C µ PD784038Y (master) VDD VDD µ PD4711A [I C] [UART] RS-232-C driver/receiver µ PD6272 (EEPROMTM) 2 RxD SDA SDA TxD SCL SCL Port µ PD78062Y (slave) µ PD4711A SDA [UART] SCL RxD2 RS-232-C driver/receiver TxD2 Port (b) UART + 3-wire serial I/O + 2-wire serial I/O µ PD784038Y (master) µ PD4711A SO1 [UART] RxD RS-232-C driver/receiver TxD Port µ PD75108 (slave) [3-wire serial I/O] SO SI1 SCK SCK1 INTPm SI Note Port INT Port VDD VDD µ PD78014 (slave) SDA SB0 SCL INTPn SCK0 Note Port INT [2-wire serial I/O] Note 40 Handshake line Port LCD µPD784035Y, 784036Y, 784037Y, 784038Y 7.8.1 Asynchronous serial interface/3-wire serial I/O (UART/IOE) Two channels of serial interfaces that can select an asynchronous serial interface mode and 3-wire serial I/O mode are provided. (1) Asynchronous serial interface mode In this mode, data of 1 byte following the start bit is transferred or received. Because an on-chip baud rate generator is provided, a wide range of baud rates can be set. Moreover, the clock input to the ASCK pin can be divided to define a baud rate. When the baud rate generator is used, a baud rate conforming to the MIDI standard (31.25 kbps) can be also obtained. Figure 7-10. Block Diagram in Asynchronous Serial Interface Mode Internal bus Receive buffer RXB, RXB2 Receive shift register RXD, RXD2 Transmit shift register TXS, TXS2 TXD, TXD2 Receive control parity check INTSR, INTSR2 INTSER, INTSER2 Trnsmit control Parity append INTST, INTST2 Baud rate generator ASCK, ASCK2 Selector 1/2m fXX/2 1/2n+1 1/2m Remark fXX: oscillation frequency or external clock input n = 0 through 11 m = 16 through 30 41 µPD784035Y, 784036Y, 784037Y, 784038Y (2) 3-wire serial I/O mode In this mode, the master device starts transfer by making the serial clock active and transfers 1-byte data in synchronization with this clock. This mode is used to communicate with a device having the conventional clocked serial interface. Basically, communication is established by using three lines: one serial clock (SCK) and two serial data (SI and SO) lines. Generally, a handshake line is necessary to check the communication state. Figure 7-11. Block Diagram in 3-wire Serial I/O Mode Internal bus Direction control circuit SIO1, SIO2 SI1, SI2 Shift register Output latch SO1, SO2 Serial clock counter Serial clock control circuit Remark fXX: oscillation frequency or external clock input n = 0 through 11 m = 1 or 16 through 30 42 Interrupt signal generation circuit Selector SCK1, SCK2 1/m INTCSI1, INTCSI2 1/2n+1 fXX/2 µPD784035Y, 784036Y, 784037Y, 784038Y 7.8.2 Clocked serial interface (CSI) In this mode, the master device starts transfer by making the serial clock active and communicates 1-byte data in synchronization with this clock. Figure 7-12. Block Diagram of Clocked Serial Interface Internal bus Direction control register Slave address register Match signal Set SI0 Selector Shift register Reset Output latch SO0/SDA N-ch open drain output (in 2-wire or I2C bus mode) Acknowledge detection control Start condition detection circuit Acknowledge detection circuit Wake-up control circuit Stop condition detection circuit Serial clock counter SCK0/SCL INTSPC Interrupt signal generation circuit Timer 3 output Serial clock control circuit Selector N-ch open drain output (in 2-wire or I2C bus mode) CLS0 CLS1 INTCSI fXX/16 Selector Prescaler fXX/2 Remark fXX: oscillation frequency or external clock input 43 µPD784035Y, 784036Y, 784037Y, 784038Y (1) 3-wire serial I/O mode This mode is to communicate with devices having the conventional clocked serial interface. Basically, communication is established in this mode with three lines: one serial clock (SCK0) and two serial data (SI0 and SO0) lines. Generally, a handshake line is necessary to check the communication status. (2) 2-wire serial I/O mode This mode is to transfer 8-bit data by using two lines: serial clock (SCL) and serial data bus (SDA). Generally, a handshake line is necessary to check the communication status. (3) I2C (Inter IC) bus mode This mode is to communicate with devices conforming to the I2C bus format. This mode is to transfer 8-bit data with two or more devices by using two lines: serial clock (SCL) and serial data bus (SDA). During transfer, a “start condition”, “data”, and “stop condition” can be output onto the serial data bus. During reception, these data can be automatically detected by hardware. 7.9 Clock Output Function The operating clock of the CPU can be divided and output to an external device. The pin that outputs the clock can also be used as a 1-bit port. When this function is used, the local bus interface cannot be used because the ASTB and CLKOUT pins are multiplexed. Figure 7-13. Block Diagram of Clock Output Function fCLK fCLK/4 Selector fCLK/2 Output control fCLK/8 fCLK/16 Output enable Output level 44 CLKOUT µPD784035Y, 784036Y, 784037Y, 784038Y 7.10 Edge Detection Function The interrupt input pins (NMI and INTP0 through INTP5) are used not only to input interrupt requests but also to input trigger signals to the internal hardware units. Because these pins operate at an edge of the input signal, they have a function to detect an edge. Moreover, a noise reduction circuit is also provided to prevent erroneous detection due to noise. Pin Name Detectable Edge Noise Reduction NMI Either of rising or falling edge By analog delay INTP0-INTP3 Either or both of rising and falling edges By clock samplingNote INTP4, INTP5 Note By analog delay INTP0 can select a sampling clock. 7.11 Watchdog Timer A watchdog timer is provided to detect a hang up of the CPU. This watchdog timer generates a non-maskable interrupt unless it is cleared by software within a specified interval time. Once enabled to operate, the watchdog timer cannot be stopped by software. Whether the interrupt by the watchdog timer or the interrupt input from the NMI pin takes precedence can be specified. Figure 7-14. Block Diagram of Watchdog Timer Timer fCLK fCLK/220 fCLK/219 Selector fCLK/221 INTWDT fCLK/217 Clear signal 45 µPD784035Y, 784036Y, 784037Y, 784038Y 8. INTERRUPT FUNCTION As the servicing in response to an interrupt request, the three types shown in Table 8-1 can be selected by program. Table 8-1. Servicing of Interrupt Request Servicing Mode Vectored interrupt Entity of Servicing Software Context switching Servicing Contents of PC and PSW Branches and executes servicing routine Saves to and restores (servicing is arbitrary). from stack. Automatically switches register bank, Saves to or restores from branches and executes servicing routine fixed area in register bank (servicing is arbitrary). Macro service Firmware Executes data transfer between memory Retained and I/O (servicing is fixed) 8.1 Interrupt Sources Table 8-2 shows the interrupt sources available. As shown, interrupts are generated by 24 types of sources, execution of the BRK instruction or BRKCS instruction, or an operand error. The priority of interrupt servicing can be set to four levels, so that nesting can be controlled during interrupt servicing and that which of the two or more interrupts that simultaneously occur should be serviced first. When the macro service function is used, however, nesting always proceeds. The default priority is the priority (fixed) of the service that is performed if two or more interrupt requests, having the same request, simultaneously generate (refer to Table 8-2). 46 µPD784035Y, 784036Y, 784037Y, 784038Y Table 8-2. Interrupt Sources Type Default Software Non-maskable Maskable Source Priority Name – BRK instruction BRKCS instruction Operand error – 0 (highest) NMI WDT INTP0 1 INTP1 2 INTP2 3 INTP3 4 5 6 INTC00 INTC01 INTC10 7 INTC11 8 INTC20 9 INTC21 10 INTC30 11 12 13 14 15 INTP4 INTP5 INTAD INTSER INTSR INTCSI1 INTST INTCSI INTSER2 INTSR2 INTCSI2 INTST2 INTSPC 16 17 18 19 20 21 (lowest) Internal/ Trigger Instruction execution If result of exclusive OR between byte of operand and byte is not FFH when “MOV STBC, #byte”, “MOV WDM, #byte”, or “LOCATION” instruction is executed Detection of pin input edge Overflow of watchdog timer Detection of pin input edge (TM1/TM1W capture trigger, TM1/TM1W event counter input) Detection of pin input edge (TM2/TM2W capture trigger, TM2/TM2W event counter input) Detection of pin input edge (TM2/TM2W capture trigger , TM2/TM2W event counter input) Detection of pin input edge (TM0 capture trigger, TM0 event counter input) Generation of TM0-CR00 match signal Generation of TM0-CR01 match signal Generation of TM1-CR10 match signal (in 8-bit operation mode) Generation of TM1W-CR10W match signal (in 16-bit operation mode) Generation of TM1-CR11 match signal (in 8-bit operation mode) Generation of TM1W-CR11W match signal (in 16-bit operation mode) Generation of TM2-CR20 match signal (in 8-bit operation mode) Generation of TM2W-CR20W match signal (in 16-bit operation mode) Generation of TM2-CR21 match signal (in 8-bit operation mode) Generation of TM2W-CR21W match signal (in 16-bit operation mode) Generation of TM3-CR30 match signal (in 8-bit operation mode) Generation of TM3W-CR30W match signal (in 16-bit operation mode) Detection of pin input edge Detection of pin input edge End of A/D conversion (transfer of ADCR) Occurrence of ASI0 reception error End of ASI0 reception or CSI1 transfer End of ASI0 transfer End of CSI1 transfer Occurrence of ASI2 reception error End of ASI2 reception or CSI2 transfer Macro service External – – External Internal External – Internal External Internal – – End of ASI2 transfer I2C bus stop condition interrupt Remark ASI: asynchronous serial interface CSI: clocked serial interface 47 µPD784035Y, 784036Y, 784037Y, 784038Y 8.2 Vectored Interrupt Execution branches to a servicing routing by using the memory contents of a vector table address corresponding to the interrupt source as the address of the branch destination. So that the CPU performs interrupt servicing, the following operations are performed: • On branching: Saves the status of the CPU (contents of PC and PSW) to stack • On returning: Restores the status of the CPU (contents of PC and PSW) from stack To return to the main routine from an interrupt service routine, the RETI instruction is used. The branch destination address is in a range of 0 to FFFFH. Table 8-3. Vector Table Address Interrupt Source Vector Table Address BRK instruction 003EH Operand error 003CH NMI 0002H WDT 0004H INTP0 0006H INTP1 0008H INTP2 000AH INTP3 000CH INTC00 000EH INTC01 0010H INTC10 0012H INTC11 0014H INTC20 0016H INTC21 0018H INTC30 001AH INTP4 001CH INTP5 001EH INTAD 0020H INTSER 0022H INTSR 0024H INTCSI1 INTST 0026H INTCSI 0028H INTSER2 002AH INTSR2 002CH INTCSI2 48 INTST2 002EH INTSPC 0030H µPD784035Y, 784036Y, 784037Y, 784038Y 8.3 Context Switching When an interrupt request is generated or when the BRKCS instruction is executed, a predetermined register bank is selected by hardware. Context switching is a function that branches execution to a vector address stored in advance in the register bank, and to stack the current contents of the program counter (PC) and program status word (PSW) to the register bank. The branch address is in a range of 0 to FFFFH. Figure 8-1. Context Switching Operation When Interrupt Request Is Generated Register bank n (0 to 7) 0000B <7> Transfer Register bank n (n = 0 to 7) PC19-16 PC15-0 <2> Save (bits 8 through 11 of temporary register) <6> Exchange A X B C R5 R4 R6 R7 <5> Save Temporary register <1> Save V VP U UP T D E W H L <3> Switching of register bank (RBS0 to RBS2 ← n) <4> RSS ← n IE ← n PSW 8.4 Macro Service This function is to transfer data between memory and a special function register (SFR) without intervention by the CPU. A macro service controller accesses the memory and SFR in the same transfer cycle and directly transfers data without loading it. Because this function does not save or restore the status of the CPU, or load data, data can be transferred at high speeds. Figure 8-2. Macro Service Read CPU Memory Write Write Macro service controller SFR Read Internal bus 49 µPD784035Y, 784036Y, 784037Y, 784038Y 8.5 Application Example of Macro Service (1) Transfer of serial interface Transfer data storage buffer (memory) Data n Data n–1 Data 2 Data 1 Internal bus TxD Transfer shift register TXS(SFR) Transfer control INTST Each time macro service request (INTST) is generated, the next transfer data is transferred from memory to TXS. When data n (last byte) has been transferred to TXS (when the transfer data storage buffer has become empty), vectored interrupt request (INTST) is generated. (2) Reception of serial interface Receive data storage buffer (memory) Data n Data n–1 Data 2 Data 1 Internal bus Receive buffer RxD RXB(SFR) Receive shift register Reception control INTSR Each time macro service request (INTSR) is generated, the receive data is transferred from RXB to memory. When data n (last byte) has been transferred to memory (when the receive data storage buffer has become full), vectored interrupt request (INTSR) is generated. 50 µPD784035Y, 784036Y, 784037Y, 784038Y (3) Real-time output port INTC10 and INTC11 serve as the output triggers of the real-time output port. The macro services for these can set the following output pattern and intervals simultaneously. Therefore, INTC10 and INTC11 can control two stepping motors independently of each other. They can also be used for PWM output or to control DC motors. Output pattern profile (memory) Output timing profile (memory) Pn Tn Pn–1 Tn–1 P2 T2 P1 T1 Internal bus Internal bus Match (SFR) P0L CR10 (SFR) INTC10 Output latch TM1 P00-P03 Each time macro service request (INTC10) is generated, the pattern and timing are transferred to the buffer register (P0L) and compare register (CR10), respectively. When the contents of the timer register 1 (TM1) coincide with those of CR10, INTC10 is generated again, and the contents of P0L are transferred to the output latch. When Tn (last byte) has transferred to CR10, vectored interrupt request (INTC10) is generated. The same applies to INTC11. 51 µPD784035Y, 784036Y, 784037Y, 784038Y 9. LOCAL BUS INTERFACE The local bus interface can connect an external memory or I/O (memory mapped I/O) and support a memory space of 1 MByte (refer to Figure 9-1). Figure 9-1. Example of Local Bus Interface Decoder µ PD784038Y A16-A19 RD Pseudo SRAM WR PROM µ PD27C1001A REFRQ Data bus AD0-AD7 ASTB Character generator µ PD24C1000 Latch A8-A15 Address bus Gate array I/O expansion Centronics I/F, etc. 9.1 Memory Expansion The memory capacity can be expanded in seven steps, from 256 Bytes to 1 MByte, by connecting an external program memory and data memory. 52 µPD784035Y, 784036Y, 784037Y, 784038Y 9.2 Memory Space The 1-MByte memory space is divided into eight spaces of logical addresses. Each space can be controlled by using the programmable wait function and pseudo static RAM refresh function. Figure 9-2. Memory Space F F F F FH 512 KBytes 8 0 0 0 0H 7 F F F FH 256 KBytes 4 0 0 0 0H 3 F F F FH 128 KBytes 2 0 0 0 0H 1 F F F FH 64 KBytes 1 0 0 0 0H 0 F F F FH 16 KBytes 0C0 0 0H 0 BF F FH 16 KBytes 0 8 0 0 0H 0 7 F F FH 16 KBytes 0 4 0 0 0H 0 3 F F FH 16 KBytes 0 0 0 0 0H 53 µPD784035Y, 784036Y, 784037Y, 784038Y 9.3 Programmable Wait The memory space can be divided into eight spaces and wait states can be independently inserted in each of these spaces while the RD and WR signals are active. Even when a memory with a different access time is connected, therefore, the efficiency of the entire system does not drop. In addition, an address wait function that extends the active period of the ASTB signal is also provided so as to have a sufficient address decode time (this function can be set to the entire space). 9.4 Pseudo Static RAM Refresh Function The following refresh operations can be performed: • Pulse refresh: A bus cycle that outputs a refresh pulse to the REFRQ pin at a fixed cycle is inserted. The memory spaces is divided into eight spaces, and a refresh pulse can be output from the REFRQ pin while a specified memory space is accessed. Therefore, the normal memory access is not kept to wait by the refresh cycle. • Power-down self-refresh: The low level is output to the REFRQ pin in the standby mode to retain the contents of the pseudo static RAM. 9.5 Bus Hold Function A bus hold function is provided to facilitate connection of a DMA controller. When a bus hold request signal (HLDRQ) is received from an external bus master, the address bus, address/data bus, and ASTB, RD, and WR pins go into a high-impedance state when the current bus cycle has been completed. This makes the bus hold acknowledge (HLDAK) signal active, and releases the bus to the external bus master. Note that, while the bus hold function is used, the external wait function and pseudo static RAM refresh function cannot be used. 54 µPD784035Y, 784036Y, 784037Y, 784038Y 10. STANDBY FUNCTION This function is to reduce the power dissipation of the chip, and can be used in the following modes: • HALT mode: Stops supply of the operating clock to the CPU. This mode is used in combination with the normal operation mode for intermittent operation to reduce the average power dissipation. • IDLE mode: Stops the entire system with the oscillation circuit continuing operation. The power dissipation in this mode is close to that in the STOP mode. However, the time required to restore the normal program operation from this mode is almost the same as that from the HALT mode. • STOP mode: Stops the oscillator and thereby to stop all the internal operations of the chip. Consequently, the power dissipation is minimized with only leakage current flowing. These modes are programmable. The macro service can be started from the HALT mode. Figure 10-1. Transition of Standby Status NM IDLE (standby) Interrupt request of masked interrupt Macro service M a En cro s d of erv on ice e pr req oc u es est sin g 1 I, Se ts ID R L IN E TP SE E m o 4, T IN inp de TP u t 5 inp ut N ot e te No ut inp 5 TP IN 4, TP IN I, NM STOP (standby) e2 ot de mo ut ST T inp s t Se ESE R OP Macro service request End of one processing End of macro service tN es qu re put e pt in od ru er SET T m Int RE HAL ts Se 1 on bilizati Program tion sta Oscilla e expires operation Waits for tim oscillation stabilization HALT (standby) Notes 1. When INTP4 and INTP5 are not masked 2. Only interrupt requests that are not masked Remark Only the externally input NMI is valid. The watchdog timer cannot be used to release the standby mode (STOP/IDLE mode). 55 µPD784035Y, 784036Y, 784037Y, 784038Y 11. RESET FUNCTION When the low level is input to the RESET pin, the internal hardware is initialized (reset status). When the RESET pin goes high, the following data are set to the program counter (PC). • Lower 8 bits of PC: contents of address 0000H • Middle 8 bits of PC: contents of address 0001H • Higher 4 bits of PC: 0 Program execution is started from a branch destination address which is the contents of the PC. Therefore, the system can be reset and started from any address. Set the contents of each register by program as necessary. The RESET input circuit has a noise reduction circuit to prevent malfunctioning due to noise. This noise reduction circuit is a sampling circuit by analog delay. Figure 11-1. Accepting RESET Signal Delay Delay Delay Initialize PC Executes instruction at reset start address RESET (input) Internal reset signal Reset starts Reset ends Assert the RESET signal active until the oscillation stabilization time (approx. 40 ms) elapses to execute a powerON reset operation. Figure 11-2. Power-ON Reset Operation Oscillation stabilization time Delay Initialize PC VDD RESET (input) Internal reset signal Reset ends 56 Executes instruction at reset start address µPD784035Y, 784036Y, 784037Y, 784038Y 12. INSTRUCTION SET (1) 8-bit instructions (The instructions in parentheses are combinations realized by describing A as r) MOV, XCH, ADD, ADDC, SU B, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, SHR, SHL, ROR4, DBNZ, PUSH, POP, MOVM, XCHM, CMPME, CMPMNE, CMPMNC, CMPMC, MOVBK, XCHBK, CMPBKE, CMPBKNE, CMPBKNC, CMPBKC, CHIKL, CHKLA Table 12-1. Instruction List by 8-Bit Addressing Second Operand #byte A r saddr r' saddr' sfr !addr16 !!addr24 First Operand A (MOV) ADD Note 1 mem MOV ADD Note 1 PSWL PSWH MOV MOV (MOV)Note 6 MOV (MOV) MOV (XCH) XCH (XCH)Note 6 (XCH) (XCH) XCH MOV MOV MOV MOV (XCH) XCH XCH XCH XCH [WHL–] [saddrp] (MOV) (MOV) [WHL+] [%saddrg] (ADD)Note 1 (ADD)Note 1 (ADD)Note 1,6 (ADD)Note 1 ADDNote 1 ADDNote 1 r r3 n None Note 2 (MOV) (XCH) (ADD)Note 1 RORNote 3 MULU DIVUW (ADD)Note 1 ADDNote 1 ADDNote 1 ADDNote 1 INC DEC saddr MOV ADDNote 1 sfr MOV (MOV)Note 6 MOV (ADD)Note 1 ADDNote 1 MOV MOV INC XCH DEC ADDNote 1 DBNZ MOV PUSH ADDNote 1 (ADD)Note 1 ADDNote 1 POP CHKL CHKLA !addr16 MOV (MOV) MOV ADDNote 1 !!addr24 mem MOV ADDNote 1 [saddrp] [%saddrg] mem3 ROR4 ROL4 r3 MOV MOV PSWL PSWH B, C DBNZ STBC, WDM [TDE+] [TDE–] MOV (MOV) (ADD) MOVBKNote 5 Note 1 MOVMNote 4 Notes 1. The operands of ADDC, SUB, SUBC, AND, OR, XOR, and CMP are the same as that of ADD. 2. Either the second operand is not used, or the second operand is not an operand address. 3. The operands of ROL, RORC, ROLC, SHR, and SHL are the same as that of ROR. 4. The operands of XCHM, CMPME, CMPMNE, CMPMNC, and CMPMC are the same as that of MOVM. 5. The operands of XCHBK, CMPBKE, CMPBKNE, CMPBKNC, and CMPBKC are the same as that of MOVBK. 6. The code length of some instructions having saddr2 as saddr in this combination is short. 57 µPD784035Y, 784036Y, 784037Y, 784038Y (2) 16-bit instructions (The instructions in parentheses are combinations realized by describing AX as rp) MOVW, XCHW, ADDW, SUBW, CMPW, MULUW, MULW, DIVUX, INCW, DECW, SHRW, SHLW, PUSH, POP, ADDWG, SUBWG, PUSHU, POPU, MOVTBLW, MACW, MACSW, SACW Table 12-2. Instruction List by 16-Bit Addressing Second Operand #word AX rp saddrp rp' saddrp' sfrp !addr16 mem !!addr24 [saddrp] First Operand AX [WHL+] byte n NoneNote 2 SHRW MULWNote 4 SHLW INCW [%saddrg] (MOVW) ADDW Note 1 (MOVW) (XCHW) Note 3 MOVW (MOVW) MOVW (MOVW) Note 3 (XCHW) XCHW XCHW (XCHW) (MOVW) (MOVW) (XCHW) (XCHW) (ADD)Note 1 (ADDW)Note 1 (ADDW)Note 1,3 (ADDW)Note 1 rp MOVW ADDW Note 1 (MOVW) MOVW MOVW MOVW (XCHW) XCHW XCHW XCHW (ADDW) saddrp Note 1 ADDW Note 1 MOVW (MOVW)Note 3 MOVW ADDWNote 1 (ADDW)Note 1 ADDWNote 1 ADDW Note 1 ADDW MOVW Note 1 DECW MOVW INCW XCHW DECW ADDWNote 1 sfrp MOVW MOVW MOVW PUSH ADDWNote 1 (ADDW)Note 1 ADDWNote 1 !addr16 MOVW (MOVW) POP MOVW MOVTBLW !!addr24 mem MOVW [saddrp] [%saddrg] PSW PUSH POP SP ADDWG SUBWG post PUSH POP PUSHU POPU [TDE+] (MOVW) SACW byte MACW MACSW Notes 1. The operands of SUBW and CMPW are the same as that of ADDW. 2. Either the second operand is not used, or the second operand is not an operand address. 3. The code length of some instructions having saddrp2 as saddrp in this combination is short. 4. The operands of MULUW and DIVUX are the same as that of MULW. 58 µPD784035Y, 784036Y, 784037Y, 784038Y (3) 24-bit instructions (The instructions in parentheses are combinations realized by describing WHL as rg) MOVG, ADDG, SUBG, INCG, DECG, PUSH, POP Table 12-3. Instruction List by 24-Bit Addressing Second Operand #imm24 WHL rg saddrg !!addr24 mem1 [%saddrg] SP (MOVG) MOVG MOVG MOVG NoneNote rg' First Operand WHL rg (MOVG) (MOVG) (MOVG) (MOVG) (ADDG) (ADDG) (ADDG) ADDG (SUBG) (SUBG) (SUBG) SUBG MOVG (MOVG) MOVG MOVG ADDG (ADDG) ADDG DECG SUBG (SUBG) SUBG PUSH MOVG INCG POP saddrg (MOVG) MOVG !!addr24 (MOVG) MOVG mem1 MOVG [%saddrg] MOVG SP MOVG MOVG INCG DECG Note Either the second operand is not used, or the second operand is not an operand address. 59 µPD784035Y, 784036Y, 784037Y, 784038Y (4) Bit manipulation instructions MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR, BFSET Table 12-4. Bit Manipulation Instructions Second Operand CY saddr.bit sfr.bit /saddr.bit /sfr. bit A.bit X.bit /A.bit /X.bit PSWL.bit PSWH.bit /PSWL.bit /PSWH.bit mem2.bit /mem2.bit First Operand !addr16.bit !!addr24.bit /!addr16.bit /!!addr24.bit CY MOV1 AND1 AND1 OR1 OR1 NoneNote NOT1 SET1 CLR1 XOR1 saddr.bit MOV1 NOT1 sfr.bit SET1 A.bit CLR1 X.bit BF PSWL.bit BT PSWH.bit BTCLR mem2.bit BFSET !addr16.bit !!addr24.bit Note 60 Either the second operand is not used, or the second operand is not an operand address. µPD784035Y, 784036Y, 784037Y, 784038Y (5) Call and return/branch instructions CALL, CALLF, CALLT, BRK, RET, RETI, RETB, RETCS, RETCSB, BRKCS, BR, BNZ, BNE, BZ, BE, BNC, BNL, BC, BL, BNV, BPO, BV, BPE, BP, BN, BLT, BGE, BLE, BGT, BNH, BH, BF, BT, BTCLR, BFSET, DBNZ Table 12-5. Call and Return/Branch Instructions Operand of Instruction $addr20 $!addr20 !addr16 !!addr20 rp rg [rp] [rg] !addr11 [addr5] RBn None Address Basic instruction Compound instruction BCNote CALL BR BR CALL CALL CALL CALL CALL CALL BR BR BR BR BR BR CALLF CALLF BRKCS BRK RET RETCS RETI RETCSB RETB BF BT BTCLR BFSET DBNZ Note The operands of BNZ, BNE, BZ, BE, BNC, BNL, BL, BNV, BPO, BV, BPE, BP, BN, BLT, BGE, BLE, BGT, BNH, and BH are the same as BC. (6) Other instructions ADJBA, ADJBS, CVTBW, LOCATION, SEL, NOT, EI, DI, SWRS 61 µPD784035Y, 784036Y, 784037Y, 784038Y 13. ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS (T A = 25 °C) Parameter Supply voltage Symbol Conditions Ratings Unit –0.5 to +7.0 V AVDD AVSS to VDD+0.5 V AVSS –0.5 to +0.5 V VDD Input voltage VI –0.5 to VDD+0.5 V Output voltage VO –0.5 to VDD+0.5 V Low-level output current IOL Per pin 15 mA Total of all output pins 100 mA High-level output current IOH Per pin –10 mA Total of all output pins –100 mA A/D converter reference input voltage AVREF1 –0.5 to VDD+0.3 V D/A converter reference input voltage AVREF2 –0.5 to VDD+0.3 V AVREF3 –0.5 to VDD+0.3 V Operating ambient temperature TA –40 to +85 °C Storage temperature Tstg –65 to +150 °C Caution Absolute maximum ratings are rated values beyond which physical damage will be caused to the product; if the rated value of any of the parameters in the above table is exceeded, even momentarily, the quality of the product may deteriorate. Always use the product within its rated values. 62 µPD784035Y, 784036Y, 784037Y, 784038Y OPERATING CONDITIONS • Operating ambient temperature (TA) : –40 to +85°C • Rising time and falling time (tr, tf) (at pins which are not specified) : 0 to 200 µs • Power supply voltage and clock cycle time : See Figure 13-1 Figure 13-1. Power Supply Voltage and Clock Cycle Time 10000 Clock Cycle Time tCYK [ns] 4000 1000 Guaranteed Operating Range 125 100 62.5 10 0 1 2 3 4 5 Power Supply Voltage [V] 6 7 CAPACITANCE (T A = 25 °C, V DD = V SS = 0 V) Parameter Input capacitance Symbol Conditions CI f = 1 MHz Output capacitance CO Unmeasured pins returned to 0 V. I/O capacitance CIO MIN. TYP. MAX. 10 pF Unit 10 pF 10 pF 63 µPD784035Y, 784036Y, 784037Y, 784038Y OSCILLATOR CHARACTERISTICS (T A = –40 to +85 °C, V DD = +4.5 to 5.5 V, VSS = 0 V) Resonator Recommended Circuit Ceramic resonator or crystal resonator VSS1 X1 C1 MIN. MAX. Unit Oscillator frequency (fXX) 4 32 MHz X1 input frequency (fX) 4 32 MHz X1 input rising/falling time (tXR, tXF) 0 10 ns X1 input high-/low-level width (tWXH, tWXL) 10 125 ns X2 C2 External clock X1 Parameter X2 HCMOS inverter Caution When using the system clock oscillator, wiring the area enclosed with the broken line should be carried out as follows to avoid an adverse effect from wiring capacitance. • Wiring should be as short as possible. • Wiring should not cross other signal lines. • Wiring should not be placed close to a varying high current. • The potential of the oscillator capacitor ground should be the same as VSS1. Do not ground wiring to a ground pattern in which a high current flows. • Do not fetch a signal from the oscillator. 64 µPD784035Y, 784036Y, 784037Y, 784038Y OSCILLATOR CHARACTERISTICS (T A = –40 to +85 °C, V DD = +2.7 to 5.5 V, VSS = 0 V) Resonator Recommended Circuit Ceramic resonator or crystal resonator VSS1 X1 C1 MIN. MAX. Unit Oscillator frequency (fXX) 4 16 MHz X1 input frequency (fX) 4 16 MHz X1 input rising/falling time (tXR, tXF) 0 10 ns X1 input high-/low-level width (tWXH, tWXL) 10 125 ns X2 C2 External clock X1 Parameter X2 HCMOS inverter Caution When using the system clock oscillator, wiring the area enclosed with the broken line should be carried out as follows to avoid an adverse effect from wiring capacitance. • Wiring should be as short as possible. • Wiring should not cross other signal lines. • Wiring should not be placed close to a varying high current. • The potential of the oscillator capacitor ground should be the same as VSS1. Do not ground wiring to a ground pattern in which a high current flows. • Do not fetch a signal from the oscillator. 65 µPD784035Y, 784036Y, 784037Y, 784038Y DC CHARACTERISTICS (T A = –40 to +85 °C, V DD = AV DD = +2.7 to 5.5 V, V SS = AV SS = 0 V) (1/2) Parameter Low-level input voltage High-level input voltage Symbol Conditions MIN. TYP. MAX. Unit V VIL1 For pins other than those described in Notes 1, 2, 3, 4, and 6 –0.3 0.3VDD VIL2 For pins described in Notes 1, 2, 3, 4, and 6 –0.3 0.2VDD V VIL3 VDD = +5.0 V±10% For pins described in Notes 2, 3, and 4 –0.3 +0.8 V VIH1 For pins other than those described in Notes 1 and 6 0.7VDD VDD+0.3 V VIH2 For pins described in Notes 1 and 6 0.8VDD VDD+0.3 V VIH3 VDD = +5.0 V±10% For pins described in Notes 2, 3, and 4 2.2 VDD+0.3 V VOL1 IOL = 2 mA For pins other than those described in Note 6 0.4 V VOL2 IOL = 3 mA For pins described in Note 6 0.4 V IOL = 6 mA For pins described in Note 6 0.6 V VOL3 VDD = +5.0 V±10% IOL = 8 mA For pins described in Notes 2 and 5 1.0 V VOH1 IOH = –2 mA VDD–1.0 V VOH2 VDD = +5.0 V±10% IOH = –5 mA For pins other than those described in Note 4 VDD–1.4 V X1 low-level input current IIL EXTC = 0 0 V ≤ VI ≤ VIL2 –30 µA X1 high-level input current IIH EXTC = 0 VIH2 ≤ VI ≤ VDD +30 µA Low-level output voltage High-level output voltage Notes 1. X1, X2, RESET, P12/ASCK2/SCK2, P20/NMI, P21/INTP0, P22/INTP1, P23/INTP2/CI, P24/INTP3, P25/INTP4/ASCK/SCK1, P26/INTP5, P27/SI0, and TEST 2. P40/AD0 to P47/AD7 and P50/A8 to P57/A15 3. P60/A16 to P63/A19, P64/RD, P65/WR, P66/WAIT/HLDRQ, and P67/REFRQ/HLDAK 4. P00 to P07 5. P10 to P17 6. P32/SCK0/SCL and P33/SO0/SDA 66 µPD784035Y, 784036Y, 784037Y, 784038Y DC CHARACTERISTICS (T A = –40 to +85 °C, V DD = AV DD = +2.7 to 5.5 V, V SS = AV SS = 0 V) (2/2) Parameter Symbol Conditions ILI 0 V ≤ VI ≤ VDD For pins other than pin X1 when EXTC = 0 Output leakage current ILO 0 V ≤ VO ≤ VDD VDD supply current IDD1 Operation mode Input leakage current IDD2 IDD3 Pull-up resistance RL HALT mode IDLE mode (EXTC = 0) VI = 0 V MIN. TYP. MAX. Unit ±10 µA ±10 µA fXX = 32 MHz VDD = +5.0 V±10% 25 45 mA fXX = 16 MHz VDD = +2.7 to 3.3 V 12 25 mA fXX = 32 MHz VDD = +5.0 V±10% 13 26 mA fXX = 16 MHz VDD = +2.7 to 3.3 V 8 12 mA fXX = 32 MHz VDD = +5.0 V±10% 12 mA fXX = 16 MHz VDD = +2.7 to 3.3 V 8 mA 80 kΩ 15 67 µPD784035Y, 784036Y, 784037Y, 784038Y AC CHARACTERISTICS (T A = –40 to +85 °C, V DD = AV DD = +2.7 to 5.5 V, V SS = AV SS = 0 V) (1) Read/write operation (1/2) Parameter Symbol Conditions MIN. MAX. Unit Address setup time tSAST VDD = +5.0 V±10% ASTB high-level width tWSTH VDD = +5.0 V±10% Address hold time (from ASTB↓) tHSTLA VDD = +5.0 V±10% Address hold time (from RD↑) tHRA RD↓ delay time from address tDAR Address float time (from RD↓) tFRA Data input time from address tDAID VDD = +5.0 V±10% (2.5+a+n)T–52 ns Data input time from ASTB↓ tDSTID VDD = +5.0 V±10% (2+n)T–40 ns (2+n)T–60 ns Data input time from RD↓ tDRID VDD = +5.0 V±10% (1.5+n)T–50 ns RD↓ delay time from tDSTR 0.5T–9 ns Data hold time (from RD↑) tHRID 0 ns Address active time from RD↑ tDRA 0.5T–8 ns 0.5T–12 ns 1.5T–8 ns 1.5T–12 ns 0.5T–17 ns (1.5+n)T–30 ns (1.5+n)T–40 ns 0.5T–14 ns (1+a)T–5 ns VDD = +5.0 V±10% (0.5+a)T–15 ns (0.5+a)T–31 ns (0.5+a)T–17 ns (0.5+a)T–40 ns 0.5T–24 ns 0.5T–34 ns 0.5T–14 ns (1+a)T–9 ns (1+a)T–15 ns 0 ns (2.5+a+n)T–37 ns (1.5+n)T–70 ns ASTB↓ ASTB↑ delay time from RD↑ tDRST RD low-level width tWRL After program is read VDD = +5.0 V±10% After data is read VDD = +5.0 V±10% VDD = +5.0 V±10% Address hold time (from WR↑) tHWA WR↓ delay time from address tDAW VDD = +5.0 V±10% Data output delay time from ASTB↓ tDSTOD VDD = +5.0 V±10% Data output delay time from WR↓ tDWOD WR↓ output delay time from ASTB↓ tDSTW (1+a)T–15 Remark T : TCYK (system clock cycle time) a : 1 (during address wait), otherwise, 0 n : Number of wait states (n ≥ 0) 68 ns 0.5T+19 0.5T–9 ns 0.5T+35 ns 0.5T–11 ns ns µPD784035Y, 784036Y, 784037Y, 784038Y (1) Read/write operation (2/2) Parameter Symbol Conditions Data setup time (to WR↑) tSODW VDD = +5.0 V±10% Data hold time VDD = +5.0 V±10% tHWOD (from WR↑) Note ASTB↑ delay time (from WR↑) tDWST WR low-level width tWWL Note VDD = +5.0 V±10% MIN. MAX. (1.5+n)T–30 Unit ns (1.5+n)T–40 ns 0.5T–5 ns 0.5T–25 ns 0.5T–12 ns (1.5+n)T–30 ns (1.5+n)T–40 ns The hold time includes the time during which VOH1 and VOL1 are held under the load conditions of CL = 50 pF and RL = 4.7 kΩ. Remark T: TCYK (system clock cycle time) n: Number of wait states (n ≥ 0) (2) Bus hold timing Parameter MAX. Unit tFHQC (6+a+n)T+50 ns HLDAK↑ delay time from HLDRQ↑ tDHQHHAH VDD = +5.0 V±10% (7+a+n)T+30 ns (7+a+n)T+40 ns HLDAK↑ delay time tDCFHA 1T+30 ns 2T+40 ns 2T+60 ns Float delay time from Symbol Conditions MIN. HLDRQ↑ from float HLDAK↓ delay time from HLDRQ↓ tDHQLHAL Active delay time from HLDAK↓ tDHAC VDD = +5.0 V±10% VDD = +5.0 V±10% 1T–20 ns 1T–30 ns Remark T: TCYK (system clock cycle time) a: 1 (during address wait), otherwise, 0 n: Number of wait states (n ≥ 0) 69 µPD784035Y, 784036Y, 784037Y, 784038Y (3) External wait timing Parameter Symbol Conditions MIN. VDD = +5.0 V±10% MAX. Unit (2+a)T–40 ns WAIT↓ input time from address tDAWT WAIT↓ input time from ASTB↓ tDSTWT VDD = +5.0 V±10% WAIT hold time from ASTB↓ tHSTWTH VDD = +5.0 V±10% WAIT↑ delay time from ASTB↓ tDSTWTH VDD = +5.0 V±10% WAIT↓ input time from RD↓ tDRWTL VDD = +5.0 V±10% WAIT↓ hold time from RD↓ tHRWT VDD = +5.0 V±10% WAIT↑ delay time from RD↓ tDRWTH VDD = +5.0 V±10% Data input time from WAIT↑ tDWTID WR↑ delay time from WAIT↑ tDWTW 0.5T ns RD↑ delay time from WAIT↑ tDWTR 0.5T ns WAIT↓ input time from WR↓ tDWWTL WAIT hold time from WR↓ tHWWT VDD = +5.0 V±10% WAIT↑ delay time from WR↓ tDWWTH VDD = +5.0 V±10% (2+a)T–60 ns 1.5T–40 ns 1.5T–60 ns (0.5+n)T+5 ns (0.5+n)T+10 ns (1.5+n)T–40 (1.5+n)T–60 ns T–50 ns T–70 nT+5 ns (1+n)T–40 VDD = +5.0 V±10% ns ns nT+10 VDD = +5.0 V±10% ns ns (1+n)T–60 ns 0.5T–5 ns 0.5T–10 ns T–5 T–75 nT+5 ns ns ns nT+10 ns (1+n)T–40 ns (1+n)T–70 ns MAX. Unit Remark T: TCYK (system clock cycle time) a: 1 (during address wait), otherwise, 0 n: Number of wait states (n ≥ 0) (4) Refresh timing Parameter Symbol Random read/write cycle time tRC REFRQ low-level pulse width tWRFQL Conditions MIN. 3T ns 1.5T–25 ns 1.5T–30 ns REFRQ delay time from tDSTRFQ ASTB↓ 0.5T–9 ns REFRQ delay time from tDRRFQ RD↑ 1.5T–9 ns REFRQ delay time from tDWRFQ WR↑ 1.5T–9 ns ASTB delay time from REFRQ↑ 0.5T–15 ns 1.5T–25 ns 1.5T–30 ns VDD = +5.0 V±10% tDRFQST REFRQ high-level pulse tWRFQH width VDD = +5.0 V±10% Remark T: TCYK (system clock cycle time) 70 µPD784035Y, 784036Y, 784037Y, 784038Y SERIAL OPERATION (T A = –40 to +85 °C, V DD = +2.7 to 5.5 V, AVSS = V SS = 0 V) (1) CSI Parameter Symbol Serial clock cycle time (SCK0) tCYSK0 Conditions Input MIN. External clock When SCK0 and SO0 are CMOS I/O Unit 10/fXX+380 ns T µs External clock When SCK0 and SO0 are CMOS I/O 5/fXX+150 ns 0.5T–40 µs External clock When SCK0 and SO0 are CMOS I/O 5/fXX+150 ns Output Input MAX. Serial clock low-level width (SCK0) tWSKL0 Serial clock high-level width (SCK0) tWSKH0 0.5T–40 µs SI0 setup time tSSSK0 40 ns SI0 hold time (from SCK0↑) tHSSK0 5/fXX+40 ns SO0 output delay time (from SCK0↓) tDSBSK1 CMOS push-pull output (3-wire serial I/O mode) 0 5/fXX+150 ns tDSBSK2 Open-drain output (2-wire serial I/O mode), RL = 1 kΩ 0 5/fXX+400 ns Output Input Output (to SCK0↑) Remarks 1. The values in this table are those when CL is 100 pF. 2. T: Serial clock cycle set by software. The minimum value is 16/fXX. 3. fXX: Oscillation frequency (2) I2C Parameter Symbol Standard mode I2C bus fXX = 4 to 32 MHz MIN. MAX. 100 High-speed mode I2C bus fXX = 8 to 32 MHz MIN. MAX. 0 400 Unit SCL clock frequency fSCL 0 Hold time of SCL clock low-level state tLOW 4.7 1.3 kHz µs Hold time of SCL clock high-level state tHIGH 4.0 0.6 µs Data hold time tHD; DAT 300 300 Data setup time tSU; DAT 250 Rising time of SDA and SCL signals tR 1000 Falling time of SDA and SCL signals tF 300 Load capacitance of each bus line Cb 400 900 ns 20+0.1Cb 300 ns 20+0.1Cb 300 ns 400 pF 100 ns 71 µPD784035Y, 784036Y, 784037Y, 784038Y (3) IOE1, IOE2 Parameter Symbol Conditions Serial clock cycle time (SCK1, SCK2) tCYSK1 Serial clock low-level width (SCK1, SCK2) tWSKL1 Serial clock high-level width (SCK1, SCK2) tWSKH1 0.5T–40 ns SI1, SI2 setup time (to SCK1, SCK2↑) tSSSK1 40 ns SI1, SI2 hold time (from SCK1, SCK2↑) tHSSK1 40 ns SO1, SO2 output delay time (from SCK1, SCK2↓) tDSOSK 0 SO1, SO2 output hold time (from SCK1, SCK2 ↑) tHSOSK Input VDD = +5.0 V±10% Output Internal clock divided by 16 Input VDD = +5.0 V±10% Output Internal clock divided by 16 Input VDD = +5.0 V±10% Output Internal clock divided by 16 During data transfer MIN. MAX. 250 500 Unit ns ns T ns 85 210 ns ns 0.5T–40 ns 85 210 ns ns 50 0.5tCYSK1–40 ns ns Remarks 1. The values in this table are those when CL is 100 pF. 2. T: Serial clock cycle set by software. The minimum value is 16/fXX. (4) UART, UART2 Parameter Symbol ASCK clock input cycle time tCYASK VDD = +5.0 V±10% 125 250 ns ASCK clock low-level width tWASKL VDD = +5.0 V±10% 52.5 ns 85 ns ASCK clock high-level width tWASKH 52.5 ns 85 ns 72 Conditions VDD = +5.0 V±10% MIN. MAX. Unit ns µPD784035Y, 784036Y, 784037Y, 784038Y CLOCK OUTPUT OPERATION Parameter Symbol CLKOUT cycle time tCYCL CLKOUT low-level width tCLL CLKOUT high-level width CLKOUT rising time CLKOUT falling time tCLH tCLR tCLF Conditions VDD = +5.0 V±10% VDD = +5.0 V±10% MIN. MAX. Unit nT ns 0.5tCYCL–10 ns 0.5tCYCL–20 ns 0.5tCYCL–10 ns 0.5tCYCL–20 ns VDD = +5.0 V±10% VDD = +5.0 V±10% 10 ns 20 ns 10 ns 20 ns MAX. Unit Remark n: Divided frequency ratio set by software in the CPU (n = 1, 2, 4, 8, 16) T: tCYK (system clock cycle time) OTHER OPERATIONS Parameter Symbol Conditions MIN. NMI low-level width tWNIL 10 µs NMI high-level width tWNIH 10 µs INTP0 low-level width tWIT0L 3tCYSMP+10 ns INTP0 high-level width tWIT0H 3tCYSMP+10 ns INTP1 to INTP3, CI low-level width tWIT1L 3tCYCPU+10 ns INTP1 to INTP3, CI high-level width tWIT1H 3tCYCPU+10 ns INTP4, INTP5 low-level width tWIT2L 10 µs INTP4, INTP5 high-level tWIT2H width 10 µs RESET low-level width tWRSL 10 µs RESET high-level width tWRSH 10 µs Remark tCYSMP: Sampling clock set by software tCYCPU: CPU operation clock set by software in the CPU 73 µPD784035Y, 784036Y, 784037Y, 784038Y A/D CONVERTER CHARACTERISTICS (T A = –40 to +85°C, V DD = AV DD = AV REF1 = +2.7 to 5.5 V, VSS = AV SS = 0 V) Parameter Symbol Conditions Resolution Total error MIN. TYP. MAX. 8 bit Note Linearity calibration 1.0 Note Quantization error Conversion time Sampling time tCONV tSAMP Unit % 0.8 % ±1/2 LSB FR = 1 120 tCYK FR = 0 180 tCYK FR = 1 24 tCYK FR = 0 36 tCYK Analog input voltage VIAN Analog input impedance RAN AVREF1 current AIREF1 0.5 1.5 mA AVDD supply current AIDD1 fXX = 32 MHz, CS = 1 2.0 5.0 mA AIDD2 STOP mode, CS = 0 1.0 20 µA Note –0.3 V MΩ Quantization error is not included. This parameter is indicated as the ratio to the full-scale value. Remark tCYK: System clock cycle time 74 AVREF1+0.3 1000 µPD784035Y, 784036Y, 784037Y, 784038Y D/A CONVERTER CHARACTERISTICS (TA = –40 to +85°C, VDD = AVDD = +2.7 to 5.5 V, VSS = AVSS = 0 V) Parameter Symbol Conditions Resolution Load conditions: 4 MΩ, 30 pF Load conditions: 2 MΩ, 30 pF Settling time Analog reference voltage MAX. Unit bit VDD = AVDD = AVREF2 = +2.7 to 5.5 V AVREF3 = 0 V 0.6 % VDD = AVDD = +2.7 to 5.5 V AVREF2 = 0.75VDD AVREF3 = 0.25VDD 0.8 % VDD = AVDD = AVREF2 = +2.7 to 5.5 V AVREF3 = 0 V 0.8 % VDD = AVDD = +2.7 to 5.5 V AVREF2 = 0.75VDD AVREF3 = 0.25VDD 1.0 % Load conditions: 2 MΩ, 30 pF RO 10 DACS0, 1 = 55 H 10 µs kΩ AVREF2 0.75VDD VDD V AVREF3 0 0.25VDD V AVREF2, AVREF3 resistance RAIREF Reference power supply input current TYP. 8 Total error Output resistance MIN. DACS0, 1 = 55 H 4 8 kΩ AIREF2 0 5 mA AIREF3 –5 0 mA 75 µPD784035Y, 784036Y, 784037Y, 784038Y DATA RETENTION CHARACTERISTICS (T A = –40 to +85 °C) Parameter Symbol Conditions Data retention voltage VDDDR STOP mode Data retention current IDDDR VDDDR = +2.7 to 5.5 V VDDDR = +2.5 V MIN. TYP. MAX. Unit 5.5 V 10 50 µA 2 10 µA 2.5 VDD rising time tRVD 200 µs VDD falling time tFVD 200 µs VDD hold time tHVD (from STOP mode setting) 0 ms STOP release signal input time tDREL 0 ms Oscillation stabilization wait time tWAIT Low-level input voltage VIL High-level input voltage VIH Note Crystal resonator 30 ms Ceramic resonator 5 ms Specific pins Note 0 0.1VDDDR V 0.9VDDDR VDDDR V RESET, P20/NMI, P21/INTP0, P22/INTP1, P23/INTP2/CI, P24/INTP3, P25/INTP4/ASCK/SCK1, P26/ INTP5, P27/SI0, P32/SCK0/SCL, and P33/SO0/SDA pins AC TIMING TEST POINTS VDD – 1 V 0.8VDD or 2.2 V 0.8VDD or 2.2 V Test Points 0.45 V 76 0.8 V 0.8 V µPD784035Y, 784036Y, 784037Y, 784038Y TIMING WAVEFORM (1) Read operation tWSTH ASTB tSAST tDRST tDSTID tHSTLA A8 to A19 tDAID tHRA AD0 to AD7 tDSTR tFRA tDAR tHRID tDRID tDRA RD tWRL (2) Write operation tWSTH ASTB tSAST tDWST tDSTOD tHSTLA A8 to A19 tHWA AD0 to AD7 tDSTW tDAW tHWOD tDWOD tSODW WR tWWL 77 µPD784035Y, 784036Y, 784037Y, 784038Y HOLD TIMING ADTB, A8 to A19, AD0 to AD7, RD, WR tFHQC tDCFHA tDHAC HLDRQ tDHQLHAL tDHQHHAH HLDAK EXTERNAL WAIT SIGNAL INPUT TIMING (1) Read operation ASTB tDSTWT tDSTWTH tHSTWTH A8 to A19 AD0 to AD7 tDAWT tDWTID RD tDWTR tDRWTL WAIT tHRWT tDRWTH (2) Write operation ASTB tDSTWT tDSTWTH tHSTWTH A8 to A19 AD0 to AD7 tDAWT WR tDWTW tDWWTL WAIT tHWWT tDWWTH 78 µPD784035Y, 784036Y, 784037Y, 784038Y REFRESH TIMING WAVEFORM (1) Random read/write cycle tRC ASTB WR tRC tRC tRC tRC RD (2) When refresh memory is accessed for read and write at the same time ASTB RD, WR tDSTRFQ tDRFQST tWRFQH REFRQ tWRFQL (3) Refresh after read ASTB tDRFQST RD tDRRFQ REFRQ tWRFQL (4) Refresh after write ASTB tDRFQST WR tDWRFQ REFRQ tWRFQL 79 µPD784035Y, 784036Y, 784037Y, 784038Y SERIAL OPERATION (1) CSI tWSKL0 tWSKH0 SCK tSSSK0 tHSSK0 tCYSK0 Input data SI tDSBSK1 tHSBSK1 Output data SO (2) I2C tR tF tHIGH tLOW SCL SDA tHD; DAT tSU; DAT (3) IOE1, IOE2 tWSKL1 tWSKH1 SCK tSSSK1 tCYSK1 Input data SI tDSOSK tHSOSK Output data SO (4) UART, UART2 tWASKH tWASKL ASCK, ASCK2 tCYASK 80 tHSSK1 µPD784035Y, 784036Y, 784037Y, 784038Y CLOCK OUTPUT TIMING tCLH tCLL CLKOUT tCLR tCLF tCYCL INTERRUPT INPUT TIMING tWNIH tWNIL tWIT0H tWIT0L tWIT1H tWIT1L tWIT2H tWIT2L NMI INTP0 CI, INTP1 to INTP3 INTP4, INTP5 RESET INPUT TIMING tWRSH tWRSL RESET 81 µPD784035Y, 784036Y, 784037Y, 784038Y EXTERNAL CLOCK TIMING tWXH tWXL X1 tXR tXF tCYX DATA RETENTION CHARACTERISTICS STOP mode setting VDD VDDDR tHVD RESET NMI (Clearing by falling edge) NMI (Clearing by rising edge) 82 tFVD tRVD tDREL tWAIT µPD784035Y, 784036Y, 784037Y, 784038Y 14. PACKAGE DRAWINGS 80 PIN PLASTIC QFP (14×14) A B 60 61 41 40 detail of lead end C D S R Q 21 20 80 1 F J G I H M K P M N L NOTE Each lead centerline is located within 0.13 mm (0.005 inch) of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS INCHES A 17.2±0.4 0.677±0.016 B 14.0±0.2 0.551 +0.009 –0.008 C 14.0±0.2 0.551 +0.009 –0.008 D 17.2±0.4 0.677±0.016 F 0.825 0.032 G 0.825 0.032 H 0.30±0.10 0.012 +0.004 –0.005 I 0.13 0.005 J 0.65 (T.P.) 0.026 (T.P.) K 1.6±0.2 L 0.8±0.2 0.063±0.008 0.031 +0.009 –0.008 M 0.15 +0.10 –0.05 0.006 +0.004 –0.003 N 0.10 0.004 P 2.7 0.106 Q 0.1±0.1 0.004±0.004 R 5°±5° 5°±5° S 3.0 MAX. 0.119 MAX. S80GC-65-3B9-4 Remark The shape and material of the ES version are the same as those of the corresponding mass-produced product. 83 µPD784035Y, 784036Y, 784037Y, 784038Y ★ 80 PIN PLASTIC QFP (14×14) A B 60 61 41 40 detail of lead end C S D R Q 80 1 21 20 F G H I M J P K M N NOTE Each lead centerline is located within 0.13 mm (0.005 inch) of its true position (T.P.) at maximum material condition. L ITEM MILLIMETERS INCHES A 17.20±0.20 0.677±0.008 B 14.00±0.20 0.551 +0.009 –0.008 C 14.00±0.20 0.551 +0.009 –0.008 D 17.20±0.20 0.677±0.008 F 0.825 0.032 G 0.825 0.032 H 0.32±0.06 0.013 +0.002 –0.003 I 0.13 0.005 J 0.65 (T.P.) 0.026 (T.P.) K 1.60±0.20 0.063±0.008 L 0.80±0.20 0.031 +0.009 –0.008 M 0.17 +0.03 –0.07 0.007 +0.001 –0.003 N 0.10 0.004 P 1.40±0.10 0.055±0.004 Q 0.125±0.075 0.005±0.003 R 3° +7° –3° 3° +7° –3° S 1.70 MAX. 0.067 MAX. P80GC-65-8BT Remark The shape and material of the ES version are the same as those of the corresponding mass-produced product. 84 µPD784035Y, 784036Y, 784037Y, 784038Y 80 PIN PLASTIC TQFP (FINE PITCH) ( 12) A B 60 41 61 40 21 F 80 1 20 H I M J K M P G R Q S D C detail of lead end N L NOTE Each lead centerline is located within 0.10 mm (0.004 inch) of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS INCHES A 14.0±0.2 0.551 +0.009 –0.008 B 12.0±0.2 0.472 +0.009 –0.008 C 12.0±0.2 0.472 +0.009 –0.008 D 14.0±0.2 0.551 +0.009 –0.008 F 1.25 0.049 G 1.25 0.049 H 0.22 +0.05 –0.04 0.009±0.002 I 0.10 0.004 J 0.5 (T.P.) 0.020 (T.P.) K 1.0±0.2 0.039 +0.009 –0.008 L 0.5±0.2 0.020 +0.008 –0.009 M 0.145 +0.055 –0.045 0.006±0.002 N 0.10 0.004 P 1.05 0.041 Q 0.05±0.05 0.002±0.002 R 5°±5° 5°±5° S 1.27 MAX. 0.050 MAX. P80GK-50-BE9-4 Remark The shape and material of the ES version are the same as those of the corresponding mass-produced product. 85 µPD784035Y, 784036Y, 784037Y, 784038Y 15. RECOMMENDED SOLDERING CONDITIONS It is recommended that the µPD784035Y, 784036Y, 784037Y, and 784038Y be soldered under the following conditions. For details on the recommended soldering conditions, refer to information document “Semiconductor Device Mounting Technology Manual” (C10535E). For soldering methods and conditions other than those recommended, please consult an NEC representative. Caution The soldering conditions for the µPD784035YGK-×××-BE9 and 784036YGK-×××-BE9 are undefined because these products are currently under development. Table 15-1. Soldering Conditions for Surface Mount Type (1/2) (1) µ PD784035YGC-×××-3B9: 80-pin plastic QFP (14 × 14 mm, 2.7-mm thick) µ PD784036YGC-×××-3B9: 80-pin plastic QFP (14 × 14 mm, 2.7-mm thick) µ PD784037YGC-×××-3B9: 80-pin plastic QFP (14 × 14 mm, 2.7-mm thick) µ PD784038YGC-×××-3B9: 80-pin plastic QFP (14 × 14 mm, 2.7-mm thick) Soldering Method Soldering Conditions Recommended Condition Symbol Infrared ray reflow Package peak temperature: 235°C, Reflow time: 30 seconds or less (210°C or more) Number of reflow processes: 3 or less IR35-00-3 VPS Package peak temperature: 215°C, Reflow time: 40 seconds or less (200°C or more) Number of reflow processes: 3 or less VP15-00-3 Wave soldering Solder bath temperature: 260°C or less, Flow time: 10 seconds or less, Number of flow processes: 1, Preheating temperature: 120°C max. (package surface temperature) WS60-00-1 Partial heating Pin temperature: 300°C or less, Flow time: 3 seconds or less (for one side of the a device) — Caution Do not apply two or more different soldering methods to one chip (except for partial heating method). (2) µ PD784035YGC-×××-8BT: 80-pin plastic QFP (14 × 14 mm, 1.4-mm thick) µ PD784036YGC-×××-8BT: 80-pin plastic QFP (14 × 14 mm, 1.4-mm thick) µ PD784037YGC-×××-8BT: 80-pin plastic QFP (14 × 14 mm, 1.4-mm thick) µ PD784038YGC-×××-8BT: 80-pin plastic QFP (14 × 14 mm, 1.4-mm thick) Soldering Method Soldering Conditions Recommended Condition Symbol Infrared ray reflow Package peak temperature: 235°C, Reflow time: 30 seconds or less (210°C or more) Number of reflow processes: 2 or less IR35-00-2 VPS Package peak temperature: 215°C, Reflow time: 40 seconds or less (200°C or more) Number of reflow processes: 2 or less VP15-00-2 Wave soldering Solder bath temperature: 260°C or less, Flow time: 10 seconds or less, Number of flow processes: 1, Preheating temperature: 120°C max. (package surface temperature) WS60-00-1 Partial heating Pin temperature: 300°C or less, Flow time: 3 seconds or less (for one side of the a device) — Caution Do not apply two or more different soldering methods to one chip (except for partial heating method). 86 µPD784035Y, 784036Y, 784037Y, 784038Y Table 15-1. Soldering Conditions for Surface Mount Type (2/2) (3) µ PD784037YGK-×××-BE9: 80-pin plastic TQFP (fine-pitch) (12 × 12 mm) µ PD784038YGK-×××-BE9: 80-pin plastic TQFP (fine-pitch) (12 × 12 mm) Soldering Method Soldering Conditions Infrared ray reflow Package peak temperature: 235°C, Reflow time: 30 seconds or less (210°C or more) Number of reflow processes: 2 or less Recommended Condition Symbol IR35-107-2 Exposure limit: 7 daysNote (10 hours of pre-baking is required at 125°C afterward) VPS Package peak temperature: 215°C, Reflow time: 40 seconds or less (200°C or more) Number of reflow processes: 2 or less Exposure limit: 7 daysNote (10 hours of pre-baking is required at 125°C afterward) Partial heating Pin temperature: 300°C or less, Flow time: 3 seconds or less (per side of a device) Note VP15-107-2 — Maximum number of days during which the product can be stored at a temperature of 25°C and a relative humidity of 65% or less after dry-pack package is opened. Caution Do not apply two or more different soldering methods to one chip (except for partial heating method). 87 µPD784035Y, 784036Y, 784037Y, 784038Y APPENDIX A DEVELOPMENT TOOLS The following development tools are available for supporting development of a system using the µPD784038Y. Language processor software RA78K4Note 1 Assembler package common to 78K/IV Series CC78K4Note 1 C compiler package common to 78K/IV Series CC78K4-LNote 1 C compiler library source file common to 78K/IV Series PROM writing tool PG-1500 PROM program writer PA-78P4026GC Programmer adapter connected to PG-1500 PA-78P4038GK PA-78P4026KK PG-1500 controllerNote 2 PG-1500 control program Debugging tool IE-784000-R In-circuit emulator common to 78K/IV Series IE-784000-R-BK Break board common to 78K/IV Series IE-784038-R-EM1 Emulation board for evaluation of µPD784038Y Subseries IE-784000-R-EM IE-70000-98-IF-B Interface adapter when PC-9800 series (except notebook type) is used as host machine IE-70000-98N-IF Interface adapter and cable when notebook type PC-9800 series is used as host machine IE-70000-PC-IF-B Interface adapter when IBM PC/ATTM is used as host machine IE-78000-R-SV3 Interface adapter and cable when EWS is used as host machine EP-78230GC-R Emulation probe for 80-pin plastic QFP (GC-3B9, GC-8BT type) common to µPD784038Y Subseries EP-78054GK-R Emulation probe for 80-pin plastic TQFP (fine pitch) (GK-BE9 type) common to µPD784038Y Subseries EV-9200GC-80 Socket mounted on board of target system created for 80-pin plastic QFP (GC-3B9, GC-8BT type) TGK-080SDW Adapter mounted on board of target system created for 80-pin plastic TQFP (fine pitch) (GK-BE9) EV-9900 Jig used to remove µPD78P4038YKK-T from EV-9200GC-80 SM78K4Note 3 System simulator common to 78K/IV Series ID78K4Note 3 Integrated debugger for IE-784000-R DF784038Note 4 Device file for µPD784038Y Subseries Real-time OS RX78K/IVNote 4 Real-time OS for 78K/IV Series MX78K4Note 2 OS for 78K/IV Series 88 µPD784035Y, 784036Y, 784037Y, 784038Y Notes. 1. • PC-9800 series (MS-DOSTM) base • IBM PC/AT and compatible machine (PC DOSTM, WindowsTM, MS-DOS, IBM DOSTM) base HP9000 series 700TM (HP-UXTM) base • • • 2. • • 3. • • • • 4. • • • • SPARCstation TM (SunOSTM) base NEWSTM (NEWS-OSTM) base PC-9800 series (MS-DOS) base IMB PC/AT and compatible machine (PC DOS, Windows, MS-DOS, IBM DOS) base PC-9800 series (MS-DOS+Windows) base IBM PC/AT and compatible machine (PC DOS, Windows, MS-DOS, IBM DOS) base HP9000 series 700 (HP-UX) base SPARCstation (SunOS) base PC-9800 series (MS-DOS) base IBM PC/AT and compatible machine (PC DOS, Windows, MS-DOS, IBM DOS) base HP9000 series 700 (HP-UX) base SPARCstation (SunOS) base Remarks 1. RA78K4, CC78K4, SM78K4, and ID78K4 are used in combination with DF784038. 2. The TGK-080SDW is a product of TOKYO ELETECH CORPORATION (Tokyo, 03-5295-1661). Consult an NEC sales representative about purchasing. 89 µPD784035Y, 784036Y, 784037Y, 784038Y APPENDIX B RELATED DOCUMENTS Documents related to device Document Name Document No. Japanese English µPD784031Y Data Sheet U11504J U11504E µPD784035Y, 784036Y, 784037Y, 784038Y Data Sheet U10741J This manual µPD78P4038Y Data Sheet U10742J U10742E µPD784038, 784038Y Subseries User’s Manual - Hardware U11316J U11316J µPD784038Y Subseries Special Function Register Table U11091J – 78K/IV Series User’s Manual - Instructions U10905J U10905E 78K/IV Series Instruction Table U10594J – 78K/IV Series Instruction Set U10595J – 78K/IV Series Application Note - Software Basics U10095J U10095E Documents related to development tools (User’s Manuals) Document Name Document No. Japanese English Operation U11334J U11334E Language U11162J — EEU-817 EEU-1402 Operation EEU-960 — Language EEU-961 — CC78K Series Library Source File U12322J — PG-1500 PROM Programmer U11940J EEU-1335 PG-1500 Controller - PC-9800 Series (MS-DOS) Based EEU-704 EEU-1291 PG-1500 Controller - IBM PC Series (PC DOS) Based EEU-5008 U10540E IE-784000-R EEU-5004 EEU-1534 IE-784038-R-EM1 U11383J U11383E EP-78230 EEU-985 EEU-1515 EP-78054GK-R EEU-932 EEU-1468 RA78K4 Assembler Package RA78K Series Structured Assembler Preprocessor CC78K4 Series SM78K4 System Simulator - Windows Based Reference U10093J U10093E SM78K Series System Simulator External component U10092J U10092E user open interface specification ID78K4 Integrated Debugger - Windows Based Reference U10440J U10440E ID78K4 Integrated Debugger HP9000 Series 700 Reference U11960J Under preparation (HP-UX) Based Caution The contents of the above related documents are subject to change without notice. Be sure to use the latest edition of a document for designing. 90 µPD784035Y, 784036Y, 784037Y, 784038Y Documents related to embedded software (User’s Manual) Document Name 78K/IV Series Real-Time OS 78K/IV Series OS MX78K4 Document No. Japanese English Basics U10603J U10603E Installation U10604J U10604E Debugger U10364J — Basics U11779J — Other documents Document Name Document No. Japanese English IC Package Manual C10943X Semiconductor Device Mounting Technology Manual C10535J C10535E Quality Grades on NEC Semiconductor Devices C11531J C11531E NEC Semiconductor Device Reliability/Quality Control System C10983J C10983E Electrostatic Discharge (ESD) Test MEM-539 — Guide to Quality Assurance for Semiconductor Devices C11893J MEI-1202 Guide to Microcontroller-Related Products by Third Parties U11416J — Caution The contents of the above related documents are subject to change without notice. Be sure to use the latest edition of a document for designing. 91 µPD784035Y, 784036Y, 784037Y, 784038Y NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 92 µPD784035Y, 784036Y, 784037Y, 784038Y Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • Ordering information • Product release schedule • Availability of related technical literature • Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) • Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) NEC Electronics (Germany) GmbH NEC Electronics Hong Kong Ltd. Santa Clara, California Tel: 800-366-9782 Fax: 800-729-9288 Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics Hong Kong Ltd. Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (France) S.A. NEC Electronics Singapore Pte. Ltd. Spain Office Madrid, Spain Tel: 01-504-2787 Fax: 01-504-2860 United Square, Singapore 1130 Tel: 253-8311 Fax: 250-3583 NEC Electronics (France) S.A. NEC Electronics (UK) Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 NEC Electronics Italiana s.r.1. Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 NEC Electronics Taiwan Ltd. NEC Electronics (Germany) GmbH Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 Taipei, Taiwan Tel: 02-719-2377 Fax: 02-719-5951 NEC do Brasil S.A. Sao Paulo-SP, Brasil Tel: 011-889-1680 Fax: 011-889-1689 J96. 8 93 µPD784035Y, 784036Y, 784037Y, 784038Y Caution Purchase of NEC I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. EEPROM and IEBUS are trademarks of NEC Corporation. MS-DOS and Windows are either registered trademarks or trademarks of Microsoft Corporatin in the United States and/or other countries. IBM DOS, PC/AT, and PC DOS are trademarks of International Business Machines Corporation. HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Corporation. SPARCstation is a trademark of SPARC International, Inc. SunOS is a trademark of Sun Microsystems, Inc. NEWS and NEWS-OS are trademarks of Sony Corporation. The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product. M4 96.5