PRELIMINARY PRODUCT INFORMATION MOS INTEGRATED CIRCUIT µPD178046, 178048 8-BIT SINGLE-CHIP MICROCONTROLLER DESCRIPTION The µPD178046 and 178048 are 8-bit single-chip CMOS microcontrollers with hardware for digital tuning systems. Employing the 78K/0 architecture as the CPU, these microcontrollers provide easy control access to the internal memories and peripheral hardware. The instructions are high-speed 78K/0 instructions suitable for system control. As the peripheral hardware, an OSD (on-screen display) controller and PWM (pulse width modulation) output for TV use, as well as many I/O ports, timers, A/D converter, serial interface, and power-ON clear circuit are provided. A flash memory model, µPD178F048, that can operate on the same supply voltage as the mask ROM models, and many development tools are under development. The functions of these microcontrollers are described in detail in the following User’s Manuals. Be sure to read these manuals when you design your system. µPD178048 Subseries User’s Manual : Planned to be published 78K/0 Series User’s Manual - Instruction : U12326E FEATURES • ROM and RAM capacities Item Program Memory Character ROM (ROM) (CROM) Part Number µPD178046 µPD178048 48K bytes 6912 bytes 60K bytes (256 characters) Data Memory Internal high-speed RAM 512 bytes Video RAM (VRAM) Internal expansion RAM 512 bytes 482 bytes (12 × 24 characters MAX.) • Instruction cycle: 0.4 µs (with 5.0-MHz crystal resonator) • Many peripheral hardware circuits General-purpose I/O ports, A/D converter, serial interface, timers, power-ON clear circuit • OSD controller and PWM output • Vectored interrupts: 17 • Supply voltage: VDD = 4.5 to 5.5 V The information contained in this document is being issued in advance of the production cycle for the device. The parameters for the device may change before final production or NEC Corporation, at its own discretion, may withdraw the device prior to its production. Document No. U13183EJ1V0PM00 (1st edition) Date Published June 1998 N CP(K) Printed in Japan © 1998 µPD178046, 178048 APPLICATION FIELD TV ORDERING INFORMATION Part Number Package µPD178046CW-××× 64-pin plastic shrink DIP (750 mil) µPD178048CW-××× 64-pin plastic shrink DIP (750 mil) Remark ××× indicates ROM code suffix. The ROM code suffix is E×× when an I2C bus is used. 2 Preliminary Product Information µPD178046, 178048 DEVELOPMENT OF µPD178048 SUBSERIES Products under development Flash memory model Mask ROM models 64 pins 64 pins µPD178048 ROM: 60 KB RAM: 1 KB µPD178F048 OSD controller: 256 types 12 lines × 24 digits 12 × 18 dots 8 colors PWM output: 8-bit resolution × 4 channels Flash memory: 60 KB RAM: 1 KB 64 pins µPD178046 ROM: 48 KB RAM: 1 KB Preliminary Product Information 3 µPD178046, 178048 FUNCTION OUTLINE (1/2) µPD178046 Part Number µPD178048 Item Internal ROM 48K bytes memory 60K bytes Character ROM (CROM) 6912 bytes (256 characters) High-speed RAM 512 bytes Expansion RAM 512 bytes Video RAM (VRAM) 432 bytes (12 × 24 characters MAX.) General-purpose register 8 bits × 32 registers (8 bits × 8 bits × 4 banks) Minimum instruction execution time 0.4 µs/0.8 µs/1.6 µs/3.2 µs/6.4 µs (with 5.0-MHz crystal resonator) Instruction set • • • • I/O ports Total • CMOS input • CMOS I/O • N-ch open-drain output A/D converter 8-bit resolution × 4 channels Serial interface • I2C bus modeNote : 2 channels (shift register: 1 channel) • 3-wire serial I/O mode : 1 channel Timer • • • • • 16-bit operation Multiplication/division (8 bits × 8 bits, 16 bits ÷ 8 bits) Bit manipulation (set, reset, test, Boolean operation) BCD adjustment, etc. 46 pins 4 pins 37 pins 5 pins Basic timer (timer carry (10 Hz)) : 1 channel 8-bit timer/event counter : 1 channel 8-bit timer : 1 channel 8-bit event counter : 1 channel 8-bit remote control timer : 1 channel • Watchdog timer Note : : : : : 1 channel If the I2C bus mode is used (including when it is implemented in software without using the peripheral hardware), inform NEC when you order a mask. 4 Preliminary Product Information µPD178046, 178048 (2/2) µPD178046 Part Number µPD178048 Item PWM output • 8-bit resolution × 4 channel • 14-bit resolution × 1 channel OSD Number of display characters 288 characters MAX. per screen (12 lines × 24 digits) controller Character type 256 types (stored in CROM) Character format 12 (width) × 18 (height) dots Character size 1 × 1, 2 × 2, 3 × 3, or 4 × 4 selectable Character color 8 colors Character frame Framed or non-framed characters selected in screen units Background No background, blank, or filled selectable. Background color (8 colors) can be specified. Half blanking Can be specified in character units. ROM correction 2 places Vectored Maskable Internal: 11, external: 5 interrupt Non-maskable Internal: 1 Software 1 source Standby function • HALT mode • STOP mode Reset • Reset by RESET pin • Internal reset by watchdog timer • Reset by power-ON clear circuit • Detection of less than 4.5 VNote (during CPU operation and on power application) • Detection of less than 2.5 VNote (in STOP mode) Supply voltage VDD = 4.5 to 5.5 V Package 64-pin plastic shrink DIP (750 mil) Note These values are the maximum values. Actually, reset is effected at lower voltages. Preliminary Product Information 5 µPD178046, 178048 PIN CONFIGURATION (Top View) • 64-pin plastic shrink DIP (750 mil) µPD178046CW-××× µPD178048CW-××× IC 1 64 VDD P47 2 63 P130/PWM00 P46 3 62 P131/PWM01 P45 4 61 P132/PWM02 P44 5 60 P133/PWM03 P43 6 59 P134/PWM1 P42 7 58 P20/SCL0 P41 8 57 P21/SCL1 P40 9 56 P22/SDA0 P67 10 55 P23/SDA1 P66 11 54 HSYNC P65 12 53 VSYNC P64 13 52 BLANK P63 14 51 B P62 15 50 G P61 16 49 R P60 17 48 I VDDPORT 18 47 GND1 P54 19 46 OSC1 P53 20 45 OSC2 P52 21 44 P00/INTP0 P51 22 43 P01/INTP1 P50 23 42 P02/INTP2 GNDPORT 24 41 P03/INTP3 TI9/P77 25 40 P10/ANI0 TO5/P76 26 39 P11/ANI1 TI5/P75 27 38 P12/ANI2 OSCMON/P74 28 37 P13/ANI3 TI21/P73 29 36 RESET SCK3/P72 30 35 X1 SO3/P71 31 34 X2 SI3/P70 32 33 GND0 Cautions 1. Directly connect IC (Internally Connected) pins to GND0 or GND1. 2. Keep the voltage at the VDDPORT pin the same as the VDD pin. 3. Keep the voltage at the GNDPORT pin the same as GND0 or GND1. 6 Preliminary Product Information µPD178046, 178048 PIN NAMES ANI0-ANI3 : A/D converter input P70-P77 : Port 7 B : Character signal output P130-P134 : Port 13 BLANK : Blanking signal output PWM00-PWM03 : 8-bit PWM output G : Character signal output PWM1 : 14-bit PWM output GND0, GND1 : Ground R : Character signal output GNDPORT : Port ground RESET : Reset input HSYNC : Horizontal sync signal input SCK3 : Serial clock input/output I : Character signal output SCL0, SCL1 : Serial clock input/output IC : Internally connected SDA0, SDA1 : Serial data input/output INTP0-INTP3 : Interrupt input SI3 : Serial data input OSC1, OSC2 : LC connection for OSD dot clock SO3 : Serial data output OSCMON : OSD clock output P00-P03 P10-P13 oscillation TI5, TI9, TI21 : 8-bit timer clock input TO5 : 8-bit timer output : Port 0 VDD : Power supply : Port 1 VDDPORT : Port power supply P20-P23 : Port 2 VSYNC : Vertical sync signal input P40-P47 : Port 4 X1, X2 : Crystal resonator connection for P50-P54 : Port 5 P60-P67 : Port 6 system clock oscillation Preliminary Product Information 7 µPD178046, 178048 BLOCK DIAGRAM TI5/P75 TO5/P76 TI9/P77 TI21/P73 8-bit TIMER /EVENT COUNTER (TM5) PORT0 4 P00-P03 8-bit REMOTE CONTROLLER TIMER (TM9) PORT1 4 P10-P13 8-bit TIMER (TM20) PORT2 4 P20-P23 8-bit EVENT COUNTER (TM21) PORT4 8 P40-P47 PORT5 5 P50-P54 PORT6 8 P60-P67 PORT7 8 P70-P77 PORT13 5 P130-P134 A/D CONVERTER 4 ANI0/P10ANI3/P13 8-bit PWM (PWM0) 4 PWM00/P130PWM03/P133 WATCHDOG TIMER BASIC TIMER (BTM1) SDA0/P22 SDA1/P23 SCL0/P20 SCL1/P21 I2CBus1 SI3/P70 SO3/P71 SCK3/P72 SERIAL INTERFACE3 (SIO3) INTP0/P00INTP3/P03 4 78K/0 CPU CORE ROM (IIC1) INTERRUPT CONTROL RAM [1K Bytes] R G B I BLANK HSYNC VSYNC OSC1 OSC2 OSCMON/P74 ON SCREEN DISPLAY CONTROLLER 14-bit PWM (PWM1) PWM1/P134 SYSTEM CONTROL RESET X1 X2 VDD PORT GNDPORT VDD VIDEO RAM [432 Bytes] CHARACTER ROM [6912 Bytes] RESET CPU PERIPHERAL VOLTAGE REGULATOR GND0 GND1 IC Remark The internal ROM capacity differs depending on the model. 8 Preliminary Product Information µPD178046, 178048 TABLE OF CONTENTS 1. PIN 1.1 1.2 1.3 FUNCTIONS ........................................................................................................................... Port Pins ............................................................................................................................... Pins Other Than Port Pins ................................................................................................. I/O Circuits of Respective Pins and Recommended Connection of Unused Pins .... 10 10 11 12 2. MEMORY SPACE .......................................................................................................................... 2.1 Memory Size Select Register (IMS) .................................................................................. 2.2 Internal Expansion RAM Size Select Register (IXS) ...................................................... 15 16 17 3. FEATURES OF PERIPHERAL HARDWARE FUNCTIONS ........................................................ 3.1 Ports ...................................................................................................................................... 3.2 Clock Generation Circuit ................................................................................................... 3.3 Timers ................................................................................................................................... 3.4 A/D Converter ...................................................................................................................... 3.5 Serial Interface .................................................................................................................... 3.6 OSD Controller .................................................................................................................... 3.7 PWM Output ......................................................................................................................... 18 18 19 19 22 23 24 25 4. INTERRUPT FUNCTION ............................................................................................................... 26 5. ROM CORRECTION ..................................................................................................................... 28 6. STANDBY FUNCTION .................................................................................................................. 29 7. RESET FUNCTION ....................................................................................................................... 29 8. INSTRUCTION SET ...................................................................................................................... 30 9. PACKAGE DRAWING ................................................................................................................... 33 APPENDIX A. DEVELOPMENT TOOLS ........................................................................................... 34 APPENDIX B. RELATED DOCUMENTS .......................................................................................... 36 Preliminary Product Information 9 µPD178046, 178048 1. PIN FUNCTIONS 1.1 Port Pins Pin Name I/O P00-P03 I/O P10-P13 Input P20, P21 I/O P22, P23 Function At Reset Shared with: Port 0. 4-bit I/O port. Can be set in input or output mode in 1-bit units. Input INTP0-INTP3 Port 1. 4-bit input port. Input ANI0-ANI3 Port 2. 4-bit I/O port. Can be set in input or output mode in 1-bit units. Input SCL0, SCL1 SDA0, SDA1 P40-P47 I/O Port 4. 8-bit I/O port. Can be set in input or output mode in 1-bit units. Input — P50-P54 I/O Port 5. 5-bit I/O port. Can be set in input or output mode in 1-bit units. Input — P60-P67 I/O Port 6. 8-bit I/O port. Input — Can be set in input or output mode in 1-bit units. P70 I/O Port 7. Input SI3 P71 8-bit I/O port. SO3 P72 Can be set in input or output mode in 1-bit units. SCK3 P73 TI21 P74 OSCMON P75 TI5 P76 TO5 P77 TI9 P130-P133 P134 10 Output Port 13. 5-bit output port. N-ch open-drain output port (5 V withstand voltage). Preliminary Product Information — PWM00-PWM03 PWM1 µPD178046, 178048 1.2 Pins Other Than Port Pins Pin Name I/O Function At Reset INTP0-INTP3 Input External maskable interrupt input whose valid edge can be specified (rising edge, falling edge, or both rising and falling edges) Input P00-P03 SI3 Input Serial data input to serial interface Input P70 SO3 Output Serial data output from serial interface Input P71 Input P22, P23 Input P72 Input P20, P21 Input P75 SDA0, SDA1 I/O Serial data input/output to/from serial interface SCK3 I/O Serial clock input/output to/from serial interface SCL0, SCL1 I/O TI5 Input N-ch open-drain I/O N-ch open-drain I/O External count clock input to 8-bit timer/event counter (TM5) Shared with: TI9 External count clock input to 8-bit remote control timer (TM9) P77 TI21 External count clock input to 8-bit event counter (TM21) P73 TO5 ANI0-ANI3 PWM00PWM03 Output Input Output PWM1 OSCMON VSYNC Input P76 Analog input to A/D converter Input P10-P13 8-bit PWM output N-ch open-drain I/O — 14-bit PWM output Output Input HSYNC R 8-bit timer/event counter (TM5) output P134 OSD clock output Input OSD vertical sync signal input Input OSD horizontal sync signal input Output RED output for OSD characters and background P130-P133 P74 — — Low-level — output — G GREEN output for OSD characters and background B BLUE output for OSD characters and background — I Character background output for OSD characters and blank background mode — BLANK OSD blanking signal output — RESET Input System reset input — — X1 Input Crystal resonator connection for system clock oscillation — — X2 — — — — — — — OSC1 Input OSC2 Output LC connection for OSD dot clock oscillation VDD — Positive power supply — — GND0, GND1 — Ground — — VDDPORT — Port power supply — — GNDPORT — Port ground — — IC — Internally connected. Directly connect this pin to GND0 or GND1. — — Preliminary Product Information 11 µPD178046, 178048 1.3 I/O Circuits of Respective Pins and Recommended Connection of Unused Pins Table 1-1 shows the I/O circuit type of each pin and the recommended connection of unused pins. For the configuration of each I/O circuit, refer to Figure 1-1. Table 1-1. I/O Circuits of Respective Pins and Recommended Connection of Unused Pins Pin Name I/O Circuit Type I/O Recommended Connection of Unused Pins P00/INTP0-P03/INTP3 8 I/O Set in general-purpose input port mode by software, and individually connect to GND0, GND1, or GNDPORT via resistor. P10/ANI0-P13/ANI3 25 Input Individually connect to VDD, VDDPORT, GND0, GND1, and GNDPORT via resistor. P20/SCL0, P21/SCL1 10-D I/O P22/SDA0, P23/SDA1 P40-P47 Set in general-purpose input port mode by software, and individually connect to VDD, VDDPORT, GND0, GND1, or GNDPORT via resistor. 5 P50-P54 P60-P67 P70/SI3 5-K P71/SO3 5 P72/SCK3 5-K P73/TI21 P74/OSCMON 5 P75/TI5 5-K P76/TO5 5 P77/TI9 5-K P130/PWM00 -P133/PWM03 19 Output 2 Input 3 Output RESET 2 Input OSC1 28 Input Set to low-level output by software and leave unconnected. P134/PWM1 VSYNC Individually connect to GND0 or GND1 via resistor. HSYNC R Set OSD display to OFF by software and leave unconnected. G B I BLANK OSC2 IC 12 Output — — — Set LC oscillation to OFF by software and leave unconnected. Leave unconnected. Directly connect to GND0 or GND1. Preliminary Product Information µPD178046, 178048 Figure 1-1. I/O Circuits of Respective Pins (1/2) Type 2 Type 5-K VDD data P-ch IN/OUT IN output disable Schmitt trigger input with hysteresis characteristics Type 3 N-ch input enable Type 8 VDD VDD data P-ch P-ch IN/OUT data OUT N-ch output disable N-ch Type 10-D Type 5 VDD VDD data data IN/OUT output disable input enable P-ch P-ch N-ch IN/OUT open drain output disable N-ch input enable Remark VDD and GND are positive power supply and ground pins for ports. Take them as VDDPORT and GNDPORT. Preliminary Product Information 13 µPD178046, 178048 Figure 1-1. I/O Circuits of Respective Pins (2/2) Type 19 Type 28 P-ch VDD N-ch OUT N-ch VDD P-ch P-ch N-ch N-ch IN N-ch OUT P-ch N-ch Type 25 P-ch Comparator + – N-ch VREF (threshold voltage) input enable Remark VDD and GND are positive power supply and ground pins for ports. Take them as VDDPORT and GNDPORT. 14 Preliminary Product Information µPD178046, 178048 2. MEMORY SPACE Figure 2-1 shows the memory map of the µPD178046 and 178048. Figure 2-1. Memory Map FFFFH Special function register (SFR) 256 × 8 bits FF00H F E F F H General-purpose register 32 × 8 bits FEE0H FEDFH Internal high-speed RAM 512 × 8 bits FD00H FCFFH nnnnH Cannot be used Data memory space F800H F7FFH Program area 1000H 0FFFH Internal expansion RAM 512 × 8 bits CALLF entry area 0800H 07FFH F600H F5FFH Program area Cannot be used CROMNote 2 (6912 byte) 0080H 007FH nnnnH+1 nnnnH CALLT table area Program memory space Note 1 Internal ROM 0040H 003FH Vector table area 0000H Notes 1. VRAMNote 3 (432 byte) 0000H The internal ROM capacity differs depending on the model (refer to the table below). Part Number Internal ROM End Address nnnnH µPD178046 BFFFH µPD178048 EFFFH 2. CROM cannot be read by software. 3. VRAM can be written via SFR. Preliminary Product Information 15 µPD178046, 178048 2.1 Memory Size Select Register (IMS) The internal memory capacities can be changed by using the memory size select register (IMS). Set IMS to the value shown in Table 2-1 depending on the internal memory capacity of each model. Use an 8-bit memory manipulation instruction to set this register. IMS is set to CFH at reset. Figure 2-2. Format of Memory Size Select Register (IMS) Symbol 7 6 5 4 IMS RAM2 RAM1 RAM0 0 3 2 1 ROM3 ROM2 ROM1 ROM0 RAM2 RAM1 RAM0 0 1 0 Others 0 At reset R/W FFF0H CFH R/W Selects internal high-speed RAM capacity 512 bytes Setting prohibited RAM3 RAM2 RAM1 RAM0 Selects internal ROM capacity 1 1 0 0 48K bytes 1 1 1 1 60K bytes Others Address Setting prohibited Table 2-1. Set Value of Memory Size Select Register (IMS) Part Number 16 Set Value of IMS µPD178046 4CH µPD178048 4FH Preliminary Product Information µPD178046, 178048 2.2 Internal Expansion RAM Size Select Register (IXS) The internal expansion RAM capacity can be selected by using the internal expansion RAM size select register. This register of the µPD178046 and 178048 must be set to 0BH. Use an 8-bit memory manipulation instruction to set IXS. The value of this register is set to 0CH at reset. Figure 2-3. Format of Internal Expansion RAM Size Select Register (IXS) Symbol 7 6 5 IXS 0 0 0 4 3 2 1 0 IXRAM4 IXRAM3 IXRAM2 IXRAM1 IXRAM0 IXRAM4 IXRAM3 IXRAM2 IXRAM1 IXRAM0 0 Others 1 0 1 1 Address At reset R/W FFF4H 0CH R/W Selects internal expansion RAM capacity 512 bytes Setting prohibited Preliminary Product Information 17 µPD178046, 178048 3. FEATURES OF PERIPHERAL HARDWARE FUNCTIONS 3.1 Ports The following three types of I/O ports are available: • CMOS input (port 1) : 4 pins • CMOS I/O (ports 0 and 2 through 7) : 37 pins • N-ch open-drain output (port 13) : 5 pins Total : 46 pins Table 3-1. Port Functions Name Pin Name Function Port 0 P00-P03 I/O port. Can be set in input or output mode in 1-bit units. Port 1 P10-P13 Input port Port 2 P20-P23 I/O port. Can be set in input or output mode in 1-bit units. Port 4 P40-P47 I/O port. Can be set in input or output mode in 1-bit units. Port 5 P50-P54 I/O port. Can be set in input or output mode in 1-bit units. Port 6 P60-P67 I/O port. Can be set in input or output mode in 1-bit units. Port 7 P70-P77 I/O port. Can be set in input or output mode in 1-bit units. Port 13 P130-P134 N-ch open-drain output port 18 Preliminary Product Information µPD178046, 178048 3.2 Clock Generation Circuit The instruction execution time can be changed as follows: • 0.4 µs/0.8 µs/1.6 µs/3.2 µs/6.4 µs (system clock: 5.0-MHz crystal resonator) Figure 3-1. Block Diagram of Clock Generation Circuit Prescaler X1 X2 System clock oscillation circuit Clock to peripheral hardware other than above Prescaler fX fX 2 fX 22 fX 23 fX 24 Selector STOP Standby control circuit Wait control circuit CPU clock (fCPU) 3.3 Timers Six timer channels are provided. • Basic timer : 1 channel • 8-bit timer/event counter : 1 channel • 8-bit timer : 1 channel • 8-bit event counter : 1 channel • 8-bit remote control timer : 1 channel • Watchdog timer : 1 channel 5.0 MHz Selector Figure 3-2. Block Diagram of Basic Timer (BTM1) Divider INTBTM1 BTMSEL Basic timer 1 mode register (BTMMD1) Internal bus Preliminary Product Information 19 µPD178046, 178048 Figure 3-3. Block Diagram of 8-Bit Timer/Event Counter (TM5) Internal bus 8-bit compare register 5 (CR5) TI5/P75 fX/2 fX/23 fX/25 fX/27 fX/29 fX/211 Selector INTTM5 S INV Q 8-bit counter 5 OVF (TM5) Selector Selector Coincidence R TO5/P76 Clear 3 S R Selector TCL52 TCL51 TCL50 TCE5 TMC56 Timer clock select register 5 (TCL5) 0 Level inversion LVS5 LVR5 TMC51 TOE5 Timer mode control register 5 (TMC5) Internal bus Figure 3-4. Block Diagram of 8-Bit Timer (TM20) Internal bus 8-bit compare register 20 (CR20) Coincidence fX/25 fX/211 Selector INTTM20 8-bit timer/counter 20 (TM20) Clear Selector 2 TCE20 TCL201 TCL200 8-bit timer mode control register 20 (TMC20) Internal bus 20 Preliminary Product Information µPD178046, 178048 Figure 3-5. Block Diagram of 8-Bit Event Counter (TM21) Internal bus 8-bit compare register 21 (CR21) Coincidence TI21/P73 Selector INTTM21 8-bit timer/counter 21 (TM21) Clear Selector 2 TCE21 TCL211 TCL210 8-bit timer mode control register 21 (TMC21) Internal bus Remark The 8-bit event counter (TM21) can be also used as an HSYNC counter. Figure 3-6. Block Diagram of 8-Bit Remote Control Timer (TM9) Internal bus INTTM10 Noise rejection Rising edge detection TI9/P77 8-bit timer capture register (CP90) fX/27 fX/28 Selector fX/26 1/2 8-bit timer register 9 (TM9) fX/29 INTTM92 Clear INTTM11 Noise rejection Falling edge detection 8-bit timer capture register (CP91) TCE1 TCL2 TCL1 Timer mode control register 9 (TMC9) Internal bus Preliminary Product Information 21 µPD178046, 178048 Figure 3-7. Block Diagram of Watchdog Timer Clock input control circuit fX/28 INTWDT Divided clock select circuit Divider Output control circuit RESET RUN Division mode select circuit 3 WDT mode signal OSTS2 OSTS1 OSTS0 Oscillation stabilization time select register (OSTS) WDCS2 WDCS1 WDCS0 RUN WDTM4 WDTM3 Watchdog timer mode register (WDTM) Watchdog timer clock select register (WDCS) Internal bus 3.4 A/D Converter An A/D converter with a resolution of 8 bits and 4 channels is provided. Figure 3-8. Block Diagram of A/D Converter Selector Tap selector Sample & hold circuit ANI0/P10 ANI1/P11 ANI2/P12 ANI3/P13 Voltage comparator VDD ADCS3 GND0, GND1 Successive approximation register (SAR) Control circuit INTAD A/D conversion result register (ADCR3) 4 ADS33 ADS32 ADS31 ADS30 ADCS3 0 Analog input channel specification register 3 (ADS3) FR32 FR31 FR30 0 0 0 A/D converter mode register 3 (ADM3) Control circuit value register 3 (PFT3) PFEN3 PFCM3 PFHRM3 Power-fail comparison mode register 3 (PFM3) Internal bus 22 Voltage comparator Power-fail comparison threshold Preliminary Product Information µPD178046, 178048 3.5 Serial Interface Two serial interface channels are provided. • Serial interface (IIC1) • Serial interface (SIO3) Table 3-2. Types and Functions of Serial Interfaces Function I2C IIC1 bus mode SIO3 (MSB first) 3-wire serial I/O mode — — (MSB first) Figure 3-9. Block Diagram of Serial Interface (IIC1) SDA0/P22 Control circuit IIC1 shift register 1 (IIC1) Output latch SDA1/P23 Control circuit Acknowledge output circuit Stop condition/start condition/acknowledge detection circuit SCL0/P20 Control circuit Serial clock counter Interrupt request signal generation circuit INTIIC1 Control circuit Serial clock control circuit Preliminary Product Information Selector SCL1/P21 fX/24 fX/25 fX/26 fX/27 23 µPD178046, 178048 Figure 3-10. Block Diagram of Serial Interface (SIO3) Internal bus 8 Direction control circuit 8 Serial I/O shift register 3 (SIO3) SI3/P70 SO3/P71 Serial clock counter Interrupt request signal generation circuit Serial clock control circuit Selector SCK3/P72 INTCSI3 3 fX/25 fX/26 fX/2 3.6 OSD Controller OSD (On-screen display) is a function to display the channel number, volume, and time on the TV screen. Userprogrammable display patterns for OSD are defied in the CROM (character ROM) area. The patterns actually displayed are stored in VRAM (video RAM). Figure 3-11. Block Diagram of OSD Controller OSC1 OSC2 LC oscillation circuit Address specification OSCMON/P74 HSYNC VSYNC 24 Video RAM (VRAM) Control data Divider Synchronization protection circuit Character ROM (CROM) Character pattern data Preliminary Product Information Output controller R G B BLACK µPD178046, 178048 3.7 PWM Output Four 8-bit PWM output channels and one 14-bit PWM output channel are provided. Figure 3-12. Block Diagram of 8-Bit PWM (PWM0) Internal bus PWM 8-bit compare register 0n (PWMCR0n) P13n output latch D 8 S PWM0n/P13n Q PWMSn I Q C C 8 fX 8-bit PWM counter 0 (PWMCT0) OVF generation circuit Remark PWMSn: Bit n of PWM output select register (PWMS) n = 0 to 3 Figure 3-13. Block Diagram of 14-Bit PWM (PWM1) Internal bus PWM14-bit compare register 1 (PWMCR1) P134 output latch D 14 S PWM1/P134 Q PWMS4 I Q C C 14 fX 14-bit PWM counter 1 (PWMCT1) OVF generation circuit Remark PWMS4: Bit 4 of PWM output select register (PWMS) Preliminary Product Information 25 µPD178046, 178048 4. INTERRUPT FUNCTION The following three types and 17 sources of interrupts are available: • Non-maskable : 1 Note • Maskable : 16 • Software : 1 Note Note One of two types of interrupt sources (INTWDT), non-maskable and maskable (internal) is selectable as the watchdog timer interrupt source. Table 4-1. Interrupt Sources Interrupt Default Type PriorityNote 1 Interrupt Source Name Internal/ External Trigger Nonmaskable — INTWDT Overflow of watchdog timer (when non-maskable interrupt is selected) Maskable 0 INTWDT Overflow of watchdog timer (when interval timer mode is selected) 1 INTP0 Detection of edge input to pin 2 INTP1 0008H 3 INTP2 000AH 4 INTP3 000CH 5 INTTM90 6 INTTM91 7 INTVSYNC Detection of VSYNC signal edge External 0012H (C) 8 INTTM21 Internal 0014H (B) Detection of 8-bit remote control timer (TM9) edge Internal Vector Basic Table Configuration Address TypeNote 2 0004H (A) (B) External Internal 0006H 000EH (C) (B) 0010H Generation of coincidence signal from 8-bit event counter (TM21) Software Notes 1. 9 INTIIC1 End of transfer of serial interface (IIC1) 0016H 10 INTTM92 Overflow of 8-bit remote control timer (TM9) 0018H 11 INTCSI3 End of transfer of serial interface (SIO3) 001AH 12 INTTM5 Generation of coincidence signal from 8-bit timer/event counter (TM5) 001CH 13 INTTM20 Generation of coincidence signal from 8-bit timer (TM20) 001EH 14 INTBTM1 Signal generation by basic timer (BTM1) at 1- or 10-ms intervals 0020H 15 INTAD End of conversion of A/D converter 0022H — BRK Execution of BRK instruction — 003EH The default priority is used if two or more maskable interrupts occur at the same time. 0 is the highest and 15 is the lowest. 2. 26 (D) (A) through (D) in Basic Configuration Type correspond to (A) through (D) in Figure 4-1. Preliminary Product Information µPD178046, 178048 Figure 4-1. Basic Configuration of Interrupt Functions (1/2) (A) Internal non-maskable interrupt Internal bus Priority control circuit Interrupt request Vector table address generation circuit Standby release signal (B) Internal maskable interrupt Internal bus MK Interrupt request IE PR ISP Priority control circuit IF Vector table address generation circuit Standby release signal (C) External maskable interrupt Internal bus External interrupt mode registers (EGP, EGN) Interrupt request Edge detection circuit MK IF IE PR Priority control circuit ISP Vector table address generation circuit Standby release signal Preliminary Product Information 27 µPD178046, 178048 Figure 4-1. Basic Configuration of Interrupt Functions (2/2) (D) Software interrupt Internal bus Interrupt request Remark IF IE Priority control circuit Vector table address generation circuit : Interrupt request flag : Interrupt enable flag ISP : In-service priority flag MK : Interrupt mask flag PR : Priority specification flag 5. ROM CORRECTION The µPD178046 and 178048 allow part of the program in the mask ROM to be replaced with a program in the internal expansion RAM for execution. By using this ROM correction function, bugs found in the mask ROM can be removed and program flow can be changed. The ROM correction function can be used at up to two places in the internal ROM (program). 28 Preliminary Product Information µPD178046, 178048 6. STANDBY FUNCTION The standby function is used to reduce the current power consumption and can be used in the following two modes. • HALT mode : The operation clock of the CPU is stopped in this mode. The average current consumption can be reduced by using this mode in combination with the normal operation mode and operating intermittently. • STOP mode: The oscillation of the system clock is stopped in this mode. All the operations using the system clock are stopped and therefore, the current consumption can be substantially reduced. Figure 6-1. Standby Function System clock operation Interrupt request STOP instruction HALT instruction Interrupt request STOP mode System clock oscillation stops. HALT mode Clock supply to CPU stops but oscillation continues. 7. RESET FUNCTION The µPD178046 and 178048 can be reset in the following three ways: • External reset by using the RESET pin • Internal reset by detecting hang-up time of the watchdog timer • Internal reset by means of power-ON clear (POC) Preliminary Product Information 29 µPD178046, 178048 8. INSTRUCTION SET (1) 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ Second #byte A rNote sfr saddr !addr16 PSW [DE] [HL] Operand [HL+byte] $addr16 1 None [HL+B] First [HL+C] Operand A r ADD MOV MOV MOV MOV ADDC XCH XCH XCH XCH SUB ADD ADD ADD MOV MOV MOV MOV ROR XCH XCH XCH ROL ADD ADD RORC ROLC SUBC ADDC ADDC ADDC ADDC ADDC AND SUB SUB SUB SUB SUB OR SUBC SUBC SUBC SUBC SUBC XOR AND AND AND AND AND CMP OR OR OR OR OR XOR XOR XOR XOR XOR CMP CMP CMP CMP CMP MOV MOV INC ADD DEC ADDC SUB SUBC AND OR XOR CMP B, C DBNZ sfr MOV MOV saddr MOV MOV DBNZ ADD INC DEC ADDC SUB SUBC AND OR XOR CMP !addr16 PSW MOV MOV MOV PUSH POP [DE] Note 30 Except r = A Preliminary Product Information µPD178046, 178048 Second #byte rNote A sfr saddr !addr16 PSW [DE] [HL] Operand [HL+byte] $addr16 1 None [HL+B] First [HL+C] Operand [HL] MOV ROR4 ROL4 [HL+byte] MOV [HL+B] [HL+C] X MULU C DIVUW Note Except r = A (2) 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW Second #word AX rp Note sfrp saddrp !addr16 SP None Operand First Operand AX ADDW MOVW SUBW XCHW MOVW MOVW MOVW MOVW CMPW rp MOVW MOVWNote INCW DECW PUSH POP sfrp MOVW MOVW saddrp MOVW MOVW !addr16 SP Note MOVW MOVW MOVW Only when rp = BC, DE, or HL Preliminary Product Information 31 µPD178046, 178048 (3) Bit manipulation instruction MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR Second A.bit sfr.bit saddr.bit PSW.bit [HL].bit CY $addr16 None Operand First Operand A.bit MOV1 BT SET1 BF CLR1 BTCLR sfr.bit MOV1 BT SET1 BF CLR1 BTCLR saddr.bit MOV1 BT SET1 BF CLR1 BTCLR PSW.bit MOV1 BT SET1 BF CLR1 BTCLR [HL].bit MOV1 BT SET1 BF CLR1 BTCLR CY MOV1 MOV1 MOV1 MOV1 MOV1 SET1 AND1 AND1 AND1 AND1 AND1 CLR1 NOT1 OR1 OR1 OR1 OR1 OR1 XOR1 XOR1 XOR1 XOR1 XOR1 (4) Call instruction/branch instruction CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ Second AX !addr16 !addr11 [addr5] $addr16 Operand First Operand Basic BR instruction CALL BR CALLF CALLT BR, BC, BNC BZ, BNZ Compound BT, BF instruction BTCLR DBNZ (5) Other instructions ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP 32 Preliminary Product Information µPD178046, 178048 9. PACKAGE DRAWING 64 PIN PLASTIC SHRINK DIP (750 mil) 64 33 1 32 A K J L I H F D C N B M R M G NOTES 1. Controlling dimension millimeter. 2. Each lead centerline is located within 0.17 mm (0.007 inch) of its true position (T.P.) at maximum material condition. 3. Item "K" to center of leads when formed parallel. ITEM MILLIMETERS INCHES A 58.0 +0.68 –0.20 2.283 +0.028 –0.008 B 1.78 MAX. 0.070 MAX. C 1.778 (T.P.) 0.070 (T.P.) D 0.50±0.10 0.020 +0.004 –0.005 F 0.9 MIN. 0.035 MIN. G 3.2±0.3 0.126±0.012 H 0.51 MIN. 0.020 MIN. I 4.05 +0.26 –0.20 0.159 +0.011 –0.008 J 5.08 MAX. 0.200 MAX. K 19.05 (T.P.) 0.750 (T.P.) L 17.0±0.2 0.669 +0.009 –0.008 M 0.25 +0.10 –0.05 0.010 +0.004 –0.003 N 0.17 0.007 R 0 to 15° 0 to 15° P64C-70-750A,C-3 Preliminary Product Information 33 µPD178046, 178048 APPENDIX A. DEVELOPMENT TOOLS The following systems are available for developing a system using the µPD178046 and 178048. Also refer to (5) Note on using development tools. (1) Language processor software RA78K/0 Common 78K/0 series assembler package CC78K/0 Common 78K/0 series C compiler package DF178048Note Device file for µPD178048 subseries CC78K/0-L Common 78K/0 series C compiler library source file (2) Flash memory writing tools Flashpro II Product name Dedicated Flash Pro pendingNote Flash writing adapter (3) Debugging tools IE-78K0-NS Common 78K/0 series in-circuit emulator IE-70000-MC-PS-B Power supply unit for IE-78K0-NS IE-70000-98-IF-C Interface adapter when PC-9800 series (except notebook type) is used as host machine IE-70000-CD-IF PC card and interface cable when notebook type of PC-9800 series is used as host machine IE-70000-PC-IF-C Interface adapter when IBM PC/ATTM or compatible machine is used as host machine IE-178048-NS-EM1Note Emulation board for emulating µPD178048 subseries Product name pendingNote Emulation probe for 64-pin plastic shrink DIP ID78K0-NSNote Integrated debugger for IE-78K0-NS SM78K0 Common system simulator for 78K/0 series DF178048Note Device file for µPD178048 subseries Note 34 Under development Preliminary Product Information µPD178046, 178048 (4) Real-time OS RX78K/0 Real-time OS for 78K/0 series MX78K0 OS for 78K/0 series (5) Notes on using development tools • Use the ID78K0-NS and SM78K0 with the DF178048. • Use the RX78K/0 with the RA78K/0 and DF178048. • The Flashpro II, flash writing adapter (product name pending), and emulation probe (product name pending) are products of Naito Densei Machida Mfg. Co., Ltd. (TEL (044) 822-3813). Consult NEC when purchasing these products. • For a description of development tools from the third parties, refer to 78K/0 Series Selection Guide (U11126E). • The host machine and OS corresponding to each software package are as follows: Host Machine [OS] Software PC EWS PC-9800 series [Japanese WindowsTM] IBM PC/AT and compatible machine [Japanese/English Windows] HP9000 series 700TM [HP-UXTM] SPARCstationTM [SunOSTM] NEWS (RISC)TM [NEWS-OSTM] RA78K/0 Note CC78K/0 Note ID78K0-NS — SM78K0 — RX78K/0 Note MX78K0 Note Note DOS-based software Preliminary Product Information 35 µPD178046, 178048 APPENDIX B. RELATED DOCUMENTS Device-related documents Document No. Document Name Japanese English µPD178F048 Preliminary Product Information U13056J Planned µPD178048 Subseries User’s Manual Planned Planned 78K/0 Series User’s Manual - Instruction U12326J U12326E 78K/0 Series Instruction Set U10904J — 78K/0 Series Instruction Table U10903J — µPD178048 Subseries Special Function Register Table Planned — 78K/0 Series Application Note Fundamentals (I) U12704J IEA-1288 Documents on development tools (User’s Manuals) Document No. Document Name Japanese RA78K0 Assembler Package Operation U11802J U11802E Assembly language U11801J U11801E Structured assembly language U11789J U11789E U12323J EEU-1402 Operation U11517J U11517E Language U11518J U11518E Programming Know-How U13034J EEA-1208 RA78K Series Structured Assembler Preprocessor CC78K0 C Compiler CC78K0 C Compiler Application Note English CC78K Series Library Source File U12322J — IE-78K0-NS Planned Planned IE-178048-NS-EM1 Planned Planned SM78K0 System Simulator Windows Based Reference U10181J U10181E SM78K Series System Simulator External part user open interface specifications U10092J 10092E ID78K0-NS Integrated Debugger PC Based Reference U12900J Planned Caution The contents of the above documents are subject to change without notice. Be sure to use the latest edition of each document for designing. 36 Preliminary Product Information µPD178046, 178048 Documents on embedded software (User’s Manuals) Document No. Document Name Japanese 78K/0 Series Real-Time OS 78K/0 Series OS MX78K0 English Fundamentals U11537J U11537E Installation U11536J U11536E Fundamentals U12257J U12257E Other related documents Document No. Document Name Japanese English IC Package Manual C10943X Semiconductor Device Mounting Technology Manual C10535J C10535E Quality Grades on NEC Semiconductor Devices C11531J C11531E NEC Semiconductor Device Reliability/Quality Control System C10983J C10983E Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892J C11892E Semiconductor Device Quality/Reliability Handbook C12769J Under preparation Microcomputer Product Series Guide U11416J — Caution The contents of the above documents are subject to change without notice. Be sure to use the latest edition of each document for designing. Preliminary Product Information 37 µPD178046, 178048 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Purchase of NEC I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or countries. PC/AT is a trademark of IBM Corporation. HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. SunOS is a trademark of Sun Microsystems, Inc. NEWS and NEWS-OS are trademarks of Sony Corporation. 38 Preliminary Product Information µPD178046, 178048 Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • Ordering information • Product release schedule • Availability of related technical literature • Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) • Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) NEC Electronics (Germany) GmbH NEC Electronics Hong Kong Ltd. Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288 Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics Hong Kong Ltd. Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (France) S.A. NEC Electronics Singapore Pte. Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Spain Office Madrid, Spain Tel: 01-504-2787 Fax: 01-504-2860 United Square, Singapore 1130 Tel: 65-253-8311 Fax: 65-250-3583 NEC Electronics Italiana s.r.1. NEC Electronics (Germany) GmbH Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 NEC Electronics (France) S.A. NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics (UK) Ltd. NEC Electronics Taiwan Ltd. Taipei, Taiwan Tel: 02-719-2377 Fax: 02-719-5951 NEC do Brasil S.A. Cumbica-Guarulhos-SP, Brasil Tel: 011-6465-6810 Fax: 011-6465-6829 J98. 2 Preliminary Product Information 39 µPD178046, 178048 The related documents referred to in this publication may include preliminary versions. However, preliminary versions are not marked as such. The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product. M4 96.5