TI SN74ALVC126D

SN74ALVC126
QUADRUPLE BUS BUFFER GATE
WITH 3-STATE OUTPUTS
SCES111E – JULY 1997 – REVISED FEBRUARY 1999
D
D
D
D
EPIC  (Enhanced-Performance Implanted
CMOS) Submicron Process
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Latch-Up Performance Exceeds 250 mA Per
JESD 17
Package Options Include Plastic
Small-Outline (D), Thin Very Small-Outline
(DGV), and Thin Shrink Small-Outline (PW)
Packages
D, DGV, OR PW PACKAGE
(TOP VIEW)
1OE
1A
1Y
2OE
2A
2Y
GND
1
14
2
13
3
12
4
11
5
10
6
9
7
8
VCC
4OE
4A
4Y
3OE
3A
3Y
description
This quadruple bus buffer gate is designed for 1.65-V to 3.6-V VCC operation.
The SN74ALVC126 features independent line drivers with 3-state outputs. Each output is disabled when the
associated output-enable (OE) input is low.
To ensure the high-impedance state during power up or power down, OE should be tied to GND through a
pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of
the driver.
The SN74ALVC126 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each buffer)
INPUTS
OE
A
OUTPUT
Y
H
H
H
H
L
L
L
X
Z
logic symbol†
1OE
1A
2OE
2A
3OE
3A
4OE
4A
1
EN
1
3
2
4
6
5
10
8
9
13
11
12
1Y
2Y
3Y
4Y
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright  1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
SN74ALVC126
QUADRUPLE BUS BUFFER GATE
WITH 3-STATE OUTPUTS
SCES111E – JULY 1997 – REVISED FEBRUARY 1999
logic diagram (positive logic)
1OE
1A
2OE
2A
1
2
3OE
3
1Y
4
5
3A
4OE
6
2Y
4A
10
9
8
3Y
13
12
11
4Y
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
2
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• DALLAS, TEXAS 75265
SN74ALVC126
QUADRUPLE BUS BUFFER GATE
WITH 3-STATE OUTPUTS
SCES111E – JULY 1997 – REVISED FEBRUARY 1999
recommended operating conditions (see Note 4)
VCC
Supply voltage
VIH
High-level input voltage
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
MIN
MAX
1.65
3.6
2
0.35 × VCC
Low-level input voltage
VI
VO
Input voltage
0
Output voltage
0
0.7
VCC = 2.7 V to 3.6 V
IOL
∆t/∆v
High level output current
High-level
VCC = 2.7 V
VCC = 3 V
VCC = 1.65 V
VCC = 2.3 V
Low level output current
Low-level
VCC = 2.7 V
VCC = 3 V
Input transition rise or fall rate
V
1.7
VIL
IOH
V
0.65 × VCC
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 1.65 V
VCC = 2.3 V
UNIT
V
0.8
VCC
VCC
V
V
–4
–12
–12
mA
–24
4
12
12
mA
24
5
ns/V
TA
Operating free-air temperature
–40
85
°C
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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• DALLAS, TEXAS 75265
3
SN74ALVC126
QUADRUPLE BUS BUFFER GATE
WITH 3-STATE OUTPUTS
SCES111E – JULY 1997 – REVISED FEBRUARY 1999
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –100 µA
IOH = –4 mA
VOH
IOH = –12 mA
IOH = –24 mA
IOL = 100 µA
Ci
Control inputs
Data inputs
1.7
UNIT
2.7 V
2.2
3V
2.4
3V
2
V
0.2
2.3 V
0.4
2.3 V
0.7
2.7 V
0.4
IO = 0
Other inputs at VCC or GND
One input at VCC – 0.6 V,
2
2.3 V
0.45
IOL = 24 mA
VI = VCC or GND
VO = VCC or GND
VI = VCC or GND,
2.3 V
1.65 V
IOL = 12 mA
ICC
∆ICC
MAX
1.65 V to 3.6 V
IOL = 4 mA
IOL = 6 mA
II
IOZ
TYP†
VCC–0.2
1.2
1.65 V
IOH = –6 mA
VOL
MIN
VCC
1.65 V to 3.6 V
V
3V
0.55
3.6 V
±5
µA
3.6 V
±10
µA
3.6 V
10
µA
3 V to 3.6 V
750
µA
VI = VCC or GND
3.5
33V
3.3
pF
F
3.5
Co
Outputs
VO = VCC or GND
† All typical values are at VCC = 3.3 V, TA = 25°C.
3.3 V
5.5
pF
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 1 through 3)
FROM
(INPUT)
TO
(OUTPUT)
tpd
A
ten
OE
tdis
OE
PARAMETER
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
MIN
MAX
MIN
MAX
Y
1.3
5.6
1
Y
1
5.9
1
Y
1.8
5.6
1
VCC = 2.7 V
MIN
VCC = 3.3 V
± 0.3 V
UNIT
MAX
MIN
MAX
3.4
3.4
1.1
3.1
ns
3.8
3.8
1
3.3
ns
3.3
4.4
1
3.7
ns
operating characteristics, TA = 25°C
PARAMETER
Cpd
4
Power dissipation
capacitance per gate
Outputs enabled
Outputs disabled
TEST
CONDITIONS
VCC = 1.8V
TYP
VCC = 2.5 V
TYP
VCC = 3.3 V
TYP
CL = 0,
f = 10 MHz
15
17
19
2
2
3
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UNIT
pF
SN74ALVC126
QUADRUPLE BUS BUFFER GATE
WITH 3-STATE OUTPUTS
SCES111E – JULY 1997 – REVISED FEBRUARY 1999
PARAMETER MEASUREMENT INFORMATION
VCC = 1.8 V ± 0.15 V
2 × VCC
S1
1 kΩ
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
1 kΩ
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC
VCC/2
VCC/2
0V
0V
tsu
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
VCC/2
0V
VCC/2
VCC/2
0V
tPLH
tPLZ
VCC
VCC/2
VCC/2
VOL
Output
Waveform 2
S1 at Open
(see Note B)
VOL + 0.15 V
VOL
tPHZ
tPZH
VOH
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC/2
tPZL
VCC
Input
VCC
Output
Control
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Output
VCC/2
Input
VCC/2
VOH
VOH – 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
SN74ALVC126
QUADRUPLE BUS BUFFER GATE
WITH 3-STATE OUTPUTS
SCES111E – JULY 1997 – REVISED FEBRUARY 1999
PARAMETER MEASUREMENT INFORMATION
VCC = 2.5 V ± 0.2 V
2 × VCC
S1
500 Ω
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC
VCC/2
Input
VCC/2
0V
0V
tsu
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
VCC/2
0V
VCC
Output
Control
VCC/2
VCC/2
Input
VCC/2
0V
tPLH
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
VCC
VCC/2
VOH
VCC/2
VOL
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
tPZH
tPHL
VCC/2
tPLZ
tPZL
VCC
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Output
VCC/2
VCC/2
VOH
VOH – 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 2. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74ALVC126
QUADRUPLE BUS BUFFER GATE
WITH 3-STATE OUTPUTS
SCES111E – JULY 1997 – REVISED FEBRUARY 1999
PARAMETER MEASUREMENT INFORMATION
VCC = 2.7 V AND 3.3 V ± 0.3 V
500 Ω
From Output
Under Test
6V
Open
S1
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
6V
GND
tw
LOAD CIRCUIT
2.7 V
2.7 V
Timing
Input
1.5 V
Input
1.5 V
1.5 V
0V
0V
tsu
VOLTAGE WAVEFORMS
PULSE DURATION
th
2.7 V
Data
Input
1.5 V
1.5 V
2.7 V
0V
Output
Control
1.5 V
1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
0V
tPLZ
tPZL
2.7 V
Input
1.5 V
1.5 V
0V
tPLH
tPHL
1.5 V
3V
1.5 V
tPZH
VOH
Output
Output
Waveform 1
S1 at 6 V
(see Note B)
1.5 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.3 V
VOL
tPHZ
1.5 V
VOH – 0.3 V
VOH
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 3. Load Circuit and Voltage Waveforms
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7
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Copyright  1999, Texas Instruments Incorporated