SN74AVC16245 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES142L – JULY 1998 – REVISED FEBRUARY 2000 D D D D D D Member of the Texas Instruments Widebus Family EPIC (Enhanced-Performance Implanted CMOS) Submicron Process DOC (Dynamic Output Control) Circuit Dynamically Changes Output Impedance, Resulting in Noise Reduction Without Speed Degradation Less Than 2-ns Maximum Propagation Delay at 2.5-V and 3.3-V VCC Dynamic Drive Capability Is Equivalent to Standard Outputs With IOH and IOL of ±24 mA at 2.5-V VCC D D D D Overvoltage-Tolerant Inputs/Outputs Allow Mixed-Voltage-Mode Data Communications Ioff Supports Partial-Power-Down Mode Operation ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) Latch-Up Performance Exceeds 250 mA Per JESD 78 Package Options Include Plastic Thin Shrink Small-Outline (DGG) and Thin Very Small-Outline (DGV) Packages description A Dynamic Output Control (DOC) circuit is implemented, which, during the transition, initially lowers the output impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1 shows typical VOL vs IOL and VOH vs IOH curves to illustrate the output impedance and drive capability of the circuit. At the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is equivalent to a high-drive standard-output device. For more information, refer to the TI application reports, AVC Logic Family Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOC) Circuitry Technology and Applications, literature number SCEA009. 3.2 TA = 25°C Process = Nominal – Output Voltage – V 2.4 VCC = 3.3 V 2.0 1.6 VCC = 2.5 V 1.2 OH VCC = 1.8 V 0.8 V VOL – Output Voltage – V 2.8 2.8 TA = 25°C Process = Nominal 2.4 2.0 1.6 1.2 0.8 VCC = 3.3 V VCC = 2.5 V 0.4 0.4 0 17 34 51 68 85 102 119 IOL – Output Current – mA 136 153 170 VCC = 1.8 V –160 –144 –128 –112 –96 –80 –64 –48 IOH – Output Current – mA –32 –16 0 Figure 1. Output Voltage vs Output Current This 16-bit (dual octal) noninverting bus transceiver is operational at 1.2-V to 3.6-V VCC, but is designed specifically for 1.65-V to 3.6-V VCC operation. The SN74AVC16245 is designed for asynchronous communication between data buses. The control-function implementation minimizes external timing requirements. This device can be used as two 8-bit transceivers or one 16-bit transceiver. It allows data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so that the buses are effectively isolated. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. DOC, EPIC, and Widebus are trademarks of Texas Instruments Incorporated. Copyright 2000, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74AVC16245 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES142L – JULY 1998 – REVISED FEBRUARY 2000 description (continued) To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The SN74AVC16245 is characterized for operation from –40°C to 85°C. terminal assignments DGG OR DGV PACKAGE (TOP VIEW) 1DIR 1B1 1B2 GND 1B3 1B4 VCC 1B5 1B6 GND 1B7 1B8 2B1 2B2 GND 2B3 2B4 VCC 2B5 2B6 GND 2B7 2B8 2DIR 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 1OE 1A1 1A2 GND 1A3 1A4 VCC 1A5 1A6 GND 1A7 1A8 2A1 2A2 GND 2A3 2A4 VCC 2A5 2A6 GND 2A7 2A8 2OE FUNCTION TABLE (each 8-bit transceiver) INPUTS 2 OPERATION OE DIR L L B data to A bus L H A data to B bus H X Isolation POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74AVC16245 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES142L – JULY 1998 – REVISED FEBRUARY 2000 logic symbol† 48 1OE 1DIR G3 1 3 EN1 [BA] 3 EN2 [AB] 25 2OE 2DIR G6 24 6 EN4 [BA] 6 EN5 [AB] 1A1 47 2 1 1B1 2 1A2 1A3 1A4 1A5 1A6 1A7 1A8 2A1 2A2 2A3 2A4 2A5 2A6 2A7 2A8 46 3 44 5 43 6 41 8 40 9 38 11 37 12 36 13 4 5 35 14 33 16 32 17 30 19 29 20 27 22 26 23 1B2 1B3 1B4 1B5 1B6 1B7 1B8 2B1 2B2 2B3 2B4 2B5 2B6 2B7 2B8 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. logic diagram (positive logic) 1DIR 1 2DIR 48 1A1 25 1OE 47 2A1 2 24 36 13 1B1 2B1 To Seven Other Channels To Seven Other Channels POST OFFICE BOX 655303 2OE • DALLAS, TEXAS 75265 3 SN74AVC16245 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES142L – JULY 1998 – REVISED FEBRUARY 2000 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Voltage range applied to any input/output when the output is in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . –0.5 V to 4.6 V Voltage range applied to any input/output when the output is in the high or low state, VO (see Notes 1 and 2) . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Package thermal impedance, θJA (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. 2. The output positive-voltage rating may be exceeded up to 4.6 V maximum if the output current rating is observed. 3. The package thermal impedance is calculated in accordance with JESD 51. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74AVC16245 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES142L – JULY 1998 – REVISED FEBRUARY 2000 recommended operating conditions (see Note 4) VCC VIH Supply voltage High-level input voltage MIN MAX Operating 1.4 3.6 Data retention only 1.2 VCC = 1.2 V VCC = 1.4 V to 1.6 V VCC 0.65 × VCC VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V 0.65 × VCC VI VO IOHS IOLS Low-level input voltage Output voltage Static high-level high level output current† low level output current† Static low-level V 2 GND 0.35 × VCC 0.35 × VCC VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V Input voltage V 1.7 VCC = 1.2 V VCC = 1.4 V to 1.6 V VIL UNIT V 0.7 0.8 0 3.6 V Active state 0 3-state 0 VCC 3.6 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V –2 VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V –8 –4 mA –12 VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V 2 VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V 8 4 mA 12 ∆t/∆v Input transition rise or fall rate VCC = 1.4 V to 3.6 V 5 ns/V TA Operating free-air temperature –40 85 °C † Dynamic drive capability is equivalent to standard outputs with IOH and IOL of ±24 mA at 2.5-V VCC. See Figure 1 for VOL vs IOL and VOH vs IOH characteristics. Refer to the TI application reports, AVC Logic Family Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOC) Circuitry Technology and Applications, literature number SCEA009. NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN74AVC16245 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES142L – JULY 1998 – REVISED FEBRUARY 2000 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOHS = –100 µA IOHS = –2 mA, VOH VIH = 0.91 V VIH = 1.07 V IOHS = –4 mA, IOHS = –8 mA, II Ioff Control inputs IOZ‡ ICC 1.4 V VIH = 1.7 V VIH = 2 V IOHS = –12 mA, IOLS = 100 µA VOL VCC 1.4 V to 3.6 V VIL = 0.49 V VIL = 0.57 V IOLS = 8 mA, IOLS = 12 mA, VIL = 0.7 V VIL = 0.8 V VI = VCC or GND VI or VO = 3.6 V VO = VCC or GND, VI = VCC or GND, Control inputs VI = VCC or GND Cio A or B ports orts VO = VCC or GND TYP† MAX VI (OE)= VCC IO = 0 UNIT VCC–0.2 1.05 1.65 V 1.2 2.3 V 1.75 3V 2.3 V 1.4 V to 3.6 V IOLS = 2 mA, IOLS = 4 mA, Ci MIN 0.2 1.4 V 0.4 1.65 V 0.45 2.3 V 0.55 V 3V 0.7 3.6 V ±2.5 µA 0 ±10 µA 3.6 V ±12.5 µA 3.6 V 40 µA 2.5 V 3 3.3 V 3 2.5 V 9 3.3 V 9 pF pF F † Typical values are measured at TA = 25°C. ‡ For I/O ports, the parameter IOZ includes the input leakage current. switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 2 through 5) FROM (INPUT) TO (OUTPUT) tpd A or B ten tdis PARAMETER VCC = 1.2 V VCC = 1.5 V ± 0.1 V VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V UNIT TYP MIN MAX MIN MAX MIN MAX MIN MAX B or A 3.9 0.8 4 0.7 3 0.6 1.9 0.5 1.7 ns OE A or B 8.4 1.5 9.2 1.4 7 1 4.3 0.7 3.7 ns OE A or B 8.4 2.3 9.3 2.2 7 1.1 4 1.2 3.9 ns operating characteristics, TA = 25°C PARAMETER Cpd d 6 Power dissipation capacitance TEST CONDITIONS Outputs enabled Outputs disabled CL = 0, 0 POST OFFICE BOX 655303 VCC = 1.8 V TYP f = 10 MHz • DALLAS, TEXAS 75265 VCC = 2.5 V TYP VCC = 3.3 V TYP 35 38 44 6 6 7 UNIT pF SN74AVC16245 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES142L – JULY 1998 – REVISED FEBRUARY 2000 PARAMETER MEASUREMENT INFORMATION VCC = 1.2 V AND 1.5 V ± 0.1 V 2 × VCC S1 2 kΩ From Output Under Test Open GND CL = 30 pF (see Note A) 2 kΩ TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND LOAD CIRCUIT tw VCC Timing Input VCC/2 VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC/2 VCC/2 0V tPLH Output Control (low-level enabling) tPLZ VCC VCC/2 tPZH VOH VCC/2 VOL VCC/2 0V Output Waveform 1 S1 at 2 × VCC (see Note B) tPHL VCC/2 VCC VCC/2 tPZL VCC Input VOLTAGE WAVEFORMS PULSE DURATION th VCC Data Input VCC/2 0V 0V tsu Output VCC VCC/2 Input Output Waveform 2 S1 at GND (see Note B) VOL + 0.1 V VOL tPHZ VCC/2 VOH VOH – 0.1 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 2. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SN74AVC16245 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES142L – JULY 1998 – REVISED FEBRUARY 2000 PARAMETER MEASUREMENT INFORMATION VCC = 1.8 V ± 0.15 V 2 × VCC S1 1 kΩ From Output Under Test Open GND CL = 30 pF (see Note A) 1 kΩ TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND LOAD CIRCUIT tw VCC Timing Input VCC/2 VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC/2 VCC/2 0V tPLH Output Control (low-level enabling) tPLZ VCC VCC/2 tPZH VOH VCC/2 VOL VCC/2 0V Output Waveform 1 S1 at 2 × VCC (see Note B) tPHL VCC/2 VCC VCC/2 tPZL VCC Input VOLTAGE WAVEFORMS PULSE DURATION th VCC Data Input VCC/2 0V 0V tsu Output VCC VCC/2 Input Output Waveform 2 S1 at GND (see Note B) VOL + 0.15 V VOL tPHZ VCC/2 VOH VOH – 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 3. Load Circuit and Voltage Waveforms 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74AVC16245 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES142L – JULY 1998 – REVISED FEBRUARY 2000 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.2 V 2 × VCC S1 500 Ω From Output Under Test Open GND CL = 30 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND LOAD CIRCUIT tw VCC Timing Input VCC/2 VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC/2 VCC/2 0V tPLH Output Control (low-level enabling) tPLZ VCC VCC/2 tPZH VOH VCC/2 VOL VCC/2 0V Output Waveform 1 S1 at 2 × VCC (see Note B) tPHL VCC/2 VCC VCC/2 tPZL VCC Input VOLTAGE WAVEFORMS PULSE DURATION th VCC Data Input VCC/2 0V 0V tsu Output VCC VCC/2 Input Output Waveform 2 S1 at GND (see Note B) VOL + 0.15 V VOL tPHZ VCC/2 VOH VOH – 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 4. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 SN74AVC16245 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES142L – JULY 1998 – REVISED FEBRUARY 2000 PARAMETER MEASUREMENT INFORMATION VCC = 3.3 V ± 0.3 V From Output Under Test 2 × VCC S1 500 Ω GND CL = 30 pF (see Note A) TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND Open 500 Ω tw LOAD CIRCUIT VCC VCC Timing Input VCC/2 Input VCC/2 0V VCC/2 0V tsu VOLTAGE WAVEFORMS PULSE DURATION th VCC Data Input VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC Output Control (low-level enabling) VCC/2 0V tPZL VCC Input VCC/2 VCC/2 0V tPLH VCC/2 tPLZ VCC VCC/2 tPZH VOH Output Output Waveform 1 S1 at 2 × VCC (see Note B) tPHL VCC/2 VOL VCC/2 Output Waveform 2 S1 at GND (see Note B) VOL + 0.3 V VOL tPHZ VCC/2 VOH VOH – 0.3 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 5. Load Circuit and Voltage Waveforms 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. 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