NEC UPD16676

DATA SHEET
MOS INTEGRATED CIRCUIT
µPD16676
1/16, 1/32 DUTY LCD CONTROLLER/DRIVER
DESCRIPTION
µPD16676 is a controller/driver containing RAMs capable of full-dot LCD displays. One of these IC chips can drive
the full-dot LCD up to 61-by-16 dots.
These ICs are the most suitable for Kanji character or Chinese character pagers, as well as graphic pagers,
displaying 16-by-16 dots per character.
FEATURES
• LCD driver with built-in display RAM
• Dot display RAM: 2560 bits
• Output: 61 segments & 16 commons
• 8-bit parallel interface
• Oscillation circuit incorporated
•
ORDERING INFORMATION
Part Number
Package
µPD16676P
Chips
µPD16676W
Wafer
µPD16676GF-3BA
100-PIN PLASTIC QFP (14 x 20 mm)
Remark
Purchasing the above products in terms of chips per wafer requires an exchange of other documents as
well, including a memorandum of the product quality. Therefore, those who are interested in this regard
are advised to contact an NEC salesperson for further details.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No.
S10561EJ5V0DS00 (5th edition)
Date Published June 1999 NS CP(K)
Printed in Japan
The mark • shows major revised points.
©
1996
µPD16676
1. BLOCK DIAGRAM
SEG0
SEG60
COM0
Segment Driver
COM15
Common Driver
16
61
Common Counter
61-bit Latch
Display Data RAM
(2560 bits)
Line Preset
Register & Counter
Line Address Decoder
RAM Read/Write
Controller
Timing
Generator
OSC1
Internal
Oscillator
OSC2
Column Address Decoder
8
Column Address
Counter & Register
8
8
8
8
DB0-DB7
A0
E(/RD)
Parallel
Interface
8
VLC1
Command
Decoder
VLC2
R,/W(/WR)
VLC3
VLC4
/RESET
VLC5
M,/S
FR
VDD VSS
Remark
2
/xxx indicates active low signals.
Data Sheet S10561EJ5V0DS00
µPD16676
2. PIN CONFIGURATION (Pad Layout)
50 49
32 31
51
52
30
29
79
80
2
1
81 82
99 100
Data Sheet S10561EJ5V0DS00
3
µPD16676
3. PIN CONNECTION
4
Pin No.
Pin Symbol
I/O
Pin No.
Pin Symbol
I/O
1
COM5
Output
51
SEG21
Output
2
COM6
Output
52
SEG20
Output
3
COM7
Output
53
SEG19
Output
4
COM8
Output
54
SEG18
Output
5
COM9
Output
55
SEG17
Output
6
COM10
Output
56
SEG16
Output
7
COM11
Output
57
SEG15
Output
8
COM12
Output
58
SEG14
Output
9
COM13
Output
59
SEG13
Output
10
COM14
Output
60
SEG12
Output
11
COM15
Output
61
SEG11
Output
12
SEG60
Output
62
SEG10
Output
13
SEG59
Output
63
SEG9
Output
14
SEG58
Output
64
SEG8
Output
15
SEG57
Output
65
SEG7
Output
16
SEG56
Output
66
SEG6
Output
17
SEG55
Output
67
SEG5
Output
18
SEG54
Output
68
SEG4
Output
19
SEG53
Output
69
SEG3
Output
20
SEG52
Output
70
SEG2
Output
21
SEG51
Output
71
SEG1
Output
22
SEG50
Output
72
SEG0
Output
23
SEG49
Output
73
A0
Input
24
SEG48
Output
74
OSC1
Input
25
SEG47
Output
75
OSC2
Output
26
SEG46
Output
76
E(/RD)
Input
27
SEG45
Output
77
R,/W(/WR)
Input
28
SEG44
Output
78
VSS
—
29
SEG43
Output
79
DB0
Input/Output
30
SEG42
Output
80
DB1
Input/Output
31
SEG41
Output
81
DB2
Input/Output
32
SEG40
Output
82
DB3
Input/Output
33
SEG39
Output
83
DB4
Input/Output
34
SEG38
Output
84
DB5
Input/Output
35
SEG37
Output
85
DB6
Input/Output
36
SEG36
Output
86
DB7
Input/Output
37
SEG35
Output
87
VDD
—
38
SEG34
Output
88
/RESET
Input
39
SEG33
Output
89
FR
Input/Output
40
SEG32
Output
90
VLC5
—
41
SEG31
Output
91
VLC3
—
42
SEG30
Output
92
VLC2
—
43
SEG29
Output
93
M,/S
Input
44
SEG28
Output
94
VLC4
—
45
SEG27
Output
95
VLC1
—
46
SEG26
Output
96
COM0
Output
47
SEG25
Output
97
COM1
Output
48
SEG24
Output
98
COM2
Output
49
SEG23
Output
99
COM3
Output
50
SEG22
Output
100
COM4
Output
Data Sheet S10561EJ5V0DS00
µPD16676
4. PIN COORDINATES
Chip Size
:
4.04 x 5.53 mm
Pad Size Al Area
:
120 x 120 µm
2
Pad Size Open Area
:
108 x 108 µm
2
2
Pin No.
X (µm)
Y (µm)
Pin No.
X (µm)
Y (µm)
Pin No.
X (µm)
Y (µm)
1
1771
−2230
36
668.8
2517.2
71
−1771
−757.2
2
1771
−2076
37
518.8
2517.2
72
−1771
−907.2
3
1771
−1922
38
368.8
2517.2
73
−1767.8
−1149.4
4
1771
−1768
39
218.8
2517.2
74
−1767.8
−1299.4
5
1771
−1614
40
68.8
2517.2
75
−1767.8
−1489.4
6
1771
−1460
41
−81.2
2517.2
76
−1767.8
−1639.4
7
1771
−1306
42
−231.2
2517.2
77
−1767.8
−1839.4
8
1771
−1152
43
−381.2
2517.2
78
−1767.8
−1989.4
9
1771
−998
44
−531.2
2517.2
79
−1767.8
−2139.4
10
1771
−844
45
−681.2
2517.2
80
−1767.8
−2289.4
11
1771
−690
46
−831.2
2517.2
81
−1745
−2513.4
12
1771
−536
47
−981.2
2517.2
82
−1595
−2513.4
13
1771
−382
48
−1131.2
2517.2
83
−1395
−2513.4
14
1771
−228
49
−1281.2
2517.2
84
−1245
−2513.4
15
1771
−74
50
−1431.2
2517.2
85
−1045
−2513.4
16
1771
80
51
−1771
2242.8
86
−895
−2513.4
17
1771
234
52
−1771
2092.8
87
−682.6
−2513.4
18
1771
388
53
−1771
1942.8
88
−532.2
−2513.4
19
1771
542
54
−1771
1792.8
89
−382.2
−2513.4
20
1771
696
55
−1771
1642.8
90
−106.6
−2513.4
21
1771
850
56
−1771
1492.8
91
69.8
−2513.4
22
1771
1004
57
−1771
1342.8
92
219.8
−2513.4
23
1771
1158
58
−1771
1192.8
93
369.8
−2513.4
24
1771
1312
59
−1771
1042.8
94
569.8
−2513.4
25
1771
1466
60
−1771
892.8
95
719.8
−2513.4
26
1771
1620
61
−1771
742.8
96
952.4
−2513.4
27
1771
1774
62
−1771
592.8
97
1102.4
−2513.4
28
1771
1928
63
−1771
442.8
98
1252.4
−2513.4
29
1771
2082
64
−1771
292.8
99
1402.4
−2513.4
30
1771
2236
65
−1771
142.8
100
1552.4
−2513.4
31
1418.8
2517.2
66
−1771
−7.2
32
1268.8
2517.2
67
−1771
−157.2
33
1118.8
2517.2
68
−1771
−307.2
34
968.8
2517.2
69
−1771
−457.2
35
818.8
2517.2
70
−1771
−607.2
Data Sheet S10561EJ5V0DS00
5
µPD16676
5. PIN DESCRIPTIONS
5.1 Power System
Pin Symbol
Pin Name
Pin No.
I/O
Function Description
VDD
Power supply pin
87
—
Power supply
VSS
Ground
78
—
Ground
VLC1 to VLC5
Reference power supply for
90,91,92,
—
Reference power supply for LCD driving
drivers
94,95
5.2 Logic system
Pin Symbol
Pin Name
Pin No.
I/O
Function Description
M,/S
Master/Slave selection
93
Input
FR
LCD to AC signal
89
Input/
Exchanges synchronizing signals (LCD-to-AC
Output
signals) in connecting cascades.
Switches between the master chip and the slave
chip.
This pin is for output if the chip is the master, and for
input if the chip is the slave.
DB0 to DB7
Data Bus
79 to 86
Input/
Data inputs/outputs
Output
A0
Data/Instruction Switching
73
Input
This pin is used for switching between the display
data and the instruction.
High level : Display data
Low level : Instruction
/RESET
Reset and 68/80-series
88
Input
switching
This pin performs reset at the edge of the low-level
pulse. At that level, it performs switching 68/80
series modes.
High level : 68 series MPU interface
Low level : 80 series MPU interface
E(/RD)
Enable and read enable
76
Input
68 series mode : Enable signal
80 series mode : Read enable signal
R,/W(/WR)
Read/Write and Write
77
Input
enable
68 series mode : Read/Write signal
80 series mode : Write enable signal
OSC1
Oscillation pin
74
Input
OSC2
Oscillation pin
75
Output
Oscillation (connected with a register between
OSC2)
Oscillation (connected with a register between
OSC1)
5.3 Driver System
Pin Symbol
SEG0 to
Pin Name
Pin No.
I/O
Description
Segment
72 to 12
Output
Segment output pins
Common
96 to 100,
Output
Common output pins
SEG60
COM0 to
COM15
1 to 11
If the chip is a slave, these pins correspond to
COM16 to COM31.
6
Data Sheet S10561EJ5V0DS00
µPD16676
6. COMMANDS
A0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Function
1
Display ON/OFF
Command
/RD /WR
1
0
0
1
0
1
0
1
1
1
0/1
2
Display start line
1
0
0
1
1
0
3
Page address set
1
0
0
1
0
1
4
Column(segment)
address set
1
0
0
0
5
Status read
0
1
0
B
U
S
Y
6
Display data write
1
0
1
Write Data
7
Display data read
0
1
1
Read data
8
ADC select
1
0
0
1
0
1
0
9
Static drive
ON/OFF
1
0
0
1
0
1
10 Duty select
1
0
0
1
0
11 Read modify write
1
0
0
1
12 END
13 Reset
1
1
0
0
0
0
1
1
ON/OFF of the whole display is
performed independent of the
display RAM’s data or internal
state.
1: ON, 0: OFF (Power save at
static drive ON)Note
Determines the RAM line
displayed on the uppermost line
(COM0) of the display.
Sets display RAM pages in the
page address register.
Sets display RAM’s column
address in the column address
register.
Reads status
BUSY
1: During internal operation
0: READY status
ADC
1: Clockwise output(Normal
rotation)
0: Counterclockwise output
(Reverse)
ON/OFF
1: Display OFF, 0: Display ON
RESET
1: Being reset, 0: Normal
Displays the
Accesses the
data bus data
display RAM of
and writes it
a pre-specified
address. After
onto the
display RAM.
access, the
Reads the data column
in the display
address is
RAM onto the incremented.
data bus.
This command is used to
reverse the correspondence
relationship between display
RAM’s column addresses and
segment driver outputs.
0: Clockwise output (Normal
rotation)
1: Counterclockwise output
(Reverse)
Selects between the normal
display operation and the static
all-lamp-driven display.
1: Static drive (Power save)Note
0: Normal display operation
Selects between two different
liquid-crystal cell driving duties.
1: 1/32 duty
0: 1/16 duty
Increments the column address
counter only when writing the
display data; but not when
reading it.
Cancels read modify write mode
Sets the display start line
register to the first line.
Sets the column address
counter and the page address
register to 0.
Display start address
(0 to 31)
1
1
0
Pages
(0 to 3)
Column addresses
(0 to 79)
A
D
C
O
N
/
O
F
F
R
E
S
E
T
0
0
0
0
0
0
0
0/1
0
0
1
0
0/1
1
0
1
0
0
0/1
1
1
0
0
0
0
0
1
1
1
1
0
0
1
0
1
0
1
1
0
0
Note If the static drive is turned ON in the display OFF state, the machine is placed in the power save state.
Data Sheet S10561EJ5V0DS00
7
µPD16676
7. DISPLAY RAM MAP
DB0
Column Address
0
0
79
Page 0
(640 bits)
DB7
7
8
Page 1
(640 bits)
15
16
Page 2
(640 bits)
23
24
Page 3
(640 bits)
31
Line Address
8
Data Sheet S10561EJ5V0DS00
µPD16676
8. Line Address Circuit
As is shown in Figure 8-1, the line address circuit specifies the line address that corresponds to a COM output for
displaying the contents of display data RAM. The display start line address set command specifies line address of to
the COM0 output.
The screen can be scrolled by dynamically changing the line address via the display start line address set
command.
Figure 8-1. Specification of Display Start Line Address in Display Data RAM
Remark
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
ADC
COM
Output
Column
Address
SEG60 13H 3CH
SEG59 14H 3BH
SEG58 15H 3AH
SEG57 16H 39H
SEG56 17H 38H
SEG55 18H 37H
SEG54 19H 36H
Page3
SEG53 1AH 35H
1
SEG7 48H 07H
1
Page2
SEG6 49H 06H
0
SEG5 4AH 05H
1
Page1
SEG4 4BH 04H
1
SEG3 4CH 03H
0
Page0
SEG2 4DH 02H
0
SEG1 4EH 01H
0
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
Line
Address
1 0
LCD
DB
0DB0
Out
Page
Address Data
DB1 DB0
SEG0 4FH 00H
•
COM16 to COM31 are valid in only 1/32 duty.
Data Sheet S10561EJ5V0DS00
9
µPD16676
•
9. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25 °C, VSS = 0 V)
Parameter
Symbol
Rating
Unit
–0.3 to +6.5
V
VDD–13 to VDD+0.3
V
Supply voltage
VDD
Driver reference supply input voltage
VLC1 to VLC4
Driver reference supply input voltage
VLC5
VDD–13 to +0.3
V
Logic system input voltage
VIN1
−0.3 to VDD + 0.3
V
Logic system output voltage
VOUT1
−0.3 to VDD + 0.3
V
Logic system input/output voltage
VI/O1
−0.3 to VDD + 0.3
V
Driver system output voltage
VOUT2
VLC5–0.3 to VDD + 0.3
V
Operating ambient temperature
TA
−40 to +85
°C
Storage temperature
Tstg
−65 to +150
°C
Cautions 1. If the absolute maximum rating of even one of the above parameters is exceeded even
momentarily, the quality of the product may be degraded. Absolute maximum ratings, therefore,
specify the values exceeding which the product may be physically damaged. Be sure to use the
product within the range of the absolute maximum ratings.
2. Ensure that the phase relationship is VDD ≥ VLC1 ≥ VLC2 ≥ VLC3 ≥ VLC4 ≥ VLC5.
Recommended Operating Range (VSS = 0 V)
Parameter
Symbol
MIN.
TYP.
MAX.
Unit
2.7
5.5
V
Supply voltage
VDD
Reference supply voltage
VLC1 to VLC4
VDD–12
VDD
V
Reference supply voltage
VLC5
VDD–12
0
V
Logic system input voltage
VIN1
0
VDD
V
10
Data Sheet S10561EJ5V0DS00
µPD16676
Electrical Characteristics (Unless otherwise specified, TA = −40
−4 to +85 °C, VDD = 2.7 to 5.5 V)
Parameter
Symbol
Condition
MIN.
TYP.Note
MAX.
Unit
High-level input voltage
VIH1
A0, DB0 to DB7, E, R,/W
0.8 VDD
V
High-level input voltage
VIH2
FR, M,/S, /RESET
0.8 VDD
V
Low-level input voltage
VIL1
A0, DB0 to DB7, E, R,/W
0.2 VDD
V
Low-level input voltage
VIL2
FR, M,/S, /RESET
0.2 VDD
V
High-level input current
IIH
A0, E, R,/W, /RESET
1
µA
Low-level input current
IIL
A0, E, R,/W, /RESET
–1
µA
High-level output voltage
VOH1
IOUT = –3 mA, DB0 to DB7,
High-level output voltage
VOH2
High-level output voltage
VOH3
0.8 VDD
V
IOUT = –2 mA, FR, VDD = 4.5 to 5.5 V
0.8 VDD
V
IOUT = –120 µA, OSC2,
0.8 VDD
V
VDD = 4.5 to 5.5 V
VDD = 4.5 to 5.5 V
Low-level output voltage
VOL1
0.2 VDD
V
IOUT = 2 mA, FR, VDD = 4.5 to 5.5 V
0.2 VDD
V
IOUT = 120 µA, OSC2,
0.2 VDD
V
IOUT = 3 mA, DB0 to DB7,
VDD = 4.5 to 5.5 V
Low-level output voltage
VOL2
Low-level output voltage
VOL3
VDD = 4.5 to 5.5 V
High-level output voltage
VOH1
High-level output voltage
VOH2
High-level output voltage
VOH3
0.8 VDD
V
IOUT = –1 mA, FR, VDD = 2.7 to 4.5 V
0.8 VDD
V
IOUT = –80 µA, OSC2,
0.8 VDD
V
IOUT = –1.5 mA, DB0 to DB7,
VDD = 2.7 to 4.5 V
VDD = 2.7 to 4.5 V
Low-level output voltage
VOL1
IOUT = 1.5 mA, DB0 to DB7,
0.2 VDD
V
VDD = 2.7 to 4.5 V
Low-level output voltage
VOL2
IOUT = 1 mA, FR, VDD = 2.7 to 4.5 V
0.2 VDD
V
Low-level output voltage
VOL3
IOUT = 80 µA, OSC2,
0.2 VDD
V
High-level leak current
ILOH
DB0 to DB7, VIN/OUT = VDD
3
µA
Low-level leak current
ILOL
DB0 to DB7, VIN/OUT = VSS
–3
µA
Driver output ON resistor
RON
TA = 25 °C, VDD = 5 V, VLC5 = VSS
7.5
kΩ
Driver output ON resistor
RON
TA = 25 °C, VDD = 3.5 V, VLC5 = VSS
50
kΩ
Static current consumption
IDD0
1.0
µA
Dynamic current consumption
IDD1
External clock: 18 kHz
15.0
µA
Self-oscillation: R = 1.3 MΩ
30.0
µA
VDD = 2.7 to 4.5 V
Dynamic current consumption
IDD3
During access: tCYC = 200 kHz
500
µA
Input capacitance
CIN
TA = 25 °C, f = 1 MHz
8.0
pF
Oscillator frequency
fOSC
In self-oscillation, VDD = 5.0 V,
15
18
21
kHz
11
16
21
kHz
1000
µs
R = 1.3 MΩ ± 2%
Oscillator frequency
fOSC
In self-oscillation, VDD = 3.0 V,
R = 1.3 MΩ ± 2%
Reset time
Remark
tR
/RESET↓→Internal reset release
1.0
The TYP. value is a reference value when TA = 25 °C.
Data Sheet S10561EJ5V0DS00
11
µPD16676
AC Characteristics 1 (Unless otherwise specified, TA = −40 to +85 °C, VDD = 4.5 to 5.5 V)
80 Series MPU Read/Write Timing
Parameter
Symbol
Address hold time
tAH8
Address setup time
tAW8
System cycle time
tCYC8
Control pulse width
tCC
Data setup time
tDS8
Data hold time
tDH8
/RD access time
tACC8
Output disable time
tOH8
Condition
A0
/WR, /RD
DB0 to DB7
MIN.
TYP.
MAX.
Unit
10
ns
20
ns
1000
ns
200
ns
80
ns
10
ns
DB0 to DB7 , CL = 100 pF
10
90
ns
60
ns
MAX.
Unit
68 Series MPU Read/Write Timing
Parameter
Symbol
System cycle time
tCYC6
Address setup time
Condition
TYP.
1000
ns
tAW6
20
ns
Address hold time
tAH6
10
ns
Data setup time
tDS6
80
ns
Data hold time
tDH6
10
ns
Output disable time
tOH6
Access time
tACC6
Enable pulse width
READ
tEW
A0, R,/W
MIN.
DB0 to DB7
DB0 to DB7, CL = 100 pF
E
WRITE
12
Data Sheet S10561EJ5V0DS00
10
60
ns
90
ns
100
ns
80
ns
µPD16676
AC Characteristics 2 (Unless otherwise specified, TA = −40 to +85 °C, VDD = 2.7 to 4.5 V)
80 Series MPU Read/Write Timing
Parameter
Symbol
Address hold time
tAH8
Address setup time
tAW8
System cycle time
tCYC8
Control pulse width
tCC
Data setup time
tDS8
Data hold time
tDH8
/RD access time
tACC8
Output disable time
tOH8
Condition
A0
/WR, /RD
DB0 to DB7
MIN.
TYP.
MAX.
Unit
20
ns
40
ns
2000
ns
400
ns
160
ns
20
ns
DB0 to DB7 , CL = 100 pF
20
180
ns
120
ns
MAX.
Unit
68 Series MPU Read/Write Timing
Parameter
Symbol
System cycle time
tCYC6
Address setup time
Condition
TYP.
2000
ns
tAW6
40
ns
Address hold time
tAH6
20
ns
Data setup time
tDS6
160
ns
Data hold time
tDH6
20
ns
Output disable time
tOH6
Access time
tACC6
Enable pulse width
READ
tEW
A0, R,/W
MIN.
DB0 to DB7
DB0 to DB7, CL = 100 pF
E
WRITE
Data Sheet S10561EJ5V0DS00
20
120
ns
180
ns
200
ns
160
ns
13
µPD16676
Test Point of Switching Characteristics
VIH
VIH
VIL
VIL
VOH
VOH
VOL
VOL
Input
Output
Waveforms of Switching Characteristics
80 Series MPU Read/Write Timing
tAH8
A0
tCYC8
tCC
tAW8
/WR,/RD
tDH8
tDS8
DB0 - DB7
(WRITE)
tACC8
tOH8
DB0 - DB7
(READ)
68 Series MPU Read/Write Timing
tCYC6
E
tAW6
tEW
R,/W
tAH6
A0
tDS6
tDH6
DB0 - DB7
(READ)
tACC6
DB0 - DB7
(READ)
14
Data Sheet S10561EJ5V0DS00
tOH6
µPD16676
Reset
/RESET
tR
Internal Status
Reset status
OSC
OSC
1/fOSC
Data Sheet S10561EJ5V0DS00
15
µPD16676
•
10. Application Circuit Example
VDD
M,/S
FR
OSC1
µ PD16676
Master Chip
16 COM
61 SEG
OSC2
LCD
16 COM
61 SEG
A0,
/RESET,
E,/RD,
R,/W, /WR
4
GND
8
DB0 - DB7
16
M,/S
µ PD16676
Slave Chip
OSC1
FR
Data Sheet S10561EJ5V0DS00
µPD16676
•
11. PACKAGE DRAWING
100 PIN PLASTIC QFP (14x20)
A
B
51
50
80
81
detail of lead end
S
C D
R
Q
31
30
100
1
F
G
H
I
J
M
P
K
M
N
S
NOTE
Each lead centerline is located within 0.15 mm of
its true position (T.P.) at maximum material condition.
L
S
ITEM
A
MILLIMETERS
23.2±0.2
B
20.0±0.2
C
14.0±0.2
D
17.2±0.2
F
0.8
G
H
0.6
0.32±0.08
I
0.15
J
0.65 (T.P.)
K
L
1.6±0.2
0.8±0.2
M
0.17 +0.08
−0.07
N
0.10
P
Q
R
S
2.7
0.125±0.075
5°±5°
2.825±0.175
S100GF-65-3BA-4
Data Sheet S10561EJ5V0DS00
17
µPD16676
•
12. RECOMMENDED SOLDERING CONDITIONS
Please consult with our sales offices for soldering conditions of the µPD16676.
Type of Surface Mount Device
µPD16676GF-3BA : 100-PIN PLASTIC QFP (14 x 20 mm)
18
Data Sheet S10561EJ5V0DS00
µPD16676
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Data Sheet S10561EJ5V0DS00
19
µPD16676
• The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
• No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
• NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
• Descriptions of circuits, software, and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these circuits,
software, and information in the design of the customer's equipment shall be done under the full responsibility
of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third
parties arising from the use of these circuits, software, and information.
• While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
• NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
M7 98. 8