DATA SHEET MOS INTEGRATED CIRCUIT µPD4416004 16M-BIT CMOS FAST SRAM 4M-WORD BY 4-BIT Description The µPD4416004 is a high speed, low power, 16,777,216 bits (4,194,304 words by 4 bits) CMOS static RAM. Operating supply voltage is 3.3 V ± 0.3 V. The µPD4416004 is packaged in a 54-PIN PLASTIC TSOP (II). Features • 4,194,304 words by 4 bits • Fast access time : 15, 17 ns (MAX.) • Output Enable input for easy application Ordering Information Part number Package • µPD4416004G5-A15-9JF 54-PIN PLASTIC TSOP (II) • µPD4416004G5-A17-9JF (10.16 mm (400)) Supply voltage Access time Supply current (MAX.) V (MAX.) ns At operating mA At standby mA 3.3 ± 0.3 15 220 10 17 210 The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. M14078EJ4V0DS00 (4th edition) Date Published December 2000 NS CP(K) Printed in Japan The mark • shows major revised points. © 1999 µPD4416004 Pin Configuration (Marking Side) /xxx indicates active low signal. 54-PIN PLASTIC TSOP (II) (10.16 mm (400)) [µPD4416004G5− −xxx− −9JF] NC VCC NC NC GND I/O 4 A0 A1 A2 A3 A4 A5 /CS VCC /WE NC A6 A7 A8 A9 A10 I/O 1 VCC NC NC GND NC 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 A0 - A21 NC GND NC NC VCC I/O 3 A21 A20 A19 A18 A17 NC /OE GND IC A16 A15 A14 A13 A12 A11 I/O 2 GND NC NC VCC NC : Address Inputs I/O1 - I/O4 : Data Inputs / Outputs /CS : Chip Select /WE : Write Enable /OE : Output Enable VCC : Power supply GND : Ground NC : No connection IC : Internal connection Note Note Leave this pin connect to GND. Remark Refer to Package Drawing for 1-pin index mark. 2 Data Sheet M14078EJ4V0DS µPD4416004 Block Diagram VCC GND A0 Address buffer A21 Row decoder Memory cell array 16,777,216 bits Sense amplifier / Switching circuit Input data controller I/O1 - I/O4 Column decoder Output data controller Address buffer /CS /WE /OE Truth Table /CS /OE /WE Mode I/O Supply current H × × Not selected High impedance ISB L L H Read DOUT ICC L × L Write DIN L H H Output disable High impedance Remark × : Don’t care Data Sheet M14078EJ4V0DS 3 µPD4416004 Electrical Specifications Absolute Maximum Ratings Parameter • • Symbol Supply voltage Condition Rating VCC Unit –0.5 Note to +4.0 V –0.5 Note to +4.0 V Input / Output voltage VT Operating ambient temperature TA 0 to 70 °C Storage temperature Tstg –55 to +125 °C Note –2.0 V (MIN.) (pulse width : 2 ns) Caution Exposing the device to stress above those listed in Absolute Maximum Rating could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended Operating Conditions Parameter Symbol Condition MIN. TYP. MAX. Unit 3.3 3.6 V Supply voltage VCC 3.0 High level input voltage VIH 2.0 VCC + 0.3 V Low level input voltage VIL –0.3 Note +0.8 V Operating ambient temperature TA 0 70 °C MAX. Unit Note –2.0 V (MIN.) (pulse width : 2 ns) DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) Parameter Symbol Test condition MIN. TYP. Input leakage current ILI VIN = 0 V to VCC –2 +2 µA Output leakage current ILO VI/O = 0 V to VCC, /CS = VIH or /OE = VIH or –2 +2 µA mA /WE = VIL • Operating supply current ICC • Standby supply current /CS = VIL, II/O = 0 mA, Cycle time : 15 ns 220 Minimum cycle time Cycle time : 17 ns 210 ISB /CS = VIH, VIN = VIH or VIL, Minimum cycle time 80 ISB1 /CS ≥ VCC – 0.2 V, 10 mA VIN ≤ 0.2 V or VIN ≥ VCC – 0.2 V High level output voltage VOH IOH = –4.0 mA Low level output voltage VOL IOL = +8.0 mA Remark 2.4 V 0.4 V MAX. Unit VIN : Input voltage, VI/O : Input / Output voltage Capacitance (TA = 25 °C, f = 1 MHz) Parameter Symbol Test condition MIN. TYP. Input capacitance CIN VIN = 0 V 6 pF Input / Output capacitance CI/O VI/O = 0 V 8 pF Remarks 1. VIN : Input voltage, VI/O : Input / Output voltage 2. These parameters are periodically sampled and not 100% tested. 4 Data Sheet M14078EJ4V0DS µPD4416004 AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) AC Test Conditions LVTTL Interface Input Waveform (Rise and Fall Time ≤ 3 ns) 3.0 V 1.5 V Test Points 1.5 V 1.5 V Test Points 1.5 V GND Output Waveform Output Load AC characteristics directed with the note should be measured with the output load shown in Figure 1 or Figure 2. Figure 1 Figure 2 (for tAA, tACS, tOE, tOH) (for tCLZ, tOLZ, tCHZ, tOHZ, tWHZ, tOW ) VTT = +1.5 V +3.3 V 50 Ω 317 Ω ZO = 50 Ω I/O (Output) I/O (Output) 30 pF CL Remark 351 Ω 5 pF CL CL includes capacitances of the probe and jig, and stray capacitances. Data Sheet M14078EJ4V0DS 5 µPD4416004 Read Cycle Parameter Symbol -A15 MIN. -A17 MAX. 15 MIN. Unit MAX. Read cycle time tRC Address access time tAA 15 17 ns /CS access time tACS 15 17 ns /OE access time tOE 7 8 ns Output hold from address change tOH 3 3 ns /CS to output in low impedance tCLZ 3 3 ns /OE to output in low impedance tOLZ 0 0 ns /CS to output in high impedance tCHZ 7 8 ns /OE to output hold in high impedance tOHZ 7 8 ns 17 ns Notes 1. See the output load shown in Figure 1. 2. Transition is measured at ±200 mV from steady-state voltage with the output load shown in Figure 2. 3. These parameters are periodically sampled and not 100% tested. Read Cycle Timing Chart 1 (Address Access) tRC Address (Input) tAA tOH I/O (Output) Previous data out Data out Remarks 1. In read cycle, /WE should be fixed to high level. 2. /CS = /OE = VIL Read Cycle Timing Chart 2 (/CS Access) tRC Address (Input) tAA tACS /CS (Input) tCLZ tCHZ /OE (Input) tOHZ tOE tOLZ I/O (Output) High impedance Data output Caution Address valid prior to or coincident with /CS low level input. Remark In read cycle, /WE should be fixed to high level. 6 Data Sheet M14078EJ4V0DS Notes High impedance 1 2, 3 µPD4416004 Write Cycle Parameter Symbol -A15 MIN. -A17 MAX. MIN. Unit MAX. Write cycle time tWC 15 17 ns /CS to end of write tCW 10 11 ns Address valid to end of write tAW 10 11 ns Write pulse width tWP 10 11 ns Data valid to end of write tDW 7 8 ns Data hold time tDH 0 0 ns Address setup time tAS 0 0 ns Write recovery time tWR 1 1 ns /WE to output in high impedance tWHZ Output active from end of write tOW 7 8 3 Notes 3 ns 1, 2 ns Notes 1. Transition is measured at ± 200 mV from steady-state voltage with the output load shown in Figure 2. 2. These parameters are periodically sampled and not 100% tested. Write Cycle Timing Chart 1 (/WE Controlled) tWC Address (Input) tCW /CS (Input) tAW tAS tWP tWR /WE (Input) tOW tWHZ I/O (Input / Output) Indefinite data output tDW High impedance tDH Data input High impedance Indefinite data output Cautions 1. /CS or /WE should be fixed to high level during address transition. • 2. Do not input data to the I/O pins while they are in the output state. Remarks 1. Write operation is done during the overlap time of a low level /CS, a low level /WE. 2. During tWHZ, I/O pins are in the output state, therefore the input signals of opposite phase to the output must not be applied. 3. When /WE is at low level, the I/O pins are always high impedance. When /WE is at high level, read operation is executed. Therefore /OE should be at high level to make the I/O pins high impedance. Data Sheet M14078EJ4V0DS 7 µPD4416004 Write Cycle Timing Chart 2 (/CS Controlled) tWC Address (Input) tAS tCW /CS (Input) tAW tWP tWR /WE (Input) tDW High impedance Data input I/O (Input) tDH High impedance Cautions 1. /CS or /WE should be fixed to high level during address transition. • 2. Do not input data to the I/O pins while they are in the output state. Remark 8 Write operation is done during the overlap time of a low level /CS and a low level /WE. Data Sheet M14078EJ4V0DS µPD4416004 Package Drawing 54-PIN PLASTIC TSOP (II) (10.16 mm (400)) 54 28 detail of lead end F P E 1 27 A H I G J S L N C D M S B K M NOTES 1. Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition. 2. Dimension "A" does not include mold fiash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15 mm per side. ITEM A MILLIMETERS 22.22±0.05 B 0.91 MAX. C 0.80 (T.P.) D 0.32+0.08 −0.07 E 0.10±0.05 F 1.1±0.1 G 1.00 H 11.76±0.20 I 10.16±0.10 J 0.80±0.20 K 0.145+0.025 −0.015 L 0.50±0.10 M 0.13 N 0.10 P 3°+7° −3° S54G5-80-9JF-2 Data Sheet M14078EJ4V0DS 9 µPD4416004 Recommended Soldering Conditions Please consult with our sales offices for soldering conditions of the µPD4416004. Type of Surface Mount Device µPD4416004 : 54-PIN PLASTIC TSOP (II) (10.16 mm (400)) 10 Data Sheet M14078EJ4V0DS µPD4416004 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Data Sheet M14078EJ4V0DS 11 µPD4416004 • The information in this document is current as of December, 2000. The information is subject to change without notice. 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