NEC UPD78C11AGQ

DATA
DATASHEET
SHEET
MOS INTEGRATED CIRCUIT
µPD78C10A, 78C11A, 78C12A
8-BIT SINGLE-CHIP MICROCOMPUTER (WITH A/D CONVERTER)
DESCRIPTION
The µPD78C11A is a CMOS 8-bit microprocessor which can integrate 16-bit ALU, ROM, RAM, an A/D converter,
a multi-function timer/event counter, and a general-purpose serial interface into a single chip, then expand the
memory (ROM/RAM) up to 60K bytes externally. The µPD78C10A is a ROM-less product of the µPD78C11A, and can
directly address the external memory up to 64k bytes. The µPD78C12A is a product which has more built-in ROM
capacity than the µPD78C11A, and its memory (ROM/RAM) can be externally extended up to 56K bytes. The
µPD78C10A, µPD78C11A, and µPD78C12A operated at low power consumption, because they have a CMOS
construction. Also, they can hold data with low power consumption by using standby function.
On-chip PROM products, µPD78CP14 and µPD78CP18 which are ideal for evaluation or preproduction use during
system development, early start-up and short-run multiple-device production of application sets, are available.
FEATURES
• Abundant 159 types of instructions : 87AD series instruction set, multiplication/division instructions,
16-bit operation instructions
• Instruction cycle : 0.8 µs (at 15 MHz operation)
• On-chip ROM : 4096W × 8 (µPD78C11A), 8192W × 8 (µPD78C12A)
Non (µPD78C10A)
• On-chip RAM : 256W × 8
• High-precision 8-bit A/D converter : 8 analog inputs
• General-purpose serial interface : Asynchronous, synchronous, I/O interface mode
• Multi-function 16-bit timer/event counter
• Two 8-bit timers
• I/O lines : 32 (µPD78C10A), 44 (µPD78C11A, 78C12A)
• Interrupt function (external - 3, internal - 8) : Non-maskable interrupt × 1, maskable interrupt × 10
• Standby function : HALT mode, hardware/software STOP mode
• Zero-cross detection function : (2 inputs)
• On-chip pull-up resistor (port A, B, C: µPD78C11A, 78C12A only) by mask option
Caution
The µPD78C10A does not hava a mask option.
The information in this document is subject to change without notice.
Document No. IC-2678C
(O. D. No. IC-7769E)
Date Published February 1995 P
Printed in Japan
The mark ★ shows major revised points.
©
1990
µPD78C10A,78C11A,78C12A
ORDERING INFORMATION
Ordering Code
µPD78C10ACW
µPD78C10AGF-3BE
µPD78C10AGQ-36
µPD78C10AL
µPD78C11ACW-×××
µPD78C11AGF-×××-3BE
µPD78C11AGQ-×××-36
µPD78C11AGQ-×××-37
µPD78C11AL-×××
µPD78C12ACW-×××
µPD78C12AGF-×××-3BE
µPD78C12AGQ-×××-36
µPD78C12AGQ-×××-37
µPD78C12AL-×××
2
Package
64-pin
64-pin
64-pin
68-pin
64-pin
64-pin
64-pin
64-pin
68-pin
64-pin
64-pin
64-pin
64-pin
68-pin
plastic
plastic
plastic
plastic
plastic
plastic
plastic
plastic
plastic
plastic
plastic
plastic
plastic
plastic
shrink DIP (750 mil)
QFP (14 × 20 mm)
QUIP
QFJ ( 950 mil)
shirink DIP (750 mil)
QFP (14 × 20 mm)
QUIP
QUIP straight
QFJ ( 950 mil)
shrink DIP (750 mil)
QFP (14 × 20 mm)
QUIP
QUIP straight
QFJ ( 950 mil)
On-Chip ROM
None
None
None
None
Mask ROM
Mask ROM
Mask ROM
Mask ROM
Mask ROM
Mask ROM
Mask ROM
Mask ROM
Mask ROM
Mask ROM
µPD78C10A,78C11A,78C12A
PIN CONFIGURATION (TOP VIEW)
PA0
1
64
V DD
PA1
2
63
STOP
PA2
3
62
PD7
PA3
4
61
PD6
PA4
5
60
PD5
PA5
6
59
PD4
PA6
7
58
PD3
PA7
8
57
PD2
PB0
9
56
PD1
PB1
10
55
PD0
PB2
11
54
PF7
PB3
12
53
PF6
PB4
13
52
PF5
PB5
14
51
PF4
PB6
15
50
PF3
PB7
16
49
PF2
PC0/T X D
17
48
PF1
PC1/R X D
18
47
PF0
PC2/SCK
19
46
ALE
PC3/INT2
20
45
WR
PC4/TO
21
44
RD
PC5/CI
22
43
AV DD
PC6/CO0
23
42
V AREF
PC7/CO1
24
41
AN7
NMI
25
40
AN6
INT1
26
39
AN5
MODE1
27
38
AN4
RESET
28
37
AN3
MODE0
29
36
AN2
X2
30
35
AN1
X1
31
34
AN0
V SS
32
33
AV SS
PD0
PF7
PF6
PF5
PF4
PF3
PF2
PF1
PF0
ALE
WR
RD
AV DD
V AREF
AN7
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
PD4
27
AV SS
V DD
58
26
V SS
PA0
59
25
X1
PA1
60
24
X2
PA2
61
23
MODE0
PA3
62
22
RESET
PA4
63
21
MODE1
PA5
64
20
19
2
3
4
5
6
7
8
m
9
10
11
12
13
14
15
16
17
18
INT1
NM1
1
PC7/CO1
57
PC6/CO0
AN0
STOP
PC5/CI
28
PC4/TO
56
PC3/INT2
AN1
PD7
PC2/SCK
29
PC1/R X D
55
PC0/T X D
AN2
PD6
PB7
30
PB6
54
PB5
AN3
PD5
PB4
31
PB3
AN4
53
PB2
33
32
PB1
34
PB0
AN5
PD1
51
52
50
PD3
AN6
PD2
For µPD78C10AGF-3BE, µPD78C11AGF-×××-3BE, µPD78C12AGF-×××-3BE
PA7
•
For µPD78C10ACW, µPD78C10AGQ-36, µPD78C11ACW-×××, µPD78C11AGQ-×××-36/37, µPD78C12ACW-×××,
µPD78C12AGQ-×××-36/37.
PA6
•
3
µPD78C10A,78C11A,78C12A
V DD
2
1
4
IC
PA0
3
PD2
PA1
4
PD3
PA2
5
PD4
PA3
6
PD5
PA4
7
PD6
PA5
8
PD7
PA6
9
STOP
IC
For µPD78C10AL, µPD78C11AL-×××, µPD78C12AL-×××
15
55
PF4
PB5
16
54
PF3
PB6
17
53
PF2
PB7
18
52
PF1
PC0/T X D
19
51
PF0
PC1/R X D
20
50
ALE
PC2/SCK
21
49
WR
PC3/INT2
22
48
RD
IC
23
47
AV DD
PC4/TO
24
46
IC
PC5/CI
25
45
V AREF
PC6/CO0
26
44
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
AN7
AN6
PF5
PB4
AN5
56
AN4
14
AN3
PF6
PB3
AN2
57
AN1
13
AN0
PF7
PB2
AV SS
58
V SS
12
X1
PD0
PB1
X2
59
MODE0
11
RESET
PD1
PB0
MODE1
68 67 66 65 64 63 62 61
60
INT1
10
NMI
PA7
PC7/C01
•
8
V
B
D
H
V'
B'
D'
H'
4
8
8
8
8
8
8
8
MAIN
G.R
16
8
8
TIMER
PC4/TO
DATA
MEMORY
(256-BYTE)
ALT
G.R
TIMER/
EVENT COUNTER
PC7-0*2
8/16
8
PB7-0*2
PA7-0*2
8
8
8
PC5/CI
PC6/CO0
PC7/CO1
PD7-0/
AD7-0
PROGRAM*1
MEMORY
A'
C'
E'
L'
BUFFER
PC3/INT2/TI
PF7-0/
AB15-8
12/
13
EA'
8
INT.
CONTROL
8
8
A
C
E
L
NMI
INT1
PORT F
SERIAL I/O
PORT D
PC0/TXD
PC1/RXD
PC2/SCK
8
PORT C
X2
PORT B
LATCH
INC/DEC
PC
SP
EA
PORT A
OSC
BLOCK DIAGRAM
8
16
X1
8
INTERNAL DATA BUS
16
16
LATCH
LATCH
8
6
8
PSW
INST.REG
AN7-0
16
A/D
CONVERTER
16
8
INST.
DECODER
ALU
(8/16)
16
READ/WRITE
CONTROL
*
SYSTEM
CONTROL
STAND BY
CONTROL
1. It depends on a product type.
The µPD78C11A has 4K bytes, and the µPD78C12A has 8K
bytes.
The µPD78C10A does not incorporate a program memory.
5
2. An on-chip pull-up resistor is available by mask option
(µPD78C11A, 78C12A only).
RD
WR
ALE MODE1 MODE0 RESET
STOP
VDD
VSS
µPD78C10A,78C11A,78C12A
VAREF
AVDD
AVSS
8
µPD78C10A,78C11A,78C12A
CONTENTS
1.
PIN FUNCTIONS .....................................................................................................................................
7
1.1
LIST OF PIN FUNCTION ................................................................................................................................
7
1.2
1.3
PIN INPUT/OUTPUT CIRCUITS ....................................................................................................................
PIN MASK OPTIONS ......................................................................................................................................
9
14
1.4
RECOMMENDED CONNECTION OF UNUSED PINS ..................................................................................
14
2.
DIFFERENCES BETWEEN µPD78C10A AND µPD78C11A, 78C12A ................................................... 15
3.
RESET OPERATIONS ............................................................................................................................. 17
4.
INSTRUCTION SET ................................................................................................................................. 20
4.1
IDENTIFIER/DESCRIPTION OF OPERAND ...................................................................................................
20
4.2
4.3
SYMBOL DESCRIPTION OF OPERATION CODE .........................................................................................
INSTRUCTION EXECUTION TIME ................................................................................................................
21
22
5.
LIST OF MODE REGISTERS .................................................................................................................. 34
6.
ELECTRICAL SPECIFICATIONS ............................................................................................................. 35
7.
CHARACTERISTIC CURVES (REFERENCE VALUES) ......................................................................... 47
8.
DIFFERENCES IN 87AD SERIES PRODUCTS ...................................................................................... 50
9.
PACKAGE INFORMATION ..................................................................................................................... 54
10. RECOMMENDED SOLDERING CONDITIONS...................................................................................... 60
APPENDIX DEVELOPMENT TOOLS ............................................................................................................ 62
6
µPD78C10A,78C11A,78C12A
1. PIN FUNCTIONS
1.1
LIST OF PIN FUNCTION (1/2)
Pin Name
I/O
Function
PA7 to PA0
(Port A)
Input/Output
8-bit input-output port, which can specify input/output bit-wise.
PB7 to PB0
(Port B)
Input/Output
8-bit input-output port, which can specify input/output bit-wise.
PC0/TXD
Input-output/
Output
Transmit Data
Output pin for serial data.
PC1/RxD
Input-output/
Input
Receive Data
Input pin for serial data.
PC2/SCK
Input-output/
Input-output
Serial Clock
Input-output pin for serial clock.
It becomes output clock for the internal
clock use, and input for the external.
PC3/INT2/TI
Input-output/
Input/Input
Interrupt Request/Timer Input
Maskable interrut input pin of the edge
trigger (falling edge), or an external clock
input pin for a timer. Also, it can be used
as a zero-cross detection pin for AC
input.
PC4/TO
Input-output/
Output
Timer Output
Square wave defining one cycle of internal
clock or timer counter time as half cycle
is output.
PC5/CI
Input-output/
Input
Counter Input
External pulse input pin to timer/event
counter.
PC6/CO0
PC7/CO1
Input-output/
Output
Counter Output 0, 1
Programmable rectangle wave output by
timer/event counter.
PD7 to PD0/
AD7 to AD0
Input-output/
Input-output
Port D
8-bit input-output port, which can specify
input-output in byte units (µPD78C11A).
Address/Data Bus
When external memory is used, it becomes multiplexed address/data bus.
PF7 to PF0/
AB15 to AB8
Input-output/
Output
Port F
8-bit input-output port, which can specify
input-output bit-wise.
Address Bus
When external memory is used, it becomes address bus.
WR
(Write Strobe)
Output
Strobe signal which is output for write operation of external memory. It becomes high in
any cycle other than the data write machine cycle of external memory. When RESET signal
is either low or in the hardware STOP mode, this signal becomes output high-impedance.
RD
(Read Strobe)
Output
Strobe signal which is output for read operation of external memory. It becomes high in any
cycle other than the read machine cycle of external memory. When RESET signal is either
low or in the hardware STOP mode, this signal becomes output high-impedance.
ALE
(Address Latch
Enable)
Output
Strobe signal to latch externally the lower address information which is output to PD7 to
PD0 pins to access external memory. When RESET signal is either low or in the hardware
STOP mode, this signal becomes output high-impedance.
Port C
8-bit input-output port,
which can specify input/ output bit-wise.
7
µPD78C10A,78C11A,78C12A
1.1
LIST OF PIN FUNCTION (2/2)
Pin Name
I/O
Function
µPD78C11A and 78C12A sets MODE0 pin to “0” (low level), and MODE1 pin to “1” (high
level*)
µPD78C10A allows you to set MODE0, MODE1 pins to select 4K, 16K, or 64K bytes for the
size of the memory which is installed externally.
MODE0
MODE1
(Mode)
Input-output
MODE0
MODE1
0
1
1
0
0
1
External Memory
4K bytes
16K bytes
64K bytes
Also, when each of MODE0 and MODE1 pins is set to “1”*, it is synchronized to ALE to output
a control signal.
★
NMI
(Non-Maskable
Interrupt)
Input
Non-maskable interrupt input pin of the edge trigger (falling edge)
INT1
(Interrupt
Request)
Input
A maskable interrupt input pin of the edge trigger (rising edge). Also, it can be used as a
zero-cross detection pin for AC input.
AN7 to AN0
(Analog Input)
Input
8 pins of analog input to A/D converter. AN7 to AN4 can be used as edge detection (falling
edge) input.
VAREF
(Reference
Voltage)
Input
A common pin serving both as a standard voltage input pin for A/D converter and as a
control pin for A/D converter operation.
AVDD
(Analog VDD)
Power supply pin for A/D converter.
AVSS
(Analog VSS)
GND pin for A/D converter.
X1, X2
(Crystal)
Crystal connection pins for system clock oscillation. X1 should be input when a clock is
supplied from outside. Input the clock of the reverse phase of X1 to X2.
RESET
(Reset)
Input
Low-level active system reset input.
STOP
(Stop)
Control signal input pin in hardware STOP mode. The oscillation stops when a clock is
supplied from outside.
VDD
Positive power supply pin.
VSS
GND pin.
* Pull-up. Pull-up resister R is 4 [kΩ] ≤ R ≤ 0.4 tCYC [kΩ] (tCYC is ns unit).
Remarks The µPD78C11A and µPD78C12A are pull-up resistor incorporation specifiable by mask option at ports
A, B and C.
8
µPD78C10A,78C11A,78C12A
1.2 PIN INPUT/OUTPUT CIRCUITS
Tables 1-1 and 1-2, and figures (1) to (15) show input- output circuits of each pin in a partially simplified form.
Table 1-1 Pin Type No. (µPD78C10A)
Pin Name
Type No.
Pin Name
Type No.
PA7 to PA0
5
RESET
2
PB7 to PB0
5
RD
4
PC1 to PC0
5
WR
4
PC2/SCK
8
ALE
4
PC3/INT2
10
STOP
2
PC7 to PC4
5
MODE0
11
PD7 to PD0
5
MODE1
11
PF7 to PF0
5
AN3 to AN0
7
NMI
5
AN7 to AN4
12
INT1
2
VAREF
13
Table 1-2 Pin Type No. (µPD78C11A and 78C12A)
Pin Name
Type No.
Pin Name
Type No.
PA7 to PA0
5-A
RESET
2
PB7 to PB0
5-A
RD
4
PC1 to PC0
5-A
WR
4
PC2/SCK
8-A
ALE
4
PC3/INT2
10-A
STOP
2
PC7 to PC4
5-A
MODE0
11
PD7 to PD0
5
MODE1
11
PF7 to PF0
5
AN3 to AN0
7
NMI
2
AN7 to AN4
12
INT1
9
VAREF
13
9
µPD78C10A,78C11A,78C12A
(1) Type 1
V DD
P- ch
IN
N- ch
(2) Type 2
IN
(3) Type 4
V DD
output data
P-ch
OUT
output disable
N-ch
(4) Type 4-A
V DD
output data
P-ch
OUT
output disable
10
N-ch
µPD78C10A,78C11A,78C12A
(5) Type 5
output data
IN/OUT
Type4
output disable
Type1
(6) Type 5-A
output data
IN/OUT
Type4-A
output disable
Type1
(7) Type 7
AV DD
P-ch
IN
+
N-ch
AV DD
Sampling
C
AV SS
AVSS
Reference Voltage
(From Voltage Tap of Series Resistance String)
(8) Type 8
output data
output disable
Type5
IN/OUT
Type2
MCC
11
µPD78C10A,78C11A,78C12A
(9) Type 8-A
output data
output disable
Type5-A
IN/OUT
Type2
MCC
(10) Type 9
self bias
enable
IN
Type1
data
(11) Type 10
output data
output disable
Type5
self bias
enable
Type9
MCC
12
IN/OUT
µPD78C10A,78C11A,78C12A
(12) Type 10-A
output data
output disable
Type5-A
self bias
enable
IN/OUT
Type9
MCC
(13) Type 11
IN/OUT
output data
N-ch
Type1
(14) Type 12
IN
Type7
Edge Detector
Type2
(15) Type 13
IN
Type1
STOP Mode
AV SS
13
µPD78C10A,78C11A,78C12A
1.3 PIN MASK OPTIONS
µPD78C11A and 78C12A has the following mask options, which can be selected bit-wise according to the
application.
Pin Name
Mask Options
PA7 to PA0
PB7 to PB0
PC7 to PC0
Cautions
➀ Pull-up resistor incorporated
➁ Pull-up resistor not incorporated
1. Zero-cross function can not be operated normally if pull-up resistor is incorporated
in PC3.
2. µPD78C10A has no mask option.
1.4
RECOMMENDED CONNECTION OF UNUSED PINS
Pin
Recommended Connection
PA7 to PA0
PB7 to PB0
PC7 to PC0
Connect to VSS or VDD via resistor
PD7 to PD0
PF7 to PF0
RD
WR
Leave open
ALE
STOP
INT1, NMI
AVDD
Connect to VDD
Connect to VSS or VDD
Connect to VDD
AVAREF
AVSS
AN7 to AN0
14
Connect to VSS
Connect to AVSS or AVDD
µPD78C10A,78C11A,78C12A
2. DIFFERENCES BETWEEN µPD78C10A AND µPD78C11A, 78C12A
The difference between the µPD78C10A and µPD78C11A, 78C12A is whether or not there is an on-chip mask
programmable ROM. The memory map differs accordingly as described below.
(1) µPD78C10A
Since the µPD78C10A does not have an on-chip ROM, all memory, except the on-chip RAM area (addresses FF00H
to FFFFH) can be installed outside. The size of this external memory can be selected from among 4K bytes (0000H
to 0FFFH), 16K bytes (0000H to 3FFFH), and 64K bytes (0000H to FEFFH) by MODE0 and MODE1 pin setting as shown
in the following table and Fig. 2-1.
Control Pin
Operation Mode
External Memory
On-Chip RAM
0
4K bytes (address 0000H to 0FFFH)
Address FF00H to FFFFH
0
1
16K bytes (address 0000H to 3FFFH)
Address FF00H to FFFFH
1
1
64K bytes (address 0000H to FEFFH)
Address FF00H to FFFFH
MODE1
MODE0
4K bytes access
0
16K bytes access
64K bytes access
External memory is accessed by using PD7 to PD0 (multiplexed address/data bus), PF7 to PF0 (address bus), and
the RD, WR, and ALE signals. When 4K-byte or 16K-byte external memory is accessed PF7 to PF0 not used as address
lines can be used as general purpose input/output ports.
The size of external memory can be specified by MODE0 and MODE1 pin setting. Preset each bit of MEMORY
MAPPING reisters MM2, MM1, and MM0 to "0".
(2) µPD78C11A and 78C12A
The µPD78C11A has an on-chip mask programmable ROM at addresses 0000H to 0FFFH and RAM at addresses
FF00H to FFFFH. Externally, memory can be extended up to 60K bytes (addresses 1000H to FEFFH) in steps. The
µPD78C12A has an on-chip mask programmable ROM at address 0000H to 1FFFH and RAM at address FF00H to
FFFFH. Externally, memory can be extended up to 56K bytes (address 2000H to FEFFH) in steps. The size of the
external extension memory can be selected from among no external memory, 256 bytes, 4K bytes, 16K bytes, and
56K/60K bytes* by MEMORY MAPPING register setting. External memory can be accessed by using PD7 to PD0
(multiplexed address/data bus), PF7 to PF0 (address bus), and the RD, WR, and ALE signals. Programs and data
can be stored in external memory. PF7 to PF0 become address lines corresponding to the size of external memory.
The remaining pins can be used as general purpose input/output ports.
*
PF7
PF6
PF5
PF4
PF3
PF2
PF1
PF0
External Memory
Port
Port
Port
Port
Port
Port
Port
Port
Maximam 256 bytes
Port
Port
Port
Port
AB11
AB10
AB9
AB8
Maximum 4K bytes
Port
Port
AB13
AB12
AB11
AB10
AB9
AB8
Maximum 16K bytes
AB15
AB14
AB13
AB12
AB11
AB10
AB9
AB8
Maximum 56K/60K bytes*
µPD78C11A: 60K bytes, µPD78C12A: 56K bytes
15
"#+,45=>FGOPABCJKL123:;<DEMN
µPD78C10A,78C11A,78C12A
Fig. 2-1 µPD78C10A Memory Map
4K Bytes Access
16K Bytes Access
64K Bytes Access
0000H
External
Memory
0FFFH
External
Memory
External
Memory
Not Used
3FFFH
Not Used
FF00H
On-Chip RAM
On-Chip RAM
On-Chip RAM
MODE0 = 0
MODE1 = 0
MODE0 = 1
MODE1 = 0
MODE0 = 1
MODE1 = 1
FFFFH
16
µPD78C10A,78C11A,78C12A
3. RESET OPERATIONS
When RESET Input becomes low, the system reset is activated to create the following status.
• INTERRUPT ENABLE F/F is reset and interrupt is disabled.
• All the interrupt mask registers are set (1) and interrupt is masked.
• An interrupt request flag is reset (0) and hold interrupt is eliminated.
• Each bit of PSW is reset (0).
• 0000H is loaded into the program counter (PC).
• The MODE A, MODE B, MODE C, and MODE F registers are set to FFH and the bits (MM0, 1, and 2) of the MODE
CONTROL C and MEMORY MAPPING registers are respectively reset (0), then all the
ports (A, B, C, D, and F) become input port (output high-impedance).
• All the test flags but SB flag are reset (0).
• A timer mode register is set to FFH, and TIMER F/F is reset.
• The mode register (ETMM, EOM) of a timer/event counter is reset (0).
• The serial mode high register(SMH) of serial interface is reset (0), while the serial mode low register (SML) is
set to 48H.
• The A/D channel mode register of the A/D converter is reset (0).
• WR, RD, ALE signals become high-impedance.
• The ZC1, ZC2 bits of the zero-cross mode register (ZCM) are set (1).
• The internal timing generator is initialized.
• Data memory and the following register contents are undefined:
Stack pointer (SP)
Expansion accumulator (EA, EA’), accumulator (A, A’)
General register (B, C, D, E, H, L, B’, C’, D’, E’, H’, L’)
Output latch of each port
TIMER REG0, 1 (TM0, TM1)
TIMER/EVENT COUNTER REG0, 1 (ETM0, ETM1)
RAE bit of MEMORY MAPPING register
SB flag of test flag
When RESET input becomes high, the reset status is released. Then, execution of the program is started from
0000H. The contents of various kinds of registers must be initialized or re-initialized in the program, if necessary.
Table 3-1 shows the state of each hardware after reset.
Table 3-2 shows the state of each pin after reset.
17
µPD78C10A,78C11A,78C12A
Table 3-1 State of Each Hardware after Reset
State after Reset
Hardware
Power-on reset
Internal data
memory
Reset input
during normal
operation
Previous contents held.
Writing
by CPU
Write address data
Undefined
Address data other than the aboove
Operation other than writing by CPU
Previous contents held.
Reset input in standby mode
Expansion accumulator (EA, EA')
Accumulator (A, A')
Undefined
General register (B, C, D, E, H, L, B', C', D', E', H', L')
Working register vector register (V, V')
Program counter (PC)
0000H
Stack pointer (SP)
Undefined
Port
Mode register (MA, MB, MC, MF)
FFH
MCC register
00H
MM register (bits MM0 to MM2)
0
Output latch of each port
Interrupt
INTERRUPT ENABLE F/F
0
Request flag
0
Mask register
FFH
Test flag (except SB flag)
Standby flag (SB)
Timer
Undefined
0
Power-on reset
1
Standby mode
Previous contents held.
Reset input during normal operation
Contents immediately before
RESET input held
Timer mode register (TMM)
FFH
Timer F/F
0
Timer register (TM0, TM1)
Undefined
Timer/event counter mode register (ETMM)
00H
Timer/event counter output mode register (EOM)
Timer/event counter Timer/event counter register (ETM0, ETM1)
Timer/event counter capture register (ECPT)
Undefined
Timer/event counter (ECNT)
Serial mode high register (SMH)
00H
Serial mode low register (SML)
48H
Serial interface
A/D channel mode register (ANM)
00H
MM register (MM3; RAE bit)
Undefined
Zero cross mode register (ZC1, ZC2 bits)
1
18
µPD78C10A,78C11A,78C12A
Table 3-2 State of Each Pin after Reset
Pin
State after Reset
WR
RD
High-impedance
ALE
All ports (PA, PB, PC, PD, PF)
19
µPD78C10A,78C11A,78C12A
4. INSTRUCTION SET
4.1
IDENTIFIER/DESCRIPTION OF OPERAND
Identifier
*
Description
r
r1
r2
V, A, B, C, D, E, H, L
EAH, EAL, B, C, D, E, H, L
A, B, C
sr
sr1
sr2
sr3
sr4
PA, PB, PC, PD, PF, MKH, MKL, ANM, SMH, SML, EOM, ETMM, TMM, MM, MCC, MA, MB, MC, MF,
TXB, TM0, TM1, ZCM
PA, PB, PC, PD, PF, MKH, MKL, ANM, SMH, EOM, TMM, RXB, CR0, CR1, CR2, CR3
PA, PB, PC, PD, PF, MKH, MKL, ANM, SMH, EOM, TMM
ETM0, ETM1
ECNT, ECPT
rp
rp1
rp2
rp3
SP, B, D, H
V, B, D, H, EA
SP, B, D, H, EA
B, D, H
rpa
rpa1
rpa2
rpa3
B, D, H, D+, H+, D–, H–
B, D, H
B, D, H, D+, H+, D–, H–, D+byte, H+A, H+B, H+EA, H+byte
D, H, D++, H++, D+byte, H+A, H+B, H+EA, H+byte
wa
8 bit immediate data
word
byte
bit
16 bit immediate data
8 bit immediate data
3 bit immediate data
f
CY, HC, Z
irf
NMI*, FT0, FT1, F1, F2, FE0, FE1, FEIN, FAD, FSR, FST, ER, OV, AN4, AN5, AN6, AN7, SB
NMI can also be described as FNMI.
Remarks
1. sr to sr4 (special register)
2. rp to rp3 (register pair)
SP
: STACK POINTER
CY
B
: BC
HC
: HALF CARRY
D
: DE
Z
: ZERO
COUNTER OUTPUT
H
: HL
MODE
V
: VA
EA
: EXTENDED
PA
: PORT A
PB
: PORT B
ETMM : TIMER/EVENT
PC
: PORT C
PD
: PORT D
PF
: PORT F
MA
: MODE A
ANM
: A/D CHANNEL MODE
MB
: MODE B
CR0
: A/D CONVERSION
MC
: MODE C
to
MCC
: MODE CONTROL C
CR3
COUNTER MODE
EOM
: TIMER/EVENT
3. rpa to rpa3 (rp addressing)
MF
: MODE F
TXB
: TX BUFFER
: MEMORY MAPPING
RXB
: RX BUFFER
TM0
: TIMER REG0
SMH
: SERIAL MODE High
TM1
: TIMER REG1
SML
: SERIAL MODE Low
TMM
: TIMER MODE
MKH
: MASK High
ETM0 : TIMER/EVENT
MKL
: MASK Low
ZCM
: ZERO CROSS MODE
ETM1 : TIMER/EVENT
COUNTER REG1
ECNT : TIMER/EVENT
COUNTER UPCOUNTER
ECPT
: TIMER/EVENT
COUNTER CAPTURE
20
ACCUMULATOR
RESULT 0 to 3
MM
COUNTER REG0
4. f (flag)
B
D
H
D+
H+
D–
H–
D++
H++
D + byte
H+A
H+B
H + EA
H + byte
:
:
:
:
:
:
:
:
:
:
:
:
:
:
(BC)
(DE)
(HL)
(DE)+
(HL)+
(DE)–
(HL)–
(DE)++
(HL)++
(DE + byte)
(HL + A)
(HL + B)
(HL + EA)
(HL + byte)
: CARRY
5. irf (interrupt flag)
NMI
: NMI INPUT
FT0
: INTFT0
FT1
: INTFT1
F1
: INTF1
F2
: INTF2
FE0
: INTFE0
FE1
: INTFE1
FEIN
: INTFEIN
FAD
: INTFAD
FSR
: INTFSR
FST
: INTFST
ER
: ERROR
OV
: OVERFLOW
AN4
: ANALOG INPUT 4 to 7
to
AN7
SB
: STANDBY
µPD78C10A,78C11A,78C12A
4.2
SYMBOL DESCRIPTION OF OPERATION CODE
r
rpa
r1
R2
R1
R0
reg
T2
T1
T0
reg
A3 A2 A1 A0
addressing
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
V
A
B
C
D
E
H
L
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
EAH
EAL
B
C
D
E
H
L
0
0
0
0
0
0
0
0
1
1
1
1
1
(BC)
(DE)
(HL)
rpa
(DE)+
(HL)+
(DE)(HL)(DE + byte)
(HL + A)
(HL + B)
(HL + EA)
(HL + byte)
r2
r
sr
S5 S4
S3
S2 S1 S0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
0
0
0
0
1
1
1
0
0
0
0
1
1
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
0
1
1
0
0
1
1
0
0
0
0
1
1
0
1
0
0
1
1
0
0
1
1
0
Special-reg
PA
PB
PC
PD
PF
MKH
MKL
ANM
SMH
SML
EOM
ETMM
TMM
MM
MCC
MA
MB
MC
MF
TXB
RXB
TM0
TM1
CR0
CR1
CR2
CR3
ZCM
0
1
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
sr3
sr1
special-reg
V0
0
1
ETM0
ETM1
0
1
0
0
1
1
0
0
1
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
0
1
0
1
rpa1
rpa2
rpa3
sr2
C3 C2 C1 C0
addressing
0
0
0
0
1
1
1
1
1
0
0
1
1
0
1
1
1
1
(DE)
(HL)
(DE)++
(HL)++
(DE + byte)
(HL + A)
(HL + B)
(HL + EA)
(HL + byte)
I4
I3
I2
I1
I0
INTF
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
0
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
0
1
0
NMI
FT0
FT1
F1
F2
FE0
FE1
FEIN
FAD
FSR
FST
ER
OV
AN4
AN5
AN6
AN7
SB
sr
1
1
0
0
1
0
0
1
1
0
1
0
1
1
0
1
0
1
irf
sr4
U0
0
0
0
0
1
1
1
1
0
1
1
1
1
special-reg
ECNT
ECPT
rp
rp1
f
P2
P1
P0
reg-pair
Q2
Q1
Q0
reg-pair
F2
F1
F0
flag
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
SP
BC
DE
HL
EA
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
VA
BC
DE
HL
EA
0
0
0
1
0
1
1
0
0
0
1
0
CY
HC
Z
rp
rp2
rp3
21
µPD78C10A,78C11A,78C12A
4.3 INSTRUCTION EXECUTION TIME
1 state shown here is composed of 3 clock cycles. When a clock cycle of 15 MHz is used, the execution time should
be 200 ns (= 3 × 1/15 µs). In this case, the 4-state instruction which is the minimum execution time should be execution
time of 0.8 µs.
22
Note 1
Mnemonic
B1
8-bit data transfer instructions
MOV
B2
State
B3
Operation
B4
r1, A
0 0 0 1 1 T2 T1 T0
4
r1 ← A
A, r1
0 0 0 0 1 T2 T1 T0
4
A ← r1
*
sr, A
0 1 0 0 1 1 0 1
1 1 S5 S4 S3 S2 S1 S0
10
sr ← A
*
A, sr1
0 1 0 0 1 1 0 0
1 1 S5 S4 S3 S2 S1 S0
10
A ← sr1
r, word
0 1 1 1 0 0 0 0
0 1 1 0 1 R2 R1 R0
Low Adrs
High Adrs
17
r ← (word)
word, r
0 1 1 1 0 0 0 0
0 1 1 1 1 R2 R1 R0
Low Adrs
High Adrs
17
(word) ← r
r, byte
0 1 1 0 1 R2 R1 R0
Data
sr2, byte
0 1 1 0 0 1 0 0
S3 0 0 0 0 S2 S1 S0
Data
14
sr2 ← byte
Data
13
(V. wa) ← byte
*
7
MVI
r ← byte
MVIW
*
wa, byte
0 1 1 1 0 0 0 1
Offset
MVIX
*
rpa1, byte
0 1 0 0 1 0 A1 A0
Data
10
(rpa1) ← byte
STAW
*
wa
0 1 1 0 0 0 1 1
Offset
10
(V. wa) ← A
LDAW
*
wa
0 0 0 0 0 0 0 1
Offset
10
A ← (V. wa)
STAX
*
rpa2
A3 0 1 1 1 A2 A1 A0
Data*1
7/13*3
(rpa2) ← A
LDAX
*
rpa2
A3 0 1 0 1 A2 A1 A0
Data*1
7/13*3
A ← (rpa2)
EXX
0 0 0 1 0 0 0 1
4
B ↔ B', C ↔ C', D ↔ D'
E ↔ E', H ↔ H', L ↔ L'
EXA
0 0 0 1 0 0 0 0
4
V, A ↔ V', A', EA ↔ EA'
EXH
0 1 0 1 0 0 0 0
4
H, L ↔ H', L'
BLOCK
0 0 1 1 0 0 0 1
13
(C + 1)
rp3, EA
1 0 1 1 0 1 P1 P0
4
rp3L ← EAL, rp3H ← EAH
EA, rp3
1 0 1 0 0 1 P1 P0
4
EAL ← rp3L, EAH ← rp3H
DMOV
Note
1. Instruction Group
23
2. 16-bit data transfer instructions
Skip
Condition
(DE) +← (HL) +, C ← C – 1
End if borrow
µPD78C10A,78C11A,78C12A
Note 2
Operation Code
Operand
Note 1
Operation Code
Operand
sr3, EA
State
B3
B2
0 1 0 0 1 0 0 0
1 1 0 1 0 0 1 U0
14
sr3 ← EA
1 1 0 0 0 0 0 V0
14
EA ← sr4
20
(word) ← C, (word + 1) ← B
EA, sr4
16-bit data transfer instructions
Operation
B1
B4
DMOV
Low Adrs
SBCD
word
SDED
word
0 0 1 0 1 1 1 0
20
(word) ← E, (word + 1) ← D
SHLD
word
0 0 1 1 1 1 1 0
20
(word) ← L, (word + 1) ← H
SSPD
word
0 0 0 0 1 1 1 0
20
(word) ← SPL, (word + 1) ← SPH
STEAX
rpa3
0 1 0 0 1 0 0 0
1 0 0 1 C3 C2 C1 C0
Data*2
*3
14/20
(rpa3) ← EAL, (rpa3 + 1) ← EAH
LBCD
word
0 1 1 1 0 0 0 0
0 0 0 1 1 1 1 1
Low Adrs
LDED
word
LHLD
0 1 1 1 0 0 0 0
0 0 0 1 1 1 1 0
High Adrs
C ← (word), B ← (word + 1)
0 0 1 0 1 1 1 1
20
E ← (word), D ← (word + 1)
word
0 0 1 1 1 1 1 1
20
L ← (word), H ← (word + 1)
LSPD
word
0 0 0 0 1 1 1 1
20
SPL ← (word), SPH ← (word + 1)
LDEAX
rpa3
0 1 0 0 1 0 0 0
*3
14/20
EAL ← (rpa3), EAH ← (rpa3 + 1)
PUSH
rp1
1 0 1 1 0 Q2 Q1 Q0
13
POP
rp1
1 0 1 0 0 Q2 Q1 Q0
10
rp2, word
0 P2 P1 P0 0 1 0 0
LXI
*
1 0 0 0 C3 C2 C1 C0
Low Byte
Data*2
High Byte
High Adrs
(SP – 1) ← rp1H, (SP – 2) ← rp1L
SP ← SP – 2
rp1L ← (SP), rp1H ← (SP + 1)
SP ← SP + 2
10
rp2 ← word
C ← (PC + 3 + A)
B ← (PC + 3 + A + 1)
0 1 0 0 1 0 0 0
1 0 1 0 1 0 0 0
17
0 1 1 0 0 0 0 0
1 1 0 0 0 R2 R1 R0
8
A←A+r
r, A
0 1 0 0
8
r←r+A
A, r
1 1 0 1
8
A ← A + r + CY
r, A
0 1 0 1
8
r ← r + A + CY
TABLE
A, r
ADD
ADC
Note
1. Instruction Group
2. 8-bit operation instructions (register)
Skip
Condition
µPD78C10A,78C11A,78C12A
20
Note 2
24
Mnemonic
Note
Mnemonic
Operation Code
Operand
State
B4
Skip
Condition
B2
0 1 1 0 0 0 0 0
1 0 1 0 0 R2 R1 R0
8
A←A+r
No Carry
r, A
0 0 1 0
8
r←r+A
No Carry
A, r
1 1 1 0
8
A ←A – r
r, A
0 1 1 0
8
r←r–A
A, r
1 1 1 1
8
A ← A – r – CY
r, A
0 1 1 1
8
r ← r – A – CY
A, r
1 0 1 1
8
A←A–r
r, A
0 0 1 1
8
r←r–A
A, r
1 0 0 0 1 R2 R1 R0
8
A←A∧r
r, A
0 0 0 0
8
r←r∧A
A, r
1 0 0 1
8
A←A∨r
r, A
0 0 0 1
8
r←r∨A
A, r
1 0 0 1 0 R2 R1 R0
8
A←A∨r
r, A
0 0 0 1
8
r←r∨A
A, r
1 0 1 0 1 R2 R1 R0
8
A–r–1
r, A
0 0 1 0
8
r–A–1
A, r
1 0 1 1
8
A–r
Borrow
r, A
0 0 1 1
8
r–A
Borrow
A, r
1 1 1 0
8
A–r
No Zero
r, A
0 1 1 0
8
r–A
No Zero
A, r
B3
Operation
B1
ADDNC
SUB
8-bit operation instructions (register)
SBB
SUBNB
ANA
ORA
XRA
No
Borrow
No
Borrow
LTA
NEA
Note
Instruction Group
25
µPD78C10A,78C11A,78C12A
GTA
No
Borrow
No
Borrow
8-bit operation
instructions (register) Note
Operation Code
Operand
State
B4
Skip
Condition
B2
0 1 1 0 0 0 0 0
1 1 1 1 1 R2 R1 R0
8
A–r
Zero
r, A
0 1 1 1
8
r–A
Zero
ONA
A, r
1 1 0 0
8
A∧r
No Zero
OFFA
A, r
1 1 0 1
8
A∧r
Zero
ADDX
rpa
1 1 0 0 0 A2 A1 A0
11
A ← A + (rpa)
ADCX
rpa
1 1 0 1
11
A ← A + (rpa) + CY
ADDNCX
rpa
1 0 1 0
11
A ← A + (rpa)
SUBX
rpa
1 1 1 0
11
A ← A – (rpa)
SBBX
rpa
1 1 1 1
11
A ← A – (rpa) – CY
SUBNBX
rpa
1 0 1 1
11
A ← A – (rpa)
ANAX
rpa
1 0 0 0 1 A2 A1 A0
11
A ← A ∧ (rpa)
ORAX
rpa
1 0 0 1
11
A ← A ∨ (rpa)
XRAX
rpa
1 0 0 1 0 A2 A1 A0
11
A ← A ∨ (rpa)
GTAX
rpa
1 0 1 0 1 A2 A1 A0
11
A – (rpa) – 1
No
Borrow
LTAX
rpa
1 0 1 1
11
A – (rpa)
Borrow
NEAX
rpa
1 1 1 0
11
A – (rpa)
No Zero
EQAX
rpa
1 1 1 1
11
A – (rpa)
Zero
ONAX
rpa
1 1 0 0
11
A ∧ (rpa)
No Zero
OFFAX
rpa
1 1 0 1
11
A ∧ (rpa)
Zero
A, r
B3
Operation
B1
EQA
Note
Instruction Group
0 1 1 1 0 0 0 0
No Carry
No
Borrow
µPD78C10A,78C11A,78C12A
8-bit operation instructions (memory)
26
Mnemonic
Note
Mnemonic
B1
*
ADI
*
ACI
Immediate data operation instructions
Operation Code
Operand
*
ADINC
*
SUI
*
SBI
SUINB
*
A, byte
0 1 0 0 0 1 1 0
Data
r, byte
0 1 1 1 0 1 0 0
0 1 0 0 0 R2 R1 R0
sr2, byte
0 1 1 0
A, byte
State
B3
7
r ← r + byte
S3 1 0 0 0 S2 S1 S0
20
sr2 ← sr2 + byte
0 1 0 1 0 1 1 0
Data
7
r, byte
0 1 1 1 0 1 0 0
0 1 0 1 0 R2 R1 R0
sr2, byte
0 1 1 0
A, byte
A ← A + byte + CY
11
r ← r + byte + CY
S3 1 0 1 0 S2 S1 S0
20
sr2 ← sr2 + byte + CY
0 0 1 0 0 1 1 0
Data
7
r, byte
0 1 1 1 0 1 0 0
0 0 1 0 0 R2 R1 R0
sr2, byte
0 1 1 0
A, byte
Data
Skip
Condition
A ← A + byte
11
Data
A ← A + byte
No Carry
11
r ← r + byte
No Carry
S3 0 1 0 0 S2 S1 S0
20
sr2 ← sr2 + byte
No Carry
0 1 1 0 0 1 1 0
Data
7
r, byte
0 1 1 1 0 1 0 0
0 1 1 0 0 R2 R1 R0
sr2, byte
0 1 1 0
A, byte
Data
A ← A – byte
11
r ← r – byte
S3 1 1 0 0 S2 S1 S0
20
sr2 ← sr2 – byte
0 1 1 1 0 1 1 0
Data
7
r, byte
0 1 1 1 0 1 0 0
0 1 1 1 0 R2 R1 R0
sr2, byte
0 1 1 0
A, byte
Data
A ← A – byte – CY
11
r ← r – byte – CY
S3 1 1 1 0 S2 S1 S0
20
sr2 ← sr2 – byte – CY
0 0 1 1 0 1 1 0
Data
7
r, byte
0 1 1 1 0 1 0 0
0 0 1 1 0 R2 R1 R0
sr2, byte
0 1 1 0
A, byte
r, byte
Data
Instruction Group
A ← A – byte
11
r ← r – byte
S3 0 1 1 0 S2 S1 S0
20
sr2 ← sr2 – byte
0 0 0 0 0 1 1 1
Data
7
0 1 1 1 0 1 0 0
0 0 0 0 1 R2 R1 R0
Data
ANI
Note
Operation
B4
Data
11
A ← A ∧ byte
r ← r ∧ byte
No
Borrow
No
Borrow
No
Borrow
27
µPD78C10A,78C11A,78C12A
*
B2
Note
ANI
*
ORI
*
XRI
Immediate data operation instructions
28
Mnemonic
*
GTI
*
LTI
*
*
EQI
Note
State
B1
B2
B3
sr2, byte
0 1 1 0 0 1 0 0
S3 0 0 0 1 S2 S1 S0
Data
A, byte
0 0 0 1 0 1 1 1
Data
r, byte
0 1 1 1 0 1 0 0
0 0 0 1 1 R2 R1 R0
sr2, byte
0 1 1 0
A, byte
Operation
B4
20
sr2 ← sr2 ∧ byte
7
A ← A ∨ byte
11
r ← r ∨ byte
S3 0 0 1 1 S2 S1 S0
20
sr2 ← sr2 ∨ byte
0 0 0 1 0 1 1 0
Data
7
r, byte
0 1 1 1 0 1 0 0
0 0 0 1 0 R2 R1 R0
sr2, byte
0 1 1 0
A, byte
Data
Skip
Condition
A ← A ∨ byte
11
r ← r ∨ byte
S3 0 0 1 0 S2 S1 S0
20
sr2 ← sr2 ∨ byte
0 0 1 0 0 1 1 1
Data
7
A – byte– 1
r, byte
0 1 1 1 0 1 0 0
0 0 1 0 1 R2 R1 R0
11
r – byte – 1
sr2, byte
0 1 1 0
S3 0 1 0 1 S2 S1 S0
14
sr2 – byte – 1
A, byte
0 0 1 1 0 1 1 1
Data
7
A – byte
Borrow
r, byte
0 1 1 1 0 1 0 0
0 0 1 1 1 R2 R1 R0
11
r – byte
Borrow
sr2, byte
0 1 1 0
S3 0 1 1 1 S2 S1 S0
14
sr2 – byte
Borrow
A, byte
0 1 1 0 0 1 1 1
Data
7
A – byte
No Zero
r, byte
0 1 1 1 0 1 0 0
0 1 1 0 1 R2 R1 R0
11
r – byte
No Zero
sr2, byte
0 1 1 0
S3 1 1 0 1 S2 S1 S0
14
sr2 – byte
No Zero
A, byte
0 1 1 1 0 1 1 1
Data
7
A – byte
Zero
r, byte
0 1 1 1 0 1 0 0
0 1 1 1 1 R2 R1 R0
11
r – byte
Zero
sr2, byte
0 1 1 0
S3 1 1 1 1 S2 S1 S0
14
sr2 – byte
Zero
Instruction Group
Data
Data
Data
Data
Data
No
Borrow
No
Borrow
No
Borrow
µPD78C10A,78C11A,78C12A
NEI
Operation Code
Operand
Note
Mnemonic
B1
Immediate data
operation instructions
B2
State
B3
Operation
B4
Skip
Condition
7
A ∧ byte
No Zero
11
r ∧ byte
No Zero
S3 1 0 0 1 S2 S1 S0
14
sr2 ∧ byte
No Zero
0 1 0 1 0 1 1 1
Data
7
A ∧ byte
Zero
r, byte
0 1 1 1 0 1 0 0
0 1 0 1 1 R2 R1 R0
11
r ∧ byte
Zero
sr2, byte
0 1 1 0
S3 1 0 1 1 S2 S1 S0
14
sr2 ∧ byte
Zero
ADDW
wa
0 1 1 1 0 1 0 0
1 1 0 0 0 0 0 0
14
A ← A +(V. wa)
ADCW
wa
1 1 0 1
14
A ← A + (V. wa) + CY
ADDNCW
wa
1 0 1 0
14
A ← A + (V. wa)
SUBW
wa
1 1 1 0
14
A ← A – (V. wa)
SBBW
wa
1 1 1 1
14
A ← A – (V. wa) – CY
SUBNBW
wa
1 0 1 1
14
A ← A – (V. wa)
ANAW
wa
1 0 0 0 1 0 0 0
14
A ← A ∧ (V. wa)
ORAW
wa
1 0 0 1
14
A ← A ∨ (V. wa)
XRAW
wa
1 0 0 1 0 0 0 0
14
A ← A ∨ (V. wa)
GTAW
wa
1 0 1 0 1 0 0 0
14
A – (V. wa) – 1
No
Borrow
LTAW
wa
1 0 1 1
14
A – (V. wa)
Borrow
NEAW
wa
1 1 1 0
14
A – (V. wa)
No Zero
EQAW
wa
1 1 1 1
14
A – (V. wa)
Zero
ONAW
wa
1 1 0 0
14
A ∧ (V. wa)
No Zero
*
ONI
*
OFFI
Note
A, byte
0 1 0 0 0 1 1 1
Data
r, byte
0 1 1 1 0 1 0 0
0 1 0 0 1 R2 R1 R0
sr2, byte
0 1 1 0
A, byte
Instruction Group
Data
Data
offset
No Carry
No
Borrow
29
µPD78C10A,78C11A,78C12A
Working register operation instructions
Operation Code
Operand
Note
Working register operation instructions
OFFAW
Operation Code
Operand
State
Operation
B1
B2
B3
B4
wa
0 1 1 1 0 1 0 0
1 1 0 1 1 0 0 0
Offset
14
A ∧ (V. wa)
Offset
Data
19
(V. wa) ← (V. wa) ∧ byte
Skip
Condition
Zero
ANIW
*
wa, byte
0 0 0 0 0 1 0 1
ORIW
*
wa, byte
0 0 0 1
19
(V. wa) ← (V. wa) ∨ byte
GTIW
*
wa, byte
0 0 1 0
13
(V. wa) – byte – 1
No
Borrow
LTIW
*
wa, byte
0 0 1 1
13
(V. wa) – byte
Borrow
NEIW
*
wa, byte
0 1 1 0
13
(V. wa) – byte
No Zero
EQIW
*
wa, byte
0 1 1 1
13
(V. wa) – byte
Zero
ONIW
*
wa, byte
0 1 0 0
13
(V. wa) ∧ byte
No Zero
OFFIW
wa, byte
0 1 0 1
13
(V. wa) ∧ byte
Zero
EADD
EA, r2
0 1 1 1 0 0 0 0
0 1 0 0 0 0 R1 R0
11
EA ← EA + r2
DADD
EA, rp3
0 1 0 0
1 1 0 0 0 1 P1 P0
11
EA ← EA + rp3
DADC
EA, rp3
1 1 0 1
11
EA ← EA + rp3 +CY
DADDNC
EA, rp3
1 0 1 0
11
EA ← EA + rp3
ESUB
EA, r2
0 0 0 0
0 1 1 0 0 0 R1 R0
11
EA ← EA – r2
DSUB
EA, rp3
0 1 0 0
1 1 1 0 0 1 P1 P0
11
EA ← EA – rp3
DSBB
EA, rp3
1 1 1 1
11
EA ← EA – rp3 – CY
DSUBNB
EA, rp3
1 0 1 1
11
EA ← EA – rp3
DAN
EA, rp3
1 0 0 0 1 1 P1 P0
11
EA ← EA ∧ rp3
DOR
EA, rp3
1 0 0 1
11
EA ← EA ∨ rp3
DXR
EA, rp3
1 0 0 1 0 1 P1 P0
11
EA ← EA ∨ rp3
Note
Instruction Group
No Carry
No
Borrow
µPD78C10A,78C11A,78C12A
16-bit operation instructions
30
Mnemonic
State
B3
Operation
B4
Skip
Condition
B1
B2
0 1 1 1 0 1 0 0
1 0 1 0 1 1 P1 P0
11
EA – rp3 – 1
No
Borrow
EA, rp3
DLT
EA, rp3
1 0 1 1
11
EA – rp3
Borrow
DNE
EA, rp3
1 1 1 0
11
EA – rp3
No Zero
DEQ
EA, rp3
1 1 1 1
11
EA – rp3
Zero
DON
EA, rp3
1 1 0 0
11
EA ∧ rp3
No Zero
DOFF
EA, rp3
1 1 0 1
11
EA ∧ rp3
Zero
MUL
r2
0 0 1 0 1 1 R1 R0
32
EA ← A × r2
DIV
r2
0 0 1 1
59
EA ← EA ÷ r2, r2 ← Remainder
INR
r2
0 1 0 0 0 0 R1 R0
4
r2 ← r2 + 1
Carry
wa
0 0 1 0 0 0 0 0
16
(V. wa) ← (V. wa) + 1
Carry
rp
0 0 P1 P0 0 0 1 0
7
rp ← rp + 1
EA
1 0 1 0 1 0 0 0
7
EA ← EA + 1
r2
0 1 0 1 0 0 R1 R0
4
r2 ← r2 – 1
Borrow
wa
0 0 1 1 0 0 0 0
16
(V. wa) ← (V. wa) – 1
Borrow
rp
0 0 P1 P0 0 0 1 1
7
rp ← rp – 1
EA
1 0 1 0 1 0 0 1
7
EA ← EA – 1
DAA
0 1 1 0 0 0 0 1
4
Decimal Adjust Accumulator
STC
0 1 0 0 1 0 0 0
0 0 1 0 1 0 1 1
8
CY ← 1
CLC
0 0 1 0 1 0 1 0
8
CY ← 0
NEGA
0 0 1 1 1 0 1 0
8
A←A+1
Note 3
Increment/decrement instructions
DGT
INRW
*
0 1 0 0 1 0 0 0
Offset
INX
DCR
DCRW
*
Offset
DCX
Note
1. Instruction Group
2. Multiplication/division instructions
31
3. Other operation instructions
µPD78C10A,78C11A,78C12A
16-bit operation instructions
Note 1
Operation Code
Operand
Note 2
Mnemonic
Note
Operation Code
Operand
RLD
Rotation/shift instructions
B3
Operation
B2
B4
0 1 0 0 1 0 0 0
0 0 1 1 1 0 0 0
17
Rotate Left Digit
1 0 0 1
17
Rotate Right Digit
Skip
Condition
r2
0 1 R1 R0
8
r2m + 1 ← r2m, r20 ← CY, CY ← r27
RLR
r2
0 0 R1 R0
8
r2m – 1 ← r2m, r27 ← CY, CY ← r20
SLL
r2
0 0 1 0 0 1 R1 R0
8
r2m + 1 ← r2m, r20 ← 0, CY ← r27
SLR
r2
0 0 R1 R0
8
r2m – 1 ← r2m, r27 ← 0, CY ← r20
SLLC
r2
0 0 0 0 0 1 R1 R0
8
r2m + 1 ← r2m, r20 ← 0, CY ← r27
Carry
SLRC
r2
0 0 R1 R0
8
r2m – 1 ← r2m, r27 ← 0, CY ← r20
Carry
DRLL
EA
1 0 1 1 0 1 0 0
8
EAn + 1 ← EAn, EA0 ← CY, CY ← EA15
DRLR
EA
0 0 0 0
8
EAn – 1 ← EAn, EA15 ← CY, CY ← EA0
DSLL
EA
1 0 1 0 0 1 0 0
8
EAn + 1 ← EAn, EA0 ← 0, CY ← EA15
DSLR
EA
0 0 0 0
8
EAn – 1 ← EAn, EA15 ← 0, CY ← EA0
10
PC ← word
4
PCH ← B, PCL ← C
10
PC ← PC + 1 + jdisp 1
10
PC ← PC + 2 + jdisp
8
PC ← EA
*
word
JB
*
1 1
word
0 1 0 0 1 1 1
0 1 0 0 1 0 0 0
*
word
Note
0 1 0 0 0 0 0 0
0 1 0 0 1 0 0 0
CALB
CALF
High Adrs
jdisp 1
word
JEA
CALL
Low Adrs
0 0 1 0 0 0 0 1
JR
JRE
0 1 0 1 0 1 0 0
*
word
Instruction Group
0 1 1 1 1
jdisp
0 0 1 0 1 0 0 0
Low Adrs
0 0 1 0 1 0 0 1
fa
High Adrs
16
17
13
(SP – 1) ← (PC + 3)H, (SP – 2) ← (PC + 3)L
PC ← word, SP ← SP – 2
(SP – 1) ← (PC + 2)H, (SP – 2) ← (PC + 2)L
PCH ← B, PCL ← C, SP ← SP – 2
(SP – 1) ← (PC + 2)H, (SP – 2) ← (PC + 2)L
PC15 – 11 ← 00001, PC10 – 0 ← fa, SP ← SP – 2
µPD78C10A,78C11A,78C12A
RLL
JMP
Jump instructions
State
B1
RRD
Call Instructions
32
Mnemonic
Note 1
Note 2
Return
instructions
Mnemonic
B1
word
CALT
Skip instructions
1 0 0
B2
State
B3
ta
16
0 1 1 1 0 0 1 0
16
RET
1 0 1 1 1 0 0 0
10
1 0 0 1
10
0 1 1 0 0 0 1 0
13
RETS
RETI
*
Operation
B4
SOFTI
Skip
Condition
(SP – 1) ← (PC + 1)H, (SP – 2) ← (PC + 1)L
PCL ← (128 + 2ta), PCH ← (129 + 2ta), SP ← SP – 2
(SP – 1) ←PSW, (SP – 2) ← (PC + 1)H, (SP – 3)
← (PC + 1)L, PC ← 0060H, SP ← SP – 3
PCL ← (SP), PCH ← (SP + 1)
SP ←SP + 2
PCL ← (SP), PCH ← (SP + 1), SP ← SP +2
PC ← PC + n
PCL ← (SP), PCH ← (SP + 1)
PSW ← (SP + 2), SP ← SP + 3
Unconditional skip
bit, wa
0 1 0 1 1 B2 B1 B0
Offset
10
Skip if (V. wa) bit = 1
(V. wa)bit
=1
SK
f
0 1 0 0 1 0 0 0
0 0 0 0 1 F2 F1 F0
8
Skip if f = 1
f=1
SKN
f
0 0 0 1
8
Skip if f = 0
f=0
SKIT
irf
0 1 0 I4 I3 I2 I1 I0
8
Skip if irf = 1, then reset irf
irf = 1
SKNIT
irf
0 1 1 I4 I3 I2 I1 I0
8
Skip if irf = 0
Reset irf, if irf = 1
irf = 0
BIT
NOP
0 0 0 0 0 0 0 0
4
No Operation
EI
1 0 1 0 1 0 1 0
4
Enable Interrupt
DI
1 0 1 1 1 0 1 0
4
Disable Interrupt
HLT
0 1 0 0 1 0 0 0
0 0 1 1 1 0 1 1
12
Set Halt Mode
STOP
0 1 0 0 1 0 0 0
1 0 1 1 1 0 1 1
12
Set Stop Mode
* 1. Data is B2 if rpa2 = D + byte, H + byte.
2. Data is B3 if rpa3 = D + byte, H + byte.
3. In the State item, a figure is in the right side of slash if rpa2 and rpa3 are D + byte, H + A, H + B, H + EA, H + byte.
Remarks
The idle state when each instruction is skipped is different from the execution state as shown below.
1-byte instruction
: 4 states
3-byte instruction (with *) : 10 states
2-byte instruction (with *) :
2-byte instruction
:
Note
1.
2.
Instruction Group
Call instructions
7 states
8 states
3-byte instruction
4-byte instruction
:
:
11 states
14 states
33
µPD78C10A,78C11A,78C12A
CPU control instructions
Operation Code
Operand
µPD78C10A,78C11A,78C12A
5. LIST OF MODE REGISTERS
Name of Mode Registers
Read/
Write
Function
MA
MODE A register
W
Specifies bit-wise the input/output of the port A.
MB
MODE B register
W
Specifies bit-wise the input/output of the port B.
MCC
MODE CONTROL
C register
W
Specifies bit-wise the port/control mode of the port C.
MC
MODE C register
W
Specifies bit-wise the input/output of the port C which is in port mode.
MM
MEMORY MAPPING
register
W
Specifies the port/extension mode of port D and port F.
MF
MODE F register
W
Specifies bit-wise the input/output of the port F which is in port mode.
TMM
Timer mode register
R/W
ETMM
Timer/event counter
mode register
W
EOM
Timer/event counter
output mode register
R/W
SML
Specifies operating mode of timer.
Specifies the operating mode of timer/event counter.
Control the output level of CO0 and CO1.
W
Serial mode register
SMH
Specifies the operating mode of serial interface.
R/W
MKL
Interrupt mask register
R/W
Specifies the enable/disable of the interrupt request.
ANM
A/D channel mode
register
R/W
Specifies the operating mode of A/D converter.
ZCM
Zero-cross mode
register
MKH
34
W
Specifies the operation of zero-cross detector circuit.
µPD78C10A,78C11A,78C12A
6. ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C)
PARAMETER
SYMBOL
TEST CONDITIONS
–0.5 to +7.0
VDD
Power supply voltage
RATING
AVDD
AVSS to VDD +0.5
UNIT
V
V
AVSS
–0.5 to +0.5
V
Input voltage
VI
–0.5 to VDD +0.5
V
Output voltage
VO
–0.5 to VDD +0.5
V
All output pins
4.0
mA
Output current low
IOL
Total of all output pins
100
mA
All output pins
–2.0
mA
Total of all output pins
–50
mA
VAREF
–0.5 to AVDD +0.3
V
Operating ambient
temperature
TA
–40 to +85
°C
Storage temperature
Tstg
–65 to +150
°C
Output current high
A/D converter reference
input voltage
Caution
IOH
Even if one of the parameters exceeds its absolute maximum rating even momentarily, the quality of
the product may be degraded. The absolute maximum rating therefore specifies the upper or lower limit
of the value at which the product can be used without physical damages. Be sure not to exceed or fall
below this value when using the product.
35
★
µPD78C10A,78C11A,78C12A
(TA = –40 to +85 °C, VDD = AVDD = +5.0 V ±10 %, VSS = AVSS = 0 V,
VDD –0.8 V ≤ AVDD ≤ VDD, 3.4 V ≤ VAREF ≤ AVDD)
OSCILLATOR CHARACTERISTICS
RESONATOR
RECOMMENDED CIRCUIT
X1
Ceramic*1
or
crystal
resonator*2
PARAMETER
TEST CONDITIONS
MHz
5.8
15
MHz
4
15
MHz
5.8
15
MHz
X1 rise time,
fall time (tr, tf)
0
20
ns
X1 input high, low
level width (t∅H, t∅L)
20
250
ns
Oscillator frequency (fXX)
C1
C2
X1
X2
X1 input frequency (fX)
A/D converter used
External
clock
HCMOS
Inverter
Cautions 1. Place oscillator circuit as close as possible to X1, X2 pins.
2. Ensure that no other signal lines pass through the shadow area.
1. The ceramic oscillators and external capacitance given in the following
table are recommended.
RECOMMENDED CONSTANTS
MAKER
PRODUCT NAME
CSA7.37MT
CST7.37MTW
Murata Mfg. Co., Ltd
CSA12.0MT
CST12.0MTW
CSA15.00MX001
C1[pF]
C2[pF]
30
30
On-chip
On-chip
30
30
On-chip
On-chip
15
15
On-chip
On-chip
FCR8.0MC
TDK Corp.
FCR10.0MC
FCR12.0OMC
FCR15.0MC
2. When a crystal oscillator is used, the following external capacitance is
recommended.
C1 = C2 = 10 pF
36
UNIT
15
A/D converter not
used
*
MAX.
4
A/D converter not
used
X2
A/D converter used
*
MIN.
µPD78C10A,78C11A,78C12A
CAPACITANCE (TA = 25 °C, VDD = VSS = 0 V)
PARAMETER
Input capacitance
SYMBOL
TEST CONDITIONS
CI
MIN.
TYP.
MAX.
UNIT
10
pF
20
pF
20
pF
fC = 1 MHz
Output capacitance
CO
Unmeasured pins returned to 0 V
Input-output capacitance
CIO
37
µPD78C10A,78C11A,78C12A
DC CHARACTERISTICS (TA = –40 to +85 °C, VDD = AVDD = +5.0 V ±10 %, VSS = AVSS = 0 V)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
VIL1
All except RESET, STOP, NMI,
SCK, INT1, TI, AN4 to AN7
0
0.8
V
VIL2
RESET, STOP, NMI, SCK, INT1,
TI, AN4 to AN7
0
0.2 VDD
V
V1IH
All except RESET, STOP, NMI,
SCK, INT1, TI, AN4 to AN7, X1, X2
2.2
VDD
V
VIH2
RESET, STOP, NMI, SCK, INT1,
TI, AN4 to AN7, X1, X2
VDD
V
VOL
IOL = 2.0 mA
0.45
V
Input voltage low
Input voltage
high
Output voltage low
Output voltage
high
0.8 VDD
IOH = –1.0 mA
VDD
–1.0
V
IOH = –100 µA
VDD
–0.5
V
VOH
Input current
II
INT1*1, TI(PC3)*2 ; 0 V ≤ VI ≤ VDD
±200
µA
Input leakage
current
ILI
All except INT1, TI (PC3),
0 V ≤ VI ≤ VDD
±10
µA
Output leakage
current
ILO
0 V ≤ VO ≤ VDD
±10
µA
AIDD1
Operating mode fXX = 15 MHz
0.5
1.3
mA
AIDD2
STOP mode
10
20
µA
IDD1
Operating mode fXX = 15 MHz
13
25
mA
IDD2
HALT mode fXX = 15 MHz
7
13
mA
Data retention
voltage
VDDDR
Hardware/software STOP mode
Data retention
current
IDDDR
AVDD power
supply current
VDD power
supply current
Pull-up resistor*4
Caution
*
RL
V
Hardware/software*3
VDDDR = 2.5 V
1
15
µA
STOP mode
VDDDR = 5 V ±10%
10
50
µA
Ports A, B and C
3.5 V ≤ VDD ≤ 5.5 V,
VI = 0 V
27
75
kΩ
17
For a detailed description of the hardware STOP mode, refer to the 87AD Series mPD78C18 User's
Manual.
1. If self-bias should be generated by ZCM register.
2. If the control mode is set by MCC register, and self-bias should be generated by ZCM register.
3. If self-bias is not generated.
4. µPD78C11A and 78C12A only.
38
2.5
µPD78C10A,78C11A,78C12A
AC CHARACTERISTICS (TA = –40 to +85 °C, VDD = AVDD = +5.0 V ±10 %, VSS = AVSS = 0 V)
Read/write Operation:
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
MAX.
UNIT
250
ns
X1 input cycle time
tCYC
66
Address setup time (to ALE ↓ )
tAL
30
ns
Address hold time (from ALE ↓ )
tLA
35
ns
RD ↓ delay time from address
tAR
100
ns
Address float time from RD ↓
tAFR
Data input time from address
tAD
Data input time from ALE ↓
tLDR
fXX = 15 MHz, CL = 100 pF
CL = 100 pF
20
ns
250
ns
135
ns
120
ns
fXX = 15 MHz, CL = 100 pF
Data input time from RD ↓
tRD
RD ↓ delay time from ALE ↓
tLR
Data hold time (from RD ↑ )
tRDH
ALE ↑ delay time from RD ↑
tRL
RD low level width
15
ns
CL = 100 pF
0
ns
fXX = 15 MHz, CL = 100 pF
80
ns
In Data Read
fXX = 15 MHz, CL = 100 pF
215
ns
In OP Code Fetch
fXX = 15 MHz, CL = 100 pF
415
ns
fXX = 15 MHz, CL = 100 pF
90
ns
30
ns
35
ns
tRR
ALE high level width
tLL
M1 setup time (to ALE ↓ )
tML
M1 hold time (from ALE ↓ )
tLM
fXX = 15 MHz
IO/M setup time (to ALE ↓ )
tIL
30
ns
IO/M hold time (from ALE ↓ )
tLI
35
ns
WR ↓ delay time from address
tAW
100
ns
fXX = 15 MHz, CL = 100 pF
Data output time from ALE ↓
tLDW
Data output time from WR ↓
tWD
WR ↓ delay time from ALE ↓
tLW
15
ns
Data setup time (to WR ↑ )
tDW
165
ns
Data hold time (from WR ↑ )
tWDH
60
ns
ALE ↑ delay time from WR ↑
tWL
80
ns
WR low level width
tWW
215
ns
CL = 100 pF
fXX = 15 MHz, CL = 100 pF
180
ns
100
ns
39
µPD78C10A,78C11A,78C12A
Serial Operation :
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
MAX.
UNIT
*1
800
ns
*2
400
ns
1.6
µs
*1
335
ns
*2
160
ns
700
ns
*1
335
ns
*2
160
ns
SCK output
700
ns
SCK input
SCK cycle time
tCYK
SCK output
SCK input
SCK low level width
tKKL
SCK output
SCK input
SCK high level width
tKKH
RXD setup time (to SCK ↑ )
tRXK
*1
80
ns
RXD hold time (from SCK ↑ )
tKRX
*1
80
ns
TXD delay time from SCK ↓
tKTX
*1
210
ns
MIN.
MAX.
UNIT
1
1.8
VACP-P
±135
mV
0.05
1
kHz
MIN.
MAX.
UNIT
1. If clock rate is × 1 in asynchronous mode, synchronous mode, or I/O interface mode.
*
2. If clock rate is × 16 or × 64 in asynchronous mode.
Remarks The numeric values in the table are those when fXX = 15 MHz, CL = 100 pF.
Zero-Cross Characteristics :
PARAMETER
SYMBOL
Zero-cross detection input
VZX
Zero-cross accuracy
AZX
Zero-cross detection input
frequency
fZX
TEST CONDITIONS
AC combination
60 Hz sine wave
Other Operation :
PARAMETER
TI high, low level width
SYMBOL
TEST CONDITIONS
tTIH, tTIL
6
tCYC
tCI1H, tCI1L
Event count mode
6
tCYC
tCI2H,tCI2L
Pulse width test mode
48
tCYC
CI high, low level width
NMI high, low level width
tNIH, tNIL
10
µs
INT1 high, low level width
tI1H, tI1L
36
tCYC
INT2 high, low level width
tI2H, tI2L
36
tCYC
AN4 to AN7, low level width
tANH, tANL
36
tCYC
RESET high, low level width
tRSH, tRSL
10
µs
40
µPD78C10A,78C11A,78C12A
A/D CONVERTER CHARACTERISTICS (TA = –40 to +85 °C, VDD = +5.0 V ±10 %, VSS = AVSS = 0 V,
VDD –0.5 V ≤ AVDD ≤ VDD, 3.4 V ≤ VAREF ≤ AVDD)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
Resolution
Sampling time
tCONV
tSAMP
Analog input voltage
VIAN
Analog input
impedance
RAN
Reference voltage
MAX.
8
Absolute accuracy*
Conversion time
TYP.
UNIT
Bits
3.4 V ≤ VAREF ≤ AVDD, 66 ns ≤ tCYC ≤ 170 ns
±0.8%
FSR
4.0 V ≤ VAREF ≤ AVDD, 66 ns ≤ tCYC ≤ 170 ns
±0.6%
FSR
TA = –10 to +70 °C,
4.0 V ≤ VAREF ≤ AVDD, 66 ns ≤ tCYC ≤ 170 ns
±0.4%
FSR
66 ns ≤ tCYC ≤ 110 ns
576
tCYC
110 ns ≤ tCYC ≤ 170 ns
432
tCYC
66 ns ≤ tCYC ≤ 110 ns
96
tCYC
110 ns ≤ tCYC ≤ 170 ns
72
tCYC
AN0 to AN7 (including unused pins)
–0.3
VAREF +0.3
50
VAREF
3.4
V
★
MΩ
AVDD
V
IAREF1
Operating mode
1.5
3.0
mA
IAREF2
STOP mode
0.7
1.5
mA
AIDD1
Operating mode fXX = 15 MHz
0.5
1.3
mA
AIDD2
STOP mode
10
20
µA
VAREF current
AVDD power supply
current
*
Quantization error (±1/2 LSB) is not included.
AC Timing Test Point
VDD – 1.0 V
0.45 V
2.2 V
0.8 V
Test Points
2.2 V
0.8 V
41
µPD78C10A,78C11A,78C12A
tCYC-Dependent AC Characteristics Expression
PARAMETER
EXPRESSION
MIN./MAX.
UNIT
tAL
2T – 100
MIN.
ns
tLA
T – 30
MIN.
ns
tAR
3T – 100
MIN.
ns
tAD
7T – 220
MAX.
ns
tLDR
5T – 200
MAX.
ns
tRD
4T – 150
MAX.
ns
tLR
T – 50
MIN.
ns
tRL
2T – 50
MIN.
ns
MIN.
ns
4T – 50 (In data read)
tRR
7T – 50 (In OP code fetch)
tLL
2T – 40
MIN.
ns
tML
2T – 100
MIN.
ns
tLM
T – 30
MIN.
ns
tIL
2T – 100
MIN.
ns
tLI
T – 30
MIN.
ns
tAW
3T – 100
MIN.
ns
tLDW
T + 110
MAX.
ns
tLW
T – 50
MIN.
ns
tDW
4T – 100
MIN.
ns
tWDH
2T – 70
MIN.
ns
tWL
2T – 50
MIN.
ns
tWW
4T – 50
MIN.
ns
MIN.
ns
MIN.
ns
MIN.
ns
12T (SCK input)*1/6T (SCK input)*2
tCYK
24T (SCK output)
5T + 5 (SCK input)*1/2.5T + 5 (SCK input)*2
tKKL
12T – 100 (SCK output)
5T + 5 (SCK input)*1/2.5T + 5 (SCK input)*2
tKKH
12T – 100 (SCK output)
*
1. If clock rate is ×1, in asynchronous mode, synchronous mode, or I/O interface mode.
2. If clock rate is 16 × 64, in asynchronous mode.
Cautions 1. T = tCYC = 1/fXX
2. Other items which are not listed in this table are not dependent on oscillator frequency (fXX).
42
µPD78C10A,78C11A,78C12A
Timing Waveform
Read operation
tCYC
X1
Address (Upper)
PF7 - 0
tAD
PD7 - 0
Address (Lower)
tLL
Read Data
tLDR
tLA
tRDH
tRL
tAFR
ALE
tAL
tRD
tRR
RD
tLR
tAR
MODE1
(M1)*1
tML
tLM
tIL
tLI
MODE0
(IO/M)*2
*
1. When MODE1 pin is pulled up, M1 signal is output to MODE1 pin in the 1st OP code fetch cycle.
2. When MODE0 pin is pulled up, IO/M signal is output to MODE0 pin in sr to sr2 register read cycle.
Write operation
X1
PF7 - 0
Address (Upper)
tLDW
PD7 - 0
Write Data
Address (Lower)
tLL
tDW
tLA
tWDH
tWD
ALE
tWW
tAL
tWL
WR
tLW
tAW
tIL
tLI
MODE0
(IO/M)*3
*
3. When MODE0 pin is pulled up, IO/M signal is output to MODE0 pin in sr to sr2 register write cycle.
43
µPD78C10A,78C11A,78C12A
Serial Operation
tCYK
tKKL
tKKH
SCK
tKTX
TXD
R XD
tRXK
tKRX
Timer Input Timing
tTIH
tTIL
tCI1H
tCI1L
tCI2H
tCI2L
TI
Timer/Event Counter Input Timing
Event Counter Mode
CI
Pulse Width Test Mode
CI
44
µPD78C10A,78C11A,78C12A
Interrupt Input Timing
tNIH
tNIL
tI1L
tI1H
tI2H
tI2L
tRSH
tRSL
NMI
INT1
INT2
Reset Input Timing
RESET
0.8 VDD
0.2 VDD
External Clock Timing
tΦ H
0.8 VDD
X1
0.8 V
tr
tf
tΦ H
tCYC
45
µPD78C10A,78C11A,78C12A
DATA MEMORY STOP MODE LOW POWER SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS
(TA = –40 to +85 °C)
PARAMETER
★
SYMBOL
Data retention power
supply voltage
VDDDR
Data retention power
supply current
IDDDR
TEST CONDITIONS
MIN.
TYP.
2.5
MAX.
UNIT
5.5
V
VDDDR = 2.5 V
1
15
µA
VDDDR = 5 V ±10%
10
50
µA
VDD rise/fall time
tRVD, tFVD
200
µs
STOP setup time
(to VDD)
tSSTVD
12T +0.5
µs
STOP hold time
(from VDD)
tHVDST
12T +0.5
µs
Data Retention Timing
90 %
VDD
10 %
tFVD
tSSTVD
STOP
VDDDR
tRVD
tHVDST
VIH2
VIL2
46
µPD78C10A,78C11A,78C12A
7. CHARACTERISTIC CURVES (REFERENCE VALUES)
IDD1, IDD2 vs VDD
(TA = 25 ˚C, fXX = 15 MHz)
20
VDD Power Supply Current IDD1, IDD2 [mA]
IDD1 (TYP.)
15
10
IDD2 (TYP.)
5
0
4.5
5.0
5.5
6
Power Supply Voltage VDD [V]
IDD1, IDD2 vs fXX
(TA = 25 ˚C, VDD = 5 V)
VDD Power Supply Current IDD1, IDD2 [mA]
30
20
IDD1 (TYP.)
10
IDD2 (TYP.)
0
5
10
15
Oscillator Frequency fXX [MHz]
47
µPD78C10A,78C11A,78C12A
IOL vs VOL
(TA = 25 ˚C, VDD = 5 V)
2.5
TYP.
Output Current Low IOL [mA]
2.0
1.5
1.0
0.5
0
0.1
0.2
0.3
0.4
0.5
Output Voltage Low VOL [V]
IOH vs VOH
(TA = 25 ˚C, VDD = 5 V)
–1.5
Output Current High IOH [mA]
TYP.
–1.0
–0.5
0
0.1
0.2
0.3
0.4
Power Supply Voltage – Output Voltage High VDD – VOH [V]
48
0.5
µPD78C10A,78C11A,78C12A
IDDDR vs VDDDR
(TA = 25 ˚C)
Data Retention Power Supply Current IDDDR [µ A]
10
8
6
TYP.
4
2
0
2
3
4
5
6
Data Retention Power Supply Voltage VDDDR [V]
49
µPD78C10A,78C11A,78C12A
8. DIFFERENCES IN 87AD SERIES PRODUCTS (1/2)
Product Name
Item
Number of instructions
On-chip ROM
µPD7810H, 7811H
µPD7810, 7811*1
159 kinds (STOP instruction
added)
158 kinds
ROM less (µPD7810)
4K × 8 bits (µPD7811)
µPD78C10, 78C11*1
ROM less (µPD7810H)
4K × 8 bits (µPD7811H)
ROM less (µPD78C10)
4K × 8 bits (µPD78C11)
256 × 8 bits
On-chip RAM
27
Nnmber of special registers
28 (ZCM register added)
Operating frequency
10 to 12 MHz
4 to 10 MHz
4 to 15 MHz
4 to 15 MHz*2
Power supply voltage
5 V ±5 %
5 V ±10 %
5 V ±10 %
5 V ±10 %
–10 to +70 °C
–40 to +85 °C
Operating temperature range
Standby function
–10 to +70 °C –40 to +85 °C
Thirty-two bytes of the on-chip RAM 256 bytes of data
are held by low power supply voltage (3.2 V)
Number of HALT instruction state
HALT
mode
CPU operation
11
12
M3 T2 cycle repeated
Stop
High level
Low level
Self-bias control impossible
Self-bias control possible (by
ZCM register specification)
By clock sampling
By analog delay
ALE
Zero crossing detector self-bias
control
NMI, RESET noise elimination
method
A/D converter operation control
Three kinds: HALT mode,
software STOP mode, and
hardware STOP mode. All
data of on-chip RAM are
held by low power supply
voltage (2.5V) in software/
hardware STOP mode.
Operation stop impossible
Operation stop possible
(VAREF pin operation)
0.4%
(TA = –10 to +70 °C,
0.6%
(TA = –40 to +85 °C,
VAREF = 4.0V to AVDD)
A/D converter absolute accuracy
(Unit: FSR)
0.4% (TA = –10 to +50 °C)
0.6% (TA = –40 to +85 °C)
0.4% (TA = –10 to +70 °C)*3
VAREF = 4.0V to AVDD)
0.8%
(TA = –40 to +85 °C
VAREF = 3.4V to AVDD)
VAREF voltage range
AVCC to 0.5V to AVCC
0V to VAREF
Analog input voltage range
AICC/AIDD1
AIDD2
IAREF/IAREF1
IAREF2
* 1.
2.
3.
50
3.4 V to AVDD
6 mA Typ.
0.5 mA Typ.
—
10 µA Typ.
0.5 mA Typ.
2.0 mA Typ.
—
1.5 mA Typ.
0.7 mA Typ.
µPD7810, 7811, 78C10 and 78C11 are maintenance products.
K, E, P masks apply from 4 MHz to 12 MHz.
The µPD7810HG and 7811HG G masks, µPD7810HCW and 7811HCW K masks apply TA = 0 to +70 °C.
µPD78C10A,78C11A,78C12A
µPD78C10A, 78C11A,
µPD78CP14
78C12A
µPD78CP18
159 kinds (STOP instruction added)
ROM less (µPD78C10A)
4K × 8 bits (µPD78C11A)
8K × 8 bits (µPD78C12A)
16K × 8 bits (PROM)
256 × 8 bits
32K × 8 bits (PROM)
1024 × 8 bits
28 (ZCM register added)
4 to 15 MHz
6 to 15 MHz
4 to 15 MHz
5 V ±10 %
–40 to +85 °C
5 V ±5 %
–40 to +85 °C
5 V ±10 %
–40 to +85 °C
Three kinds: Halt mode, software STOP mode, and hardware STOP mode. All data of
on-chip RAM are held by low power supply voltage (2.5 V) in software/hardware STOP
mode.
12
STOP
Low level
Self-bias control possible
(by ZCM register specification)
By analog delay
Operation stop impossible (VAREF pin operation)
0.4% (TA = –10 to +70 °C, VAREF = 4.0 V to AVDD)
0.6% (TA = –40 to +85 °C, VAREF = 4.0 V to AVDD)
0.8% (TA = –40 to +85 °C, VAREF = 3.4 V to AVDD)
3.4V to AVDD
–0.3 V to VAREF + 0.3 V
0V to VAREF
–0.3 V to VAREF + 0.3 V
0.5mA Typ.
10 µA Typ.
1.5 mA Typ.
0.7 mA Typ.
51
µPD78C10A,78C11A,78C12A
DIFFERENCES IN 87AD SERIES PRODUCTS (2/2)
Product Name
Item
RD/WR
Operation
during RESET
µPD78C10, 78C11*1
High level
ALE
PD/PF*4
µPD7810H, 7811H
µPD7810, 7811*1
Output
High-impedance
Zero is output at the pin specified by the address bus.
Other pins are high impedance.
On-chip pull-up register
(Mask option)
Impossible
Device configuration
NMOS
CMOS
50 µA MAX.
3.2 mA (–10 to +70°C) MAX.
3.2 mA MAX.
(VDD = 5 V ±10 %)
203.2 mA MAX.
25 mA MAX.
Standby current
3.5 mA (–40 to +85°C) MAX.
203.2 mA (–10 to +70°C) MAX.
Current consumption
SCK
(Unit: ns)
★
223.5 mA (–40 to +85°C) MAX.
Cycle time input
20T
Low level width
10T + 80
High level width
10T – 80
*5
TLDW
Bus
timing
TWD
(Unit: ns)
TDW
T + 110
100
4T – 100
Hardware STOP mode restrictions
—
Yes
Asyncronous mode restrictions
during external SCK input.
No
Yes
64-pin plastic shrink DIP
64-pin plastic QUIP
straight*8
64-pin plastic QUIP
64-pin plastic QFP
(14 × 20 mm, 2.05 mm
thickness)
64-pin plastic QFP
(14 × 20 mm, 2.70 mm
thickness)
64-pin plastic shrink DIP
64-pin plastic QUIP straight*7
64-pin plastic QUIP
Package
68-pin plastic QFJ
Pin connection*10
* 1.
4.
VCC (64-pin), VDD (63-pin)
VDD (64-pin), STOP (63-pin)
µPD7810, 7811, 78C10 and 78C11 are maintenance products.
For µPD7810, 7810H, 78C10 and 78C10A.
5.
(Unit : ns)
SCK
Remarks
52
For the asyncronous mode with clock
rate x1, syncronous mode, and I/O
interface mode
For the asyncronous mode with clock
rate ×16 and ×64
Cycle time input
12T
6T
Low level width
5T + 5
2.5T + 5
High level width
5T + 5
2.5T + 5
T = tCYC = 1/fxx
µPD78C10A,78C11A,78C12A
µPD78C10A, 78C11A,
µPD78CP14
78C12A
µPD78CP18
High-impedance
Only µPD78C11A, 78C12A
possible (ports A, B, C)
Impossible
CMOS
50 µA MAX.
(VDD = 5 V ±10 %)
50 µA MAX.
(VDD = 5 V ±10 %)
1 mA MAX.
(VDD = 5 V ±5 %)
25 mA MAX.
35 mA MAX.
32 mA MAX.
*5
T + 110
T + 130
110
140
4T – 100
4T – 140
Yes*6
★
No
No
64-pin plastic shrink DIP
64-pin plastic QUIP
64-pin plastic QFP (14 × 20
64-pin plastic shrink DIP
mm, 2.70 mm thickness)
64-pin plastic QUIP straight*9 68-pin plastic QFJ
64-pin plastic QUIP
64-pin ceramic shrink DIP
64-pin plastic QFP (14 × 20 with window
mm, 2.70 mm thickness)
64-pin ceramic QUIP with
68-pin plastic QFJ
window
64-pin plastic shrink DIP
64-pin plastic QUIP
64-pin plastic QFP (14 × 20
mm, 2.70 mm thickness)
64-pin ceramic shrink DIP
with window
64-pin ceramic WQFN
64-pin ceramic WQFN
VDD (64-pin), STOP (63-pin)
*
6. K mask products only
7. µPD7811, 7811H only
8. µPD78C11, only
9. µPD78C11A, 78C12A only
10. Items in the parentheses are the pin numbers for the 64-pin plastic shrink DIP, 64-pin plastic QUIP straight
and 64-pin plastic QUIP.
Caution
Since the oscillator characteristics, I/O level, and some internal operation timing are different, be careful
when studying direct replacement of the mPD78C10A, 78C11A, 78C12A and µPD7810, 7811, 7810H,
7811H, 78C10, 78C11.
53
µPD78C10A,78C11A,78C12A
9. PACKAGE INFORMATION
64 PIN PLASTIC SHRINK DIP (750 mil)
64
33
1
32
A
K
H
G
J
I
L
F
D
N
M
NOTE
B
C
M
R
ITEM
MILLIMETERS
INCHES
1) Each lead centerline is located within 0.17 mm (0.007 inch) of
its true position (T.P.) at maximum material condition.
A
58.68 MAX.
2.311 MAX.
B
1.78 MAX.
0.070 MAX.
2) Item "K" to center of leads when formed parallel.
C
1.778 (T.P.)
0.070 (T.P.)
D
0.50±0.10
0.020 +0.004
–0.005
F
0.9 MIN.
0.035 MIN.
G
3.2±0.3
0.126±0.012
H
0.51 MIN.
0.020 MIN.
I
4.31 MAX.
0.170 MAX.
J
5.08 MAX.
0.200 MAX.
K
19.05 (T.P.)
0.750 (T.P.)
L
17.0
0.669
M
0.25 +0.10
–0.05
0.010 +0.004
–0.003
N
0.17
0.007
R
0~15°
0~15°
P64C-70-750A,C-1
54
µPD78C10A,78C11A,78C12A
55
µPD78C10A,78C11A,78C12A
56
µPD78C10A,78C11A,78C12A
64PIN PLASTIC QFP (14 × 20) (UNIT: mm)
A
B
33
32
64
1
20
19
detail of lead end
F
Q
5°±5°
D
C
S
51
52
G
H
I M
J
M
P
K
N
L
P64GF-100-3B8,3BE,3BR-1
NOTE
Each lead centerline is located within 0.20
mm (0.008 inch) of its true position (T.P.) at
maximum material condition.
ITEM
MILLIMETERS
INCHES
A
23.6 ± 0.4
0.929 ± 0.016
B
20.0 ± 0.2
0.795+0.009
–0.008
C
14.0 ± 0.2
0.551+0.009
–0.008
D
17.6 ± 0.4
0.693 ± 0.016
F
1.0
0.039
G
1.0
0.039
H
0.40 ± 0.10
0.016 +0.004
–0.005
I
0.20
0.008
J
1.0 (T.P.)
0.039 (T.P.)
K
1.8 ± 0.2
0.071–0.009
L
0.8 ± 0.2
0.031+0.009
–0.008
M
0.15+0.10
–0.05
0.006+0.004
–0.003
N
0.12
0.005
P
2.7
0.106
Q
0.1 ± 0.1
0.004 ± 0.004
S
3.0 MAX.
0.119 MAX.
+0.008
57
µPD78C10A,78C11A,78C12A
ES 64PIN CERAMIC QFP (REFERENCE DRAWING) (UNIT: mm)
Cautions
1.
The metal cap is connected to
pin 26 and is VSS (GND) level.
2.
The bottom leads are tilted.
3.
Since cutting of the end of the
leads is no process-controlled,
the lead length is unspecified.
58
µPD78C10A,78C11A,78C12A
68PIN PLASTIC QFJ (
950 mil) (UNIT: mm)
A
B
C
D
F
E
H
G
U
J
68
1
I
T
Q
K
M
N
M
P
P68L-50A1-2
NOTE
Each lead centerline is located within 0.12
mm (0.005 inch) of its true position (T.P.) at
maximum material condition.
ITEM
MILLIMETERS
INCHES
A
25.2 ± 0.2
0.992 ± 0.008
B
24.20
0.953
C
24.20
0.953
D
25.2 ± 0.2
0.992 ± 0.008
E
1.94 ± 0.15
0.076+0.007
–0.006
F
0.6
0.024
G
4.4 ± 0.2
0.173+0.009
–0.008
H
2.8 ± 0.2
0.110+0.009
–0.008
I
0.9 MIN.
0.035 MIN.
J
3.4
0.134
K
1.27 (T.P.)
0.050 (T.P.)
M
0.40 ± 1.0
0.016+0.004
–0.005
N
0.12
0.005
P
23.12 ± 0.20
0.910+0.009
–0.008
Q
0.15
0.006
T
R 0.8
R 0.031
U
0.20 +0.10
–0.05
0.008+0.004
–0.002
59
µPD78C10A, 78C11A, 78C12A
★
10. RECOMMENDED SOLDERING CONDITIONS
The µPD78C10A, 78C11A, and 78C12A should be soldered and mounted under the conditions recommended in
the table below.
For detail of recommended soldering conditions, refer to the information document "Semiconductor Device
Mounting Technology Manual" (IEI-1207).
For soldering methods and conditions other than those recommended below, contact our sales personnel.
Table 10-1 Surface Mounting Type Soldering Conditions
(1) µPD78C10AGF-3BE
: 64-pin plastic QFP (14 × 20 mm)
µPD78C11AGF-×××-3BE : 64-pin plastic QFP (14 × 20 mm)
µPD78C12AGF-×××-3BE : 64-pin plastic QFP (14 × 20 mm)
Soldering Method
Soldering Conditions
Recommended
Condition Symbol
Infrared reflow
Package peak temperature : 235 °C, Duration : 30 sec. max. (210
°C min.), Number of times : 2 max.
<Points to note>
(1) Start the second reflow after the device temperature by the first
reflow returns to normal.
(2) Flux washing by the water after the first reflow should be avoided.
IR35-00-2
VPS
Package peak temperature : 215 °C, Duration : 40 sec. max. (200
°C min.), Number of times : 2 max.
<Points to note>
(1) Start the second reflow after the device temperature by the first
VP15-00-2
reflow returns to normal.
(2) Flux washing by the water after the first reflow should be avoided.
Wave soldering
Solder bath temperature : 260 °C max., Duration : 10 sec. max.,
Number of times : 1
Pre-heating temperature : 120 °C max. (package surface temperature)
Pin part heating
Pin temperature : 300 °C max.,
Duration: 3 sec. max. (per device side)
Caution
WS60-00-1
Do not use two or more soldering methods in combination (except the pin part heating method).
(2) µPD78C10AL
µPD78C11AL-×××
:
:
68-pin plastic QFJ (
68-pin plastic QFJ (
950 mil)
950 mil)
µPD78C12AL-×××
:
68-pin plastic QFJ (
950 mil)
Soldering Conditions
Soldering Method
Infrared reflow
Package peak temperature : 230 °C, Duration : 30 sec. max.
Recommended
Condition Symbol
IR30-00-1
(210 °C min.), Number of times : 1
Package peak temperature : 215 °C, Duration : 40 sec. max.
VPS
VP15-00-1
(200 °C min.), Number of times : 1
Pin part heating
Pin temperature : 300 °C max., Duration : 3 sec. max. (per device
side)
Caution
60
Do not use two or more soldering methods in combination (except the pin part heating method).
µPD78C10A, 78C11A, 78C12A
Table 10-2 Inserted Type Soldering Conditions
(1) µPD78C10ACW
µPD78C11ACW-×××
µPD78C12ACW-×××
µPD78C10AGQ-36
µPD78C11AGQ-×××-36
µPD78C12AGQ-×××-36
Soldering Method
: 64-pin plastic shrink DIP (750 mil)
: 64-pin plastic shrink DIP (750 mil)
: 64-pin plastic shrink DIP (750 mil)
: 64-pin plastic QUIP
: 64-pin plastic QUIP
: 64-pin plastic QUIP
Soldering Conditions
Wave soldering
Solder bath temperature: 260 °C max.
(pin only)
Duration: 10 sec. max.
Pin temperature: 300 °C max.
Pin part heating
Caution
Duration: 3 sec. max. (per pin)
Ensure that the application of wave soldering is limited to
the pins and no solder touches the main unit directly.
(2) µPD78C11AGQ-×××-37
µPD78C12AGQ-×××-37
Soldering Method
Pin part heating
: 64-pin plastic QUIP straight
: 64-pin plastic QUIP straight
Soldering Conditions
Pin temperature: 300 °C max.
Duration: 3 sec. max. (per pin)
61
µPD78C10A,78C11A,78C12A
★
APPENDIX DEVELOPMENT TOOLS
The following development tools are available to develop a system which uses 87AD series products.
Language Processor
This is a program which converts a program written in mnemonic to an object code that microcomputer execution is possible.
Besides, it contains a function to automatically create a symbol/table, and optimize a branch
instruction.
Host Machine
OS
Supply Medium
Ordering Code (Product Name)
3.5-inch 2HD
µS5A13RA87
PC-9800 series
MS-DOSTM
Ver. 2.11
to
Ver. 5.00A*
5-inch 2HD
µS5A10RA87
PC DOSTM
(Ver. 3.1)
3.5-inch 2HC
µS7B13RA87
5-inch 2HC
µS7B10RA87
87AD series
relocatable assembler
(RA87)
IBM PC/ATTM
Hardware
PROM Write Tools
PG-1500
With an provided board and an optional programmer adapter connected, this PROM programmer
can manipulate from a stand-alone or host machine to perform programming on single-chip
microcomputer which incorporates PROM.
It is also capable of programming a typical PROM ranging from 256K to 4M bits.
PA-78CP14CW/
GF/GQ/KB/L
PROM programmer adapter for µPD78CP14/78CP18. Used by connecting to PG-1500.
PA-78CP14CW
For µPD78CP14CW, 78CP14DW, 78CP18CW, 78CP18DW
PA-78CP14GF
For µPD78CP14GF-3BE, 78CP18GF-3BE
PA-78CP14GQ
For µPD78CP14G-36, 78CP14R, 78CP18GQ-36
PA-78CP14KB
For µPD78CP14KB, 78CP18KB
PA-78CP14L
For µPD78CP14L
Software
Connected PG-1500 to a host machine by using serial and parallel interface, to control the PG1500 on a host machine.
Host Machine
OS
PC-9800 series
MS-DOS
Ver. 2.11
to
Ver. 5.00A*
PG-1500
controller
IBM PC/AT
PC DOS
(Ver. 3.1)
Supply Medium
Ordering Code (Product Name)
3.5-inch 2HD
µS5A13PG1500
5-inch 2HD
µS5A10PG1500
5-inch 2HC
µS7B10PG1500
* Ver. 5.00/5.00A has a task swap function, but this function cannot be used with this software.
Remarks Operation of assemblers and the PG-1500 controller are guaranteed only on the host machines and
operating systems quoted above.
62
µPD78C10A,78C11A,78C12A
Debugging tools
Hardware
An in-circuit emulator (IE-78C11-M) is available as a program debugging tool for 87AD series. The following table
shows its system configuration.
IE-78C11-M
The IE-78C11-M is an in-circuit emulator which works with 87AD series.
Only the IE-78C11-M should be used for a plastic QUIP package, while it should be used with a
conversion socket for a plastic shrink DIP package.
It can be connected to a host machine to perform efficient debugging.
EV-9001-64
Conversion sockets for plastic shrink DIP.
Used in combination with the IE-78C11-M.
EV-9200G-64
64-pin LCC socket. Can be used as a substitute for 64-pin plastic QFP products with window in
combination with the µPD78CP14KB/78CP18KB.
Software
Connects the IE-78C11-M to host machine by using the RS-232-C, then controls the IE-78C11-M
on host machine.
Host Machine
OS
PC-9800 series
MS-DOS
Ver. 2.11
to
Ver. 3.30D
IE-78C11-M
control program
(IE controller)
IBM PC/AT
Remarks
PC DOS
(Ver. 3.1)
Supply Medium
Ordering Code (Product Name)
3.5-inch 2HD
µS5A13IE78C11
5-inch 2HD
µS5A10IE78C11
5-inch 2HC
µS7B10IE78C11
Operation of the IE controller is guaranteed only on the host machine and operating systems quoted
above.
63
µPD78C10A,78C11A,78C12A
[MEMO]
64
µPD78C10A,78C11A,78C12A
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction of
the gate oxide and ultimately degrade the device operation. Steps must be
taken to stop generation of static electricity as much as possible, and quickly
dissipate it once, when it has occurred.
Environmental control must be
adequate. When it is dry, humidifier should be used. It is recommended to
avoid using insulators that easily build static electricity.
Semiconductor
devices must be stored and transported in an anti-static container, static
shielding bag or conductive material. All test and measurement tools including
work bench and floor should be grounded. The operator should be grounded
using wrist strap. Semiconductor devices must not be touched with bare
hands. Similar precautions need to be taken for PW boards with semiconductor
devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input
level may be generated due to noise, etc., hence causing malfunction. CMOS
device behave differently than Bipolar or NMOS devices. Input levels of CMOS
devices must be fixed high or low by using a pull-up or pull-down circuitry. Each
unused pin should be connected to VDD or GND with a resistor, if it is considered
to have a possibility of being an output pin. All handling related to the unused
pins must be judged device by device and related specifications governing the
devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production
process of MOS does not define the initial operation status of the device.
Immediately after the power source is turned ON, the devices with reset
function have not yet been initialized. Hence, power-on does not guarantee
out-pin levels, I/O settings or contents of registers. Device is not initialized
until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
65
µPD78C10A,78C11A,78C12A
The export of these products from Japan is regulated by the Japanese government. The export of some or all of these products
may be prohibited without governmental license. To export or re-export some or all of these products from a country other
than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.
The customer must judge : µPD78C11ACW-×××, 78C11AGF-×××-3BE, 78C11AGQ-×××-36, 78C11AGQ-×××-37,
the need for license
µPD78C11AL-×××, 78C12ACW-×××, 78C12AGF-×××-3BE, 78C12AGQ-×××-36,
µPD78C12AGQ-×××-37, 78C12AL-×××
License not needed :
µPD78C10ACW, 78C10AGF-3BE, 78C10AGQ-36, 78C10AL
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this
document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from use of a device described herein or any other liability arising
from use of such device. No license, either express, implied or otherwise, is granted under any patents,
copyrights or other intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customer must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
“Standard“, “Special“, and “Specific“. The Specific quality grade applies only to devices developed based on
a customer designated “quality assurance program“ for a specific application. The recommended applications
of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each
device before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices in “Standard“ unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact NEC Sales Representative in advance.
Anti-radioactive design is not implemented in this product.
M4 94.11
MS-DOS is a trademark of Microsoft Corporation.
PC/AT and PC DOS are trademarks of IBM Corporation.