DATA SHEET MOS INTEGRATED CIRCUIT µPD78F9177, 78F9177Y 8-BIT SINGLE-CHIP MICROCONTROLLER The µPD78F9177 and µPD78F9177Y are µPD789177, 789177Y Subseries (small, general-purpose) in the 78K/0S Series. The µPD78F9177 replaces the internal ROM of the µPD789176 and µPD789177 with flash memory, while the µPD78F9177Y replaces the ROM of the µPD789176Y and µPD789177Y with flash memory. Because flash memory allows the program to be written and erased electrically with the device mounted on the board, this product is ideal for the evolution stages of system development, small-scale production and rapid development of new products. Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before designing. µPD789167, 789177, 789167Y, 789177Y Subseries User’s Manual: U14186E 78K/0S Series User's Manual Instruction: U11047E FEATURES • • • • • • • • • • Pin compatible with mask ROM version (except VPP pin) Flash memory: 24 Kbytes High-speed RAM: 512 bytes Minimum instruction execution time can be changed from high-speed (0.4 µs: @5.0-MHz operation with main system clock) to ultra-low-speed (122 µs: @ 32.768-kHz operation with subsystem clock) 10-bit resolution A/D converter: 8 channels I/O ports: 31 Serial interface: 2 channels • 3-wire serial I/O mode / UART mode: 1 channel • SMB (µPD78F9177Y only): 1 channel Timers: 6 channels • 16-bit timer: 1 channel • 8-bit timer/event counter: 2 channels • 8-bit timer: 1 channel • Watch timer: 1 channel • Watchdog timer: 1 channel On-chip 16-bit multiplier Power supply voltage: VDD = 1.8 to 5.5 V The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. U14022EJ1V0DS00 (1st edition) Date Published August 2000 NS CP(K) Printed in Japan The mark shows major revised © 2000 µPD78F9177, 78F9177Y APPLICATIONS Power windows, battery management unit, side air bags, etc ORDERING INFORMATION (1) µPD78F9177 Part Number Package µPD78F9177GB-8ES 44-pin plastic QFP (10 × 10) (2) µPD78F9177Y Part Number 2 Package µPD78F9177YGB-8ES 44-pin plastic LQFP (10 X 10) µPD78F9177YGA-9EU 48-pin plastic TQFP (fine pitch) (7 X 7) Data Sheet U14022EJ1V0DS00 µPD78F9177, 78F9177Y 78K/0S SERIES DEVELOPMENT The products in the 78K/0S Series are listed below. The names enclosed in boxes are subseries names. Products under mass production Products under development Y subseries supports SMB. Small, general-purpose 44 pins 42/44 pins 28 pins µ PD789026 with subsystem clock added µ PD789014 with timer reinforced and ROM and RAM expanded µ PD789046 µ PD789026 µ PD789014 UART. Low-voltage (1.8-V) operation Small, general-purpose + A/D µ PD789177 µ PD789167 µ PD789156 µ PD789146 µ PD789134A µ PD789124A µ PD789114A µ PD789104A 44 pins 44 pins 30 pins 30 pins 30 pins 30 pins 30 pins 30 pins µ PD789177Y µ PD789167Y µ PD789167 with improved A/D µ PD789104A with improved timer µ PD789146 with improved A/D µ PD789104A with EEPROM added µ PD789124A with improved A/D RC oscillation model of µ PD789104A µ PD789104A with improved A/D µ PD789026 with A/D and multiplier added For inverter control µ PD789842 44 pins 78K/0S series Internal inverter control circuit and UART For driving LCD 80 pins 80 pins 64 pins 64 pins 64 pins 64 pins 64 pins 64 pins µ PD789417A µ PD789407A µ PD789456 µ PD789446 µ PD789436 µ PD789426 µ PD789316 µ PD789306 µ PD789407A with improved A/D µ PD789456 with improved I/O µ PD789446 with improved A/D µ PD789426 with improved display output µ PD789426 with improved A/D µ PD789306 with A/D added RC oscillation model of µ PD789306 Basic subseries for driving LCD For driving Dot LCD 144 pins 88 pins µ PD789835 µ PD789830 Segment/common output: 96 pins Segment: 40 pins, common: 16 pins For ASSP 52 pins 52 pins 44 pins 44 pins 20 pins 20 pins µ PD789467 µ PD789327 µ PD789800 µ PD789840 µ PD789861 µ PD789860 µ PD789327 with A/D added For remote controller. Internal LCD controller/driver For PC keyboard. Internal USB function For key pad. Internal POC RC oscillation model of µPD789860 For keyless entry. Internal POC and key return circuit Data Sheet U14022EJ1V0DS00 3 µPD78F9177, 78F9177Y The major differences between subseries are shown below. Function Subseries Name ROM Capacity Small, µPD789046 16 K generalµPD789026 4 K-16 K purpose µPD789014 2 K-4 K Small, µPD789177 16 K-24 K generalµPD789167 purpose µPD789156 8 K-16 K + A/D Timer 8-bit 1 ch 16-bit 1 ch Watch WDT 1 ch 1 ch 8-bit A/D 10-bit A/D Serial Interface I/O VDD MIN Value Remark − − 1 ch (UART:1 ch) 34 pins 1.8 V − 1.8 V − − 2 ch − 3 ch 1 ch 22 pins 1 ch 1 ch − 1 ch µPD789146 − 8 ch 8 ch − − 4 ch 4 ch − µPD789134A 2 K-8 K 20 pins Internal EEPROM 4 ch RC oscillation version µPD789124A 4 ch − µPD789114A − 4 ch µPD789104A 4 ch − 8 ch − 1 ch (UART: 1 ch) 30 pins 4.0 V − 7 ch 1 ch (UART: 1 ch) 43 pins 1.8 V − µPD789842 8 K-16 K 3 ch Note 1 ch 1 ch For LCD µPD789417A 12 K-24 K driving µPD789407A 3 ch 1 ch 1 ch 1 ch µPD789456 12 K-16 K 2 ch For inverter control 1 ch (UART: 1 ch) 31 pins 7 ch − − 6 ch µPD789446 6 ch − µPD789436 − 6 ch µPD789426 6 ch − µPD789316 8 K to 16K − − 30 pins 40 pins 2 ch (UART: 1 ch) 23 pins RC oscillation version µPD789306 − For Dot LCD driving µPD789835 24 K-60 K 6 ch − µPD789830 24 K 1 ch 1 ch ASSP µPD789467 4 K-24 K 2 ch − 1 ch 1 ch 2 ch 1 ch µPD789840 µPD789861 4 K − 1 ch 1 ch − 1 ch 1 ch − 1.8 V 30 pins 2.7 V 18 pins 1.8 V 1 ch 21 pins − 2 ch (USB: 1 ch) 31 pins 4.0 V 1 ch 29 pins 2.8 V 14 pins 1.8 V − µPD789860 − − Internal LCD − RC oscillation version, Internal EEPROM Internal EEPROM Note 10-bit timer: 1 channel 4 − 28 pins − 4 ch − 1 ch − µPD789327 µPD789800 8 K 3 ch Data Sheet U14022EJ1V0DS00 µPD78F9177, 78F9177Y OVERVIEW OF FUNCTIONS µPD78F9177 Item Internal memory Flash memory 24 Kbytes High-speed RAM 512 bytes µPD78F9177Y Minimum instruction execution time • 0.4/1.6 µs (@5.0-MHz operation with main system clock) • 122 µs (@ 32.768-kHz operation with subsystem clock) General-purpose registers 8 bits × 8 registers Instruction set • 16-bit operations • Bit manipulations (set, reset, test) Multiplier 8 bits × 8 bits = 16 bits I/O ports Total: 31 • CMOS input: • CMOS I/O: • N-ch open drain: 8 17 6 A/D converters 10-bit resolution × 8 channels Serial interfaces 3-wire serial I/O/UART : 1 channel • 3-wire serial I/O / UART: 1 channel • SMB: 1 channel Timers • • • • • Timer output 4 output Buzzer output 1 Vectored interrupt Maskable 16-bit timer:1 channel 8-bit timer/event counter:2 channels 8-bit timer:1 channel Watch timer:1 channel Watchdog timer:1 channel Internal: 10, External: 4 (µPD78F9177) Internal: 12, External: 4 (µPD78F9177Y) sources Non-maskable Internal: 1 Power supply voltage VDD = 1.8 to 5.5 V Operating ambient temperature TA = −40°C to +85°C Package 44-pin plastic LQFP (10 × 10) • 44-pin plastic LQFP (10 X10) • 48-pin plastic TQFP (fine pitch) (7 x 7) Data Sheet U14022EJ1V0DS00 5 µPD78F9177, 78F9177Y CONTENTS 1. PIN CONFIGURATION (TOP VIEW) ................................................................................................. 7 2. BLOCK DIAGRAM............................................................................................................................. 10 3. PIN FUNCTIONS................................................................................................................................ 11 3.1 Port Pins .................................................................................................................................................. 11 3.2 Non-Port Pins.......................................................................................................................................... 12 3.3 Pin I/O Circuits and Recommended Connection of Unused Pins ...................................................... 13 4. CPU ARCHITECTURE....................................................................................................................... 15 5. FLASH MEMORY PROGRAMMING ................................................................................................ 16 5.1 Selecting Communication Mode .......................................................................................................... 16 5.2 Function of Flash Memory Programming ............................................................................................ 17 5.3 Flashpro III Connection Example ......................................................................................................... 17 5.4 Example of Settings for Flashpro III (PG-FP3) .................................................................................... 19 INSTRUCTION SET OVERVIEW ...................................................................................................... 20 6.1 Conventions ........................................................................................................................................... 20 6.2 Operations .............................................................................................................................................. 22 7. ELECTRICAL SPECIFICATIONS...................................................................................................... 27 8. CHARACTERISTICS CURVES ........................................................................................................ 45 9. PACKAGE DRAWING ...................................................................................................................... 46 10. RECOMMENDED SOLDERING CONDITIONS ............................................................................... 48 APPENDIX A. DIFFERENCES BETWEEN µPD78F9177, 78F9177Y, AND MASK ROM VERSIONS...... 49 APPENDIX B. DEVELOPMENT TOOLS ............................................................................................... 50 APPENDIX C. RELATED DOCUMENTS ............................................................................................... 52 6. 6 Data Sheet U14022EJ1V0DS00 µPD78F9177, 78F9177Y 1. PIN CONFIGURATION (TOP VIEW) • 44-pin plastic LQFP (10 × 10) µPD78F9177GB-8ES P02 P03 P04 VSS1 P05 P50 P51 P52 P53 30 P25/TI80/SS20 P64/ANI4 5 29 VDD0 P65/ANI5 6 28 VSS0 P66/ANI6 7 27 X1 P67/ANI7 8 26 X2 AVSS 9 25 RESET P10 10 24 XT1 P11 11 23 12 13 14 15 16 17 18 19 20 21 22 XT2 VPP 4 P24/SDA0Note P26/TO80 P63/ANI3 P23/SCL0Note 31 P22/SI20/RXD20 3 P21/SO20/TXD20 P00 P62/ANI2 VDD1 32 P20/SCK20/ASCK20 2 P33/INTP3/TO82/BZO90 P01 P61/ANI1 P32/INTP2/TO90 44 43 42 41 40 39 38 37 36 35 34 1 33 P31/INTP1/TO81 P60/ANI0 P30/INTP0/TI81/CPT90 Note AVDD AVREF µPD78F9177YGB-8ES The SCL0 and SDA0 pins are available in µPD78F9177Y product only. Cautions 1. Connect the VPP pin directly to VSS0 or VSS1. 2. Connect the AVDD pin to VDD0. 3. Connect the AVSS pin to VSS0. Data Sheet U14022EJ1V0DS00 7 µPD78F9177, 78F9177Y • 44-pin plastic QFP (fine pitch) (7 × 7) AVREF AVDD P53 P52 IC0 P51 P50 P05 VSS1 P04 P03 P02 µPD78F9177YGA-9EU 1 2 3 4 5 6 7 8 9 10 11 12 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 P01 P00 P26/TO80 P25/Tl80/SS20 VDD0 IC2 VSS0 X1 X2 RESET XT1 XT2 P30/INTP0/Tl81/CPT90 P31/INTP1/TO81 P32/INTP2/TO90 P33/INTP3/TO82/BZO90 P20/SCK20/ASCK20 VDD1 IC2 P21/SO20/TxD20 P22/Sl20/RxD20 P23/SCL0 P24/SDA0 VPP P60/ANI0 P61/ANI1 P62/ANI2 P63/ANI3 P64/ANI4 P65/ANI5 P66/ANI6 P67/ANI7 AVSS P10 P11 IC2 Cautions 1. Connect the VPP pin directly to the VSS0 or VSS1 pin in normal operation mode. 2. Connect the IC0 (Internally Connected) pin directly to VSS0 or VSS1. 3. Leave the IC2 pin open. 4. Connect the AVDD pin to VDD0. 5. Connect the AVSS pin to VSS0. 8 Data Sheet U14022EJ1V0DS00 µPD78F9177, 78F9177Y ANI0 to ANI7: Analog Input RESET: Reset ASCK20: Asynchronous Serial Input RxD20: Receive Data AVDD: Analog Power Supply SCK20: Serial Clock (for SIO20) AVREF: Analog Reference Voltage SCL0 Note2 Note2 : Serial Clock (for SMB0) AVSS: Analog Ground SDA0 BZO90: Buzzer Output SI20: Serial Input Capture Trigger Input SO20: Serial Output Internally Connected SS20: Chip Select Input INTP0 to INTP3: Interrupt from Peripherals TI80, TI81: Timer Input P00 to P05: Port 0 TO80 to TO82, TO90: Timer Output P10, P11: Port 1 TxD20: Transmit Data P20 to P26: Port 2 VDD0, VDD1: Power Supply P30 to P33: Port 3 VPP: Programming Power Supply P50 to P53: Port 5 VSS0, VSS1: Ground P60 to P67: Port 6 X1, X2: Crystal (Main System Clock) XT1, XT2: Crystal (Subsystem Clock) CPT90: IC0 Note1 ,IC2 Note2 : : Serial Data Notes 1. The IC0 pin is available in 48-pin plastic TQFP (fine pitch) only. 2. The IC2, SCL0, and SDA0 pins are available in µPD78F9177Y product only. Data Sheet U14022EJ1V0DS00 9 µPD78F9177, 78F9177Y 2. BLOCK DIAGRAM TI80/SS20/P25 TO80/P26 8-BIT TIMER/ EVENT COUNTER80 PORT0 P00-P05 TI81/INTP0/CPT90/P30 TO81/INTP1/P31 8-BIT TIMER/ EVENT COUNTER81 PORT1 P10, P11 TO82/INTP3/BZO90/P33 8-BIT TIMER82 PORT2 P20-P26 CPT90/INTP0/TI81/P30 TO90/INTP2/P32 BZO90/INTP3/TO82/P33 16-BIT TIMER90 PORT3 P30-P33 PORT5 P50-P53 PORT6 P60-P67 SYSTEM CONTROL RESET X1 X2 XT1 XT2 WATCH TIMER 78K/0S CPU CORE ROM WATCHDOG TIMER SCK20/ASCK20/P20 SO20/TXD20/P21 SI20/RXD20/P22 SS20/TI80/P25 SCL0/P23 SDA0/P24 ANI0/P60ANI7/P67 AVDD AVSS AVREF SIO20 RAM SMBNote1 INTERRUPT CONTROL A/D CONVERTER MULTIPLIER VDD0 VDD1 VSS0 VSS1 VPP IC0 Note2 IC2 Note3 Notes 1. SMB is available in µPD78F9177Y product only. 10 2. The IC0 pin is available in 48-pin plastic TQFP (fine pitch) only. 3. The IC2 pin is available in µPD78F9177Y product only. Data Sheet U14022EJ1V0DS00 INTP0/TI81/CPT90/P30 INTP1/TO81/P31 INTP2/TO90/P32 INTP3/TO82/BZO90/P33 µPD78F9177, 78F9177Y 3. PIN FUNCTIONS 3.1 Port Pins Pin Name I/O P00 to P05 I/O P10, P11 P20 After Reset Alternate Function Port 0 6-bit input/output port Input/output mode can be specified in 1-bit units When used as an input port, an on-chip pull-up resistor can be specified by software. Input − I/O Port 1 2-bit input/output port Input/output mode can be specified in 1-bit units When used as an input port, an on-chip pull-up resistor can be specified by software. Input − I/O Port 2 7-bit input/output port Input/output mode can be specified in 1-bit units For P20 to P22, P25, and P26, an on-chip pull-up resistor can be specified by software. Only P23 and P24 can be used as N-ch open-drain input/output port pins. Input P21 P22 P23 P24 Function SCK20/ASCK20 SO20/TxD20 SI20/RxD20 SCL0 Note SDA0 Note P25 TI80/SS20 P26 TO80 P30 I/O P31 P32 Port 3 4-bit input/output port Input/output mode can be specified in 1-bit units On-chip pull-up resistor can be specified by software. Input INTP0/TI81/CPT90 INTP1/TO81 INTP2/TO90 INTP3/TO82/BZO90 P33 P50 to P53 I/O P60 to P67 Input Port 5 4-bit N-ch open-drain input/output port Input/output mode can be specified in 1-bit units Input Port 6 8-bit input-only port Input − ANI0 to ANI7 Note µPD78F9177Y only Data Sheet U14022EJ1V0DS00 11 µPD78F9177, 78F9177Y 3.2 Non-Port Pins Pin Name INTP0 I/O Function After Reset Input External interrupt input for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified Input INTP1 Alternate Function P30/TI81/CPT90 P31/TO81 INTP2 P32/TO90 INTP3 P33/TO82/BZO90 SI20 Input Serial data input to serial interface Input P22/RxD20 SO20 Output Serial data output from serial interface Input P21/TxD20 Serial clock input/output for serial interface Input P20/ASCK20 SCK20 I/O SS20 Input Chip select input to serial interface Input P25/TI80 ASCK20 Input Serial clock input for asynchronous serial interface Input P20/SCK20 RxD20 Input Serial data input for asynchronous serial interface Input P22/SI20 TxD20 Output Serial data output for asynchronous serial interface Input P21/SO20 SCL0 SDA0 Note1 I/O SMB0 clock input/output Input P23 Note1 I/O SMB0 data input/output Input P24 TI80 Input External count clock input to 8-bit timer/event counter (TM80) Input P25/SS20 TI81 Input External count clock input to 8-bit timer/event counter (TM81) Input P30/INTP0/CPT90 TO80 Output 8-bit timer/event counter (TM80) output Input P26 TO81 Output 8-bit timer/event counter (TM81) output Input P31/INTP1 TO82 Output 8-bit timer (TM82) output Input P33/INTP3/BZO90 TO90 Output 16-bit timer (TM90) output Input P32/INTP2 BZO90 Output 16-bit timer (TM90) Buzzer output Input P33/INTP3/TO82 CPT90 Input Capture edge input Input P30/INTP0/TI81 ANI0 to ANI7 Input A/D converter analog input Input P60 to P67 AVREF − A/D converter reference voltage − − AVSS − A/D converter ground potential − − AVDD − A/D converter analog power supply − − X1 Input X2 − Connecting crystal resonator for main system clock oscillation − − − − − − − − XT1 Input XT2 − VDD0 − Positive power supply − − VDD1 − Positive power supply (other than ports) − − VSS0 − Ground potential − − VSS1 − Ground potential (other than ports) − − Input − − − RESET Input − VPP Connecting crystal resonator for subsystem clock oscillation System reset input Sets flash memory programming mode. Applies high voltage when a program is written or verified. Connect directly to VSS0 or VSS1 in normal operation mode. IC0 IC2 Note2 − Internally connected. Connect this pin directly to the VSS0 or VSS1 pin. − − Note1 − Internally connected. Leave this pin open. − − Notes 1. µPD78F9177Y only. 2. 48-pin plastic TQFP (fine pitch) only. 12 Data Sheet U14022EJ1V0DS00 µPD78F9177, 78F9177Y 3.3 Pin I/O Circuits and Recommended Connection of Unused Pins The input/output circuit type of each pin and recommended connection of unused pins is shown in Table 3-1. For the input/output circuit configuration of each type, refer to Figure 3-1. Table 3-1. Type of I/O Circuit for Each Pin and Connection of Unused Pins Pin Name P00 to P05 I/O Circuit Type I/O 5-H I/O P10, P11 P20/SCK20/ASCK20 Recommended Connection of Unused Pins Input: Independently connects to VDD0, VDD1 or VSS0, VSS1 via a resistor. Output: Leave open. 8-C P21/SO20/TxD20 P22/SI20/RxD20 Note1 P23/SCL0 13-X Input: Note1 P24/SDA0 Independently connects to VDD0 or VDD1 via a resistor. Output: Leave open. P25/TI80/SS20 8-C Independently connects to VDD0, VDD1 or VSS0, VSS1 via a resistor. Output: Leave open. Input: P26/TO80 Input: P30/INTP0/TI81/CPT90 P31/INTP1/TO81 Independently connects to VSS0 or VSS1 via a resistor. Output: Leave open. P32/INTP2/TO90 P33/INTP3/TO82/BZO90 P50 to P53 13-T Input: Independently connects to VDD0 or VDD1 via a resistor. Output: Leave open. P60/ANI0 to P67/ANI7 XT1 9-C Input Connect directly to VDD0, VDD1 or VSS0, VSS1. − Input Connect to VSS0 or VSS1. − XT2 RESET 2 Input VPP − − IC0 IC2 Leave open. − Connect directly to VSS0 or VSS1. Note2 Note1 Leave open. Notes 1. The IC2, SCL0, and SDA0 pins are available in µPD78F9177Y product only. 2. 48-pin plastic TQFP (fine pitch) only. Data Sheet U14022EJ1V0DS00 13 µPD78F9177, 78F9177Y Figure 3-1. Pin Input/Output Circuits Type 2 Type 9-C Comparator P-ch N-ch IN IN + − AVSS VREF (Threshold voltage) Schmitt-triggered input with hysteresis characteristics Input enable Type 5-H Type 13-T VDD0 Pull-up enable P-ch IN/OUT VDD0 Data Output data Output disable P-ch IN/OUT Output disable N-ch N-ch VSS0 Input enable VSS0 Input buffer with intermediate withstand voltage Input enable Type 8-C Type 13-X VDD0 Pull-up enable P-ch IN/OUT VDD0 Data Output data Output disable P-ch IN/OUT Output disable 14 N-ch N-ch VSS0 Input buffer with 5-V withstand voltage VSS0 Comparator Data Sheet U14022EJ1V0DS00 µPD78F9177, 78F9177Y 4. CPU ARCHITECTURE Products in the µPD78F9177 and µPD78F9177Y can access up to 64 Kbytes of memory space. Figure 4-1 shows the memory map. Figure 4-1. Memory Map FFFFH Special function registers 256 × 8 bits FF00H FEFFH Internal high-speed RAM 512 × 8 bits Data memory space FD00H FCFFH Reserved 5FFFH 6000H 5FFFH Program area Program memory space Internal flash memory 24576 x 8 bits 0080H 007FH CALLT table area 0040H 003FH 0024H 0023H Program area Vector table area 0000H 0000H Data Sheet U14022EJ1V0DS00 15 µPD78F9177, 78F9177Y 5. FLASH MEMORY PROGRAMMING The on-chip program memory in the µPD78F9177 and µPD78F9177Y is flash memory. The flash memory can be written with the µPD78F9177 and µPD78F9177Y mounted on the target system (onboard). Connect the dedicated flash programmer (Flashpro III (part number: FL-PR3, PG-FP3)) to the host machine and target system to write the flash memory. Remark FL-PR3 is made by Naito Densei Machida Mfg. Co., Ltd. 5.1 Selecting Communication Mode The flash memory is written by using Flashpro III and by means of serial communication. Select a communication mode from those listed in Table 5-1. To select a communication mode, the format shown in Figure 5-1 is used. Each communication mode is selected by the number of VPP pulses shown in Table 5-1. Table 5-1. Communication Mode Communication Mode Pins Used Number of VPP Pulses 3-wire serial I/O SCK20/ASCK20/P20 0 SO20/TxD20/P21 SI20/RxD20/P22 SMB Note1 SCL0/P23 4 SDA0/P24 UART TxD20/SO20/P21 8 RxD20/SI20/P22 Pseudo 3-wire mode Note2 12 P00 (Serial clock input) P01 (Serial data output) P02 (Serial data input) Notes 1. µPD78F9177Y only 2. Serial transfer is performed by controlling a port by software. Caution Be sure to select a communication mode based on the VPP pulse number shown in Table 5-1. Figure 5-1. Communication Mode Selection Format 10 V VPP VDD 1 VSS VDD RESET VSS 16 Data Sheet U14022EJ1V0DS00 2 n µPD78F9177, 78F9177Y 5.2 Function of Flash Memory Programming By transmitting/receiving commands and data in the selected communication mode, operations such as writing to the flash memory are performed. Table 5-2 shows the major functions of flash memory programming. Table 5-2. Functions of Flash Memory Programming Function Description Batch erase Erases all contents of memory Batch blank check Checks erased state of entire memory Data write Write to flash memory based on write start address and number of data written (number of bytes) Batch verify Compares all contents of memory with input data 5.3 Flashpro III Connection Example How the Flashpro III is connected to the µPD78F9177 and µPD78F9177Y differs depending on the communication mode (3-wired serial I/O, SMB, UART, or pseudo 3-wire mode). Figures 5-2 to 5-5 show the connection in the respective mode. Figure 5-2. Flashpro III Connection in 3-wired Serial I/O Mode µ PD78F9177, 78F9177Y Flashpro III VPPnNote VPP VDD VDD0, VDD1, AVDD RESET RESET CLK X1 SCK SCK20 SO SI20 SI SO20 GND VSS0, VSS1, AVSS Note n = 1, 2 Data Sheet U14022EJ1V0DS00 17 µPD78F9177, 78F9177Y Figure 5-3. Flashpro III Connection in SMB Mode µ PD78F9177Y Flashpro III VPPnNote VPP VDD VDD0, VDD1, AVDD RESET RESET CLK X1 SO SCL0 SI SDA0 VSS0, VSS1, AVSS GND Note n = 1, 2 Figure 5-4. Flashpro III Connection in UART Mode µ PD78F9177, 78F9177Y Flashpro III VPPnNote VPP VDD VDD0, VDD1, AVDD RESET RESET CLK X1 SO RxD20 SI TxD20 GND VSS0, VSS1, AVSS Note n = 1, 2 Figure 5-5. Flashpro III Connection in Pseudo Serial I/O Mode (When Port 0 is Used) µ PD78F9177, 78F9177Y Flashpro III VPPnNote VPP VDD VDD0, VDD1, AVDD RESET RESET CLK X1 SCK P00 (Serial clock) SO P02 (Serial input) SI P01 (Serial output) VSS0, VSS1, AVSS GND Note n = 1, 2 18 Data Sheet U14022EJ1V0DS00 µPD78F9177, 78F9177Y 5.4 Example of Settings for Flashpro III (PG-FP3) Set as follows when writing to flash memory using the Flashpro III (PG-FP3). <1> Download the parameter file. <2> Select the serial mode and the serial clock using the type command. <3> The following is a setting example using the PG-FP3. Table 5-3. Example Using PG-FP3 Communication mode 3-wired serial I/O mode Setting example using PG-FP3 COMM PORT SIO ch-0 CPU CLK On target board Number of V PP pulses Note1 0 In Flashpro On target board SMB Note2 UART Pseudo 3-wire mode 4.1943 MHz SIO CLK 1.0 MHz In Flashpro 4.0 MHz SIO CLK 1.0 MHz COMM PORT IIC-ch0 SLAVE ADDRESS 10H IIC CLOCK 100 kHz CPU CLOCK In Flashpro Flashpro Clock 4.0 MHz Multiple Rate 01.00 COMM PORT UART-ch0 CPU CLK On target board On target board 4.1943 MHz UART BPS 9600 bps COMM PORT Port A CPU CLK On target board 4 Note3 8 Note4 12 In Flashpro On target board 4.1943 MHz SIO CLK 1.0 MHz In Flashpro 4.0 MHz SIO CLK 1.0 MHz Notes 1. The number of VPP pulses supplied from the Flashpro III during serial communication initialization. The pins to be used in communication are determined by this number of pulses. 2. µPD78F9177Y only. 3. Select one of 4.0 MHz or 3.125 MHz. 4. Select one of 9600 bps, 19200 bps, 38400 bps, or 76800 bps. Remark COMM PORT : Selection of serial port SIO CLK : Selection of serial clock frequency CPU CLK : Selection of CPU clock source to be input Data Sheet U14022EJ1V0DS00 19 µPD78F9177, 78F9177Y 6. INSTRUCTION SET OVERVIEW This section lists the µPD78F9177 and µPD78F9177Y instruction set. 6.1 Conventions 6.1.1 Operand identifiers and description methods Operands are described in the “Operand” column of each instruction in accordance with the description method of the instruction operand identifier (refer to the assembler specifications for detail). When there are two or more description methods, select one of them. Alphabetic letters in capitals and the symbols, #, !, $, and [ ], are keywords and must be described as they are. Each symbol has the following meaning. • #: Immediate data specification • $: • !: • [ ]: Indirect address specification Absolute address specification Relative address specification In the case of immediate data, describe an appropriate numeric value or a label. When using a label, be sure to describe the #,!, $, or [ ] symbols. For operand register identifiers, r and rp, either function names (X, A, C, etc.) or absolute names (names in parentheses in the table below, R0, R1, R2, etc.) can be used for description. Table 6-1. Operand Identifiers and Description Methods Identifier Description Method r rp sfr X (R0), A (R1), C (R2), B (R3), E (R4), D (R5), L (R6), H (R7), AX (RP0), BC (RP1), DE (RP2), HL (RP3) Special function register symbol saddr saddrp FE20H to FF1FH immediate data or label FE20H to FF1FH immediate data or label (even address only) addr16 addr5 0000H to FFFFH immediate data or label (Only even addresses for 16-bit data transfer instructions) 0040H to 007FH immediate data or label (even address only) word byte bit 16-bit immediate data or label 8-bit immediate data or label 3-bit immediate data or label 20 Data Sheet U14022EJ1V0DS00 µPD78F9177, 78F9177Y 6.1.2 Descriptions of the operation field A: A register; 8-bit accumulator X: X register B: B register C: C register D: D register E: E register H: H register L: L register AX: AX register pair; 16-bit accumulator BC: BC register pair DE: DE register pair HL: HL register pair PC: Program counter SP: Stack pointer PSW: Program status word CY: Carry flag AC: Auxiliary carry flag Z: Zero flag IE: Interrupt request enable flag NMIS: Non-maskable interrupt servicing flag ( ): Memory contents indicated by address or register contents in parentheses XH, XL: Higher 8 bits and lower 8 bits of 16-bit register ∧: Logical product (AND) ∨: Logical sum (OR) ∨: Exclusive OR : Inverted data addr16: 16-bit immediate data or label jdisp8: Signed 8-bit data (displacement value) 6.1.3 Description of the flag operation field (Blank): Not affected 0: Cleared to 0 1: Set to 1 ×: Set/cleared according to the result R: Previously saved value is restored Data Sheet U14022EJ1V0DS00 21 µPD78F9177, 78F9177Y 6.2 Operations Flags Mnemonic Operand Bytes Clock Operation Z MOV r. #byte 3 6 r ← byte saddr, #byte 3 6 (saddr) ← byte sfr, #byte 3 6 sfr ← byte Note 1 2 4 A←r Note 1 2 4 r←A A, r r, A XCH A, saddr 2 4 A ← (saddr) saddr, A 2 4 (saddr) ← A A, sfr 2 4 A ← sfr sfr, A 2 4 sfr ← A A, !addr16 3 8 A ← (addr16) !addr16, A 3 8 (addr16) ← A PSW, #byte 3 6 PSW ← byte A, PSW 2 4 A ← PSW PSW, A 2 4 PSW ← A A, [DE] 1 6 A ← (DE) [DE], A 1 6 (DE) ← A A, [HL] 1 6 A ← (HL) [HL], A 1 6 (HL) ← A A, [HL + byte] 2 6 A ← (HL + byte) [HL + byte], A 2 6 (HL + byte) ← A 1 4 A ←→ X A, r 2 6 A ←→ r A, saddr 2 6 A ←→ (saddr) A, sfr 2 6 A ←→ (sfr) A, [DE] 1 8 A ←→ (DE) A, [HL] 1 8 A ←→ (HL) A, [HL + byte] 2 8 A ←→ (HL+byte) rp, #word 3 6 rp ← word AX, saddrp 2 6 AX ← (saddrp) saddrp, AX A, X Note 2 MOVW 2 8 (saddrp) ← AX Note 3 1 4 AX ← rp Note 3 1 4 rp ← AX AX, rp rp, AX AC CY × × × × × × Notes 1. Except r = A 2. Except r = A, X 3. Only when rp = BC, DE, HL Remark One clock of an instruction is one clock of the CPU clock (fCPU) selected using the processor clock control register (PCC). 22 Data Sheet U14022EJ1V0DS00 µPD78F9177, 78F9177Y Flags Mnemonic Operand Bytes Clock Operation Z AC CY XCHW AX, rp 1 8 AX ←→ rp ADD A, #byte 2 4 A, CY ← A + byte × × × saddr, #byte 3 6 (saddr), CY ← (saddr) + byte × × × A, r 2 4 A, CY ← A + r × × × A, saddr 2 4 A, CY ← A + (saddr) × × × A, !addr16 3 8 A, CY ← A + (addr16) × × × A, [HL] 1 6 A, CY ← A + (HL) × × × A, [HL + byte] 2 6 A, CY ← A + (HL + byte) × × × A, #byte 2 4 A, CY ← A + byte + CY × × × saddr, #byte 3 6 (saddr), CY ← (saddr) + byte + CY × × × A, r 2 4 A, CY ← A + r + CY × × × A, saddr 2 4 A, CY ← A+ (saddr) + CY × × × A, !addr16 3 8 A, CY ← A+ (addr16) +CY × × × A, [HL] 1 6 A, CY ← A + (HL) + CY × × × A, [HL + byte] 2 6 A, CY ← A+ (HL + byte) + CY × × × A, #byte 2 4 A, CY ← A – byte × × × saddr, #byte 3 6 (saddr), CY ← (saddr) – byte × × × A, r 2 4 A, CY ← A – r × × × A, saddr 2 4 A, CY ← A – (saddr) × × × A, !addr16 3 8 A, CY ← A – (addr16) × × × A, [HL] 1 6 A, CY ← A – (HL) × × × A, [HL + byte] 2 6 A, CY ← A – (HL + byte) × × × A, #byte 2 4 A, CY ← A – byte – CY × × × saddr, #byte 3 6 (saddr), CY ← (saddr) – byte – CY × × × A, r 2 4 A, CY ← A – r – CY × × × A, saddr 2 4 A, CY ← A – (saddr) – CY × × × A, !addr16 3 8 A, CY ← A – (addr16) – CY × × × A, [HL] 1 6 A, CY ← A – (HL) – CY × × × A, [HL + byte] 2 6 A, CY ← A – (HL + byte) – CY × × × ADDC SUB SUBC Note Note Only when rp = BC, DE, HL Remark One clock of an instruction is one clock of the CPU clock (fCPU) selected using the processor clock control register (PCC). Data Sheet U14022EJ1V0DS00 23 µPD78F9177, 78F9177Y Flags Mnemonic Operand Bytes Clock Operation Z AND A, #byte 2 4 A ← A ∧ byte × saddr, #byte 3 6 (saddr) ← (saddr) ∧ byte × A, r 2 4 A←A∧r × A, saddr 2 4 A ← A ∧ (saddr) × A, !addr16 3 8 A ← A ∧ (addr16) × AC CY A, [HL] 1 6 A ← A ∧ (HL) × A, [HL + byte] 2 6 A ← A ∧ (HL + byte) × A, #byte 2 4 A ← A ∨ byte × saddr, #byte 3 6 (saddr) ← (saddr) ∨ byte × A, r 2 4 A←A∨r × A, saddr 2 4 A ← A ∨ (saddr) × A, !addr16 3 8 A ← A ∨ (addr16) × A, [HL] 1 6 A ← A ∨ (HL) × A, [HL + byte] 2 6 A ← A ∨ (HL + byte) × A, #byte 2 4 A ← A ∨ byte × saddr, #byte 3 6 (saddr) ← (saddr) ∨ byte × A, r 2 4 A←A∨r × A, saddr 2 4 A ← A ∨ (saddr) × A, !addr16 3 8 A ← A ∨ (addr16) × A, [HL] 1 6 A ← A ∨ (HL) × A, [HL + byte] 2 6 A ← A ∨ (HL + byte) × A, #byte 2 4 A – byte × × × saddr, #byte 3 6 (saddr) – byte × × × A, r 2 4 A–r × × × A, saddr 2 4 A – (saddr) × × × A, !addr16 3 8 A – (addr16) × × × A, [HL] 1 6 A – (HL) × × × A, [HL + byte] 2 6 A – (HL + byte) × × × ADDW AX, #word 3 6 AX, CY ← AX + word × × × SUBW AX, #word 3 6 AX, CY ← AX – word × × × CMPW AX, #word 3 6 AX – word × × × INC r 2 4 r←r+1 × × saddr 2 4 (saddr) ← (saddr) + 1 × × r 2 4 r ← r– 1 × × saddr 2 4 (saddr) ← (saddr) – 1 × × OR XOR CMP DEC Remark One clock of an instruction is one clock of the CPU clock (fCPU) selected using the processor clock control register (PCC). 24 Data Sheet U14022EJ1V0DS00 µPD78F9177, 78F9177Y Flags Mnemonic Operand Bytes Clock Operation Z AC CY INCW rp 1 4 rp ← rp + 1 DECW rp 1 4 rp ← rp – 1 ROR A, 1 1 2 (CY, A7 ← A0, Am-1 ← Am) × 1 × ROL A, 1 1 2 (CY, A0 ← A7, Am+1 ← Am) × 1 × RORC A, 1 1 2 (CY ← A0, A7 ← CY, Am-1 ← Am) × 1 × ROLC A, 1 1 2 (CY ← A7, A0 ← CY, Am+1 ← Am) × 1 × SET1 saddr.bit 3 6 (saddr.bit) ← 1 sfr.bit 3 6 sfr.bit ← 1 A.bit 2 4 A.bit ← 1 PSW.bit 3 6 PSW.bit ← 1 [HL].bit 2 10 (HL).bit ← 1 saddr.bit 3 6 (saddr.bit) ← 0 sfr.bit 3 6 sfr.bit ← 0 A.bit 2 4 A.bit ← 0 PSW.bit 3 6 PSW.bit ← 0 [HL].bit 2 10 (HL).bit ← 0 SET1 CY 1 2 CY ← 1 1 CLR1 CY 1 2 CY ← 0 0 NOT1 CY 1 2 CY ← CY × CALL !addr16 3 6 (SP – 1) ← (PC + 3)H, (SP – 2) ← (PC + 3)L, PC ← addr16, SP ←SP – 2 CALLT [addr5] 1 8 (SP – 1) ← (PC + 1)H, (SP – 2) ← (PC + 1)L, PCH ← (00000000, addr5 + 1) PCL ← (00000000, addr5) SP ← SP – 2 RET 1 6 PCH ← (SP + 1), PCL ← (SP), SP ← SP + 2 RETI 1 8 PCH ← (SP + 1), PCL ← (SP), PSW ← (SP + 2), SP ← SP + 3, NMIS ← 0 PSW 1 2 (SP – 1) ← PSW, SP ← SP – 1 rp 1 4 (SP – 1) ← rpH, (SP – 2) ← rpL, SP ← SP -– 2 PSW 1 4 PSW ← (SP), SP ← SP + 1 rp 1 6 rpH ← (SP + 1), rpL ← (SP), SP ← SP + 2 SP, AX 2 8 SP ← AX AX, SP 2 6 AX ← SP CLR1 PUSH POP MOVW Remark × × × × × × R R R R R R One clock of an instruction is one clock of the CPU clock (fCPU) selected using the processor clock control register (PCC). Data Sheet U14022EJ1V0DS00 25 µPD78F9177, 78F9177Y Flags Mnemonic Operand Bytes Clock Operation Z !addr16 3 6 PC ← addr16 $addr16 2 6 PC ← PC + 2 + jdisp8 AX 1 6 PCH ← A, PCL ← X BC $addr16 2 6 PC ← PC + 2 + jdisp8 if CY = 1 BNC $addr16 2 6 PC ← PC + 2 + jdisp8 if CY = 0 BZ $addr16 2 6 PC ← PC + 2 + jdisp8 if Z = 1 BNZ $addr16 2 6 PC ← PC + 2 + jdisp8 if Z = 0 BT saddr.bit, $saddr16 4 10 PC ← PC + 4 + jdisp8 if (saddr. bit) = 1 sfr.bit, $addr16 4 10 PC ← PC + 4 + jdisp8 if sfr. bit = 1 A.bit, $saddr16 3 8 PC ← PC + 3 + jdisp8 if A. bit = 1 PSW.bit $addr16 4 10 PC ← PC + 4 + jdisp8 if PSW. bit = 1 saddr.bit, $addr16 4 10 PC ← PC + 4 + jdisp8 if (saddr. bit) = 0 sfr.bit, $addr16 4 10 PC ← PC + 4 + jdisp8 if sfr. bit = 0 A.bit, $addr16 3 8 PC ← PC + 3 + jdisp8 if A. bit = 0 PSW.bit, $addr16 4 10 PC ← PC + 4 + jdisp8 if PSW. bit = 0 B, $addr16 2 6 B ← B – 1, then PC ← PC + 2 + jdisp8 if B ≠ 0 C, $addr16 2 6 C ← C – 1, then PC ← PC + 2 + jdisp8 if C ≠ 0 saddr, $addr16 3 8 (saddr) ← (saddr) – 1, then PC ← PC + 3 + jdisp8 if (saddr) ≠ 0 NOP 1 2 No Operation EI 3 6 IE ← 1 (Enable Interrupt) DI 3 6 IE ← 0 (Disable Interrupt) HALT 1 2 Set HALT Mode STOP 1 2 Set Stop Mode BR BF DBNZ Remark One clock of an instruction is one clock of the CPU clock (fCPU) selected using the processor clock control register (PCC). 26 AC CY Data Sheet U14022EJ1V0DS00 µPD78F9177, 78F9177Y 7. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25°°C) Parameter Supply voltage Symbol VDD Conditions AVDD − 0.3 V ≤ VDD ≤ AVDD + 0.3 V AVREF AVREF ≤ VDD + 0.3 V V V −0.3 to VDD + 0.3 V Pins other than P50 to P53, P23, P24 VI2 P23, P24 −0.3 to +5.5 V VI3 P50 to P53 −0.3 to +13 V −0.3 to VDD + 0.3 V Per pin −10 mA Total for all pins −30 mA Per pin 30 mA Total for all pins 160 mA In normal operation mode −40 to +85 °C During flash memory programming +10 to +40 °C −40 to +125 °C IOH Caution −0.3 to +10.5 VI1 Output current, high Storage temperature V V VO Operating ambient temperature −0.3 to +6.5 AVREF ≤ AVDD + 0.3 V Output voltage Output current, low Unit AVDD VPP Input voltage Ratings IOL TA Tstg Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins. Data Sheet U14022EJ1V0DS00 27 µPD78F9177, 78F9177Y Main System Clock Oscillator Characteristics (TA = −40 to +85 °C, VDD = 1.8 to 5.5 V) Resonator Recommended Circuit Parameter Conditions Note 1 Ceramic Oscillation frequency (fX) VPP X1 resonator X2 Oscillation stabilization time C2 1.0 TYP. MAX. Unit 5.0 MHz 4 ms 5.0 MHz 10 ms voltage range Note 2 C1 VDD = oscillation MIN. After VDD reaches oscillation voltage range MIN. Note 1 Crystal VPP X1 X2 Oscillation frequency (fX) 1.0 resonator C1 C2 Note 2 Oscillation stabilization time VDD = 4.5 to 5.5 V 30 Note 1 External X1 X2 X1 input frequency (fX) 1.0 5.0 MHz X1 input high-/low-level width 85 500 ns clock (tXH, tXL) Note 1 X1 X1 input frequency (fX) VDD = 2.7 to 5.5 V 1.0 5.0 MHz X1 input high-/low-level width VDD = 2.7 to 5.5 V 85 500 ns X2 OPEN (tXH, tXL) Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. 2. Time required to stabilize oscillation after reset or STOP mode release. Use a resonator that stabilizes oscillation within the oscillation wait time. Cautions 1. When using the main system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. • Keep the wiring length as short as possible. • Do not cross the wiring with the other signal lines. • Do not route the wiring near a signal line through which a high fluctuating current flows. • Always make the ground point of the oscillator capacitor the same potential as VSS0. • Do not ground the capacitor to a ground pattern through which a high current flows. • Do not fetch signals from the oscillator. 2. When the main system clock is stopped and the device is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock. Remark For the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. 28 Data Sheet U14022EJ1V0DS00 µPD78F9177, 78F9177Y Subsystem Clock Oscillator Characteristics (TA = −40 to +85 °C, VDD = 1.8 to 5.5 V) Resonator Recommended Circuit Parameter Conditions Note 1 Crystal VPP XT1 resonator C3 XT2 R C4 Oscillation frequency (fXT) Note 2 Oscillation stabilization time XT1 XT2 TYP. MAX. Unit 32 32.768 35 kHz 1.2 2 s 10 s 32 35 kHz 14.3 15.6 µs VDD = 4.5 to 5.5 V Note 1 External MIN. XT1 input frequency (fXT) clock XT1 input high-/low-level width (tXTH, tXTL) Notes 1. Indicates only oscillator characteristics. Refer AC Characteristics for instruction execution time. 2. Time required to stabilize oscillation after reset or STOP mode release. Cautions 1. When using the subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. • Keep the wiring length as short as possible. • Do not cross the wiring with the other signal lines. • Do not route the wiring near a signal line through which a high fluctuating current flows. • Always make the ground point of the oscillator capacitor the same potential as VSS0. • Do not ground the capacitor to a ground pattern through which a high current flows. • Do not fetch signals from the oscillator. 2. The subsystem clock oscillator is designed as a low-amplitude circuit for reducing current consumption, and is more prone to malfunction due to noise than the main system clock oscillator. Particular care is therefore required with the wiring method when the subsystem clock is used. Remark For the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. Data Sheet U14022EJ1V0DS00 29 µPD78F9177, 78F9177Y DC Characteristics (TA = −40 to +85°°C, VDD = 1.8 to 5.5 V) Parameter Output current, Symbol IOH high Conditions MIN. TYP. MAX. Unit −1 mA −15 mA 10 mA 80 mA 0.7 VDD 0.9 VDD 0.7 VDD 0.9 VDD VDD VDD 12 12 V V V V 0.8 VDD 0.9 VDD VDD VDD V V VDD VDD 0.3 VDD 0.1 VDD 0.3 VDD 0.1 VDD 0.2 VDD 0.1 VDD 0.4 0.1 V V V V V V V V V V V Per pin Total for all pins Output current, low IOL Per pin Total for all pins Input voltage, high VIH1 P00 to P05, P10, P11,P60 to P67 VDD = 2.7 to 5.5 V VIH2 P50 to P53 VIH3 VDD = 2.7 to 5.5 V VDD = 1.8 to 5.5 V, TA = 25 to +85°C VDD = 2.7 to 5.5 V RESET, P20 to P26, P30 to P33 X1, X2, XT1, XT2 VDD = 4.5 to 5.5 V VIL1 P00 to P05, P10, P11, P60 to P67 VDD = 2.7 to 5.5 V VIL2 P50 to P53 VDD = 2.7 to 5.5 V VIL3 RESET,P20 to P26, P30 to P33 VDD = 2.7 to 5.5 V VIL4 X1, X2, XT1, XT2 VDD = 4.5 to 5.5 V VOH Pins other than P23, P24, P50 to P53 VDD = 4.5 to 5.5 V, IOH = −1 mA VDD − 0.5 VDD − 0.1 0 0 0 0 0 0 0 0 VDD − 1.0 VDD = 1.8 to 5.5 V, IOH = −100 µA VDD − 0.5 VOL1 Pins other than P50 to P53 VOL2 P50 to P53 ILIH1 VI = VDD ILIH2 ILIH3 ILIL1 VI = 12 V VI = 0 V VDD = 4.5 to 5.5 V, IOL = 10 mA VDD = 1.8 to 5.5 V, IOL = 400 µA VDD = 4.5 to 5.5 V, IOL = 10 mA VDD = 1.8 to 5.5 V, IOL = 1.6 mA Pins other than P50 to P53 (N-ch open-drain) X1, X2, XT1, and XT2 X1, X2, XT1, XT2 P50 to P53 (N-ch open drain) Pins other than P50 to P53 (N-ch open-drain) X1, X2, XT1, and XT2 X1, X2, XT1, XT2 P50 to P53 (N-ch open drain) VIH4 Input voltage, low Output voltage, high Output voltage, low Input leakage current, high Input leakage current, low ILIL2 ILIL3 V 1.0 0.5 1.0 0.4 3 V V V V µA 20 20 −3 µA µA µA −20 µA µA Note −3 Output leakage current, high ILOH VO = VDD 3 µA Output leakage current, low ILOL VO = 0 V −3 µA Software pull-up resistor R1 200 kΩ VI = 0 V, for pins other than P23, P24, and P50 to P53 50 100 Note A low-level input leakage current of -60 µA(MAX.) flows only during the 1-cycle time after a read instruction is executed to P50 to P53 and P50 to P53 are set to input mode. At times other than this, -3 µA (MAX.) current flows. Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins. 30 Data Sheet U14022EJ1V0DS00 µPD78F9177, 78F9177Y DC Characteristics (TA = −40 to +85 °C, VDD = 1.8 to 5.5 V) Parameter Symbol Note 1 Power supply current IDD1 Conditions 5.0-MHz crystal oscillation operating mode (C1 = C2 = 22pF) TYP. MAX. Unit Note 4 MIN. 5.0 15.0 mA Note 5 2.0 5.0 mA Note 5 1.5 3.0 mA Note 4 2.0 6.0 mA Note 5 1.0 2.5 mA Note 5 0.75 1.5 mA VDD = 5.0 V ± 10% 250 750 µA VDD = 3.0 V ± 10% 200 600 µA VDD = 2.0 V ± 10% 150 450 µA VDD = 5.0 V ± 10% VDD = 3.0 V ± 10% VDD = 2.0 V ± 10% Note 1 IDD2 5.0-MHz crystal oscillation HALT mode (C1 = C2 = 22pF) VDD = 5.0 V ± 10% VDD = 3.0 V ± 10% VDD = 2.0 V ± 10% IDD3 Note 1 32.768-kHz crystal oscillation operating Note 3 mode (C3 = C4 = 22pF, R = 220kΩ) IDD4 IDD5 IDD6 Note 1 VDD = 5.0 V ± 10% 50 150 µA oscillation HALT mode (C3 = C4 = 22pF, R = 220kΩ) VDD = 3.0 V ± 10% 30 90 µA VDD = 2.0 V ± 10% 20 60 µA 32.768-kHz crystal stop STOP mode VDD = 5.0 V ± 10% 0.1 30 µA VDD = 3.0 V ± 10% 0.05 10 µA VDD = 2.0 V ± 10% 0.05 10 µA Note 4 6.0 17.0 mA Note 5 3.0 7.0 mA Note 5 2.5 5.0 mA 32.768-kHz crystal Note 3 Note 1 Note 2 5.0-MHz crystal oscillation A/D operating mode (C1 = C2 = 22pF) VDD = 5.0 V ± 10% VDD = 3.0 V ± 10% VDD = 2.0 V ± 10% Notes 1. The AVREFON (ADCS0 (bit 7 of ADM0; A/D converter mode register 0) = 1), AVDD, and the port current (including the current flowing through the internal pull-up resistors) are not included. 2. The AVREFOn (ADCS0 =1) and port current (including the current flowing through the internal pull-up resistors) are not included. Refer to the A/D converter characteristics for the current flowing through AVREF. 3. When the main system clock is stopped. 4. During high-speed mode operation (when the processor clock control register (PCC) is set to 00H.) 5. During low-speed mode operation (when PCC is set to 02H) Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins. Data Sheet U14022EJ1V0DS00 31 µPD78F9177, 78F9177Y AC Characteristics (1) Basic operation (TA = −40 to +85°°C, VDD = 1.8 to 5.5 V) Parameter Symbol Cycle time (minimum instruction execution time) TCY Conditions Operation based on the main system clock MIN. VDD = 2.7 to 5.5 V Operation based on the subsystem clock TI80 and TI81 input frequency fTI TI80 and TI81 input high-/low-level width tTIH, tTIL Interrupt input high/low-level width TYP. MAX. Unit 0.4 8 µs 1.6 8 µs 125 µs 0 4 MHz 0 275 kHz 114 VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V tINTH, tINTL INTP0 to INTP3 122 0.1 µs 1.8 µs 10 µs RESET input lowlevel width tRSL 10 µs CPT90 input high/low-level width tCPH, tCPL 10 µs TCY vs VDD (main system clock) 60 Cycle time TCY [ µ s] 10 Guaranteed operation range 2.0 1.0 0.5 0.4 0.1 1 2 3 4 5 Supply voltage VDD [V] 32 Data Sheet U14022EJ1V0DS00 6 µPD78F9177, 78F9177Y (2) Serial interface (TA = −40 to +85 °C, VDD = 1.8 to 5.5 V) (a) 3-wire serial I/O mode (SCK20...Internal clock) Parameter Symbol SCK20 cycle time tKCY1 SCK20 high-/lowlevel width tKH1, tKL1 SI20 setup time (to SCK20 ↑) tSIK1 SI20 hold time (from SCK20 ↑) tKSI1 SO20 output delay time from SCK20↓ tKSO1 Conditions VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V R = 1 kΩ, C = 100 pF VDD = 2.7 to 5.5 V MIN. TYP. MAX. Unit 800 ns 3200 ns tKCY1/2−50 ns tKCY1/2−150 ns 150 ns 500 ns 400 ns 600 ns 0 250 ns 0 1000 ns MAX. Unit Note Note R and C are the load resistance and load capacitance of the SO20 output line. (b) 3-wire serial I/O mode (SCK20...External clock) Parameter Symbol SCK20 cycle time tKCY2 SCK20 high-/lowlevel width tKH2, tKL2 SI20 setup time (to SCK20 ↑) tSIK2 SI20 hold time (from SCK20 ↑) tKSI2 SO20 output delay time from SCK20 ↓ tKSO2 SO20 setup time (when using SS20, to SS20 ↓) tKAS2 SO20 disable time (when using SS20, from SS20 ↑) tKDS2 Conditions VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V R = 1 kΩ, C = 100 pF VDD = 2.7 to 5.5 V MIN. TYP. 900 ns 3500 ns 400 ns 1600 ns 100 ns 150 ns 400 ns 600 ns 0 300 ns 0 1000 ns 120 ns 400 ns 240 ns 800 ns MAX. Unit 78125 bps 19531 bps Note VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V Note R and C are the load resistance and load capacitance of the SO20 output line. (c) UART mode (dedicated baud rate generator output) Parameter Transfer rate Symbol Conditions VDD = 2.7 to 5.5 V Data Sheet U14022EJ1V0DS00 MIN. TYP. 33 µPD78F9177, 78F9177Y (d) UART mode (external clock input) Parameter ASCK20 cycle time ASCK20 high-/lowlevel width Symbol tKCY3 tKH3, tKL3 Transfer rate ASCK20 rise time, fall time 34 Conditions VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V tR, tF Data Sheet U14022EJ1V0DS00 MIN. TYP. MAX. Unit 900 ns 3500 ns 400 ns 1600 ns 39063 bps 9766 bps 1 µs µPD78F9177, 78F9177Y (3) Serial interface SMB0 (TA = −40 to +85 °C, VDD = 1.8 to 5.5 V) (µPD78F9177Y only) (a) DC Characteristics Parameter Symbol Conditions Input voltage, high VIH SCL0, SDA0 (at hysteresis) Input voltage, low VIL SCL0, SDA0 (at hysteresis) Output voltage, high VOL SCL0, SDA0 Input leakage current, high ILIH SCL0, SDA0 Input leakage current, low ILIL SCL0, SDA0 MIN. TYP. MAX. Unit 0.8 VDD VDD V 0 0.2 VDD V VDD = 4.5 to 5.5 V, IOL = 10 mA 1.0 V VDD = 1.8 to 5.5 V, IOL = 400 µ A 0.5 V VI = VDD 3 µA VI = 0 V −3 µA MAX. Unit 5.5 V (b) DC Characteristics (When using comparator) Parameter Symbol Conditions MIN. TYP. Input range VSDA, VSCL VDD = 1.8 to 5.5 V 0 Transfer level VISDA, VISCL 4.5 ≤ VDD ≤ 5.5 V 0.72 VISMB VISMB 1.28 VISMB V 3.3 ≤ VDD < 4.5 V 0.78 VISMB VISMB 1.22 VISMB V 2.7 ≤ VDD < 3.3 V 0.75 VISMB VISMB 1.25 VISMB V 1.8 ≤ VDD < 2.7 V 0.90 VISMB VISMB 1.45 VISMB V Input level threshold value VISMB LVL01, LVL00 = 0, 1 0.25 × VDD V LVL01, LVL00 = 1, 0 0.375 × VDD V LVL01, LVL00 = 1, 1 0.5 × VDD V Note VISMB is an input level threshold value selected by bits LVL00 and LVL01 (bits 0 and 1 of SMB input level setting register 0 (SMBVI0)). According to the SMB standard (V1.1), the maximum value of low-level input voltage is 0.8 V, and the minimum value of high-level input voltage, 2.1 V. To satisfy these conditions, set LVL01 and LVL00 as follows; • When VDD = 1.8 to 3.3 V: LVL01, LVL00 = 1, 1 (0.5 × VDD) • When VDD = 3.3 to 4.5 V: LVL01, LVL00 = 1, 0 (0.375 × VDD) • When VDD = 4.5 to 5.5 V: LVL01, LVL00 = 0, 1 (0.25 × VDD) "LVL01, LVL00 = 0, 0" is not available since this setting does not satisfy the SMB standard (V1.1). Data Sheet U14022EJ1V0DS00 35 µPD78F9177, 78F9177Y (c) AC Characteristics 2 SMB Mode Parameter 2 Standard Mode I C High-speed Mode I C Bus Bus Symbol Unit MIN. MAX. MIN. MAX. MIN. MAX. SCL0 clock frequency fCLK 10 100 0 100 0 400 kHz Bus free time tBUF 4.7 − 4.7 − 1.3 − µs Hold time tHD:STA 4.0 − 4.0 − 0.6 − µs Start/restart condition setup time tSU:STA 4.7 − 4.7 − 0.6 − µs Stop condition setup time tSU:STO 4.0 − 4.0 − 0.6 − µs Data hold When using CBUScompatible master time tHD:DAT − − 5 − − − µs 300 − − − 0 100 (between stop and start condition) Note1 When using SMB/IIC bus Note2 Note3 900 Note4 ns − ns 1.3 − µs − 0.6 − µs − 300 − 300 ns 1000 − 1000 − 300 ns − − − − 0 50 ns tTIMEOUT 25 35 − − − − ms Total extended time of SCL0 clock low-level period (slave) tLOW:SEXT − 25 − − − − ms Total extended time of cumulative clock low-level period (master) tLOW:MEXT − 10 − − − − ms Capacitive load per each bus line Cb − − − 400 − 400 pF Data setup time tSU:DAT 250 − 250 − SCL0 clock low-level width tLOW 4.7 − 4.7 − SCL0 clock high-level width tHIGH 4.0 50 4.0 SCL0 and SDA0 signal fall time tF − 300 SCL0 and SDA0 signal rise time tR − Spike pulse width controlled by input filter tSP Timeout Notes 1. In the start condition, the first clock pulse is generated after this hold time. 2. To fill in the underfined area of the SCL0 falling edge, it is necessary for the device to internally provide at least 300 ns of hold time for the SDA0 signal (which is V IHmin. of the SCL0 signal). 3. If the device does not extend the SCL0 signal low hold time (tLOW), only maximum data hold time tHD:DAT needs to be fulfilled. 2 2 4. The high-speed mode I C bus is available in the SMB mode and the standard mode I C bus system. At this time, the conditions described below must be satisfied. If the device extends the SCL0 signal low state hold time tSU:DAT ≥ 250 ns If the device extends the SCL0 signal low state hold time Be sure to transmit the next data bit to the SDA0 line before the SCL0 line is released (tRmax.+ 2 tSU:DAT = 1000 + 250 = 1250 ns by the SMB mode or the standard mode I C bus specification). 36 Data Sheet U14022EJ1V0DS00 µPD78F9177, 78F9177Y AC Timing Measurement Points (excluding the X1 and XT1 inputs) 0.8 VDD 0.8 VDD Point of measurement 0.2 VDD 0.2 VDD Clock Timing 1/fX tXL tXH VIH4 (MIN.) X1 input VIL4 (MAX.) 1/fXT tXTL tXTH VIH4 (MIN.) XT1 input VIL4 (MAX.) TI Timing 1/fTI tTIL t TIH TI80, TI81 Data Sheet U14022EJ1V0DS00 37 µPD78F9177, 78F9177Y Interrupt Input Timing tINTL tINTH INTP0-INTP3 RESET Input Timing tRSL RESET CPT90 Input Timing tCPL CPT90 38 Data Sheet U14022EJ1V0DS00 tCPH µPD78F9177, 78F9177Y Serial Transfer Timing 3-wire serial I/O mode: tKCYm tKHm tKLm SCK20 tSIKm tKSIm Input data SI20 tKSOm Output data SO20 Remark m = 1, 2 3-wire serial I/O mode (when using SS20): SS20 tKAS2 tKDS2 SO20 Output data UART mode (external clock input): tKCY3 tKL3 tKH3 tR tF ASCK20 Data Sheet U14022EJ1V0DS00 39 µPD78F9177, 78F9177Y SMB mode: tLOW tR SCL0 tHD:DAT tHD:STA tHIGH tF tSU:STA tHD:STA tSP tSU:STO tSU:DAT SDA0 tBUF Stop condition Start condition 40 Restart condition Data Sheet U14022EJ1V0DS00 Stop condition µPD78F9177, 78F9177Y 10-Bit A/D Converter Characteristics (TA = −40 to +85 °C, 1.8 ≤ AVREF ≤ AVDD = VDD ≤ 5.5 V, AVSS = VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit 10 10 10 bit 4.5 V ≤ AVREF ≤ AVDD ≤ 5.5 V ±0.2 ±0.4 %FSR 2.7 V ≤ AVREF ≤ AVDD ≤ 5.5 V ±0.4 ±0.6 %FSR 1.8 V ≤ AVREF ≤ AVDD ≤ 5.5 V ±0.8 ±1.2 %FSR Resolution Note Overall error Conversion time Zero-scale error tCONV Note Note Full-scale error Integral linearity INL Note error Differential linearity DNL Note error 4.5 V ≤ AVREF ≤ AVDD ≤ 5.5 V 14 100 µs 2.7 V ≤ AVREF ≤ AVDD ≤ 5.5 V 14 100 µs 1.8 V ≤ AVREF ≤ AVDD ≤ 5.5 V 28 100 µs 4.5 V ≤ AVREF ≤ AVDD ≤ 5.5 V ±0.4 %FSR 2.7 V ≤ AVREF ≤ AVDD ≤ 5.5 V ±0.6 %FSR 1.8 V ≤ AVREF ≤ AVDD ≤ 5.5 V ±1.2 %FSR 4.5 V ≤ AVREF ≤ AVDD ≤ 5.5 V ±0.4 %FSR 2.7 V ≤ AVREF ≤ AVDD ≤ 5.5 V ±0.6 %FSR 1.8 V ≤ AVREF ≤ AVDD ≤ 5.5 V ±1.2 %FSR 4.5 V ≤ AVREF ≤ AVDD ≤ 5.5 V ±2.5 LSB 2.7 V ≤ AVREF ≤ AVDD ≤ 5.5 V ±4.5 LSB 1.8 V ≤ AVREF ≤ AVDD ≤ 5.5 V ±8.5 LSB 4.5 V ≤ AVREF ≤ AVDD ≤ 5.5 V ±1.5 LSB 2.7 V ≤ AVREF ≤ AVDD ≤ 5.5 V ±2.0 LSB 1.8 V ≤ AVREF ≤ AVDD ≤ 5.5 V ±3.5 LSB VIAN 0 AVREF V Reference voltage AVREF 1.8 AVDD V Resistance between AVREF and AVSS RAIREF 20 Analog input voltage 40 kΩ Note Excludes quantization error (±0.05%FSR). Remark FSR: Full scale range Data Sheet U14022EJ1V0DS00 41 µPD78F9177, 78F9177Y FLASH MEMORY WRITE/DELETE CHARACTERISTICS (TA = 10 to 40 °C, VDD = 1.8 to 5.5 V) Parameter Write current (VDD pin) IDDW Note TYP. When VPP supply voltage = VPP1 MAX. Unit 18 mA IPPW When VPP supply voltage = VPP1 7.5 mA IDDE When VPP supply voltage = VPP1 18 mA 100 mA 1 s 20 s Note (5.0-MHz crystal oscillation operation mode) Delete current (VPP pin) MIN. Note Delete current (VDD pin) Conditions (5.0-MHz crystal oscillation operation mode) Write current (VPP pin) Symbol IPPE When VPP supply voltage = VPP1 Note Unit delete time ter Total delete time tera Write count 0.5 1 Delete/write are regarded as 1 cycle VPP supply voltage VPP0 In normal operation VPP1 During flash memory programming 0 9.7 10.0 20 Times 0.2VDD V 10.3 V Note The current flowing to the ports (including the current flowing through an on-chip pull-up resistor) and AVDD current are not included. Data Memory Stop Mode Low Power Supply Voltage Data Retention Characteristics (TA = −40 to +85 °C) Parameter Symbol Conditions MIN. Data retention power supply voltage VDDDR 1.8 Release signal set time tSREL 0 Oscillation stabilization Note 1 wait time tWAIT Release by RESET Release by interrupt request TYP. MAX. Unit 5.5 V µs 15 2 /fX s Note 2 s Notes 1. The oscillation stabilization time is the time the CPU operation is stopped to prevent unstable 2. By using bits 0 to 2 (OSTS0 to OSTS2) of the oscillation stabilization time selection register (OSTS), operation when oscillation starts. 212/fX, 215/fX, or 217/fX can be selected. Remark 42 fX: Main system clock oscillation frequency Data Sheet U14022EJ1V0DS00 µPD78F9177, 78F9177Y Data Retention Timing (STOP Mode Release by RESET) Internal reset operation HALT mode STOP mode Operating mode Data retention mode VDD VDDDR tSREL STOP instruction execution RESET tWAIT Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal) HALT mode STOP mode Operating mode Data retention mode VDD VDDDR tSREL STOP instruction execution Standby release signal (interrupt request) tWAIT Data Sheet U14022EJ1V0DS00 43 µPD78F9177, 78F9177Y 8. CHARACTERISTICS CURVES (TA = 25 ˚C) 10.0 Main system clock operating mode (PCC1 = 0, CSS0 = 0) Main system clock operating mode (PCC1 = 1, CSS0 = 0) 1.0 Main system clock operation HALT mode (PCC1 = 1, CSS0 = 0) Supply current IDD (mA) 0.5 Main system clock operation HALT mode (PCC1 = 1, CSS0 = 0) Subsystem clock operating mode (CSS0 = 1, MCC = 1) 0.1 0.05 Subsystem clock operation HALT mode (CSS0 = 1, MCC = 1) 0.01 XT2 X2 XT1 Crystal Crystal resonator resonator 220 kΩ 5.0 MHz 32.768 kHz X1 0.005 22 pF 22 pF 33 pF VSS 33 pF VSS 0.001 0 1 2 3 4 5 Supply voltage VDD (V) 44 Data Sheet U14022EJ1V0DS00 6 7 8 µPD78F9177, 78F9177Y 9. PACKAGE DRAWING 44 PIN PLASTIC QFP (10x10) A B detail of lead end 23 22 33 34 S P C T D R 12 11 44 1 L U Q F J G H I M K M N S S NOTE ITEM Each lead centerline is located within 0.16 mm of its true position (T.P.) at maximum material condition. A 12.0±0.2 B 10.0±0.2 C 10.0±0.2 D 12.0±0.2 F 1.0 G 1.0 H 0.37 +0.08 −0.07 I 0.2 J 0.8 (T.P.) K 1.0±0.2 L 0.5 M 0.17 +0.03 −0.06 N 0.10 P Q 1.4±0.05 0.1±0.05 R 3° +4° −3° S U Data Sheet U14022EJ1V0DS00 MILLIMETERS 1.6 MAX. 0.6±0.15 S44GB-80-8ES-1 45 µPD78F9177, 78F9177Y 48-PIN PLASTIC TQFP (FINE PITCH) (7x7) A B detail of lead end 25 24 36 37 S P C T D R 48 13 12 1 L U Q F G J H I M K S N S M NOTE ITEM Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition. A MILLIMETERS 9.0±0.2 B 7.0±0.2 C 7.0±0.2 D F 9.0±0.2 0.75 G 0.75 H 0.22 +0.05 −0.04 I 0.10 J 0.5 (T.P.) K L 1.0±0.2 0.5±0.2 0.17 +0.03 −0.07 M N 0.08 P 1.0±0.1 Q 0.1±0.05 3°+4° −3° R S 1.27 MAX. P48GA-50-9EU 46 Data Sheet U14022EJ1V0DS00 µPD78F9177, 78F9177Y 10. RECOMMENDED SOLDERING CONDITIONS The µPD78F9177 and µPD789177Y should be soldered and mounted under the following recommended conditions. For the details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact your NEC sales representative. Table 10-1. Surface Mounting Type Soldering Conditions (1/2) µPD78F9177GB-8ES: 44-pin plastic LQFP (10 × 10) µPD78F9177YGB-8ES: 44-pin plastic LQFP (10 × 10) Soldering Method Recommended Condition Symbol Soldering Conditions Infrared reflow Package peak temperature: 235 °C, Time: 30 seconds max. (at 210 °C or higher), Count: Twice or less IR35-00-2 VPS Package peak temperature: 215 °C, Time: 40 seconds max. (at 200 °C or higher), Count: Twice or less VP15-00-2 Wave soldering Solder bath temperature: 260 °C max., Time: 10 seconds max., Count: Once, Preheating temperature: 120 °C max. (package surface temperature) WS60-00-1 Partial heating Pin temperature: 300 °C max., Time: 3 seconds max. (per pin row) Caution − Do not use different soldering methods together (except for partial heating). Table 10-1. Surface Mounting Type Soldering Conditions (2/2) µPD78F9177YGA-9EU: 48-pin plastic TQFP (7 × 7) Soldering Method Infrared reflow Soldering Conditions Package peak temperature: 235 °C, Time: 30 seconds max. Note (at 210 °C or higher), Count: Twice or less, Number of days:3 (After Recommended Condition Symbol IR35-103-2 that, prebaking sis necessary at 125 °C for 10 hours) Package peak temperature: 215 °C, Time: 40 seconds max. Note (at 200 °C or higher), Count: Twice or less, Number of days:3 (After VPS VP15-103-2 that, prebaking sis necessary at 125 °C for 10 hours) Partial heating Pin temperature: 300 °C max., Time: 3 seconds max. (per pin row) − Note The number of days for storage at 25°C, 65% RH MAX after the dry pack has been opened. Caution Do not use different soldering methods together (except for partial heating). Data Sheet U14022EJ1V0DS00 47 µPD78F9177, 78F9177Y APPENDIX A. DIFFERENCES BETWEEN µPD78F9177, 78F9177Y, AND MASK ROM VERSIONS The µPD78F9177 and µPD78F9177Y are flash memory version of the Mask ROM version. The differences between the µPD78F9177, 78F9177Y and the Mask ROM versions are shown in Table A-1. Table A-1. Differences between µPD78F9177, 78F9177Y and Mask ROM Versions Product Name Flash Memory Version µPD78F9177, 78F9177Y Item Internal ROM 24 KB memory High-speed RAM 512 bytes Mask ROM Version µPD789166, 789166Y µPD789167, 789167Y 789176, 789176Y 789177, 789177Y 16 KB 24 KB VPP pin Provided Not provided Pull-up resistor 17 (Software control) 21 (Software control: 17, mask option specification: 4) A/D resolution 10 bits 8 bits (µPD789166, 789167, 789166Y, 789167Y) 10 bits (µPD789176, 789177, 789176Y, 789177Y) Electrical specifications See the relevant data sheet Cautions 1. There are differences in the amount of noise immunity and noise radiation between the flash memory and mask ROM versions. When pre-producing an application set with the flash memory version and then mass producing it with the mask ROM versions, be sure to conduct sufficient evaluations on the commercial samples (CS) (not engineering sample, ES) of the mask ROM version. 2. When the µPD78F9177, a flash memory counterpart of the µPD789166 or µPD789167, is used, however, ADCR0 can be manipulated with an 8-bit memory manipulation instruction. In this case, use an object file assembled with the µPD789166 or µPD789167. The same is also true for the µPD78F9177Y, a flash memory counterpart of the µPD789166Y or µPD789167Y. When the µPD78F9177Y is used, ADCR0 can be manipulated with an 8-bit memory manipulation instruction. In this case, use an object file assembled with the µPD789166Y or µPD789167Y. 48 Data Sheet U14022EJ1V0DS00 µPD78F9177, 78F9177Y APPENDIX B. DEVELOPMENT TOOLS The following development tools are available for developing systems using the µPD78F9177 and µPD78F9177Y. Language Processing Software RA78K0S Notes 1, 2, 3 CC78K0S Assembler package common to 78K/0S Series Notes 1, 2, 3 DF789177 C compiler package common to 78K/0S Series Notes 1, 2, 3 Device file for µPD789167, 789177, 789167Y, and 789177Y Subseries Notes 1, 2, 3 C compiler library source file common to 78K/0S Series CC78K0S-L Flash Memory Writing Tools Flashpro lIl Flash programmer dedicated for on-chip flash memory microcontrollers Note 4 (Part No. FL-PR3 FA-44GB-8ES , PG-FP3) Note 4 Flash memory programming adapter for 44-pin plastic LQFP (GB-8ES type) FA-48GA Flash memory programming adapter for 48-pin plastic TQFP (fine pitch) (GA-9EU type) Debugging Tools(1/2) IE-78K0S-NS In-circuit emulator In-circuit emulator used to debug hardware or software when application systems which use the 78K/0S Series are developed. The IE-78K0S-NS supports an integrated debugger (ID78K0S-NS). The IE-78K0S-NS is used in combination with an interface adapter for connection to an AC adapter, emulation probe, or host machine. IE-70000-MC-PS-B AC adapter Adapter used to supply power from a 100- to 240-V AC outlet IE-70000-98-IF-C Interface adapter Adapter required when using the PC-9800 series (excluding notebook PCs) as the host machine for the IE-78K0S-NS (C bus supported) IE-70000-CD-IF-A PC card/interface PC card and interface cable required when using a notebook PC as the host machine for the IE-78K0S-NS (PCMCIA socket supported) IE-70000-PC-IF-C Interface adapter Adapter required when using an IBM PC/AT IE-70000-PCI-IF Interface adapter Adapter required when using a PC equipped with a PCI bus as the host machine for the IE-78K0S-NS IE-789177-NS-EM1 Emulation board Emulation board used to emulate the peripheral hardware specific to the device. This is used in combination with the in-circuit emulator. NP-44GB TM or compatible as the host machine for the IE-78K0S-NS (ISA bus supported) Note 4 Board to connect an in-circuit emulator to the target system. This is used in combination with the EV-9200G-44 Emulation probe EV-9200G-44 conversion socket Note 4 Conversion socket to connect the target system board on which a 44-pin plastic LQFP can be mounted and the NP-44GB Board to connect an in-circuit emulator to the target system. This is used in combination with the TGB-044SAP. NP-44GB-TQ Emulation probe TGB-044SAP Note 5 conversion socket Conversion socket to connect the target system board on which a 44-pin plastic LQFP can be mounted and the NP-44GB-TQ Data Sheet U14022EJ1V0DS00 49 µPD78F9177, 78F9177Y Debugging Tools(2/2) NP-48GA Note 4 Board to connect an in-circuit emulator to the target system. This is used in combination with the TGA-048SDP. Emulation probe TGA-048SDP Note 5 conversion socket SM78K0S Notes 1, 2 ID78K0S-NS DF789177 Conversion socket to connect the target system board on which a 48-pin plastic TQFP (fine pitch) can be mounted and the NP-48GA System simulator common to 78K/0S Series Notes 1, 2 Integrated debugger common to 78K/0S Series Notes 1, 2 Device file for µPD789167, 789177, 789167, and 789177Y Subseries Real-Time OS MX78K0S Notes 1, 2 OS for 78K/0S Series TM Notes 1. Based on the PC-9800 series (Japanese Windows ) 2. Based on IBM PC/AT and compatibles (Japanese Windows/English Windows) 3. Based on the HP9000 series 700 TM TM (HP-UX ), SPARCstation TM TM TM (NEWS-OS ) 4. Product made by and available from Naito Densei Machida Mfg. Co., Ltd. (+81-44-822-3813). 5. Product made by TOKYO ELETECH CORPORATION. Refer to: Daimaru Kogyo, Ltd. Tokyo Electronic Division (+81-3-3820-7112) Osaka Electronic Division (+81-6-6244-6672) Remark 50 The RA78K0S, CC78K0S, and SM78K0S can be used in combination with the DF789177. Data Sheet U14022EJ1V0DS00 TM (SunOS , Soraris ), and NEWS TM µPD78F9177, 78F9177Y APPENDIX C. RELATED DOCUMENTS Documents Related to Devices Document Name Document No. Japanese English µPD789166, 167, 176, 177, 166Y, 167Y, 176Y, 177Y, 166(A), 167(A), 176(A), 177(A), 166Y(A), 167Y(A), 176Y(A), 177Y(A) Data Sheet U14017J U14017E µPD78F9177, 78F9177Y Data Sheet U14022J This manual µPD789167, 789177, 789167Y, 789177Y Subseries User’s Manual U14186J U14186E 78K/0S Series Instruction User’s Manual U11047J U11047E Document Related to Development Tools (User’s Manuals) Document Name Document No. Japanese RA78K0S Assembler Package English Operation U11622J U11622E Assembly Language U11599J U11599E Structured Assembly Language U11623J U11623E Operation U11816J U11816E Language U11817J U11817E SM78K0S System Simulator Windows based Reference U11489J U11489E SM78K Series System Simulator External Parts User Open Interface Specifications U10092J U10092E ID78K0S-NS Windows based Reference U12901J U12901E IE-78K0S-NS In-circuit Emulator U13549J U13549E IE-789177-NS-EM1 Emulation Board U14621J U14621E CC78K0S C Compiler Documents Related to Embedded Software (User’s Manuals) Document Name Document No. Japanese OS for 78K/0S Series MX78K0S Caution Fundamental U12938J English U12938E The related documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing. Data Sheet U14022EJ1V0DS00 51 µPD78F9177, 78F9177Y Other Documents Document Name Document No. Japanese English SEMICONDUCTOR SELECTION GUIDE Products & Packages (CD-ROM) X13769X Semiconductor Device Mounting Technology Manual C10535J C10535E Quality Grades on NEC Semiconductor Device C11531J C11531E NEC Semiconductor Device Reliability/Quality Control System C10983J C10983E Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892J C11892E Guide to Microcomputer-Related Products by Third Party U11416J − Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing. The related document indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. 52 Data Sheet U14022EJ1V0DS00 µPD78F9177, 78F9177Y [MEMO] Data Sheet U14022EJ1V0DS00 53 µPD78F9177, 78F9177Y NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. EEPROM is a trademark of NEC Corporation. Windows is either a registered trademark or a trademark of Microsoft Corporation in the United States and/or other countries. PC/AT is a trademark of International Business Machines Corporation. HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. Solaris and SunOS are trademarks of Sun Microsystems, Inc. NEWS and NEWS-OS are trademarks of SONY Corporation. 54 Data Sheet U14022EJ1V0DS00 µPD78F9177, 78F9177Y Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • Ordering information • Product release schedule • Availability of related technical literature • Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) • Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) NEC Electronics (Germany) GmbH NEC Electronics Hong Kong Ltd. Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288 Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics (France) S.A. Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (France) S.A. NEC Electronics Singapore Pte. Ltd. Madrid Office Madrid, Spain Tel: 91-504-2787 Fax: 91-504-2860 United Square, Singapore Tel: 65-253-8311 Fax: 65-250-3583 NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics (UK) Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 NEC Electronics Hong Kong Ltd. NEC Electronics Taiwan Ltd. NEC Electronics Italiana s.r.l. NEC Electronics (Germany) GmbH Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951 NEC do Brasil S.A. Electron Devices Division Guarulhos-SP Brasil Tel: 55-11-6462-6810 Fax: 55-11-6462-6829 J00.7 Data Sheet U14022EJ1V0DS00 55 µPD78F9177, 78F9177Y • The information in this document is current as of August, 2000. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. • No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. • NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. • Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. • While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. • NEC semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above). M8E 00. 4