DATA SHEET MOS INTEGRATED CIRCUIT µPD78F0833Y 8-BIT SINGLE-CHIP MICROCONTROLLERS DESCRIPTION The µPD78F0833Y is a product of the µPD780833Y Subseries in the 78K/0 Series, and equivalent to the µPD780833Y with a flash memory in place of internal ROM. This device can be programmed (write, delete, rewrite) without being removed from the board. Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before designing. µPD780833Y Subseries User's Manual: U13892E 78K/0 Series User’s Manual Instructions: U12326E FEATURES • Pin-compatible with mask ROM versions (except VPP pin) • Flash memory: 60 KB (self-programming supported) • Internal high-speed RAM: 1,024 bytes • Internal expansion RAM: 2,048 bytes • Supply voltage: VDD = 4.5 to 5.5 V Remark For the differences between the flash memory version and the mask ROM version, refer to 4 DIFFERENCES BETWEEN µPD78F0833Y AND MASK ROM VERSION. APPLICATIONS Car audios, etc. ORDERING INFORMATION Part Number µPD78F0833YGC-8BT Package 80-pin plastic QFP (14 × 14) The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. U15013EJ2V0DS00 (2nd edition) Date Published January 2001 N CP(K) Printed in Japan © 2001 µPD78F0833Y 78K/0 SERIES LINEUP The products in the 78K/0 Series are listed below. The names enclosed in boxes are subseries names. Products in mass production Products under development Y subseries products are compatible with I2C bus. 100-pin Control µ PD78075B µ PD78078 100-pin µ PD78070A 100-pin µ PD78054 with timer added and enhanced external interface µ PD78070AY ROMless version of µ PD78078 µPD780018AY 100-pin 80-pin µ PD780058 80-pin µ PD78058F 80-pin µ PD78054 µ PD780065 80-pin µ PD78078 with reduced EMI noise µ PD78078Y µ PD780058Y µ PD78058FY µ PD78054Y µ PD78054 with reduced EMI noise µ PD78018F with UART and D/A added, and enhanced I/O µ PD780024A with expanded RAM µ PD780078Y µ PD780034A with timer added and enhanced serial I/O 64-pin µ PD780078 µPD780034A 64-pin µPD780024A µPD780034AY µPD780024AY 64-pin 64-pin µ PD78014H µ PD78018F µ PD78018FY 42/44-pin µ PD78083 64-pin µ PD78078Y with enhanced serial I/O and limited functions µ PD78054 with enhanced serial I/O µ PD780024A with enhanced A/D µ PD78018F with enhanced serial I/O µ PD78018F with reduced EMI noise Basic subseries for control On-chip UART and capable of low voltage operation (1.8 V) Inverter control 64-pin µ PD780988 100-pin µ PD780208 µ PD78044F with enhanced I/O and VFD C/D. Display output total: 53 80-pin µ PD780232 For panel control. On-chip VFD C/D. Display output total: 53 On-chip inverter controller and UART. Reduced EMI noise. VFD drive 78K/0 Series 80-pin µ PD78044H µ PD78044F with N-ch open drain I/O added. Display output total: 34 80-pin µ PD78044F Basic subseries for driving VFD. Display output total: 34 120-pin LCD drive µ PD780338 120-pin µ PD780328 120-pin µ PD780318 100-pin µ PD780308 100-pin µ PD78064B 100-pin µ PD78064 µ PD780308 with enhanced display function and timer. Segment signal output: 40 pins max. µ PD780308 with enhanced display function and timer. Segment signal output: 32 pins max. µ PD780308 with enhanced display function and timer. Segment signal output: 24 pins max. µ PD780308Y µ PD78064 with enhanced SIO and expanded ROM, RAM µ PD78064 with reduced EMI noise µ PD78064Y Basic subseries for driving LCD. On-chip UART. Bus interface supported 100-pin µ PD780948 80-pin µ PD78098B On-chip DCAN controller µ PD78054 with IEBusTM controller added. Reduced EMI noise. 80-pin µ PD780701Y On-chip DCAN/IEBus controller 80-pin µ PD780833Y On-chip J1850 (CLASS2) controller Meter control 100-pin µ PD780958 For industrial meter control 80-pin µ PD780852 On-chip controller/driver for automobile meter drive 80-pin µ PD780824 For automobile meter drive. On-chip DCAN controller Remark VFD (Vacuum Fluorescent Display) is referred to as FIPTM (Fluorescent Indicator Panel) in some documents, but the functions of the two are the same. 2 Data Sheet U15013EJ2V0DS µPD78F0833Y The major functional differences among the subseries are listed below. Function Subseries Name Control ROM Capacity Timer 8-bit 16-bit Watch WDT A/D µPD78078Y 48 K to 60 K 4 ch µPD78070AY 8-bit 10-bit 8-bit 1 ch 1 ch 1 ch 8 ch A/D – 2 ch 3 ch (UART: 1 ch, – – µPD780058Y 24 K to 60 K 2 ch 1 ch) µPD78058FY 48 K to 60 K 3 ch (UART: 1 ch, µPD78054Y 16 K to 60 K I2C: 1 ch) 2 ch µPD780034AY 8 K to 32 K 1 ch – µPD780024AY 8 ch 8 ch – µPD780308Y 48 K to 60 K 2 ch 1 ch 1 ch 1 ch 8 ch – – – µPD78064Y 16 K to 32 K µPD780701Y 60 K VDD External MIN. Value Expansion 88 1.8 V 61 2.7 V Yes 88 68 1.8 V 69 2.7 V 2.0 V 4 ch (UART: 2 ch, I2C: 1 ch) 52 3 ch (UART: 1 ch, 51 1.8 V I2C: 1 ch) µPD78018FY 8 K to 60 K Bus 3 ch (I2C: 2 ch 3 ch (time-division UART: 1ch, I2C: 1 ch) µPD780078Y 48 K to 60 K I/O D/A I2C: 1 ch) µPD780018AY 48 K to 60 K LCD drive Serial Interface 2 ch (I2C: 1 ch) 53 3 ch (time-division UART: 1 ch, I2C: 1 ch) 57 2.0 V – 4 ch (UART: 1 ch, 67 3.5 V – I2C: 1 ch) 65 4.5 V 2 ch (UART: 1 ch, I2C: 1 ch) 3 ch 2 ch 1 ch 1 ch 16 ch – – interface µPD780833Y supported Data Sheet U15013EJ2V0DS 3 µPD78F0833Y FUNCTION OVERVIEW µPD78F0833Y Item Internal memory 60 KB High-speed RAM 1,024 bytes Expansion RAM 2,048 bytes Memory space 64 KB General-purpose registers 8 bits × 32 registers (8 bits × 8 registers × 4 banks) Minimum instruction execution time On-chip minimum instruction execution time variable function 0.48 µs/0.96 µs/1.92 µs/3.84 µs/7.68 µs (@ 4.19 MHz operation) Instruction set • • • • I/O ports Total: • CMOS input: • TTL input/CMOS output: • N-ch open-drain I/O: A/D converter • 8-bit resolution × 8 channels × 2 Serial interface • • • 3-wire serial I/O mode: 2 channels UART mode: 1 channel I2 C bus mode: 1 channel Timer • • • • 16-bit timer/event counter: 8-bit timer/event counter: Watch timer: Watchdog timer: Timer outputs 5 (8-bit PWM output: 3) Clock output 32.8 kHz, 65.5 kHz, 130.9 kHz, 261.9 kHz, 523.6 kHz, 1.05 MHz, 2.10 MHz, 4.19 MHz (@ 4.19 MHz operation with system clock) Bus controller J1850 (CLASS2) bus interface Vectored interrupts 4 Flash memory 16-bit operation Multiply/divide (8 bits × 8 bits, 16 bits ÷ 8 bits) Bit manipulation (set, reset, test, and Boolean operation) BCD adjust, etc. Maskable Internal: 19 External: 9 Non-maskable Internal: 1 Software 1 65 54 8 3 Power supply voltage VDD = 4.5 to 5.5 V Operating ambient temperature TA = –40 to +85°C Package 80-pin plastic QFP (14 × 14) 2 3 1 1 channels channels channel channel Data Sheet U15013EJ2V0DS µPD78F0833Y CONTENTS 1. PIN CONFIGURATION (TOP VIEW) ................................................................................................... 6 2. BLOCK DIAGRAM ...............................................................................................................................8 3. PIN FUNCTIONS ..................................................................................................................................9 3.1 Port Pins ...................................................................................................................................................... 9 3.2 Non-Port Pins ............................................................................................................................................ 10 3.3 Pin I/O Circuits and Recommended Connection of Unused Pins ..................................................... 12 4. DIFFERENCES BETWEEN µPD78F0833Y AND MASK ROM VERSION ...................................... 16 5. MEMORY SIZE SWITCHING REGISTER (IMS) ............................................................................... 17 6. INTERNAL EXPANSION RAM SIZE SWITCHING REGISTER (IXS) ............................................. 18 7. FLASH MEMORY PROGRAMMING ................................................................................................. 19 7.1 Selection of Communication Mode........................................................................................................ 19 7.2 Flash Memory Programming Functions ................................................................................................ 20 7.3 Flashpro II and Flashpro III Connection ............................................................................................... 20 7.4 Flash Memory Programming by Self Write ........................................................................................... 21 8. ELECTRICAL SPECIFICATIONS ...................................................................................................... 28 9. PACKAGE DRAWING ........................................................................................................................44 10. RECOMMENDED SOLDERING CONDITIONS ................................................................................ 45 APPENDIX A. DEVELOPMENT TOOLS ................................................................................................46 APPENDIX B. RELATED DOCUMENTS ............................................................................................... 51 Data Sheet U15013EJ2V0DS 5 µPD78F0833Y 1. PIN CONFIGURATION (TOP VIEW) • 80-pin plastic QFP (14 × 14) AVSS0 P97/ANI70 P96/ANI60 P95/ANI50 P94/ANI40 P93/ANI30 P92/ANI20 P91/ANI10 P90/ANI00 AVREF0 AVDD0 VDD1 VSS1 X1 X2 VPP RESET C2TX C2RX P67 µPD78F0833YGC-8BT 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 1 59 2 58 3 57 4 56 5 55 6 54 7 53 8 52 9 51 10 50 11 49 12 48 13 47 14 46 15 45 16 44 17 43 18 42 19 41 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 P66 P65 P64 P27/TI51/TO51 P26/ASCK0/TI52/TO52 P25/TxD0 P24/RxD0 P23/TI50/TO50 P07/INTP7 P06/INTP6 P05/INTP5 P04/INTP4 P22/SCK31 P21/SO31 P20/SI31 P57 P56 P55 P54 P53 P40 P41 P42 P43 P44 P45 P46 P47 P30/SI30 P31/SO30 P32/SCK30 VDD0 VSS0 P33 P34/TO00 P35/TI000 PTI010 P50 P51 P52 P70/PCL P71/SDA0 P72/SCL0 P73/TO01 P74/TI001 P75/TI011 P00/INTP0 P01/INTP1 P02/INTP2 P03/INTP3 AVREF1 P80/ANI01 P81/ANI11 P82/ANI21 P83/ANI31 P84/ANI41 P85/ANI51 P86/ANI61 P87/ANI71 AVSS1 Cautions 1. Connect the VPP pin directly to V SS0 or VSS1 in normal operation mode. 2. Connect the AVDD0 pin to VDD0. 3. Connect the AVSS0 and AVSS1 pins to VSS0. 6 Data Sheet U15013EJ2V0DS µPD78F0833Y PIN IDENTIFICATION PCL: ANI00 to ANI70, Programmable clock ANI01 to ANI71: Analog input RxD0: Receive data ASCK0: Asynchronous serial clock RESET: Reset AVDD0: Analog power supply SCK30, SCK31: Serial clock AVREF0, AVREF1: Analog reference voltage SCL0: Serial clock AVSS0, AVSS1: Analog ground SDA0: Serial data C2RX: CLASS2 receive data SI30, SI31: Serial input C2TX: CLASS2 transmit data SO30, SO31: Serial output INTP0 to INTP7: External interrupt input TI000, TI010, P00 to P07: Port 0 TI001, TI011, P20 to P27: Port 2 TI50, TI51, TI52: Timer input P30 to P36: Port 3 TO00, TO01, P40 to P47: Port 4 TO50, TO51, P50 to P57: Port 5 TO52: Timer output P64 to P67: Port 6 TxD0: Transmit data P70 to P75: Port 7 VDD0, VDD1: Power supply P80 to P87: Port 8 VPP: Programming power supply P90 to P97: Port 9 VSS0, VSS1: Ground X1, X2: Crystal Data Sheet U15013EJ2V0DS 7 µPD78F0833Y 2. BLOCK DIAGRAM TO00/P34 TI000/P35 TI010/P36 TO01/P73 TI001/P74 16-bit timer/ event counter 00 Port 0 P00 to P07 Port 2 P20 to P27 Port 3 P30 to P36 Port 4 P40 to P47 Port 5 P50 to P57 Port 6 P64 to P67 Port 7 P70 to P75 Port 8 P80 to P87 Port 9 P90 to P97 16-bit timer/ event counter 01 TI011/P75 TI50/TO50/P23 8-bit timer/ event counter 50 TI51/TO51/P27 8-bit timer/ event counter 51 TI52/TO52/P26 8-bit timer/ event counter 52 Watchdog timer 78K/0 CPU core Flash memory Watch timer SI30/P30 SO30/P31 SCK30/P32 Serial interface 30 SI31/P20 SO31/P21 SCK31/P22 Serial interface 31 RxD0/P24 TxD0/P25 ASCK0/P26 UART0 SDA0/P71 SCL0/P72 I2C bus ANI00/P90 to ANI70/P97 AVDD0 AVSS0 AVREF0 A/D converter 00 ANI01/P80 to ANI71/P87 AVSS1 AVREF1 A/D converter 01 C2RX C2TX INTP0/P00 to INTP7/P07 PCL/P70 8 Internal high-speed RAM 1,024 bytes Internal expansion RAM 2,048 bytes J1850 bus I/F (CLASS2) Interrupt control Clock output control VDD0 VDD1 VSS0 VSS1 VPP Data Sheet U15013EJ2V0DS System control RESET X1 X2 µPD78F0833Y 3. PIN FUNCTIONS 3.1 Port Pins (1/2) Pin Name I/O P00 to P07 I/O P20 I/O P21 P22 Function After Reset Alternate Function Port 0 8-bit I/O port Input/output can be specified in 1-bit units. An on-chip pull-up resistor can be specified by software. Input INTP0 to INTP7 Port 2 8-bit I/O port Input/output can be specified in 1-bit units. An on-chip pull-up resistor can be specified by software. Input SI31 SO31 SCK31 P23 TI50/TO50 P24 RxD0 P25 TxD0 P26 ASCK0/TI52/TO52 P27 TI51/TO51 P30 I/O P31 P32 P33 Port 3 7-bit I/O port Input/output can be specified in 1bit units. An on-chip pull-up resistor can be specified by software. Input SO30 SCK30 — N-ch open-drain I/O port LEDs can be driven directly. An on-chip pull-up resistor can be specified by software. P34 P35 SI30 TO00 TI000 P36 TI010 P40 to P47 I/O Port 4 8-bit I/O port Input/output can be specified in 1-bit units. An on-chip pull-up resistor can be specified by software. Interrupt request flag (KRIF) is set to 1 by falling edge detection. Input — P50 to P57 I/O Port 5 8-bit I/O port TTL level input/CMOS output Input/output can be specified in 1-bit units. An on-chip pull-up resistor can be specified by software. Input — P64 to P67 I/O Port 6 4-bit I/O port Input/output can be specified in 1-bit units. An on-chip pull-up resistor can be specified by software. Input — Data Sheet U15013EJ2V0DS 9 µPD78F0833Y 3.1 Port Pins (2/2) Pin Name P70 I/O I/O P71 P72 P73 Function Port 7 6-bit I/O port Input/output can be specified in 1bit units. An on-chip pull-up resistor can be specified by software. After Reset Input N-ch open-drain I/O port PCL SDA0 SCL0 TO01 An on-chip pull-up resistor can be specified by software. P74 Alternate Function TI001 P75 TI011 P80 to P87 I/O Port 8 1-bit I/O port Input/output can be specified in 1-bit units. Input ANI01 to ANI71 P90 to P97 I/O Port 9 1-bit I/O port Input/output can be specified in 1-bit units. Input ANI00 to ANI70 Alternate Function 3.2 Non-Port Pins (1/2) Pin Name I/O Function After Reset INTP0 to INTP7 Input External interrupt request input for which valid edge can be specified (rising edge, falling edge, both rising and falling edges) Input P00 to P07 SI30 Input Serial interface SIO30 serial data input Input P30 SI31 SO30 Serial interface SIO31 serial data input Output SO31 Serial interface SIO30 serial data output P20 Input Serial interface SIO31 serial data output P31 P21 SDA0 I/O Serial interface IIC0 serial data input/output Input P71 SCK30 I/O Serial interface SIO30 serial clock input/output Input P32 SCK31 Serial interface SIO31 serial clock input/output P22 SCL0 Serial interface IIC0 serial clock input/output P72 RxD0 Input Asynchronous serial interface serial data input Input P24 TxD0 Output Asynchronous serial interface serial data output Input P25 ASCK0 Input Asynchronous serial interface serial clock input Input P26/TI52/TO52 TI000 Input External count clock input to 16-bit timer/event counter 00 Capture trigger input to capture register (CR000 and CR010) of 16-bit timer/event counter 00 Input P35 TI010 Capture trigger input to capture register (CR000) of 16-bit P36 timer/event counter 00 TI001 External count clock input to 16-bit timer/event counter 01 Capture trigger input to capture register (CR001 and CR011) of 16-bit timer/event counter 01 P74 TI011 Capture trigger input to capture register (CR001) of 16-bit timer/event counter 01 P75 10 Data Sheet U15013EJ2V0DS µPD78F0833Y 3.2 Non-Port Pins (2/2) Pin Name I/O Function After Reset Alternate Function TI50 Input External count clock input to 8-bit timer/event counter 50 Input P23/TO50 TI51 External count clock input to 8-bit timer/event counter 51 P27/TO51 TI52 External count clock input to 8-bit timer/event counter 52 P26/ASCK0/TO52 TO00 Output 16-bit timer/event counter 00 output Input P34 TO01 16-bit timer/event counter 01 output P73 TO50 8-bit timer/event counter 50 output P23/TI50 TO51 8-bit timer/event counter 51 output P27/TI51 TO52 8-bit timer/event counter 52 output P26/ASCK0/TI52 PCL Output ANI00 to ANI70 Input ANI01 to ANI71 AVREF0 Clock output A/D converter (AD00) analog input Input P70 Input P90 to P97 A/D converter (AD01) analog input — A/D converter (AD00) reference voltage input P80 to P87 — — AVREF1 A/D converter (AD01) analog power supply and reference voltage input — AV DD0 A/D converter (AD00) analog power supply — AV SS0 A/D converter (AD00) ground potential. Make the same potential as V SS0 or VSS1 . — AV SS1 A/D converter (AD01) ground potential. Make the same potential as V SS0 or VSS1 . — CLASS 2 data input — CLASS 2 data output — C2RX Input C2TX Output RESET Input System reset input — X1 Input Connecting crystal resonator for oscillation — X2 — — VDD0 Positive power supply for ports — VDD1 Positive power supply (other than for ports) — VSS0 Ground potential for ports — VSS1 Ground potential (other than for ports) — VPP Applying high voltage for program write/verify Connect directly to VSS0 or VSS1 in normal operation mode. — Data Sheet U15013EJ2V0DS 11 µPD78F0833Y 3.3 Pin I/O Circuits and Recommended Connection of Unused Pins The I/O circuit type of each pin and recommended connection of unused pins are shown in Table 3-1. For the I/O circuit configuration of each type, see Figure 3-1. Table 3-1. Pin I/O Circuit Types and Recommended Connection of Unused Pins (1/2) Pin Name I/O Circuit Type I/O P00/INTP0 to P07/INTP7 8-C I/O P20/SI31 P21/SO31 P22/SCK31 Recommended Connection of Unused Pins Independently connect to V SS0 via a resistor. Output: Leave open. Input: Input: Independently connect to V DD0 or VSS0 via a resistor. 5-H Output: Leave open. 8-C P23/TI50/TO50 P24/RxD0 P25/TxD0 5-H P26/ASCK0/TI52/TO52 8-C P27/TI51/TO51 P30/SI30 P31/SO30 5-H P32/SCK30 8-C P33 13-P Input: P34/TO00 5-H Input: P35/TI000 Independently connect to V DD0 via a resistor. Output: Leave open. 8-C Output: Leave open. P36/TI010 P40 to P47 Independently connect to V DD0 or VSS0 via a resistor. 5-H Input: Independently connect to V DD0 via a resistor. Output: Leave open. P50 to P57 5-T P64 to P67 5-H Input: resistor. Output: Leave open. P70/PCL P71/SDA0 13-R Input: P74/TI001 5-H Input: Independently connect to V DD0 or VSS0 via a resistor. 8-C Output: Leave open. P75/TI011 P80/ANI01 to P87/ANI71 Independently connect to V DD0 via a resistor. Output: Leave open. P72/SCL0 P73/TO01 Independently connect to V DD0 or VSS0 via a 11-E P90/ANI00 to P97/ANI70 C2RX 2 Input C2TX 3-B Output 2 Input RESET 12 Connect to V SS0 via a resistor. Leave open. Data Sheet U15013EJ2V0DS — µPD78F0833Y Table 3-1. Pin I/O Circuit Types and Recommended Connection of Unused Pins (2/2) Pin Name AVDD0 I/O Circuit Type I/O — — Recommended Connection of Unused Pins Connect to V DD0. AVREF0 AVREF1 AVSS0 Connect to V SS0. AVSS1 VPP Connect directly to V SS0 or VSS1 . Data Sheet U15013EJ2V0DS 13 µPD78F0833Y Figure 3-1. Pin I/O Circuit List (1/2) TYPE 2 VDD0 TYPE 5-T Pull-up enable P-ch VDD0 IN Data P-ch IN/OUT Output disable N-ch TTL input Schmitt-triggered input with hysteresis characteristics VSS0 Input enable TYPE 3-B TYPE 8-C VDD0 VDD0 Pull-up enable P-ch P-ch VDD0 Data Data P-ch OUT IN/OUT N-ch Output disable VSS0 TYPE 5-H N-ch VSS0 TYPE 11-E VDD0 VDD0 Pull-up enable Data Data VDD0 IN/OUT P-ch IN/OUT Output disable Input enable 14 P-ch P-ch Output disable Comparator N-ch P-ch VSS0 + – N-ch N-ch AVSS VREF (threshold voltage) VSS0 Input enable Data Sheet U15013EJ2V0DS µPD78F0833Y Figure 3-1. Pin I/O Circuit List (2/2) TYPE 13-R TYPE 13-P IN/OUT IN/OUT Data Output disable Data Output disable N-ch N-ch VSS0 VSS0 Input enable Data Sheet U15013EJ2V0DS 15 µPD78F0833Y 4. DIFFERENCES BETWEEN µPD78F0833Y AND MASK ROM VERSION The µPD78F0833Y incorporates flash memory in which a program can be written, deleted, and overwritten while mounted on the board. Table 4-1 lists the differences between the µPD78F0833Y and the mask ROM versions. Table 4-1. Difference Between µPD78F0833Y and Mask ROM Version µPD78F0833Y Item µPD780833Y Internal ROM capacity 60 KB Internal ROM structure Flash memory Mask ROM IC pin Not provided Provided VPP pin Provided Not provided Electrical specifications, recommended soldering conditions Refer to the data sheet of individual products. Caution There are differences in noise immunity and noise radiation between the flash memory and mask ROM versions. When pre-producing an application set with the flash memory version and then mass-producing it with the mask ROM version, be sure to conduct sufficient evaluations on the commercial samples (CS) (not engineering sample, ES) of the mask ROM version. 16 Data Sheet U15013EJ2V0DS µPD78F0833Y 5. MEMORY SIZE SWITCHING REGISTER (IMS) This register sets the internal memory capacity by software. IMS is set with an 8-bit memory manipulation instruction. RESET input sets IMS to CFH. Figure 5-1. Format of Memory Size Switching Register (IMS) Symbol 7 6 5 4 3 2 1 0 Address After reset R/W IMS RAM2 RAM1 RAM0 0 ROM3 ROM2 ROM1 ROM0 FFF0H CFH R/W RAM2 RAM1 RAM0 1 1 0 Other than above Selection of internal high-speed RAM capacity 1,024 bytes Setting prohibited ROM3 ROM2 ROM1 ROM0 1 1 0 0 48 KB 1 1 1 1 60 KB Other than above Selection of internal ROM capacity Setting prohibited Data Sheet U15013EJ2V0DS 17 µPD78F0833Y 6. INTERNAL EXPANSION RAM SIZE SWITCHING REGISTER (IXS) This register sets the internal expansion RAM capacity by software. IXS is set with an 8-bit memory manipulation instruction. RESET input sets IXS to 0CH. Caution The default value of IXS is 0CH (setting prohibited). Be sure to set 08H as the initial setting. Figure 6-1. Format of Internal Expansion RAM Size Switching Register (IXS) Symbol 7 6 5 4 IXS 0 0 0 IXRAM4 IXRAM4 IXRAM3 IXRAM2 0 1 Other than above 18 0 3 1 0 IXRAM3 IXRAM2 IXRAM1 IXRAM0 IXRAM1 IXRAM0 0 2 0 Address After reset R/W FFF4H 0CH R/W Selection of internal high-speed RAM capacity 2,048 bytes Setting prohibited Data Sheet U15013EJ2V0DS µPD78F0833Y 7. FLASH MEMORY PROGRAMMING Writing to flash memory can be performed without removing the memory from the target system. Writing is performed with the dedicated flash programmer Flashpro II (part number: FL-PR2) and Flashpro III (part number: FLPR3 and PG-FP3) connected to the host machine and the target system. Moreover, writing to flash memory can also be performed using a flash memory writing adapter connected to Flashpro II or Flashpro III. Remark FL-PR2 and FL-PR3 are products of Naito Densei Machida Mfg. Co., Ltd. 7.1 Selection of Communication Mode Writing to flash memory is performed using Flashpro II or Flashpro III via a serial communication mode. The communication mode is selected from those in Table 7-1. The selection of the communication mode is made by using the format shown in Figure 7-1. Each communication mode is selected by the number of VPP pulses shown in Table 7-1. Table 7-1. List of Communication Modes Communication Mode 3-wire serial I/O (SIO3) Pin UsedNote Channels 2 VPP Pulses SI30/P30 SO30/P31 SCK30/P32 2 SI31/P20 SO31/P21 SCK31/P22 1 Note Shifting to the flash memory programming mode sets all pins not used for flash memory programming to the same state as immediately after reset. Therefore, all ports enter an output high-impedance state. If the external devices do not acknowledge an output high-impedance state, handling such as connecting to VDD via a resistor or connecting to VSS via a resistor is required. Cautions 1. Be sure to select the number of VPP pulses shown in Table 7-1 for the communication mode. 2. If performing write operations to flash memory via the UART communication mode, set the system clock oscillation frequency to 3 MHz or higher. Figure 7-1. Format of Communication Mode Selection VPP pulses 10 V VPP VDD 1 2 n VSS VDD RESET VSS Flash memory write mode Data Sheet U15013EJ2V0DS 19 µPD78F0833Y 7.2 Flash Memory Programming Functions Operations such as writing to flash memory are performed by various command/data transmission and reception operations according to the selected communication mode. Table 7-2 shows major functions of flash memory programming. Table 7-2. Major Functions of Flash Memory Programming Function Description Reset Used to detect write stop and communication synchronization. Batch verify Compares entire memory contents and input data. Batch contents verify Compares entire memory contents in the different modes. Batch delete Deletes the entire memory contents. Batch blank check Checks the deletion status of the entire memory. High-speed write Writes to flash memory according to write start address and number of write data (bytes). Continuous write Successively writes using the data input in a high-speed write operation. Batch prewrite Writes 00H to entire memory. Status Checks the current operation mode and whether operation has ended. Oscillation frequency setting Inputs the resonator oscillation frequency information. Delete time setting Inputs the memory delete time. Silicon signature read Outputs the device name, memory capacity, and device block information. 7.3 Flashpro II and Flashpro III Connection The connection of the Flashpro II and Flashpro III and the µPD78F0833Y is shown in Figure 7-2. Figure 7-2. Connection of Flashpro II and Flashpro III in 3-Wire Serial I/O (SIO3) Mode µ PD78F0833Y Flashpro II or Flashpro III VPP VPP VDD VDD0 RESET RESET SCK SCK3n SO SI3n SI SO3n GND VSS0 n = 0, 1 20 Data Sheet U15013EJ2V0DS µPD78F0833Y 7.4 Flash Memory Programming by Self Write With the µPD78F0833Y, it is possible to rewrite the flash memory using a program. (1) Flash memory configuration The configuration of the flash memory is shown in Figure 7-3. Figure 7-3. Flash Memory Configuration Normal operation mode F7FFH F000H EFFFH Internal expansion RAM area (2 KB) Self-write mode F7FFH F000H EFFFH Internal expansion RAM area (2 KB) FLPMC ← 09H 9BFFH Flash memory area (60 KB) Flash memory area (60 KB) FLPMC ← 08H 0000H Erase/write routine call * This area cannot be accessed with a normal instruction. Firmware area (including erase/ write routine) Erase/ 8000H write 0000H (2) Flash programming mode control register (FLPMC) The flash programming mode control register (FLPMC) is a register for checking the operating mode selection and VPP pin status. FLPMC is set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 08H. Data Sheet U15013EJ2V0DS 21 µPD78F0833Y Figure 7-4. Format of Flash Programming Mode Control Register (FLPMC) Symbol FLPMC 7 6 5 4 3 2 1 0 Address After reset R/W 0 0 0 0 1 VPP 0 FLSPM0 FFCDH 08HNote 1 R/WNote 2 VPP VPP pin voltage application status 0 The voltage required for flash memory erase/write is not applied to VPP pin. 1 Voltage greater than that of VDD pin is applied to VPP pin. FLSPM0 Operating mode selection 0 Normal operating mode 1 Self-write mode Notes 1. Bit 2 changes depending on the level of the VPP pin. 2. Bit 2 is read-only. Cautions 1. Be sure to set bits 1 and bits 4 to 7 to 0, and set bit 3 to 1. 2. The VPP bit indicates the status of the voltage applied to the VPP pin. If the VPP bit is 0, the voltage required for erase/write is not applied. However, even if VPP bit is 1, it does necessarily mean that the voltage required for erase/write is applied. Configure the hardware so that the voltage required for erase/write is applied to the VPP pin. Also, if software will be used in addition to hardware to check that the voltage required for erase/write is applied, provide an external hardware detection circuit and use its output. (3) Self-write procedure The procedure for performing self write is shown below (see Figure 7-5). (1) Disable interrupts. (2) Designate the self-write mode (FLPMC = 09H). (3) Select register bank 3. (4) Specify the start address of the entry RAM for the HL register. (5) VPP: ON (ON signal for power supply IC) (6) Check the VPP level. (7) Initialize the flash subroutine. (8) Set the parameters. (9) Control the flash memory (erase, write, etc.). (10) VPP: OFF (OFF signal for power supply IC) (11) Designate the normal operating mode (FLPMC = 08H). 22 Data Sheet U15013EJ2V0DS µPD78F0833Y Figure 7-5. Self-Programming Flowchart (1) Disable interrupts. (2) Designate the self-write mode (FLPMC = 09H). (3) Select register bank 3. (4) Specify the entry RAM address. (5) VPP: ON (6) VPP = 1? No Yes (7) Initialize the flash subroutine. (8) Set the parameters. Pre-write Erase Yes Error? No Less than n timesNote (9) Number of errors? Write data nth timeNote Yes Error? No Verify Yes Error? No (10) VPP: OFF (11) Designate normal operating mode (FLPMC = 08H). Flash memory error Note Differs depending on the user program. Data Sheet U15013EJ2V0DS 23 µPD78F0833Y Figure 7-6. Self-Write Timing 5V 4.5 V 4.5 V VDD 0V 10 V 9.7 V VPP 0.2VDD 0V 5V RESET 0.2VDD 0V 0.2VDD TRSL CPU operation and program processing Reset mode Normal operating mode Normal Mode program setting processing Self-write mode Erase Write Verify FLPMC ← 09H VPP: ON Writing to flash memory. VPP = 10 V ±0.3 V VPP: OFF FLPMC ← 08H 24 Data Sheet U15013EJ2V0DS Normal operating mode Normal Mode program setting processing Reset mode µPD78F0833Y (4) CPU resources The CPU resources used during self write are as follows: • Register bank: BANK3 (8 bytes) B register: Status flag C register: Function number HL register: Entry RAM area start address • Stack area: Maximum 16 bytes • Write data storage area: 1 to 256 bytes • Entry RAM area: 32 bytes RAM area used by the self-write subroutines. Can be specified by the user using the HL register. • Status register 7 6 5 4 3 2 1 0 Parameter setting error — — Verify error Write error — Blank check error — (5) Entry RAM area A description of the entry RAM area is shown in Table 7-3. Table 7-3. Entry RAM Area Offset Value Example Description +0 Reserved area (1 byte) +1 Reserved area (1 byte) +2 Flash memory start address (2 bytes) +4 Flash memory end address (2 bytes) +6 Number of bytes written to flash memory (1 byte) +7 Write time data (1 byte) +8 Erase time data (3 bytes) +11 Reserved area (3 bytes) +14 Write data storage buffer start address (2 bytes) +16 Total block number (1 byte) +17 Total area number (1 byte) +18 · · Reserved area (14 bytes) When the value of the HL register of register bank 3 is 0FD00H 0FD00H: Status 0FD02H: Flash memory start address 0FD06H: Number of bytes written to flash memory · · Data Sheet U15013EJ2V0DS 25 µPD78F0833Y Next, the entry RAM area will be explained in detail. (a) Flash memory start address This is the flash memory address value used by the _FlashByteWrite subroutine. (b) Flash memory end address This is the flash memory address value used by the _FlashGetInfo subroutine. (c) Number of bytes written in flash memory Area number and number of bytes written in the flash memory. (d) Write time data Set the following values based on the operating frequency. fX (MHz) Setting Value 1.00 to 1.28 20H 1.29 to 2.56 40H 2.57 to 5.12 60H 5.13 to 8.38 80H (e) Erase time data Setting value = Erase time (s) × Operating frequency/29 + 1 (Erase time range: 0.5 to 20 seconds) Example Erase time: 2 seconds, operating frequency: 4.19 MHz Setting value = 2 × 4194304/512 + 1 = 16385 (decimal) = 4001H (hexadecimal) (f) Write data storage buffer start address This area contains the start address of the write data storage buffer area. The RAM data (write data), for which the data in this area is specified as the address, is written to the flash memory (_FlashByteWrite subroutine). The data in this area is specified as the start address and it is possible to specify up to a maximum of 256 bytes of write data. (g) Total block number This is the total flash memory block number used by the _FlashGetInfo subroutine. (h) Total area number This is the total flash memory area used by the _FlashGetInfo subroutine. 26 Data Sheet U15013EJ2V0DS µPD78F0833Y (6) Self-write subroutines The self-write subroutines and their functions are shown in Table 7-4 below. Table 7-4. List of Self-Write Subroutines Function Number Subroutine Name Function Decimal Hexadecimal 0 00H _FlashEnv Initializes the flash subroutine. 1 01H _FlashSetEnv Sets the parameters. 2 02H _FlashGetInfo Reads flash memory data 16 10H _FlashAreaBlankCheck Performs a blank check of a specified area. 32 20H _FlashAreaPreWrite Performs prewrite for a specified area. 48 30H _FlashAreaErase Erases a specified area. 80 50H _FlashByteWrite Writes continuously in byte units. 96 60H _FlashAreaVerify Performs internal verification of a specified area. (7) Self-write circuit configuration The configuration of the self-write circuit is shown in Figure 7-7. Figure 7-7. Self-Write Circuit Configuration µ PD78F0833Y VDD VOUT = 9.7 to 10.2 V VPP IC for power supply (µPC29S10, etc.) OUTPUT INPUT ON/OFF VSS VIN = 11 to 13.5 V 10 kΩ Output port VSS ≥ 10 kΩ Data Sheet U15013EJ2V0DS 27 µPD78F0833Y 8. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25°C) Parameter Supply voltage Symbol VDD Conditions V DD = AVDD = AVREF –0.3 to +6.5 V V AVREF V AVSS Output voltage Unit AVDD VPP Input voltage Ratings VI1 P00 to P07, P20 to P27, P30 to P32, P34 to P36, P40 to P47, P50 to P57, P64 to P67, P70 to P75, P80 to P87, P90 to P97, C2RX, X1, X2, RESET VI2 P33 VO P00 to P07, P20 to P27, P30 to P36, P40 to P47, P50 to P57, P64 to P67, P70 to P75, P80 to P87, P90 to P97, N-ch open-drain –0.3 to +10.5 V –0.3 to +0.3 V –0.3 to VDD + 0.3 V –0.3 to +16 V –0.3 to VDD + 0.3 V AV SS – 0.3 to AVREF + 0.3 and –0.3 to V DD + 0.3 V C2TX Analog input voltage VAN ANI00 to ANI70 Analog input pin ANI01 to ANI71 Output current, high I OH Per pin for P00 to P07, P20 to P27, P30 to P32, P34 to P36, P40 to P47, P50 to P57, P64 to P67, P70, P73 to P75, P80 to P87, P90 to P97, C2TX –10 mA Total for all pins –30 mA Output current, lowNote I OL Per pin for P00 to P07, P20 to P27, P30 to P32, P34 to P36, P40 to P47, P50 to P57, Peak value 20 mA P64 to P67, P70 to P75, P80 to P87, P90 to P97, C2TX rms value 10 mA Peak value 30 mA rms value 15 mA 100 mA 60 mA During normal operation –40 to +85 °C During flash memory programming +10 to +40 °C –65 to +150 °C P33 Total for all pins Peak value rms value Operating ambient TA temperature Storage temperature Tstg Note The rms value should be calculated as follows: [rms value] = [Peak value] × √Duty Caution Product quality may suffer if the absolute maximum rating is exceeded for even single parameter or even momentarily. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions ensuring that the absolute maximum ratings are not exceeded. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. 28 Data Sheet U15013EJ2V0DS µPD78F0833Y System Clock Oscillator Characteristics (T A = –40 to 85 °C, V DD = 4.5 to 5.5 V) Resonator Ceramic resonator Recommended Circuit X2 VPP R1 C2 Crystal resonator X1 X2 C1 X1 VPP R1 C2 C1 Parameter Conditions Oscillation frequency (f X)Note 1 MIN. TYP. MAX. Unit 8.4 MHz 4 ms 4.2 MHz 10 ms 4.0 Oscillation stabilization time Note 2 Oscillation frequency (f X)Note 1 4.0 Oscillation stabilization time Note 2 Notes 1. Indicates only oscillator characteristics. 2. Time required to stabilize oscillation after reset or STOP mode release. Caution When using the system clock oscillator, wiring in the area enclosed with the broken line in the above figures should be carried out as follows to avoid an adverse effect from wiring capacitance. • Keep the wiring length as short as possible. • Do not cross the wiring with the other signal lines. • Do not route the wiring near a line through which a high fluctuating current flows. • Always keep the ground point of the oscillator to the same potential as VSS1 . • Do not ground the capacitor to a ground pattern in which a high current flows. • Do not fetch signals from the oscillator. Remark For the resonator selection and oscillator constant, users are required to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. Data Sheet U15013EJ2V0DS 29 µPD78F0833Y Capacitance (TA = 25°C, VDD = VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Input capacitance CIN f = 1 MHz Unmeasured pins returned to 0 V. 15 pF Output capacitance COUT f = 1 MHz Unmeasured pins returned to 0 V. 15 pF I/O capacitance CIO f = 1 MHz P00 to P07, Unmeasured pins returned to 0 V. P27, P30 to P34 to P36, P47, P50 to P64 to P67, P75, P80 to P90 to P97 15 pF 20 pF P33 P20 to P32, P40 to P57, P70 to P87, Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. 30 Data Sheet U15013EJ2V0DS µPD78F0833Y DC Characteristics (TA = –40 to +85°C, VDD = AVDD = AVREF = 4.5 to 5.5 V) Parameter Input voltage, high Symbol Conditions MIN. TYP. MAX. Unit VIH1 P21, P25, P31, P34, P40 to P47, P64 to P67, P70 to P73, P80 to P87, P90 to P97 0.7VDD VDD V VIH2 P00 to P07, P20, P22 to P24, P26, P27, P30, P32, P35, P36, P74, P75, RESET 0.8VDD VDD V VIH3 P50 to P57 2.3 VDD V VIH4 P33 (N-ch open-drain) 0.7VDD 15 V VIH5 X1, X2 VDD − 0.5 VDD V VIH6 C2RX 0.8VDD VDD + 0.2 V VIL1 P21, P25, P31, P34, P40 to P47, P64 to P67, P70 to P73, P80 to P87, P90 to P97 0 0.3VDD V VIL2 P00 to P07, P20, P22 to P24, P26, P27, P30, P32, P35, P36, P74, P75, C2RX, RESET 0 0.2VDD V VIL3 P50 to P57 0 0.75 V VIL4 P33 (N-ch open-drain) 0 0.3VDD V VIL5 X1, X2 0 0.4 V VOH1 I OH = −1 mA P00 to P07, P20 to P27, P30 to P32, VDD − 1.0 P34 to P36, P40 to P47, P50 to P57, VDD V VOH2 I OH = −100 µ A P64 to P67, P70, P73 to P75, P80 to VDD − 0.5 P87, P90 to P97, C2TX VDD V Output voltage, VOL1 I OL = 15 mA P33 2.0 V low VOL2 I OL = 1.6 mA P71, P72 0.4 V VOL3 I OL = 1 mA P00 to P07, P20 to P27, P30 to P32, P34 to P36, P40 to P47, P50 to P57, 1.0 V VOL4 I OL = 500 µA P64 to P67, P70, P73 to P75, P80 to P87, P90 to P97, C2TX 0.5 V I LIH1 VIN = VDD P00 P34 P64 P90 3 µA X1 20 µA 80 µA −3 µA −20 µA Input voltage, low Output voltage, high Input leakage current, high I LIH2 Input leakage current, low I LIH3 VIN = 15 V P33 I LIL1 VIN = 0 V P00 P34 P64 P90 I LIL2 I LIL3 0.4 to to to to to to to to P07, P36, P67, P97, P07, P36, P67, P97, P20 to P40 to P70 to C2RX, P20 to P40 to P70 to C2RX, P27, P30 to P32, P47, P50 to P57, P75, P80 to P87, RESET P27, P30 to P32, P47, P50 to P57, P75, P80 to P87, RESET X1 P33 −3 Note µA Note A low-level input leakage current of −200 µA (MAX.) flows only for 1 clock after a read instruction has been executed to P33 or port 33 (P33). At times other than this 1-clock interval a −3 µA (MAX.) current flows. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. Data Sheet U15013EJ2V0DS 31 µPD78F0833Y DC Characteristics (TA = –40 to +85°C, V DD = AVDD = AVREF = 4.5 to 5.5 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Output leakage current, high I LOH VOUT = V DD P00 to P07, P34 to P36, P64 to P67, P87, P90 to P20 to P27, P30 to P32, P40 to P47, P50 to P57, P70, P73 to P75, P80 to P97, C2TX 3 µA Output leakage current, low I LOL VOUT = 0 V P00 to P07, P20 to P27, P30 to P36, P40 to P47, P50 to P57, P64 to P67, P70 to P75, P80 to P87, P90 to P97, C2TX −3 µA Software pull-up resistor R1 VIN = 0 V P00 to P07, P20 to P27, P30 to P32, P34 to P36, P40 to P47, P50 to P57, P64 to P67, P70, P73 to P75 30 90 kΩ Supply I DD1 4.19 MHz crystal oscillation operation modeNote 2 6 12 mA modeNote 2 currentNote 1 8.38 MHz crystal oscillation operation I DD2 I DD3 15 11 22 mA 4.19 MHz crystal oscillation HALT modeNote 3 400 700 µA 8.38 MHz crystal oscillation HALT modeNote 3 700 1,200 µA 0.1 30 µA STOP mode Notes 1. Total current flowing in the internal power supply (V DD1 and VSS1 ). AVREF, AVDD, and port current (onchip pull-up resistor) are not included. 2. During high-speed mode operation (when the processor clock control register (PCC) is set to 00H). 3. During low-speed mode operation (when the processor clock control register (PCC) is set to 04H). The WTN0 operating current and the receive wait state operating current of the CLASS2 signal (when bits 5 and 4 (C2SC1 and C2SC0) of the class2 clock selection register (C2CLK) are set to 00B) are included. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. 32 Data Sheet U15013EJ2V0DS µPD78F0833Y AC Characteristics (1) Basic operation (TA = –40 to +85°C, VDD = 4.5 to 5.5 V) Parameter Cycle time Symbol TCY (Minimum instruction execution time) Conditions MIN. TYP. MAX. Unit Using ceramic resonator 0.238 8 µs Using crystal resonator 0.476 8 µs µs TI000, TI010, TI001, TI011 input high-/low-level width t TIH0 t TIL0 2/f sam + 0.1 Note TI50, TI51, TI52 input frequency f TI5 0 TI50, TI51, TI52 input high-/low-level width t TIH5 t TIL5 160 ns Interrupt request input high-/low-level width t INTH t INTL 10 µs RESET low-level width t RSL 10 µs INTP0 to INTP7, P40 to P47 2.5 MHz Note Selection of f sam = f X, fX/4, fX/64 is available with bits 0 and 1 (PRM0n0, PRM0n1) of prescaler mode register 0n (PRM0n). However, if the TI00n valid edge is selected as the count clock, the value becomes fsam = fX/ 8 (n = 0, 1). Data Sheet U15013EJ2V0DS 33 µPD78F0833Y (2) Serial interface (TA = –40 to +85°C, VDD = 4.5 to 5.5 V) (a) SIO3 3-wire serial I/O mode (internal clock output): SIO30, SIO31 Parameter Symbol SCK3 cycle time t KCY1 SCK3 high-/low-level width t KH1, t KL1 SI3 setup time (to SCK3↑) Conditions MIN. TYP. MAX. Unit 952 ns tKCY1/2 – 50 ns t SIK1 100 ns SI3 hold time (from SCK3↑) t KSI1 400 ns Delay time from SCK3↓ to SO3 output t KSO1 C = 100 pF Note 300 ns MAX. Unit Note C is the load capacitance of the SCK3 and SO3 output lines. (b) SIO3 3-wire serial I/O mode (external clock input): SIO30, SIO31 Parameter Symbol Conditions MIN. TYP. SCK3 cycle time t KCY2 800 ns SCK3 high-/low-level width t KH2, t KL2 400 ns SI3 setup time (to SCK3↑) t SIK2 100 ns SI3 hold time (from SCK3↑) t KSI2 400 ns Delay time from SCK3↓ to SO3 output t KSO2 C = 100 pF Note 300 ns MAX. Unit 131,250 bps MAX. Unit Note C is the load capacitance of the SO3 output line. (c) UART0 (dedicated baud rate generator output) Parameter Symbol Conditions MIN. TYP. Transfer rate (d) UART0 (external clock input) Parameter ASCK0 cycle time ASCK0 high-/low-level width Symbol Conditions TYP. t KCY3 800 ns t KH3, tKL3 400 ns Transfer rate 34 MIN. 39,063 Data Sheet U15013EJ2V0DS bps µPD78F0833Y (e) I 2C bus mode Parameter Symbol Standard Mode High-Speed Mode MIN. MAX. MIN. MAX. 100 0 400 Unit SCL0 clock frequency f SCL 0 Bus free time (between stop and start condition) t BUF 4.7 1.3 µs Hold timeNote 1 t HD:STA 4.0 0.6 µs SCL0 clock low-level width t LOW 4.7 1.3 µs SCL0 clock high-level width t HIGH 4.0 0.6 µs Start/restart condition setup time t SU:STA 4.7 0.6 µs Data hold time t HD:DAT CBUS compatible master I 2C bus kHz 5.0 — — µs 0 Note 2 0 Note 2 0.9Note 3 µs 250 100 Note 4 Data setup time t SU:DAT SDA0 and SCL0 signal rise time tR 1,000 300 ns SDA0 and SCL0 signal fall time tF 300 300 ns Stop condition setup time t SU:STO Capacitive load per each bus line Cb 4.0 ns µs 0.6 400 400 pF Notes 1. Upon occurrence of the start condition, the first clock pulse is generated after hold period. 2. To fill the undefined area of the SCL0 falling edge, it is necessary for the device to internally provide a SDA0 signal (on VIHmin. of SCL0 signal) with at least 300 ns of hold time. 3. If the device does not extend the SCL0 signal low hold time (t LOW), only the maximum data hold time t HD:DAT needs to be fulfilled. 4. The high-speed-mode I 2C bus is available in the standard-mode I2C bus system. At this time, the conditions described below must be satisfied. • If the device does not extend the SCL0 signal low state hold time tSU:DAT ≥ 250 ns • If the device extends the SCL0 signal low state hold time Be sure to transmit the next data bit to the SDA0 line before the SCL0 line is released (tRmax. + tSU:DAT = 1,000 + 250 = 1,250 ns by standard mode I2C bus specification). Data Sheet U15013EJ2V0DS 35 µPD78F0833Y (3) CLASS2 (TA = –40 to +85°C, VDD = 4.5 to 5.5 V) (a) Internal clock count limit Parameter Symbol Internal clock cycle time Conditions tCCLK MIN. TYP. MAX. Unit 510 ns MAX. Unit 467 (b) In normal mode Parameter Symbol Conditions MIN. TYP. Rise transfer delay time (from C2TX↑ to C2RX↑) tPDR 62 tCCLK µs Fall transfer delay time (from C2TX↓ to C2RX↓) tPDF 62 tCCLK µs MAX. Unit (c) In ×4 speed mode Parameter Symbol Conditions MIN. TYP. Rise transfer delay time (from C2TX↑ to C2RX↑) tPDRX 8 tCCLK µs Fall transfer delay time (from C2TX↓ to C2RX↓) tPDFX 8 tCCLK µs (d) Transmit and receive pulse width (in normal mode) Symbol tXMIN tXNOM tXMAX tRMIN t RMAX Unit When Passive “0”, Active “1” 60 64 68 37 91 or lower µs When Passive “1”, Active “0” 122 128 134 100 157 or lower µs When Active “SOF” 193 200 207 170 230 µs When Passive “EOF” 271 280 289 249 320 or lower µs 320 or higher 8 tCCLK µs Idle point When Active “Break” 768 µs 249 or higher (e) Transmit and receive pulse width (in ×4 speed mode) Symbol tXMIN tXNOM tXMAX tRMIN t RMAX Unit When Passive “0”, Active “1” 15 16 17 10 22 µs When Passive “1”, Active “0” 30 32 34 25 39 µs When Active “SOF” 48 50 52 43 57 µs When Passive “EOF” 68 70 72 63 80 µs 80 8 tCCLK µs Idle point When Active “Break” 36 768 63 Data Sheet U15013EJ2V0DS µs µPD78F0833Y AC Timing Test Points (Excluding X1 Input) 0.8VDD Test points 0.2VDD 0.8VDD 0.2VDD Clock Timing 1/fX tXL tXH VIH5 (MIN.) VIL5 (MAX.) X1 input TI Timing tTIL0 tTIH0 TI000, TI010, TI001, TI011 1/fTI5 tTIL5 tTIH5 TI50, TI51, TI52 Interrupt Request Input Timing tINTL tINTH INTP0 to INTP7 RESET Input Timing tRSL RESET Data Sheet U15013EJ2V0DS 37 µPD78F0833Y Serial Transfer Timing 3-wire serial I/O mode: tKCYn tKLn tKHn SCK30, SCK31 tSIKn SI30, SI31 tKSIn Input data tKSOn Output data SO30, SO31 UART mode (external clock input): tKCY3 tKH3 tKL3 ASCK0 I2C bus mode tR tLOW SCL0 tHIGH tHD:DAT tHD:STA tF tSP tSU:STA tHD:STA tSU:STO tSU:DAT SDA0 tBUF Stop condition 38 Start condition Restart condition Data Sheet U15013EJ2V0DS Stop condition µPD78F0833Y CLASS2 Transfer Waveform (Example of Short Pulse Width) C2TX tPDR 64 µ s-tPDF tPDF 64 µ s-tPDR tPDR C2RX 64 µ s 64 µ s C2TX tPDRX 16 µ s-tPDFX tPDFX 16 µ s-tPDRX tPDRX C2RX 16 µ s 16 µ s Remarks 1. The meanings of the symbols in above figure are as follows. tPDR: CLASS2 transceiver rise transfer delay time in normal mode tPDF : CLASS2 transceiver fall transfer delay time in normal mode tPDRX: CLASS2 transceiver rise transfer delay time in ×4 speed mode tPDFX: CLASS2 transceiver fall transfer delay time in ×4 speed mode 2. The values of tPDR, tPDF, tPDRX, and tPDFX can be specified using the class 2 rise transfer delay time correct register (C2PDR) and the class 2 fall transfer delay time correct register (C2PDF). Data Sheet U15013EJ2V0DS 39 µPD78F0833Y A/D Converter Characteristics (T A = –40 to +85 °C, V DD = AVDD = AVREF = 4.5 to 5.5 V, VSS = AVSS = 0 V) Parameter Symbol Conditions Resolution Overall MIN. TYP. MAX. Unit 8 8 8 bit ±0.6 %FSR errorNote Conversion time t CONV 14 100 µs Analog input voltage VIAN AVSS AVREF V AVREF resistance RAIREF 37 kΩ 9.5 15 Note Excluding quantization error (±1/2%FSR). This value is indicated as a ratio to the full-scale value. Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (T A = –40 to +85°C) Parameter Symbol Data retention power supply voltage VDDDR Data retention power supply current I DDDR Release signal set time t SREL Oscillation stabilization wait time t WAIT Conditions MIN. TYP. 2.0 VDDDR = 2.0 V 0.1 MAX. Unit 5.5 V 10 µA µs 0 Release by RESET 217 /fX ms Release by interrupt request Note ms Note Selection of 212/fX , 214/fX, 2 15/f X, 216/f X, and 217/fX is possible with bits 0 to 2 (OSTS0 to OSTS2) of the oscillation stabilization time select register (OSTS). Data Retention Timing (STOP Mode Release by RESET) Internal reset operation HALT mode Operating mode STOP mode Data retention mode VDD VDDDR tSREL STOP instruction execution RESET tWAIT 40 Data Sheet U15013EJ2V0DS µPD78F0833Y Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Request Signal) HALT mode Operating mode STOP mode Data retention mode VDD VDDDR tSREL STOP instruction execution Standby release signal (Interrupt request) tWAIT Data Sheet U15013EJ2V0DS 41 µPD78F0833Y Flash Memory Programming Characteristics (VDD = 2.7 to 5.5 V, V SS = 0 V, VPP = 9.7 to 10.3 V) (1) Basic Characteristics Parameter Symbol Conditions VDD supply voltage VDD Operating voltage during write operation VPP supply voltage VPPL When detecting V PP low level VPP When programming flash memory VPP supply current I PP VPP = 10.0 V Programming temperature TPRG Write time CWRT MIN. MAX. Unit 4.5 5.5 V 0 0.2VDD V 10.3 V 100 mA +40 °C 20 Times 9.7 TYP. 10.0 +10 TPRG = +10 to +40°C 20 20 Remark The operating clock range in flash memory programming mode is the same as in normal operating mode. (2) Write Operation Characteristics Parameter Symbol Conditions MIN. TYP. MAX. Unit VPP set time t PSRON VPP high voltage 1.0 µs Set time from VDD↑ to VPP ↑ t DRPSR VPP high voltage 1.0 µs Set time from VPP↑ to RESET↑ t PSRRF VPP high voltage 1.0 µs Time from RESET↑ to VPP count start t RFCF 1.0 µs Count execution time t COUNT VPP counter high-/low-level width t CH, t CL VPP counter noise elimination width t NFW 2.0 ms µs 8.0 40 ns (3) Self-Programming Characteristics Parameter Symbol Conditions MIN. TYP. MAX. Unit Time from VPP ↓ to RESET↑ t PAFRF 0 µs Time from RESET↓ to VDD t RFDF 0 µs 42 Data Sheet U15013EJ2V0DS µPD78F0833Y Flash Write Mode Setting Timing 5V 4.5 V 4.5 V VDD TRFDF 0V 10 V 9.7 V VPP 0.2VDD 0V TPAFRF 5V 0.8VDD RESET 0.2VDD 0V CPU operation and program processing 0.2VDD TRSL TRSL Normal operation mode Reset Mode mode Normal program processing setting Self-write mode Erase Write Normal operation mode Verify Mode setting Normal program processing Reset mode FLPMC ← 09H VPP on During flash memory write VPP = 10 V ±0.3 V VPP off FLPMC ← 08H Data Sheet U15013EJ2V0DS 43 µPD78F0833Y 9. PACKAGE DRAWING 80-PIN PLASTIC QFP (14x14) A B 60 61 41 40 detail of lead end S C D R Q 80 1 21 20 F J G I H M P K S N S L M NOTE Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS A 17.20±0.20 B 14.00±0.20 C 14.00±0.20 D 17.20±0.20 F 0.825 G 0.825 H I 0.32±0.06 0.13 J 0.65 (T.P.) K 1.60±0.20 L 0.80±0.20 M 0.17 +0.03 −0.07 N P 0.10 1.40±0.10 Q 0.125±0.075 R 3° +7° −3° S 1.70 MAX. P80GC-65-8BT-1 44 Data Sheet U15013EJ2V0DS µPD78F0833Y 10. RECOMMENDED SOLDERING CONDITIONS The µ PD78F0833Y should be soldered and mounted under the following recommended conditions. For details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact an NEC sales representative. Table 10-1. Surface Mounting Type Soldering Conditions µ PD78F0833YGC-8BT: 80-pin plastic QFP (14 × 14) Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher), Count: Three times or less, Exposure limit: 7 days Note (after that, prebake at 125°C for 10 hours) IR35-107-3 VPS Package peak temperature: 215°C, Time: 40 seconds max. (at 200°C or higher), Count: Three times or less, Exposure limit: 7 daysNote (after that, prebake at 125°C for 10 hours) VP15-107-3 Wave soldering Solder bath temperature: 260°C max., Time 10 seconds max., Count: Once, Preheating temperature: 120°C max. (package surface temperature), Exposure limit 7 daysNote (after that, prebake at 125°C for 10 hours) WS60-107-1 Partial heating Pin temperature: 300°C max., Time: 3 seconds max. (per pin row) − Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period. Caution Do not use different soldering methods together (except for partial heating). Data Sheet U15013EJ2V0DS 45 µPD78F0833Y APPENDIX A. DEVELOPMENT TOOLS The following development tools are available for system development using the µ PD78F0833Y. Also refer to (5) Cautions on using development tools. (1) Language Processing Software RA78K0 Assembler package common to 78K/0 Series CC78K0 C compiler package common to 78K/0 Series DF780833 Device file for µ PD780833Y Subseries CC78K0-L C compiler library source file common to 78K/0 Series (2) Flash Memory Writing Tools Flashpro II (FL-PR2), Flashpro III (FL-PR3, PG-FP3) Flash programmer dedicated to on-chip flash memory microcontroller FA-80GC Adapter for flash memory writing used with connected to Flashpro II or Flashpro III. 80-pin plastic QFP (GC-8BT type). (3) Debugging Tools • When using in-circuit emulator IE-78K0-NS IE-78K0-NS In-circuit emulator common to 78K/0 Series IE-70000-MC-PS-B Power supply unit for IE-78K0-NS IE-70000-98-IF-C Interface adapter when using PC-9800 series as host machine (excluding notebook PCs) (C bus supported) IE-70000-CD-IF-A PC card and interface cable when using notebook PC as host machine (PCMCIA socket supported) IE-70000-PC-IF-C Interface adapter when using IBM PC/AT TM compatible as host machine (ISA bus supported) IE-70000-PCI-IF-A Adapter necessary when using on-chip PCI bus PC as host machine IE-780833-NS-EM4 Emulation board to emulate µPD780833Y Subseries IE-78K0-NS-P02 I/O board necessary when using IE-780833-NS-EM4 NP-80GC Emulation probe for 80-pin plastic QFP (GC-8BT type) EV-9200GC-80 Conversion socket for connecting target system board designed to mount an 80-pin plastic QFP (GC8BT type) and NP-80GC ID78K0-NS Integrated debugger for IE-78K0-NS SM78K0 System simulator common to 78K/0 Series DF780833 Device file common to µPD780833Y Subseries 46 Data Sheet U15013EJ2V0DS µPD78F0833Y • When using in-circuit emulator IE-78001-R-A IE-78001-R-A In-circuit emulator common to 78K/0 Series IE-70000-98-IF-C Interface adapter when using PC-9800 series as host machine (excluding notebook PCs) (C bus supported) IE-70000-PC-IF-C Interface adapter when using IBM PC/AT compatible as host machine (ISA bus supported) IE-70000-PCI-IF Adapter necessary when using on-chip PCI bus PC as host machine IE-78000-R-SV3 Interface adapter and cable when using EWS as host machine IE-780833-NS-EM4 Emulation board to emulate µPD780833Y Subseries IE-78K0-NS-P02 I/O board necessary to use IE-780833-NS-EM4 IE-78K0-R-EX1 Emulation probe conversion board necessary to use IE-780833-NS-EM4 + IE-78K0-NS-P02 on IE78001-R-A EP-78230GC-R Emulation probe for 64-pin plastic QFP (GC-AB8 type) EV-9200GC-80 Conversion socket to connect target system board for 64-pin plastic QFP (GC-AB8 type) and EP78230GC-R ID78K0 Integrated debugger for IE-78001-R-A SM78K0 System simulator common to 78K/0 Series DF780833 Device file common to µPD780833Y Subseries (4) Real-time OS RX78K0 Real-time OS for 78K/0 Series MX78K0 OS for 78K/0 Series Data Sheet U15013EJ2V0DS 47 µPD78F0833Y (5) Cautions on using development tools • The ID78K0-NS, ID78K0, and SM78K0 are used in combination with the DF780833. • The CC78K0 and RX78K0 are used in combination with the RA78K0 and the DF780833. • The FL-PR2, FL-PR3, FA-80GC, and NP-80GC are products made by Naito Densei Machida Mfg. Co., Ltd. (TEL: +81-44-822-3813). • For third-party development tools, see the Single-Chip Microcontroller Development Tool Selection Guide (U11069E). • The host machines and OSs supporting each software are as follows. Host Machine PC EWS Software PC-9800 series [WindowsTM] IBM PC/AT compatible [Japanese/English Windows] HP9000 series 700TM [HP-UX TM] SPARCstationTM [SunOSTM, Solaris TM] NEWSTM (RISC) [NEWS-OSTM] RA78K0 √ Note √ CC78K0 √ Note √ ID78K0-NS √ — ID78K0 √ √ SM78K0 √ — RX78K0 √ Note √ MX78K0 √ Note √ [OS] Note DOS-based software 48 Data Sheet U15013EJ2V0DS µPD78F0833Y Conversion Socket (EV-9200GC-80) Package Drawing and Recommended Board Mounting Pattern Figure A-1. EV-9200GC-80 Package Drawing (for reference) (unit: mm) Based on EV-9200GC-80 (1) Package drawing (in mm) A E M B N O L K S J C D R F EV-9200GC-80 Q 1 No.1 pin index P G H I EV-9200GC-80-G0E ITEM MILLIMETERS INCHES A 18.0 0.709 B 14.4 0.567 C 14.4 0.567 D 18.0 0.709 E 4-C 2.0 4-C 0.079 F 0.8 0.031 G 6.0 0.236 H 16.0 0.63 I 18.7 0.736 J 6.0 0.236 K 16.0 0.63 L 18.7 0.736 M 8.2 0.323 O 8.0 0.315 N 2.5 0.098 P 2.0 0.079 Q 0.35 0.014 R φ 2.3 φ 0.091 S 1.5 0.059 Data Sheet U15013EJ2V0DS 49 µPD78F0833Y Figure A-2. EV-9200GC-80 Recommended Board Mounting Pattern (for reference) (unit: mm) Based on EV-9200GC-80 (2) Pad drawing (in mm) G J H D E F K I L C B A EV-9200GC-80-P1E ITEM MILLIMETERS A 19.7 B 15.0 0.776 0.591 C 0.65±0.02 × 19=12.35±0.05 D +0.003 0.65±0.02 × 19=12.35±0.05 0.026 +0.001 –0.002 0.748=0.486 –0.002 0.026+0.001 –0.002 × 0.748=0.486 +0.003 –0.002 E 15.0 0.591 F 19.7 0.776 G 6.0 ± 0.05 0.236 +0.003 –0.002 H 6.0 ± 0.05 0.236 +0.003 –0.002 I 0.35 ± 0.02 0.014 +0.001 –0.001 J φ 2.36 ± 0.03 φ 0.093+0.001 –0.002 K φ 2.3 φ 0.091 L φ 1.57 ± 0.03 φ 0.062+0.001 –0.002 Caution 50 INCHES Dimensions of mount pad for EV-9200 and that for target device (QFP) may be different in some parts. For the recommended mount pad dimensions for QFP, refer to "SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL" (C10535E). Data Sheet U15013EJ2V0DS µPD78F0833Y APPENDIX B. RELATED DOCUMENTS The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents Related to Devices Document Name Document No. µPD780833Y Subseries User’s Manual U13892E µPD780833Y Data Sheet U15012E µPD78F0833Y Data Sheet This document 78K/0 Series User’s Manual Instructions U12326E 78K/0, 78K/0S Series Application Note Flash Memory Write U14458E Documents Related to Development Tools (User’s Manuals) Document Name RA78K0 Assembler Package CC78K0 C Compiler Document No. Operation U11802E Language U11801E Structured Assembly Language U11789E Operation U11517E Language U11518E PG-FP3 Flash Memory Programmer U13502E IE-78K0-NS U13731E IE-78K0-R-EX1 To be prepared IE-780833-NS-EM4 To be prepared SM78K0S, SM78K0 System Simulator Windows Based Operation U14611E SM78K Series System Simulator Ver. 2.10 or Later External Part User Open Interface Specifications ID78K0-NS Integrated Debugger Ver. 2.00 or Later Windows Based Operation U14379E ID78K0 Integrated Debugger Windows Based Guide U11649E Reference U11539E To be prepared Caution The above related documents are subject to change without notice. Be sure to read the latest documents before designing. Data Sheet U15013EJ2V0DS 51 µPD78F0833Y Documents Related to Embedded Software (User’s Manuals) Document Name 78K/0 Series Real-Time OS 78K/0 Series OS MX78K0 Document No. Fundamentals U11537E Installation U11536E Fundamental U12257E Other Documents Document Name Document No. SEMICONDUCTOR SELECTION GUIDE Products & Packages (CD-ROM) X13769X Semiconductor Device Mounting Technology Manual C10535E Quality Grades on NEC Semiconductor Devices C11531E NEC Semiconductor Device Reliability/Quality Control System C10983E Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892E Caution The above related documents are subject to change without notice. Be sure to read the latest documents before designing. 52 Data Sheet U15013EJ2V0DS µPD78F0833Y [MEMO] Data Sheet U15013EJ2V0DS 53 µPD78F0833Y NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Purchase of NEC I2C components conveys a license under the Philips I 2C Patent Rights to use these components in an I2 C system, provided that the system conforms to the I 2C Standard Specification as defined by Philips. FIP and IEBus are trademarks of NEC Corporation. Windows is either a registered trademark or a trademark of Microsoft Corporation in the United States and/or other countries. PC/AT is a trademark of International Business Machines Corporation. HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. Solaris and SunOS are trademarks of Sun Microsystems, Inc. NEWS and NEWS-OS are trademarks of Sony Corporation. 54 Data Sheet U15013EJ2V0DS µPD78F0833Y Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • Ordering information • Product release schedule • Availability of related technical literature • Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) • Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) NEC Electronics (Germany) GmbH NEC Electronics Hong Kong Ltd. Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288 Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics Hong Kong Ltd. Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (France) S.A. NEC Electronics Singapore Pte. Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Madrid Office Madrid, Spain Tel: 91-504-2787 Fax: 91-504-2860 United Square, Singapore Tel: 65-253-8311 Fax: 65-250-3583 NEC Electronics Italiana s.r.l. NEC Electronics (Germany) GmbH Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 NEC Electronics (France) S.A. NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics (UK) Ltd. NEC Electronics Taiwan Ltd. Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951 NEC do Brasil S.A. Electron Devices Division Guarulhos-SP Brasil Tel: 55-11-6462-6810 Fax: 55-11-6462-6829 J00.7 Data Sheet U15013EJ2V0DS 55 µPD78F0833Y • The information in this document is current as of October, 2000. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. • No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. • NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. • Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. • While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. • NEC semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above). M8E 00. 4