DATA SHEET MOS INTEGRATED CIRCUIT µPD78F0233 8-BIT SINGLE-CHIP MICROCONTROLLER DESCRIPTION The µPD78F0233 is a member of the µPD780232 Subseries that belongs to the 78K/0 Series. It replaces the internal ROMNote of the µPD780232 with a flash memory. Since the µPD78F0233 can be written/erased electrically while mounted on a board, it is suitable for applications involving system evaluation during system development, small-scale production, and for systems that are expected to be frequently upgraded. Note The internal ROM capacity varies (refer to 4. DIFFERENCES BETWEEN µPD78F0233 AND MASK ROM VERSION for details). Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before designing. µPD780232 Subseries User’s Manual: U13364E 78K/0 Series User’s Manual – Instructions: U12326E FEATURES • Pin-compatible with mask ROM versions (except VPP pin) • Flash memory: 24 KBNote • Internal high-speed RAM: 768 bytes • Internal buffer RAM: 32 bytes • VFD display RAM: 112 bytes • Operable in the same supply voltage as mask ROM version (VDD = 4.5 to 5.5 V) Note The flash memory capacity can be changed with the internal memory size switching register (IMS). Remark Refer to 4. DIFFERENCES BETWEEN µPD78F0233 AND MASK ROM VERSION for the differences between the flash memory version and mask ROM versions. APPLICATIONS Monolithic mini components, separated mini components, tuners, cassette decks, CD/MD players, audio amplifiers, etc. ORDERING INFORMATION Part Number Package Internal ROM µPD78F0233GC-8BT 80-pin plastic QFP (14 × 14) Flash memory The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. U13322EJ2V0DS00 (2nd edition) Date Published May 2001 N CP(K) Printed in Japan The mark shows major revised points. © 1998 µPD78F0233 78K/0 SERIES LINEUP The products in the 78K/0 Series are listed below. The names enclosed in boxes are subseries names. Products in mass production Products under development Y subseries products are compatible with I2C bus. Control 100-pin 100-pin 100-pin µ PD78075B µ PD78078 µ PD78070A 100-pin 80-pin 80-pin µ PD780058 µ PD78058F EMI-noise reduced version of the µPD78078 µPD78078Y µPD78054 with added timer and enhanced external interface µ PD78070AY ROM-less version of the µPD78078 µ PD78078Y with enhanced serial I/O and limited function µ PD780018AY µ PD780058Y µ PD78058FY µPD78054 µPD780065 µ PD78054Y 80-pin 64-pin µ PD780078 64-pin 64-pin 64-pin µ PD780034A µ PD780024A µPD78014H µ PD780078Y µ PD780034AY µ PD780024AY 64-pin 42-/44-pin µPD78018F µ PD78083 64-pin µPD780988 80-pin µ PD78018FY µ PD78054 with enhanced serial I/O EMI-noise reduced version of the µ PD78054 µPD78018F with enhanced UART and D/A converter and enhanced I/O RAM capacity of the µ PD780024A increased. µPD780034A with added timer and enhanced serial I/O µ PD780024A with enhanced A/D converter µ PD78018F with enhanced serial I/O EMI-noise reduced version of the µPD78018F Basic subseries for control On-chip UART, capable of operating at low voltage (1.8 V) Inverter control On-chip inverter controller and UART. EMI-noise reduced. VFD drive 78K/0 Series 100-pin µ PD780208 µ PD78044F with enhanced I/O and VFD C/D. Display output total: 53 80-pin For panel control. On-chip VFD and C/D. Display output total: 53 80-pin µ PD780232 µPD78044H 80-pin µPD78044F Basic subseries for VFD drive. Display output total: 34 µ PD78044F with added N-ch open-drain I/O. Display output total: 34 LCD drive 120-pin µ PD780338 120-pin µ PD780328 µPD780318 µ PD780308 µPD78064B µPD78064 120-pin 100-pin 100-pin 100-pin µ PD780308 with enhanced display function and timer. Segment signal output: 40 pins max. µ PD780308 with enhanced display function and timer. Segment signal output: 32 pins max. µ PD780308 with enhanced display function and timer. Segment signal output: 24 pins max. µPD780308Y µ PD78064 with enhanced SIO, and increased ROM, RAM capacity EMI-noise reduced version of the µ PD78064 µ PD78064Y Basic subseries for LCD drive, on-chip UART Bus interface supported 100-pin 80-pin µ PD780948 µ PD78098B On-chip D-CAN controller µPD78054 with added IEBusTM controller. EMI-noise reduced. 80-pin µ PD780701Y On-chip D-CAN/IEBus controller 80-pin µ PD780833Y On-chip controller compliant with J1850 (Class 2) Meter control 100-pin µPD780958 For industrial meter control 80-pin µPD780852 µPD780824 On-chip automobile meter controller/driver For automobile meter driver. On-chip D-CAN controller 80-pin Remark VFD (Vacuum Fluorescent Display) is referred to as FIPTM (Fluorescent Indicator Panel) in some documents, but the functions of the two are the same. 2 Data Sheet U13322EJ2V0DS µPD78F0233 The major functional differences among the subseries are shown below. Function Subseries Name ROM Capacity Timer 8-Bit 16-Bit Watch WDT A/D µPD78075B 32 K to 40 K 4 ch Control µPD78078 µPD78070A 8-Bit 10-Bit 8-Bit 1 ch 1 ch 1 ch 8 ch A/D – Serial Interface I/O VDD External MIN. Expansion Value 88 1.8 V 61 2.7 V D/A 2 ch 3 ch (UART: 1 ch) 48 K to 60 K – µPD780058 24 K to 60 K 2 ch 3 ch (time-division UART: 1 ch) 68 1.8 V µPD78058F 48 K to 60 K 3 ch (UART: 1 ch) 69 2.7 V µPD78054 √ 16 K to 60 K 2.0 V µPD780065 40 K to 48 K – µPD780078 48 K to 60 K 2 ch µPD780034A 8 K to 32 K 1 ch – µPD780024A 8 ch 8 ch 4 ch (UART: 1 ch) 60 2.7 V 3 ch (UART: 2 ch) 52 1.8 V 3 ch (UART: 1 ch) 51 2 ch 53 1 ch (UART: 1 ch) 33 – µPD78014H µPD78018F 8 K to 60 K µPD78083 8 K to 16 K – Inverter control µPD780988 16 K to 60 K 3 ch Note VFD drive µPD780208 32 K to 60 K 2 ch – – 1 ch – 8 ch – 3 ch (UART: 2 ch) 47 4.0 V √ 1 ch 1 ch 1 ch 8 ch – – 2 ch 74 2.7 V – µPD780232 16 K to 24 K 3 ch – – 4 ch 40 4.5 V µPD78044H 32 K to 48 K 2 ch 1 ch 1 ch 8 ch 68 2.7 V 54 1.8 V 1 ch µPD78044F 16 K to 40 K LCD drive – µPD780338 48 K to 60 K 3 ch 2 ch 2 ch 1 ch 1 ch – 10 ch 1 ch 2 ch (UART: 1 ch) µPD780328 62 µPD780318 70 µPD780308 48 K to 60 K 2 ch 1 ch 8 ch – – µPD78064B 32 K µPD78064 3 ch (time-division UART: 1 ch) – 57 2.0 V 79 4.0 V √ 69 2.7 V – 2 ch (UART: 1 ch) 16 K to 32 K Bus µPD780948 60 K 2 ch interface supported µPD78098B 40 K to 60 K 2 ch Meter control µPD780958 48 K to 60 K 4 ch 2 ch – 1 ch – – – 2 ch (UART: 1 ch) 69 2.2 V – Dash board control µPD780852 32 K to 40 K 3 ch 1 ch 1 ch 1 ch 5 ch – – 3 ch (UART: 1 ch) 56 4.0 V – 2 ch (UART: 1 ch) 59 Note 1 ch 1 ch 8 ch – 1 ch – 3 ch (UART: 1 ch) 2 ch µPD780824 32 K to 60 K 16-bit timer: 2 channels 10-bit timer: 1 channel Data Sheet U13322EJ2V0DS 3 µPD78F0233 OVERVIEW OF FUNCTIONS Item Internal memory Function Flash memory 24 KBNote High-speed RAM 768 bytes Buffer RAM 32 bytes VFD display RAM 112 bytes General-purpose register Minimum instruction execution time 8 bits × 32 registers (8 bits × 8 registers × 4 banks) • On-chip minimum instruction execution time variable function • 0.4 µs/0.8 µs/1.6 µs/3.2 µs/6.4 µs (@ 5.0 MHz operation with system clock) Instruction set • Multiply/divide (8 bits × 8 bits, 16 bits ÷ 8 bits) • Bit manipulate (set, reset, test, Boolean operation) I/O ports (including alternate-function pins for VFD) Total: 40 • CMOS I/Os: 11 • P-ch open-drain I/Os: 13 • P-ch open-drain outputs:16 VFD controller/driver Total of display outputs: 53 • 15 mA display current: 20 • 5 mA display current: 33 A/D converter • 8-bit resolution × 4 channels • Power supply voltage: AVDD = 4.5 to 5.5 V Serial interface • 2-wire serial mode (transmit only): 1 channel • 3-wire serial mode (with automatic transmit/receive function): 1 channel Timer • 8-bit remote control timer: 1 channel • 8-bit timer: 2 channels • Watchdog timer: 1 channel Vectored interrupt sources Maskable Internal: 10, external: 2 Non-maskable Internal: 1 Software 1 Power supply voltage VDD = 4.5 to 5.5 V Package 80-pin plastic QFP (14 × 14) Note The flash memory capacity can be changed with the internal memory size switching register (IMS). 4 Data Sheet U13322EJ2V0DS µPD78F0233 CONTENTS 1. PIN CONFIGURATION (TOP VIEW) ................................................................................................. 6 2. BLOCK DIAGRAM ............................................................................................................................. 8 3. PIN FUNCTION LIST .......................................................................................................................... 9 3.1 Port Pins ....................................................................................................................................................... 9 3.2 Non-Port Pins ............................................................................................................................................. 10 3.3 Pin I/O Circuits and Recommended Connection of Unused Pins ...................................................... 11 4. DIFFERENCES BETWEEN µPD78F0233 AND MASK ROM VERSION ...................................... 13 5. MEMORY SIZE SWITCHING REGISTER (IMS) ............................................................................. 14 6. FLASH MEMORY PROGRAMMING ............................................................................................... 15 6.1 Selection of Communication Mode ......................................................................................................... 15 6.2 Flash Memory Programming Functions ................................................................................................. 16 6.3 Connection to Flashpro III ........................................................................................................................ 17 7. ELECTRICAL SPECIFICATIONS ................................................................................................... 18 8. PACKAGE DRAWING ...................................................................................................................... 29 9. RECOMMENDED SOLDERING CONDITIONS .............................................................................. 30 APPENDIX A. DEVELOPMENT TOOLS ............................................................................................... 31 APPENDIX B. RELATED DOCUMENTS .............................................................................................. 35 Data Sheet U13322EJ2V0DS 5 µPD78F0233 1. PIN CONFIGURATION (TOP VIEW) • 80-pin plastic QFP (14 × 14) FIP0 FIP1 FIP2 FIP3 FIP4 FIP5 FIP6 FIP7 FIP8 FIP9 FIP10 FIP11 FIP12 FIP13 FIP14 FIP15 FIP16 FIP17 FIP18 FIP19 µPD78F0233GC-8BT 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 VDD1 VSS1 X1 X2 VPP RESET P27/SCK1 P26/SI1 P25/SO1 P24/BUSY P23 P22 P21/SO3 P20/SCK3 P00/INTP0 P01/INTP1 P02/TI AVSS ANI3 ANI2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 VLOAD VDD2 FIP20 FIP21 FIP22 FIP23 FIP24/P30 FIP25/P31 FIP26/P32 FIP27/P33 FIP28/P34 FIP29/P35 FIP30/P36 FIP31/P37 FIP32/P40 FIP33/P41 FIP34/P42 FIP35/P43 FIP36/P44 FIP37/P45 ANI1 ANI0 VSS0 AVDD VDD0 P64/FIP52 P63/FIP51 P62/FIP50 P61/FIP49 P60/FIP48 P57/FIP47 P56/FIP46 P55/FIP45 P54/FIP44 P53/FIP43 P52/FIP42 P51/FIP41 P50/FIP40 P47/FIP39 P46/FIP38 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Cautions 1. Connect directly VPP pin to VSS1 in normal operation mode. 2. Connect AVDD pin to VDD1. 3. Connect AVSS pin to VSS1. Remark When the µPD78F0233 is used in applications where the noise generated inside the microcontroller needs to be reduced, the implementation of noise reduction measures, such as supplying voltage to VDD0 and VDD1 individually and connecting VSS0 and VSS1 to different ground lines, is recommended. 6 Data Sheet U13322EJ2V0DS µPD78F0233 ANI0 to ANI3: Analog input P60 to P64: Port 6 AVDD: Analog power supply RESET: Reset AVSS: Analog ground SCK1 and SCK3: Serial clock BUSY: Busy SI1: Serial input FIP0 to FIP52: Fluorescent indicator panel SO1 and SO3: Serial output INTP0 and INTP1: External interrupt input TI: Timer input P00 to P02: Port 0 VDD0 to VDD2: Power supply P20 to P27: Port 2 VLOAD: Negative power supply P30 to P37: Port 3 VPP: Programming power supply P40 to P47: Port 4 VSS0 and VSS1: Ground P50 to P57: Port 5 X1 and X2: Crystal Data Sheet U13322EJ2V0DS 7 µPD78F0233 2. BLOCK DIAGRAM TI/P02 8-bit remote controller timer 9 Port 0 P00 to P02 Port 2 P20 to P27 Port 3 P30 to P37 Port 4 P40 to P47 Port 5 P50 to P57 Port 6 P60 to P64 8-bit timer 80 78K/0 CPU core 8-bit timer 81 Flash memory (24 KB) Watchdog timer SCK3/P20 SO3/P21 Serial interface (2-wire mode) FIP0 to 23 RAM 768 bytes FIP24/P30 to FIP31/P37 BUSY/P24 SO1/P25 SI1/P26 Serial interface (3-wire mode) VFD controller/driver SCK1/P27 ANI0 to ANI3 AVDD INTP1/P01 VLOAD VDD2 Interrupt control (INT) System control VDD0, VDD1 8 FIP40/P50 to FIP47/P57 FIP48/P60 to FIP52/P64 A/D converter (A/D1) AVSS INTP0/P00 FIP32/P40 to FIP39/P47 VSS0, VSS1 VPP Data Sheet U13322EJ2V0DS RESET X1 X2 µPD78F0233 3. PIN FUNCTION LIST 3.1 Port Pins Pin Name P00 I/O Function After Reset I/O Port 0. 3-bit I/O port. Input/output can be specified in 1-bit units. When used as an input port, an on-chip pull-up resistor can be connected by software. Input Port 2. Input P01 P02 P20 I/O P22, P23 P24 INTP0 INTP1 TI 8-bit I/O port. Input/output can be specified in 1-bit units. When used as an input port, an on-chip pull-up resistor can be connected by software. P21 Alternate Function SCK3 SO3 — BUSY P25 SO1 P26 SI1 P27 SCK1 P30 to P37 Output Port 3. Output FIP24 to FIP31 Output FIP32 to FIP39 8-bit output-dedicated port. P40 to P47 Output Port 4. 8-bit output-dedicated port. P50 to P57 I/O Port 5. 8-bit I/O port. Input/output can be specified in 1-bit units. Input FIP40 to FIP47 P60 to P64 I/O Port 6. 5-bit I/O port. Input/output can be specified in 1-bit units. Input FIP48 to FIP52 Data Sheet U13322EJ2V0DS 9 µPD78F0233 3.2 Non-Port Pins Pin Name INTP0 I/O Input INTP1 TI SCK3 SO3 BUSY Input I/O Output Input Function After Reset Alternate Function Valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. External interrupt request input. Input P00 8-bit remote control timer 9 (TM9) timer input Input P02 Serial interface serial clock I/O Input P20 P01 Serial interface serial data output Input P21 Serial interface automatic transmit/receive busy signal output Input P24 Serial interface serial data output Input P25 SO1 Output SI1 Input Serial interface serial data input Input P26 I/O Serial interface serial clock I/O Input P27 SCK1 FIP0 to FIP23 Output VFD controller/driver high-voltage tolerant large current output. Output — On-chip pull-down resistor FIP24 to FIP31 VFD controller/driver high-voltage tolerant large current output P30 to P37 FIP32 to FIP39 P40 to P47 FIP40 to FIP47 Input FIP48 to FIP52 VLOAD P50 to P57 P60 to P64 VFD controller/driver pull-down resistor connection — — RESET Input System reset input — — X1 Input Crystal connection for system clock oscillation — — X2 — — — ANI0 to ANI3 — Input — AVDD — A/D converter analog power supply/reference voltage input; Keep the same potential with VDD1. — — AVSS — A/D converter ground potential; Keep the same potential with VSS1. — — VDD0 — Positive power supply for ports — — VDD1 — Positive power supply except for ports, analog, and VFD controller/driver — — VDD2 — Positive power supply for VFD controller/driver — — VSS0 — Ground potential for ports — — VSS1 — Ground potential except for ports and analog — — VPP — High-voltage applied during program writing/verifying; Connect directly to VSS1 pin in normal operation mode. — — 10 Input A/D converter analog input Data Sheet U13322EJ2V0DS µPD78F0233 3.3 Pin I/O Circuits and Recommended Connection of Unused Pins The I/O circuit type of each pin and the recommended connection of unused pins are shown in Table 3-1. For the I/O circuit configuration of each type, see Figure 3-1. Table 3-1. Types of Pin I/O Circuits Pin Name P00/INTP0 I/O Circuit Type I/O 8-C I/O Recommended Connection of Unused Pins Input: Independently connect to VSS0 via a resistor. Output: Leave open. P01/INTP1 P02/TI P20/SCK3 8-C I/O 14-E Output 15-E I/O 14-C Output RESET 2 Input ANI0 to ANI3 7 Input AVDD — — P21/SO3 Input: Independently connect to VDD0 or VSS0 via a resistor. Output: Leave open. P22, P23 P24/BUSY P25/SO1 P26/SI1 P27/SCK1 P30/FIP24 to P37/FIP31 Leave open. P40/FIP32 to P47/FIP39 P50/FIP40 to P57/FIP47 P60/FIP48 to P64/FIP52 FIP0 to FIP23 AVSS Input: Independently connect to VDD0 or VSS0 via a resistor. Output: Leave open. Leave open. — Connect to VDD0 or VSS0. Connect to VDD1. Connect to VSS1. VLOAD VPP Connect to VSS1 directly. Data Sheet U13322EJ2V0DS 11 µPD78F0233 Figure 3-1. Pin I/O Circuits Type 2 Type 14-C VDD0 VDD0 P-ch P-ch IN OUT Data N-ch Schmitt trigger input with hysteresis characteristics VLOAD VSS0 Type 14-E Type 7 VDD0 VDD0 P-ch IN P-ch Comparator P-ch N-ch + OUT Data – VREF (Threshold voltage) N-ch VSS0 Type 15-E Type 8-C VDD0 VDD0 P-ch Pull-up enable P-ch P-ch IN/OUT Data VDD0 N-ch Data P-ch VSS0 IN/OUT Output disable N-ch VSS0 N-ch RD VSS0 12 VDD0 Data Sheet U13322EJ2V0DS µPD78F0233 4. DIFFERENCES BETWEEN µPD78F0233 AND MASK ROM VERSION The µPD78F0233 is a product provided with an internal flash memory that enables on-board electrical writing/ erasing/rewriting. The functions of the µPD78F0233, except those specified for flash memory, can be made the same as those of the mask ROM versions by setting the memory size switching register (IMS). Table 4-1 shows the differences between the flash memory version (µPD78F0233) and the mask ROM version (µPD780232). Table 4-1. Differences Between µPD78F0233 and Mask ROM Versions µPD78F0233 Item Mask ROM Version Internal ROM structure Flash memory Mask ROM Internal ROM capacity 24 KB 16 KB IC pin Not provided Provided VPP pin Provided Not provided Pull-down resistor in FIP0 to FIP23 Provided Selected by mask option Pull-down resistor in P30/FIP24 to P37/FIP31, P40/FIP32 to P47/FIP39, P50/FIP40 to P57/FIP47, P60/FIP48 to P64/FIP52 Not provided Electrical specifications and recommended soldering conditions Refer to the data sheets of individual products. Caution There are differences in noise immunity and noise radiation between the flash memory and mask ROM versions. When pre-producing an application set with the flash memory version and then mass producing it with the mask ROM version, be sure to conduct sufficient evaluations on the commercial samples (CS) (not engineering samples (ES)) of the mask ROM versions. Data Sheet U13322EJ2V0DS 13 µPD78F0233 5. INTERNAL MEMORY SIZE SWITCHING REGISTER (IMS) IMS is a register that is set by software and is used to specify a part of the internal memory that is not to be used. By setting IMS, the internal memory of the uPD78F0233 can be mapped identically to that of a mask ROM version. IMS is set with an 8-bit memory manipulation instruction. RESET input sets IMS to CFH. Figure 5-1. Format of Internal Memory Size Switching Register Symbol IMS 7 6 5 RAM2 RAM1 RAM0 4 0 3 2 1 0 ROM3 ROM2 ROM1 ROM0 Address After reset R/W FFF0H CFH R/W ROM3 ROM2 ROM1 ROM0 Selection of internal ROM capacity 0 1 0 0 16 KB 0 1 1 0 24 KB Other than above Setting prohibited RAM2 RAM1 RAM0 Selection of internal high-speed RAM capacity 0 0 0 Other than above Caution 768 bytes Setting prohibited RESET input set IMS to CFH. After RESET input, always set IMS as follows. • µPD78F0233: 06H • When µPD78F0233 is used with the same memory map as the one used in the mask ROM version (µPD780232): 14 Data Sheet U13322EJ2V0DS 04H µPD78F0233 6. FLASH MEMORY PROGRAMMING The flash memory of the µPD78F0233 can be written while the microcontroller is mounted on the target system board. Rewriting is possible by using the dedicated flash programmer (Flashpro III (FL-PR3, PG-FP3)) or a program. When using Flashpro III, connect it to both the host machine and the target system. In addition, the flash memory can be written on the flash-programming adapter connected to Flashpro III. Remark FL-PR3 is a product of Naito Densei Machida Mfg. Co., Ltd. 6.1 Selection of Communication Mode Write operations to the flash memory are performed using Flashpro III in the serial communication mode. Choose a proper communication mode out of the ones listed in Table 6-1 to perform write operations. When selecting the communication mode, use the format illustrated in Figure 6-1. Select the communication mode according to the number of VPP pulses shown in Table 6-1. Table 6-1. List of Communication Modes Communication Modes PinsNote 1 No. of Channels VPP Pulses 3-wire serial I/O 1 SCK1/P27 SI1/P26 SO1/P25 0 Pseudo 3-wire serial I/ONote 2 1 P20/SCK3 (serial clock I/O) P21/SO3 (serial data output) P22 (serial data input) 12 Notes 1. Shifting to the flash memory programming mode sets all pins not used for flash memory programming to the same state as immediately after reset. Therefore, all ports enter an output high-impedance state. If the external device does not acknowledge an output high-impedance state, handling such as connecting to VDD0 via a resistor or connecting to VSS0 via a resistor is required. 2. Performs serial transmission by controlling ports with software. Caution Be sure to select the communication mode according to the number of VPP pulses shown in Table 6-1. Figure 6-1. Format of Communication Mode Selection VPP pulses 10 V VPP VDD 1 2 n VSS RESET VDD VSS Flash memory writing mode Data Sheet U13322EJ2V0DS 15 µPD78F0233 6.2 Flash Memory Programming Functions Operations such as writing to the flash memory are performed by various commands/data transmission and reception operations according to the selected communication mode. Table 6-2 describes the main flash memory programming functions. Table 6-2. Main Flash Memory Programming Functions Function Description Reset Used in cancellation of writing and transmission synchronization detection. Batch verify Compares the contents of the entire memory and the input data. Batch erase Erases the contents of the entire memory. Batch blank check Checks that the entire memory has been deleted. High-speed writing Writes to the flash memory based on writing-starting address and the number of writing data (bytes) Continuous writing Writes continuously based on information input at high-speed writing. Status Used to check the current operation mode and the end of operation. Oscillation frequency setting Inputs information of frequency of resonator. Erase time setting Inputs the time-length to erase the contents of the memory. Silicon signature reading Outputs the device name, memory capacity, and information of device block. 16 Data Sheet U13322EJ2V0DS µPD78F0233 6.3 Connection to Flashpro III The connection of the Flashpro III and the µPD78F0233 differs according to the communication mode. The connection for each communication mode is shown in Figure 6-2 and 6-3. Figure 6-2. Connection to Flashpro III in 3-Wire Serial I/O Mode µ PD78F0233 Flashpro III VPP VPP VDD VDD0 RESET RESET SCK SCK1 SO SI1 SI SO1 GND VSS0 Figure 6-3. Connection to Flashpro III in Pseudo 3-Wire Serial I/O Mode µ PD78F0233 Flashpro III VPP VPP VDD VDD0 RESET RESET SCK P20 (serial clock input) P22 (serial data input) P21 (serial data output) VSS0 SO SI GND Data Sheet U13322EJ2V0DS 17 µPD78F0233 7. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25°C) Parameter Supply voltage Symbol Rating Unit VDD Conditions –0.3 to +6.5 V VPP –0.3 to +10.5 V VLOAD VDD – 45 to VDD + 0.3 V AVDD –0.3 to VDD + 0.3 V AVSS –0.3 to +0.3 V –0.3 to VDD + 0.3 V Input voltage VI1 P00 to P02, P20 to P27, X1, X2, RESET VI2 P50 to P57, P60 to P64 VDD – 45 to VDD + 0.3 V Output voltage VO1 –0.3 to VDD + 0.3 V VO2 VDD – 45 to VDD + 0.3 V AVSS to AVDD V P-ch open drain Analog input voltage VAN ANI0 to ANI3 Output current, high IOH 1 pin among P00 to P02 and P20 to P27 –10 mA Total of P00 to P02 and P20 to P27 –30 mA 1 pin among FIP0 to FIP23, P30 to P37, P40 to P47, P50 to P57, and P60 to P64 –30 mA Total of FIP0 to FIP23, P30 to P37, P40 to P47, P50 to P57, and P60 to P64 Peak value –300 mA rms –120 mA 1 pin among P00 to P02 and P20 to P27 Peak value 10 mA rms 5 mA Total of P00 to P02 and P20 to P27 Peak value 20 mA rms 10 mA 700 mW Output current, low IOLNote Analog input pins Total loss PT TA = –40 to +60°C 500 mW Operating ambient temperature TA –40 to +85 °C Storage temperature Tstg –40 to +125 °C TA = –60 to +85°C Note The rms value should be calculated as follows: [rms value] = [peak value] × √Duty Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. 18 Data Sheet U13322EJ2V0DS µPD78F0233 System Clock Oscillator Characteristics (TA = –40 to +85°C, VDD = 4.5 to 5.5 V) Resonator Ceramic resonator Recommended Circuit VSS1 X1 X2 C1 Crystal resonator C2 VSS1 X1 X2 C1 C2 External clock X1 X2 µ PD74HCU04 Parameter Oscillation frequency (fX)Note 1 Conditions VDD = Oscillation voltage range MIN. TYP. MAX. Unit 1 Oscillation stabilization After VDD reaches timeNote 2 the minimum value of oscillation voltage range Oscillation frequency (fX)Note 1 1 Oscillation stabilization timeNote 2 5 MHz 4 ms 5 MHz 10 ms X1 input frequency (fX)Note 1 1 5 MHz X1 input high-/low-level width (tXH/tXL) 85 450 ns Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. 2. Time required to stabilize oscillation after reset or STOP mode release. Caution When using the main system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. • Keep the wiring length as short as possible. • Do not cross the wiring with the other signal lines. • Do not route the wiring near a signal line through which a high fluctuating current flows. • Always make the ground point of the oscillator capacitor the same potential as VSS1. • Do not ground the capacitor to a ground pattern through which a high current flows. • Do not fetch signals from the oscillator. Data Sheet U13322EJ2V0DS 19 µPD78F0233 Recommended Oscillator Constant System clock: Ceramic resonator (TA = –40 to +85°C) Manufacturer Murata Mfg. Co., Ltd. Part Number Frequency (MHz) Recommended Circuit Constant Oscillation Voltage Range C1 (pF) C2 (pF) MIN. (V) MAX. (V) CSB1000JNote 1.00 100 100 4.5 5.5 CSA2.00MG040 2.00 100 100 On-chip On-chip CST2.00MG040 CSA3.58MG 3.58 CST3.58MGW CSA4.19MG 30 On-chip 30 30 On-chip On-chip 4.19 CST4.19MGW CSA5.00MG 30 On-chip 5.00 CST5.00MGW 30 30 On-chip On-chip Remark Rd = 2.2 kΩ Note When using the CSB1000J (1.0 MHz) of Murata Mfg. Co., Ltd. as a ceramic resonator, a limiting resistor (Rd = 2.2 kΩ) is necessary (refer to the figure below). A limiting resistor is not necessary when another recommended resonator is used. X1 X2 CSB1000J C1 Caution Rd C2 The oscillator constant and oscillation voltage range indicate conditions of stable oscillation. Oscillation frequency precision is not guaranteed. For applications requiring oscillation frequency precision, the oscillation frequency must be adjusted on the implementation circuit. For details, please contact directly the manufacturer of the resonator you will use. 20 Data Sheet U13322EJ2V0DS µPD78F0233 Capacitance (TA = 25°C, VDD = VSS = 0 V) Parameter Input capacitance Output capacitance Symbol Conditions CIN COUT MIN. TYP. MAX. Unit f = 1 MHz P00 to P02, P20 to P27 Unmeasured pins returned to 0 V P50 to P57, P60 to P64 15 pF 35 pF f = 1 MHz P00 to P02, P20 to P27 Unmeasured pins returned to 0 V P30 to P37, P40 to P47, P50 to P57, P60 to P64, 15 pF 35 pF 15 pF 35 pF MAX. Unit 0.7 VDD VDD V FIP0 to FIP23 I/O capacitance CIO f = 1 MHz P00 to P02, P20 to P27 Unmeasured pins returned to 0 V P50 to P57, P60 to P64 DC Characteristics (TA = –40 to +85°C, VDD = 4.5 to 5.5 V) Parameter Symbol Input voltage, high Conditions MIN. VIH1 P00 to P02, P20 to P27, RESET VIH2 P50 to P57, P60 to P64 VIH3 X1, X2 Input voltage, low VIL1 P00 to P02, P20 to P27, RESET VIL2 X1, X2 Output voltage, high VOH IOH = –1 mA IOH = –100 µA VDD – 0.5 Output voltage, low VOL P00 to P02, P20 to P27 IOL = 400 µA Input leakage current, high ILIH1 P00 to P02, P20 to P27, P50 to P57, P60 to P64, RESET VIN = VDD ILIH2 X1, X2 ILIL1 P00 to P02, P20 to P27, RESET ILIL2 X1, X2 ILIL3 P50 to P57, P60 to P64 VIN = VLOAD = VDD – 40 V ILOH P00 to P02, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P64 VOUT = VDD Output leakage ILOL1 P00 to P02, P20 to P27 current, low ILOL2 P30 to P37, P40 to P47, P50 to P57, P60 to P64 FIP0 to FIP19 VOD = VDD – 2 V Input leakage current, low Output leakage current, high VFD output current IOD TYP. 0.7 VDD VDD V VDD – 0.5 VDD V 0 0.2 VDD V 0 0.4 V VDD – 1.0 VDD V VDD V 0.5 V 3 µA 20 µA –3 µA –20 µA –10 µA 3 µA VOUT = 0 V –3 µA VOUT = VLOAD = VDD – 40 V –10 µA –15 mA –5 mA VIN = 0 V FIP20 to FIP52 Software pull-up resistor R1 P00 to P02, P20 to P27 VIN = 0 V 10 30 100 kΩ On-chip pull-down resistor R2 FIP0 to FIP23 VOD – VLOAD = 40 V 30 60 135 kΩ Power supply currentNote IDD1 5 MHz crystal oscillation operation mode PCC = 00H 9 18 mA IDD2 5 MHz crystal oscillation HALT mode 2.5 7.5 mA IDD3 STOP mode 1 30 µA Note Refers to current flowing to the VDD pin. The current flowing to the on-chip pull-up and pull-down resistors is not included. Remarks 1. Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. 2. PCC: Processor clock control register Data Sheet U13322EJ2V0DS 21 µPD78F0233 AC Characteristics (1) Basic operation (TA = –40 to +85°C, VDD = 4.5 to 5.5 V) Parameter Cycle time Symbol Conditions MIN. TYP. MAX. Unit 32 µs TCY Operated with main system clock 0.4 Interrupt request input high-/low-level width tINTH tINTL INTP0, INTP1 10 µs RESET low-level width tRSL 10 µs (minimum instruction execution time) TCY vs VDD 60 Guaranteed Operating Range 30 Cycle time TCY (µs) µ 10 2.0 1.0 0.5 0.4 0 1 2 3 4 5 6 Supply voltage VDD (V) (2) Timer/counter (TA = –40 to +85°C, VDD = 4.5 to 5.5 V) Parameter TI input high-/ low-level width Symbol Conditions tTIH tTIL MIN. 2/Fcount +0.2Note TYP. MAX. Unit µs Note Fcount is the frequency of the count clock selected by TM9 (the frequency can be selected from fX/26, fX/27, fX/28, and fX/29). 22 Data Sheet U13322EJ2V0DS µPD78F0233 (3) Serial interface (TA = –40 to +85°C, VDD = 4.5 to 5.5 V) (a) Serial interface (3-wire serial mode) (i) 3-wire serial mode (SCK1…Internal clock output) Parameter Symbol Conditions MIN. TYP. MAX. Unit SCK1 cycle time tKCY1 800 ns SCK1 high-/low-level width tKH1 tKL1 tKCY1/2 – 50 ns SI1 setup time (to SCK1↑) tSIK1 100 ns SI1 hold time tKSI1 400 ns (from SCK1↑) Delay time from tKSO1 C = 100 pFNote 300 ns MAX. Unit SCK1↓ to SO1 output Note C is the load capacitance of the SCK1 and SO1 output lines. (ii) 3-wire serial mode (SCK1…External clock input) Parameter Symbol Conditions MIN. TYP. SCK1 cycle time tKCY2 800 ns SCK1 high-/lowlevel width tKH2 tKL2 400 ns SI1 setup time (to SCK1↑) tSIK2 100 ns SI1 hold time (from SCK1↑) tKSI2 400 ns Delay time from SCK1↓ to SO1 output tKSO2 SCK1 rise/fall time C = 100 pFNote tR2 tF2 300 ns 1 µs Note C is the load capacitance of the SO1 output line. Data Sheet U13322EJ2V0DS 23 µPD78F0233 (b) Serial interface (2-wire serial mode) (i) 2-wire serial mode (SCK3…Internal clock output) Parameter Symbol Conditions MIN. TYP. MAX. Unit SCK3 cycle time tKCY3 800 ns SCK3 high-/low-level width tKH3 tKL3 tKCY3/2 – 50 ns Delay time from SCK3↓ to SO3 output tKSO3 C = 100 pFNote 300 ns MAX. Unit Note C is the load capacitance of the SCK3 and SO3 output lines. (ii) 2-wire serial mode (SCK3…External clock input) Parameter Symbol Conditions MIN. TYP. SCK3 cycle time tKCY4 800 ns SCK3 high-/lowlevel width tKH4 tKL4 400 ns Delay time from SCK3↓ to SO3 output tKSO4 SCK3 rise/fall time C = 100 pFNote tR4 tF4 Note C is the load capacitance of the SO3 output line. 24 Data Sheet U13322EJ2V0DS 300 ns 1 µs µPD78F0233 AC Timing Test Points (Excluding X1 input) 0.8VDD 0.8VDD Test points 0.2VDD 0.2VDD Clock Timing 1/fX tXL tXH VDD –0.5 V (MIN.) X1 input 0.4 V (MAX.) Interrupt Request Input Timing tINTL tINTH INTP0, INTP1 RESET Input Timing tRSL RESET TI Timing tTIL tTIH TI Data Sheet U13322EJ2V0DS 25 µPD78F0233 Serial Transfer Timing 3-wire serial mode: tKCY1, 2 tKL1, 2 tKH1, 2 tR2 tF2 SCK1 tSIK1, 2 SI1 tKSI1, 2 Input data tKSO1, 2 SO1 Output data 2-wire serial mode: tKCY3,4 tKL3,4 tR4 tKH3,4 tF4 SCK3 tKSO3,4 SO3 A/D Converter Characteristics (TA = –40 to +85°C, AVDD = VDD = 4.0 to 5.5 V, AVSS = VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit 8 bit ±1.0 % Resolution Overall errorNote 1 Conversion timeNote 2 Analog input voltage tCONV 14 VIAN AVSS µs AVDD Notes 1. Excludes quantization error (±1/2LSB). It is indicated as a ratio to the full-scale value. 2. Set the A/D conversion time to 14 µs or more. 26 Data Sheet U13322EJ2V0DS V µPD78F0233 Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = –40 to +85°C) Parameter Symbol Data retention supply voltage VDDDR Data retention supply current IDDDR Release signal tSREL Conditions MIN. TYP. 2.0 0.1 MAX. Unit 5.5 V 30 µA µs 0 set time Oscillation stabilization wait time tWAIT Release by RESET 217/fX ms Release by interrupt request Note ms Note Selection of 212/fX and 214/fX to 217/fX is possible with bits 0 to 2 (OSTS0 to OSTS2) of the oscillation stabilization time selection register (OSTS). Data Retention Timing (STOP Mode Release by RESET) Internal reset operation HALT mode STOP mode Operating mode Data retention mode VDD VDDDR tSREL STOP instruction execution RESET tWAIT Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal) HALT mode STOP mode Operating mode Data retention mode VDD VDDDR tSREL STOP instruction execution Standby release signal (interrupt request) tWAIT Data Sheet U13322EJ2V0DS 27 µPD78F0233 Flash Memory Programming Characteristics (VDD = 4.5 to 5.5 V, VSS = 0 V, VPP = 9.7 to 10.3 V) (1) Basic characteristics Parameter Operating frequency Symbol Conditions MIN. fX Supply voltage VDD Operation voltage when writing VPP Upon VPP high-level detection VPPH Upon VPP high-voltage detection VDD supply current IDD VPP supply current IPP Write time (per byte) TWRT Number of rewrites CWRT Erase time Programming temperature TYP. MAX. Unit 1.0 5.0 MHz 4.5 5.5 V 0.8VDD VDD 1.2VDD V 9.7 10.0 10.3 V 10 mA 100 mA 500 µs 20 Times VPP =10.0 V 75 50 TERASE 1 20 s TPRG +10 +40 °C MAX. Unit (2) Serial write operation characteristics Parameter Symbol Conditions MIN. TYP. VPP set time tPSRON VPP high voltage 1.0 µs Set time from VDD↑ to VPP↑ tDRPSR VPP high voltage 1.0 µs Set time from VPP↑ to RESET↑ tPSRRF VPP high voltage 1.0 µs VPP count start time from RESET↑ tRFCF 1.0 µs Count execution time tCOUNT 2.0 ms VPP counter high-level width tCH 8.0 µs VPP counter low-level width tCL 8.0 µs VPP counter noise elimination width tNFW 40 Flash Memory Write Mode Set Timing VDD VDD 0V tDRPSR tRFCF tCH VPPH VPP VPP tCL VPPL tPSRON tPSRRF tCOUNT VDD RESET (input) 0V 28 Data Sheet U13322EJ2V0DS ns µPD78F0233 8. PACKAGE DRAWING 80-PIN PLASTIC QFP (14x14) A B 60 61 41 40 detail of lead end S C D R Q 80 1 21 20 F J G I H M P K S N S L M NOTE Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS A 17.20±0.20 B 14.00±0.20 C 14.00±0.20 D 17.20±0.20 F 0.825 G 0.825 H I 0.32±0.06 0.13 J 0.65 (T.P.) K 1.60±0.20 L 0.80±0.20 M 0.17 +0.03 −0.07 N P 0.10 1.40±0.10 Q 0.125±0.075 R +7° 3° −3° S 1.70 MAX. P80GC-65-8BT-1 Data Sheet U13322EJ2V0DS 29 µPD78F0233 9. RECOMMENDED SOLDERING CONDITIONS The µPD78F0233 should be soldered and mounted under the following recommended conditions. For details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact an NEC sales representative. Table 9-1. Surface Mounting Type Soldering Conditions µPD78F0233GC-8BT: 80-pin plastic QFP (14 × 14) Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher), Count: Two times or less IR35-00-2 VPS Package peak temperature: 215°C, Time: 40 seconds max. (at 200°C or higher), Count: Two times or less VP15-00-2 Wave soldering Solder bath temperature: 260°C max., Time: 10 seconds max., Count: Twice Preheating temperature: 120°C max. (package surface temperature) WS60-00-2 Partial heating Pin temperature: 300°C max., Time: 3 seconds max. (per pin row) Caution Do not use different soldering methods together (except for partial heating). 30 Data Sheet U13322EJ2V0DS — µPD78F0233 APPENDIX A. DEVELOPMENT TOOLS The following development tools are available for system development using the µPD78F0233. Also refer to (6) Notes on using development tools. (1) Software Package SP78K0 78K/0 Series common software package (2) Language Processing Software RA78K0 78K/0 Series common assembler package CC78K0 78K/0 Series common C compiler package DF780233 µPD780232 Subseries device file CC78K0-L 78K/0 Series common C compiler library source file (3) Flash Memory Writing Tools Flashpro III (FL-PR3, GP-FP3) Dedicated flash programmer for on-chip flash memory microcontrollers FA-80GC Adapter for flash memory writing Used by connecting to Flashpro III • For 80-pin plastic QFP (GC-8BT type) (4) Debugging Tools • When in-circuit emulator IE-78K0-NS (-A) is used IE-78K0-NS (-A) In-circuit emulator common to 78K/0 Series IE-70000-MC-PS-B Power supply unit for IE-78K0-NS IE-78K0-NS-PA Performance board that enhances and expands the IE-78K0-NS functions IE-70000-98-IF-C Adapter required when PC-9800 series (except notebook type) is used as host machine (C bus supported) IE-70000-CD-IF-A PC card and interface cable required when notebook type PC is used as host machine (PCMCIA socket supported) IE-70000-PC-IF-C Adapter required when IBM PC/AT™ or compatible is used as host machine IE-70000-PCI-IF-A Adapter required when PC incorporating PCI bus is used as host machine IE-780233-NS-EM4, IE-78K0-NS-P01 Emulation board and I/O board to emulate the µPD780232 Subseries NP-80GC NP-80GC-TQ NP-H80GC-TQ Emulation probe for 80-pin plastic QFP (GC-8BT type) EV-9200GC-80 Conversion socket to connect the NP-80GC and the target system board on which 80-pin plastic QFP (GC-8BT type) can be mounted TGC-080SBP Conversion adapter to connect the NP-80GC-TQ or NP-H80GC-TQ and a target system board on which an 80-pin plastic QFP (GC-8BT type) can be mounted ID78K0-NS Integrated debugger for IE-78K0-NS SM78K0 System simulator common to 78K/0 Series DF780233 Device file for µPD780232 Subseries Data Sheet U13322EJ2V0DS 31 µPD78F0233 • When in-circuit emulator IE-78001-R-A is used IE-78001-R-A In-circuit emulator common to 78K/0 Series IE-70000-98-IF-C Adapter required when PC-9800 series (except notebook type) is used as host machine (C bus supported) IE-70000-PC-IF-C Adapter required when IBM PC/AT or compatible is used as host machine (ISA bus supported) IE-70000-PCI-IF-A Adapter required when PC incorporating PCI bus is used as host machine IE-70000-R-SV3 Interface adapter and cable required when EWS is used as host machine IE-780233-NS-EM4, IE-78K0-NS-P01 Emulation board and I/O board to emulate the µPD780232 Subseries IE-78K0-R-EX1 Emulation probe conversion board required when using IE-780232-NS-EM1 on IE-78001-R-A EP-78230GC-R Emulation probe for 80-pin plastic QFP (GC-8BT type) EV-9200GC-80 Conversion socket to connect the EP-78230GC-R and the target system board on which 80-pin plastic QFP (GC-8BT type) can be mounted ID78K0 Integrated debugger for IE-78001-R-A SM78K0 System simulator common to 78K/0 Series DF780233 Device file for µPD780232 Subseries (5) Real-Time OSs RX78K0 Real-time OS for 78K/0 Series MX78K0 OS for 78K/0 Series (6) Notes on using development tools • The ID78K0-NS, ID78K0, and SM78K0 in combination with the DF780233. • The CC78K0 and RX78K0 are used in combination with the RA78K0 and DF780233. • FL-PR3, FA-80GC, NP-80GC, NP-80GC-TQ, and NP-H80GC-TQ are products made by Naito Densei Machida Mfg. Co., Ltd. (+81-45-475-4191). • TGK-080SBP is a product made by TOKYO ELETECH CORPORATION. For further information, contact Daimaru Kogyo, Ltd. Tokyo Electronics Department (+81-3-3820-7112) Osaka Electronics Department (+81-6-6244-6672) • For third-party development tools, refer to Single-Chip Microcontroller Selection Guide (U11069E). • The host machines and OS suitable for each software are as follows: Host Machine [OS] PC EWS HP9000 series 700™ [HP-UX™] SPARCstation™ [SunOS™, Solaris™] Software PC-9800 series [Windows™] IBM PC/AT or compatibles [Japanese/English Windows] RA78K0 √Note √ CC78K0 √Note √ ID78K0-NS √ — ID78K0 √ — SM78K0 √ — RX78K0 √Note √ MX78K0 √Note √ Note DOS-based software 32 Data Sheet U13322EJ2V0DS µPD78F0233 CONVERSION SOCKET (EV-9200GC-80) DRAWING AND RECOMMENDED BOARD MOUNTING PATTERN Figure A-1. EV-9200GC-80 Drawing (for reference only) A E M B N O L K S J C D R F EV-9200GC-80 Q 1 No.1 pin index P G H I EV-9200GC-80-G1E ITEM MILLIMETERS INCHES A 18.0 0.709 B 14.4 0.567 C 14.4 0.567 D 18.0 0.709 E 4-C 2.0 4-C 0.079 F 0.8 0.031 G 6.0 0.236 H 16.0 0.63 I 18.7 0.736 J 6.0 0.236 K 16.0 0.63 L 18.7 0.736 M 8.2 0.323 N 8.0 0.315 O 2.5 0.098 P 2.0 0.079 Q 0.35 0.014 R φ 2.3 φ 0.091 S φ 1.5 φ 0.059 Data Sheet U13322EJ2V0DS 33 µPD78F0233 Figure A-2. EV-9200GC-80 Recommended Board Mounting Pattern (for reference only) G J H D E F K I L C B A EV-9200GC-80-P1E ITEM MILLIMETERS A 19.7 0.776 B 15.0 0.591 C +0.003 0.65±0.02 × 19=12.35±0.05 0.026+0.001 –0.002 × 0.748=0.486 –0.002 D +0.003 0.65±0.02 × 19=12.35±0.05 0.026 +0.001 –0.002 × 0.748=0.486 –0.002 E 15.0 0.591 F 19.7 0.776 G 6.0 ± 0.05 0.236 +0.003 –0.002 H 6.0 ± 0.05 0.236 +0.003 –0.002 I 0.35 ± 0.02 0.014 +0.001 –0.001 J φ 2.36 ± 0.03 φ 0.093+0.001 –0.002 K φ 2.3 φ 0.091 L φ 1.57 ± 0.03 φ 0.062+0.001 –0.002 Caution 34 INCHES Dimensions of mount pad for EV-9200 and that for target device (QFP) may be different in some parts. For the recommended mount pad dimensions for QFP, refer to "SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL" (C10535E). Data Sheet U13322EJ2V0DS µPD78F0233 APPENDIX B. RELATED DOCUMENTS The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents Related to Device Document Name Document No. µPD780232 Subseries User’s Manual U13364E µPD780232 Data Sheet U13415E µPD78F0233 Data Sheet This manual 78K/0 Series User’s Manual - Instructions U12326E Documents Related to Development Tool (User’s Manual) Document Name RA78K0 Assembler Package CC78K0 C Compiler Document No. Operation U14445E Language U14446E Structured Assembly Language U11789E Operation U14297E Language U14298E IE-78K0-NS In-Circuit Emulator U13731E IE-78K0-NS-A In-Circuit Emulator U14889E IE-78001-R-A In-Circuit Emulator U14142E IE-78K0-R-EX1 In-Circuit Emulator To be prepared IE-780233-NS-EM4 Emulation Board U14666E EP-78230 Emulation Probe EEU-1515 SM78K0S, SM78K0 System Simulator Ver. 2.10 or Later Windows Based Operation U14611E SM78K Series System Simulator Ver. 2.10 or Later External Part User Open Interface Specifications U15006E ID78K0-NS Integrated Debugger Ver. 2.00 or Later Windows Based Operation U14379E ID78K0-NS, ID78K0S-NS Integrated Debugger Ver. 2.20 or Later Windows Based Operation U14910E ID78K0 Integrated Debugger Windows Based Reference U11539E Guide U11649E Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing. Data Sheet U13322EJ2V0DS 35 µPD78F0233 Documents Related to Embedded Software (User’s Manuals) Document Name 78K/0 Series Real-Time OS 78K/0 Series OS MX78K0 Document No. Fundamental U11537E Installation U11536E Fundamental U12257E Other Related Documents Document Name Document No. SEMICONDUCTOR SELECTION GUIDE - Products & Packages - (CD-ROM) X13769E Semiconductor Device Mounting Technology Manual C10535E Quality Guides on NEC Semiconductor Devices C11531E NEC Semiconductor Device Reliability and Quality Control C10983E Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892E Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing. 36 Data Sheet U13322EJ2V0DS µPD78F0233 [MEMO] Data Sheet U13322EJ2V0DS 37 µPD78F0233 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 38 Data Sheet U13322EJ2V0DS µPD78F0233 Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • Ordering information • Product release schedule • Availability of related technical literature • Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) • Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) NEC Electronics (Germany) GmbH NEC Electronics Hong Kong Ltd. Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288 Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics Hong Kong Ltd. Velizy-Villacoublay, France Tel: 01-3067-5800 Fax: 01-3067-5899 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (France) S.A. NEC Electronics Singapore Pte. Ltd. Madrid Office Madrid, Spain Tel: 091-504-2787 Fax: 091-504-2860 Novena Square, Singapore Tel: 253-8311 Fax: 250-3583 NEC Electronics (France) S.A. NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics (UK) Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 NEC Electronics Taiwan Ltd. NEC Electronics Italiana s.r.l. NEC Electronics (Germany) GmbH Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951 NEC do Brasil S.A. Electron Devices Division Guarulhos-SP, Brasil Tel: 11-6462-6810 Fax: 11-6462-6829 J01.2 Data Sheet U13322EJ2V0DS 39 µPD78F0233 FIP and IEBus are trademarks of NEC Corporation. Windows is either a registered trademark or a trademark of Microsoft Corporation in the United States and/ or other countries. PC/AT is a trademark of International Business Machines Corporation. HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. Solaris and SunOS are trademarks of Sun Microsystems, Inc. • The information in this document is current as of February, 2001. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. • No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. • NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. • Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. • While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. • NEC semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above). M8E 00. 4