NEC UPD75P3116

DATA SHEET
MOS INTEGRATED CIRCUIT
µPD75P3116
4-BIT SINGLE-CHIP MICROCONTROLLER
The µPD75P3116 replaces the µPD753108’s internal mask ROM with a one-time PROM, and features expanded ROM
capacity.
Because the µ PD75P3116 supports programming by users, it is suitable for use in evaluation of systems in the
development stage using the µ PD753104, 753106, or 753108, and for use in small-scale production.
Detailed information about functions is provided in the following User’s Manual. Be sure to read it before
designing:
µ PD753108 User’s Manual : U10890E
FEATURES
Compatible with µ PD753108
Memory capacity:
• PROM : 16384 x 8 bits
• RAM
: 512 x 4 bits
Can be operated in same power supply voltage range as the mask version µ PD753108
• VDD = 1.8 to 5.5 V
On-chip LCD controller/driver
QTOPTM microcontroller
Remark QTOP microcontrollers are microcontrollers with on-chip one-time PROM that are totally supported by NEC.
The support include writing application programs, marking, screening, and verification.
ORDERING INFORMATION
Part Number
Package
µ PD75P3116GC-AB8
64-pin plastic QFP (14 x 14 mm, 0.8-mm pitch)
µ PD75P3116GK-8A8
64-pin plastic QFP (12 x 12 mm, 0.65-mm pitch)
Caution This device does not provide an internal pull-up resistor connection function by means of mask
option.
The information in this document is subject to change without notice.
Document No. U11369EJ2V0DS00 (2nd edition)
Date Published March 1997 N
Printed in Japan
The mark
shows major revised points.
©
1994
µ PD75P3116
FUNCTION OUTLINE
Item
2
Function
Instruction execution time
• 0.95, 1.91, 3.81, or 15.3 µs (main system clock: @ 4.19 MHz)
• 0.67, 1.33, 2.67, or 10.7 µs (main system clock: @ 6.0 MHz)
• 122 µs (subsystem clock: @ 32.768 kHz)
Internal memory
PROM
16384 x 8 bits
RAM
512 x 4 bits
General-purpose register
• 4-bit manipulation: 8 x 4 banks
• 8-bit manipulation: 4 x 4 banks
I/O ports
CMOS input
8
Internal pull-up resistor connection can be specified by software: 7
CMOS I/O
20
Internal pull-up resistor connection can be specified by software: 12
Shared by segment pin: 8
N-ch open-drain I/O
4
13-V withstand voltage
Total
32
LCD controller/driver
• Segment number selection : 16/20/24 segments (Switchable to CMOS I/O
ports in a batch of 4 pins, max. 8 pins)
• Display mode selection
: static, 1/2 duty (1/2 bias), 1/3 duty (1/2 bias),
1/3 duty (1/3 bias), 1/4 duty (1/3 bias)
Timers
5 channels: • 8-bit timer/event counter : 3 channels
(Can be used as 16-bit timer/event counter, carrier generator,
and timer with gate)
• Basic interval timer/watchdog timer : 1 channel
• Watch timer : 1 channel
Serial interface
• 3-wire serial I/O mode ··· MSB/LSB first switchable
• 2-wire serial I/O mode
• SBI mode
Bit sequential buffer (BSB)
16 bits
Clock output (PCL)
Φ, 524, 262, and 65.5 kHz (main system clock: @ 4.19 MHz)
Φ, 750, 375, and 93.8 kHz (main system clock: @ 6.0 MHz)
Buzzer output (BUZ)
• 2, 4, and 32 kHz (main system clock: @ 4.19 MHz or subsystem clock: @ 32.768 kHz)
• 2.93, 5.86, 46.9 kHz (main system clock: @ 6.0 MHz)
Vectored interrupts
• External : 3
• Internal : 5
Test inputs
• External : 1
• Internal : 1
System clock oscillation circuit
• Ceramic/crystal oscillation circuit for main system clock
• Crystal oscillation circuit for subsystem clock
Standby function
STOP/HALT mode
Power supply voltage
VDD = 1.8 to 5.5 V
Package
• 64-pin plastic QFP (14 x 14 mm, 0.8-mm pitch)
• 64-pin plastic QFP (12 x 12 mm, 0.65-mm pitch)
µ PD75P3116
CONTENTS
1. PIN CONFIGURATION (Top View) ..................................................................................................
4
2. BLOCK DIAGRAM ............................................................................................................................
5
3. PIN FUNCTIONS ...............................................................................................................................
6
3.1
Port Pins ...................................................................................................................................................
6
3.2
Non-port Pins ...........................................................................................................................................
8
3.3
Equivalent Circuits for Pins .................................................................................................................... 10
3.4
Recommended Connection of Unused Pins ......................................................................................... 12
4. Mk I AND Mk II MODE SELECTION FUNCTION ............................................................................. 13
4.1
Differences between Mk I Mode and Mk II Mode ................................................................................... 13
4.2
Setting of Stack Bank Selection (SBS) Register ................................................................................... 14
5. DIFFERENCES BETWEEN µPD75P3116 AND µPD753104, 753106, AND 753108 ...................... 15
6. MEMORY CONFIGURATION ........................................................................................................... 16
7. INSTRUCTION SET .......................................................................................................................... 18
8. ONE-TIME PROM (PROGRAM MEMORY) WRITE AND VERIFY ................................................... 27
8.1
Operation Modes for Program Memory Write/Verify ............................................................................ 27
8.2
Program Memory Write Procedure ......................................................................................................... 28
8.3
Program Memory Read Procedure ......................................................................................................... 29
8.4
One-time PROM Screening ..................................................................................................................... 30
9. ELECTRICAL SPECIFICATIONS ..................................................................................................... 31
10. CHARACTERISTIC CURVES (REFERENCE VALUES) .................................................................. 46
11. PACKAGE DRAWINGS ................................................................................................................... 48
12. RECOMMENDED SOLDERING CONDITIONS ................................................................................ 50
APPENDIX A. FUNCTION LIST OF µPD75308B, 753108, AND 75P3116 ........................................... 51
APPENDIX B. DEVELOPMENT TOOLS ................................................................................................ 53
APPENDIX C. RELATED DOCUMENTS ............................................................................................... 57
3
µ PD75P3116
1. PIN CONFIGURATION (Top View)
• 64-pin plastic QFP (14 x 14 mm, 0.8-mm pitch) : µ PD75P3116GC-AB8
COM3
COM2
COM1
COM0
S0
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
• 64-pin plastic QFP (12 x 12 mm, 0.65-mm pitch) : µ PD75P3116GK-8A8
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
1
47
2
46
3
45
4
44
5
43
6
42
7
41
8
40
9
39
10
38
11
37
12
36
13
35
14
34
15
33
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
S12
S13
S14
S15
P93/S16
P92/S17
P91/S18
P90/S19
P83/S20
P82/S21
P81/S22
P80/S23
P23/BUZ
P22/PCL/PTO2
P21/PTO1
P20/PTO0
P63/KR3/D3
RESET
XT1
XT2
VPP Note
X1
X2
VDD
P00/INT4
P01/SCK
P02/SO/SB0
P03/SI/SB1
P10/INT0
P11/INT1
P12/INT2/TI1/TI2
P13/TI0
BIAS
VLC0
VLC1
VLC2
P30/LCDCL/MD0
P31/SYNC/MD1
P32/MD2
P33/MD3
Vss
P50/D4
P51/D5
P52/D6
P53/D7
P60/KR0/D0
P61/KR1/D1
P62/KR2/D2
Note
Always connect the VPP pin directly to VDD during normal operation.
PIN IDENTIFICATIONS
4
P00-P03
: Port0
COM0 to COM3 : Common Output 0 to 3
P10-P13
: Port1
VLC0 to VLC2
: LCD Power Supply 0 to 2
P20-P23
: Port2
BIAS
: LCD Power Supply Bias Control
P30-P33
: Port3
LCDCL
: LCD Clock
P50-P53
: Port5
SYNC
: LCD Synchronization
P60-P63
: Port6
TI0 to TI2
: Timer Input 0 to 2
P80-P83
: Port8
PTO0 to PTO2
: Programmable Timer Output 0 to 2
P90-P93
: Port9
BUZ
: Buzzer Clock
KR0-KR3
: Key Return 0 to 3
PCL
: Programmable Clock
SCK
: Serial Clock
INT0, 1, 4
: External Vectored Interrupt 0, 1, 4
SI
: Serial Input
INT2
: External Test Input 2
SO
: Serial Output
X1, X2
: Main System Clock Oscillation 1, 2
SB0, SB1
: Serial Data Bus 0, 1
XT1, XT2
: Subsystem Clock Oscillation 1, 2
RESET
: Reset
VPP
: Programming Power Supply
MD0 to MD3
: Mode Selection 0 to 3
VDD
: Positive Power Supply
D0 to D7
: Data Bus 0 to 7
Vss
: Ground
S0 to S23
: Segment Output 0 to 23
µ PD75P3116
2. BLOCK DIAGRAM
WATCH
TIMER
BUZ/P23
INTW fLCD
BASIC
INTERVAL
TIMER/
WATCHDOG
TIMER
SP (8)
PROGRAM
COUNTER (14)
CY
SBS
ALU
TI1/TI2/
P12/INT2
8-BIT
TIMER/EVENT
COUNTER #0
PTO1/P21
PTO2/
PCL/P22
TOUT0
INTT0 TOUT0
INTT1
8-BIT
CASCADED
TIMER/EVENT 16-BIT
COUNTER #1 TIMER/
EVENT
8-BIT
TIMER/EVENT COUNTER
COUNTER #2
GENERAL
REG.
PROGRAM
MEMORY
(PROM)
16384 x 8 BITS
DECODE
AND
CONTROL
INTT2
SI/SB1/P03
SO/SB0/P02
SCK/P01
4
P00 to P03
PORT1
4
P10 to P13
PORT2
4
P20 to P23
PORT3
4
P30/MD0 to
P33/MD3
PORT5
4
P50/D4 to
P53/D7
PORT6
4
P60/D0 to
P63/D3
PORT8
4
P80 to P83
PORT9
4
P90 to P93
16
S0 to S15
4
S16/P93 to
S19/P90
4
S20/P83 to
S23/P80
4
COM0 to COM3
BANK
INTBT
TI0/P13
PTO0/P20
PORT0
CLOCKED
SERIAL
INTERFACE
DATA
MEMORY
(RAM)
512 x 4 BITS
INTCSI TOUT0
INT0/P10
INT1/P11
INT4/P00
INT2/P12/TI1/TI2
P60/KR0 to
P63/KR3
LCD
CONTROLLER/
DRIVER
INT1
INTERRUPT
CONTROL
4
fx/2 N
BIT SEQ.
BUFFER (16)
CPU CLOCK Φ
SYSTEM CLOCK
CLOCK
CLOCK GENERATOR
STAND BY
OUTPUT
DIVIDER
CONTROL
CONTROL
MAIN
SUB
PCL/PTO2/P22
X1 X2 XT1 XT2
fLCD
BIAS
VLC0
VLC1
VLC2
SYNC/P31
LCDCL/P30
VDD Vss VPP RESET
5
µ PD75P3116
3. PIN FUNCTIONS
3.1 Port Pins (1/2)
Pin name
I/O
Alternate function
Function
Status
after reset
I/O circuit
typeNote 1
X
Input
<B>
P00
Input
INT4
P01
I/O
SCK
P02
I/O
SO/SB0
<F>-B
P03
I/O
SI/SB1
<M>-C
P10
Input
INT0
P11
INT1
P12
TI1/TI2/INT2
P13
TI0
P20
I/O
PTO0
P21
PTO1
P22
PCL/PTO2
P23
BUZ
P30
I/O
LCDCL/MD0
P31
SYNC/MD1
P32
MD2
P33
MD3
P50 Note 2
I/O
D4
P51 Note 2
D5
P52 Note 2
D6
P53 Note 2
D7
4-bit input port (PORT0)
P01 to P03 are 3-bit pins for which connection of
an internal pull-up resistor can be specified by
software.
8-bit
I/O
<F>-A
4-bit input port (PORT1)
Connection of an internal pull-up resistor can be
specified by software in 4-bit units.
P10/INT0 can select noise elimination circuit.
X
Input
<B>-C
4-bit I/O port (PORT2)
Connection of an internal pull-up resistor
can be specified by software in 4-bit units.
X
Input
E-B
Programmable 4-bit I/O port (PORT3)
Input and output in single-bit units can be specified.
When set for 4-bit units, connection of an internal
pull-up resistor can be specified by software.
X
Input
E-B
N-ch open-drain 4-bit I/O port (PORT5)
When set to open-drain, voltage is 13 V.
X
High
impedance
M-E
Notes 1. Circuit types enclosed in brackets indicate Schmitt trigger input.
2. Low-level input leakage current increases when input instructions or bit manipulation instructions are executed.
6
µ PD75P3116
3.1 Port Pins (2/2)
Pin name
P60
I/O
I/O
Alternate function
KR0/D0
P61
KR1/D1
P62
KR2/D2
P63
KR3/D3
P80
I/O
S23
P81
S22
P82
S21
P83
S20
P90
I/O
S19
P91
S18
P92
S17
P93
S16
Function
8-bit
I/O
Status
after reset
I/O circuit
type Note 1
Programmable 4-bit I/O port (PORT6)
Input and output in single-bit units can be specified.
When set for 4-bit units, connection of an internal
pull-up resistor can be specified by software.
X
Input
<F>-A
4-bit I/O port (PORT8)
When set for 4-bit units, connection of an internal
pull-up resistor can be specified by softwareNote 3.
Input
H
Programmable 4-bit I/O port (PORT9)
When set for 4-bit units, connection of an internal
pull-up resistor can be specified by softwareNote 3.
Input
H
Notes 1. Circuit types enclosed in brackets indicate Schmitt trigger input.
2. Low-level leak current increases when an input instruction or a bit manipulation instruction is performed.
3. Do not connect an internal pull-up resistor by software when used as the segment signal output.
7
µ PD75P3116
3.2 Non-port Pins (1/2)
Pin name
TI0
I/O
Input
TI1
Alternate function
P13
Function
Status
after reset
I/O circuit
typeNote 1
External event pulse input to timer/event counter
Input
<B>-C
Timer/event counter output
Input
E-B
Input
<F>-A
P12/INT2/TI2
TI2
P12/INT2/TI1
PTO0
Output
P20
PTO1
P21
PTO2
P22/PCL
PCL
P22/PTO2
Clock output
BUZ
P23
Frequency output (for buzzer or system clock trimming)
P01
Serial clock I/O
SO/SB0
P02
Serial data output
Serial data bus I/O
<F>-B
SI/SB1
P03
Serial data input
Serial data bus I/O
<M>-C
SCK
I/O
INT4
Input
P00
Edge detection vectored interrupt input
(valid for detecting both rising and falling edges)
INT0
Input
P10
Edge detection vectored interrupt input With noise elimination
(detection edge is selectable)
circuit/asynch is selectable
P11
INT0/P10 can select noise elimination circuit. Asynch
INT1
INT2
KR0 to KR3
Input
P12/TI1/TI2
Rising edge detection testable input
I/O
P60 to P63
Parallel falling edge detection testable input
X1
Input
X2
—
XT1
Input
XT2
—
RESET
Input
MD0 to MD3
Input
D0 to D3
I/O
D4 to D7
VPP
Note 2
<B>
Input
<B>-C
Input
<F>-A
Asynch
—
Ceramic/crystal resonator connection for main system
clock oscillation. If using an external clock, input signal to X1
and input inverted phase to X2.
—
—
—
Crystal resonator connection for subsystem clock oscillation.
If using an external clock, input signal to XT1 and input inverted
phase to XT2. XT1 can be used as a 1-bit (test) input.
—
—
—
System reset input (low-level active)
—
<B>
Input
E-B
Input
<F>-A
P30 to P33
Mode selection for program memory (PROM) write/verify
P60/KR0 to P63/KR3 Data bus for program memory (PROM) write/verify
P50 to P53
M-E
—
—
Programmable power supply voltage applied for program
memory (PROM) write/verify.
For normal operation, connect directly to VDD .
Apply +12.5 V for PROM write/verify.
—
—
VDD
—
—
Positive power supply
—
—
Vss
—
—
Ground potential
—
—
Notes 1. Circuit types enclosed in brackets indicate Schmitt trigger input.
2. The VPP pin does not operate correctly when it is not connected to the VDD pin during normal operation.
8
µ PD75P3116
3.2 Non-port Pins (2/2)
Pin name
I/O
Alternate function
S0 to S15
Output
—
S16 to S19
Output
S20 to S23
Output
COM0 to COM3 Output
VLC0 to VLC2
BIAS
LCDCL Note 3
SYNC
Note 3
Status
after reset
I/O circuit
type
Segment signal output
Note 1
G-A
P93 to P90
Segment signal output
Input
H
P83 to P80
Segment signal output
Input
H
Common signal output
Note 1
G-B
—
Function
—
—
Power supply for driving LCD
Output
—
Output for external split resistor cut
—
—
Note 2
—
I/O
P30/MD0
Clock output for driving external expansion driver
Input
E-B
I/O
P31/MD1
Clock output for synchronization of external expansion driver
Input
E-B
Notes 1. The VPP pin does not operate normally if it is not connected with V DD pin when normal operation.
2. The VLCX (X = 0, 1, 2) shown below are selected as the input source for the display outputs.
S0 to S23: VLC1, COM0 to COM2: VLC2, COM3: VLC0
3. When the split resistor is incorporated
: Low level
When the split resistor is not incorporated : High impedance
4. These pins are provided for future system expansion. Currently, only P30 and P31 are used.
9
µ PD75P3116
3.3 Equivalent Circuits for Pins
The equivalent circuits for the µPD75P3116’s pins are shown in abbreviated form below.
TYPE A
TYPE D
VDD
VDD
Data
P-ch
OUT
P-ch
IN
Output
disable
N-ch
CMOS standard input buffer
TYPE B
N-ch
Push-pull output that can be set to high impedance output
(with both P-ch and N-ch OFF).
TYPE E-B
VDD
P.U.R.
P.U.R.
enable
P-ch
IN
Data
IN/OUT
Type D
Output
disable
Type A
Schmitt trigger input with hysteresis characteristics.
P.U.R. : Pull-Up Resistor
TYPE B-C
TYPE F-A
VDD
VDD
P.U.R.
P.U.R.
enable
P.U.R.
P-ch
P.U.R.
enable
P-ch
Data
IN/OUT
Type D
Output
disable
IN
Type B
P.U.R. : Pull-Up Resistor
P.U.R. : Pull-Up Resistor
(Continued)
10
µ PD75P3116
(Continued)
TYPE F-B
TYPE H
VDD
P.U.R.
P.U.R.
enable
P-ch
Output
disable
(P)
VDD
SEG
data
P-ch
Type G-A
IN/OUT
N-ch
P-ch
IN/OUT
Data
Output
disable
N-ch
Data
Output
disable
(N)
Type E-B
Output
disable
P.U.R. : Pull-Up Resistor
TYPE G-A
TYPE M-C
VDD
P-ch
N-ch
VLC0
VLC1
P.U.R.
P-ch
N-ch
P.U.R.
enable
P-ch
P-ch N-ch
IN/OUT
OUT
SEG
data
Data
N-ch
Output
disable
N-ch
P-ch
N-ch
VLC2
N-ch
P.U.R. : Pull-Up Resistor
TYPE G-B
TYPE M-E
IN/OUT
VLC0
VLC1
Data
P-ch
N-ch
N-ch
(+13-V
withstand
voltage)
Output
disable
P-ch
N-ch
VDD
P-ch N-ch
Input instruction
OUT
P-ch
Note
P.U.R.
COM
data
N-ch P-ch
P-ch
N-ch
VLC2
N-ch
Voltage
controller
(+13-V
withstand
voltage)
Note Pull-up resistor that operates only when an input
instruction is executed. (The current flows from
VDD to a pin when the pin is at low level.)
11
µ PD75P3116
3.4 Recommended Connection of Unused Pins
Table 3-1. List of Unused Pin Connection
Pin
Recommended connection
P00/INT4
Connect to Vss or VDD
P01/SCK
Individually connect to Vss or VDD through a resistor.
P02/SO/SB0
P03/SI/SB1
Connect to Vss
P10/INT0 and P11/INT1
Connect to Vss or VDD
P12/TI1/TI2/INT2
P13/TI0
P20/PTO0
Input status
: Individually connect to Vss or V DD
P21/PTO1
P22/PTO2/PCL
through a resistor
Output status : Leave open
P23/BUZ
P30/LCDCL/MD0
P31/SYNC/MD1
P32/MD2
P33/MD3
P50/D4 to P53/D7
Connect to Vss
P60/KR0/D0 to P63/KR3/D3
Input status : Individually connect to Vss or VDD through a resistor
Output status : Leave open
S0 to S15
Leave open
COM0 to COM3
S16/P93 to S19/P90
Input status
: Individually connect to Vss or VDD through a resistor
S20/P83 to S23/P80
Output status : Leave open
VLC0 to VLC2
Connect to Vss
BIAS
Connect to Vss only when neither of VLC0, VLC1 and
VLC2 is used. In other cases, leave open.
XT1 Note
Connect to Vss or VDD
XT2 Note
Leave open
VPP
Always connect to VDD directly
Note In case the subsystem clock is not used, set SOS.0 = 1 (on-chip feedback
resistor not used).
12
µ PD75P3116
4. Mk I AND Mk II MODE SELECTION FUNCTION
Setting a stack bank selection (SBS) register for the µPD75P3116 enables the program memory to be switched between
the Mk I mode and Mk II mode. This function is applicable when using the µPD75P3116 to evaluate the µPD753104,
753106, or 753108.
When the SBS bit 3 is set to 1 : sets the Mk I mode (supports the Mk I mode for the µPD753104, 753106, and 753108)
When the SBS bit 3 is set to 0 : sets the Mk II mode (supports the Mk II mode for the µPD753104, 753106, and 753108)
4.1 Differences between Mk I Mode and Mk II Mode
Table 4-1 lists differences between the Mk I mode and the Mk II mode for the µPD75P3116.
Table 4-1. Differences between Mk I Mode and Mk II Mode
Item
Mk I mode
Mk II mode
Program counter
PC13-0
Program memory (bytes)
16384
Data memory (bits)
512 x 4
Stack
Stack bank
Selectable via memory banks 0, 1
No. of stack bytes
2 bytes
3 bytes
BRA !addr1 instruction
Not available
Available
3 machine cycles
4 machine cycles
execution time CALLF !faddr instruction
2 machine cycles
3 machine cycles
Supported mask ROMs
When set to Mk I mode:
µPD753104, 753106, and 753108
When set to Mk II mode:
µPD753104, 753106, and 753108
Instruction
CALLA !addr1 instruction
Instruction
Caution
CALL !addr instruction
The Mk II mode supports a program area exceeding 16 Kbytes for the 75X and 75XL Series. Therefore,
this mode is effective for enhancing software compatibility with products that have a program area of
more than 16 Kbytes.
With regard to the number of stack bytes during execution of subroutine call instructions, the usable
area increases by 1 byte per stack compared to the Mk I mode when the Mk II mode is selected.
However, when the CALL !addr and CALLF !faddr instructions are used, the machine cycle becomes
longer by 1 machine cycle. Therefore, if more emphasis is placed on RAM use efficiency and
processing performance than on software compatibility, the Mk I mode should be used.
13
µ PD75P3116
4.2 Setting of Stack Bank Selection (SBS) Register
Use the stack bank selection register to switch between the Mk I mode and Mk II mode. Figure 4-1 shows the format of
the stack bank selection register.
The stack bank selection register is set using a 4-bit memory manipulation instruction. When using the Mk I mode, be
sure to initialize the stack bank selection register to 100XB Note at the beginning of the program. When using the Mk II mode,
be sure to initialize it to 000XB Note.
Note Set the desired value for X.
Figure 4-1. Format of Stack Bank Selection Register
Address
F84H
3
2
1
0
SBS3
SBS2
SBS1
SBS0
Symbol
SBS
Stack area specification
0
0
Memory bank 0
0
1
Memory bank 1
1
0
Setting prohibited
1
1
0
Be sure to enter “0” for bit 2.
Mode selection specification
Caution
0
Mk II mode
1
Mk I mode
SBS3 is set to “1” after RESET input, and consequently the CPU operates in the Mk I mode. When using
instructions for the Mk II mode, set SBS3 to “0” and set the Mk II mode before using the instructions.
14
µPD75P3116
5. DIFFERENCES BETWEEN µPD75P3116 AND µPD753104, 753106, 753108
The µPD75P3116 replaces the internal mask ROM in the µPD753104, 753106, and 753108 with a one-time PROM and
features expanded ROM capacity. The µPD75P3116’s Mk I mode supports the Mk I mode in the µPD753104, 753106,
and 753108 and the µPD75P3116’s Mk II mode supports the Mk II mode in the µPD753104, 753106, and 753108.
Table 5-1 lists differences among the µPD75P3116 and the µPD753104, 753106, and 753108. Be sure to check the
differences among these products before using them with PROMs for debugging or prototype testing of application
systems or, later, when using them with a mask ROM for full-scale production.
For details on the CPU functions and internal hardware, refer to the User’s Manual.
Table 5-1. Differences between µPD75P3116 and µPD753104, 753106, and 753108
µPD753104
Item
µPD753106
µPD753108
µPD75P3116
Program counter
12 bits
13 bits
Program memory (bytes)
Mask ROM
4096
Mask ROM
6144
Data memory (x 4 bits)
512
Mask options
Available
(On chip/not on chip can be specified.)
Not available
(Not on chip)
Wait time after
RESET
Available
(Selectable between 217/fX and 215/fX)
Not available
(fixed to 215/fX) Note
Feedback resistor
of subsystem clock
Available
(Use/not use can be selected.)
Not available
(Enable)
Pin Nos. 5 to 8
P30 to P33
P30/MD0 to P33/MD3
Pin Nos. 10 to 13
P50 to P53
P50/D4 to P53/D7
Pin Nos. 14 to 17
P60/KR0 to P63/KR3
P60/KR0/D0 to P63/KR3/D3
Pin No. 21
IC
VPP
Pull-up resistor for
PORT5
14 bits
Mask ROM
8192
One-time PROM
16384
Split resistor for
LCD driving power supply
Pin configuration
Other
Note
Noise resistance and noise radiation may differ due to the different circuit sizes and mask
layouts.
217/fX : 21.8 ms at 6.0-MHz operation, 31.3 ms at 4.19-MHz operation
215/fX : 5.46 ms at 6.0-MHz operation, 7.81 ms at 4.19-MHz operation
Caution Noise resistance and noise radiation are different in PROM and mask ROMs. When changing from
PROM versions to mask ROM versions when switching from prototype development to full production,
be sure to fully evaluate the mask ROM version’s CS (not ES).
15
µPD75P3116
6. MEMORY CONFIGURATION
Figure 6-1. Program Memory Map
0000H
7
6
MBE
RBE
5
0
Internal reset start address (upper 6 bits)
Internal reset start address (lower 8 bits)
0002H
MBE
RBE
INTBT/INT4 start address (upper 6 bits)
INTBT/INT4 start address (lower 8 bits)
0004H
MBE
RBE
INT0 start address (upper 6 bits)
CALLF
!faddr instruction
entry address
INT0 start address (lower 8 bits)
0006H
MBE
RBE
INT1 start address (upper 6 bits)
INT1 start address (lower 8 bits)
0008H
MBE
RBE
INTCSI start address (upper 6 bits)
INTCSI start address (lower 8 bits)
000AH
MBE
RBE
INTT0 start address (upper 6 bits)
INTT0 start address (lower 8 bits)
000CH
MBE
RBE
INTT1/INTT2 start address (upper 6 bits)
INTT1/INTT2 start address (lower 8 bits)
BRCB
!caddr instruction
branch address
Branch addresses for
the following instructions
• BR !addr
• CALL !addr
• BRA !addr1 Note
• CALLA !addr1Note
• BR BCDE
• BR BCXA
Branch/call
address
by GETI
0020H
Reference table for GETI instruction
007FH
0080H
BR $addr instruction
relative branch address
(–15 to –1,
+2 to +16)
07FFH
0800H
0FFFH
1000H
BRCB
!caddr instruction
branch address
1FFFH
2000H
BRCB
!caddr instruction
branch address
2FFFH
3000H
BRCB
!caddr instruction
branch address
3FFFH
Note Can be used only in the Mk II mode
Remark
For instructions other than those noted above, the BR PCDE and BR PCXA instructions can be used to branch
to addresses with changes in the PC’s lower 8 bits only.
16
µPD75P3116
Figure 6-2. Data Memory Map
Data memory
Memory bank
000H
(32 x 4)
General-purpose register area
01FH
020H
256 x 4
(224 x 4)
Stack area Note
Data area
static RAM
(512 x 4)
0
0FFH
100H
256 x 4
(224 x 4)
1DFH
1E0H
Display data memory
1
(24 x 4)
1F7H
1F8H
(8 x 4)
1FFH
Not incorporated
F80H
128 x 4
Peripheral hardware area
15
FFFH
Note
Memory bank 0 or 1 can be selected as the stack area.
17
µPD75P3116
7. INSTRUCTION SET
(1) Representation and coding formats for operands
In the instruction’s operand area, use the following coding format to describe operands corresponding to the instruction’s
operand representations (for further description, refer to the RA75X Assembler Package User’s Manual Language
(EEU-1363)). When there are several codes, select and use just one. Codes that consist of upper-case letters and + or
– symbols are key words that should be entered as they are.
For immediate data, enter an appropriate numerical value or label.
Enter register flag symbols as label descriptors instead of mem, fmem, pmem, bit, etc. (for further description, refer to the
User’s Manual). The number of labels that can be entered for fmem and pmem are restricted.
Representation
Coding format
reg
X, A, B, C, D, E, H, L
reg1
X, B, C, D, E, H, L
rp
XA, BC, DE, HL
rp1
BC, DE, HL
rp2
BC, DE
rp’
XA, BC, DE, HL, XA’, BC’, DE’, HL’
rp’1
BC, DE, HL, XA’, BC’, DE’, HL’
rpa
HL, HL+, HL–, DE, DL
rpa1
DE, DL
n4
4-bit immediate data or label
n8
8-bit immediate data or label
mem
8-bit immediate data or labelNote
bit
2-bit immediate data or label
fmem
FB0H to FBFH, FF0H to FFFH immediate data or label
pmem
FC0H to FFFH immediate data or label
addr
0000H to 3FFFH immediate data or label
addr1
0000H to 3FFFH immediate data or label (Mk II mode only)
caddr
12-bit immediate data or label
faddr
11-bit immediate data or label
taddr
20H to 7FH immediate data (however, bit0 = 0) or label
PORTn
PORT0 to PORT3, PORT5, PORT6, PORT8, PORT9
IEXXX
IEBT, IECSI, IET0 to IET2, IE0 to IE2, IE4, IEW
RBn
RB0 to RB3
MBn
MB0, MB1, MB15
Note When processing 8-bit data, only even-numbered addresses can be specified.
18
µPD75P3116
(2) Operation legend
A
: A register; 4-bit accumulator
B
: B register
C
: C register
D
: D register
E
: E register
H
: H register
L
: L register
X
: X register
XA
: Register pair (XA); 8-bit accumulator
BC
: Register pair (BC)
DE
: Register pair (DE)
HL
: Register pair (HL)
XA’
: Expansion register pair (XA’)
BC’
: Expansion register pair (BC’)
DE’
: Expansion register pair (DE’)
HL’
: Expansion register pair (HL’)
PC
: Program counter
SP
: Stack pointer
CY
: Carry flag; bit accumulator
PSW
: Program status word
MBE
: Memory bank enable flag
RBE
: Register bank enable flag
PORTn : Port n (n = 0 to 3, 5, 6, 8, 9)
IME
: Interrupt master enable flag
IPS
: Interrupt priority selection register
IEXXX
: Interrupt enable flag
RBS
: Register bank selection register
MBS
: Memory bank selection register
PCC
: Processor clock control register
.
: Delimiter for address and bit
(XX)
: Addressed data with xx
XXH
: Hexadecimal data
19
µPD75P3116
(3) Description of symbols used in addressing area
MB = MBE • MBS
*1
MBS = 0, 1, 15
*2
MB = 0
MBE = 0
: MB = 0 (000H to 07FH)
MB = 15 (F80H to FFFH)
*3
MBE = 1
Data memory
addressing
: MB = MBS
MBS = 0, 1, 15
*4
MB = 15, fmem = FB0H to FBFH, FF0H to FFFH
*5
MB = 15, pmem = FC0H to FFFH
*6
addr = 0000H to 3FFFH
addr, addr1 = (Current PC) –15 to (Current PC) –1
*7
(Current PC) +2 to (Current PC) +16
caddr = 0000H to 0FFFH (PC13, 12 = 00B) or
1000H to 1FFFH (PC13, 12 = 01B) or
*8
2000H to 2FFFH (PC13, 12 = 10B) or
Program memory
addressing
3000H to 3FFFH (PC13, 12 = 11B)
*9
faddr = 0000H to 07FFH
*10
taddr = 0020H to 007FH
*11
addr1 = 0000H to 3FFFH (Mk II mode only)
Remarks 1. MB indicates access-enabled memory banks.
2. In area *2, MB = 0 for both MBE and MBS.
3. In areas *4 and *5, MB = 15 for both MBE and MBS.
4. Areas *6 to *11 indicate corresponding address-enabled areas.
(4) Description of machine cycles
S indicates the number of machine cycles required for skipping of skip-specified instructions. The value of S varies as
shown below.
• No skip ..................................................................... S = 0
• Skipped instruction is 1-byte or 2-byte instruction .... S = 1
• Skipped instruction is 3-byte instructionNote .............. S = 2
Note 3-byte instructions: BR !addr, BRA !addr1, CALL !addr, and CALLA !addr1
Caution
The GETI instruction is skipped for one machine cycle.
One machine cycle equals one cycle (= tCY) of the CPU clock Φ. Use the PCC setting to select among four cycle times.
20
µPD75P3116
Instruction
group
Transfer
Mnemonic
MOV
XCH
Table
reference
MOVT
Operand
No. of Machine
bytes cycle
Operation
Addressing
area
Skip
condition
A, #n4
1
1
A<-n4
String-effect A
reg1, #n4
2
2
reg1<-n4
XA, #n8
2
2
XA<-n8
String-effect A
HL, #n8
2
2
HL<-n8
String-effect B
rp2, #n8
2
2
rp2<-n8
A, @HL
1
1
A<-(HL)
*1
A, @HL+
1
2+S
A<-(HL), then L<-L+1
*1
L=0
A, @HL–
1
2+S
A<-(HL), then L<-L–1
*1
L=FH
A, @rpa1
1
1
A<-(rpa1)
*2
XA, @HL
2
2
XA<-(HL)
*1
@HL, A
1
1
(HL)<-A
*1
@HL, XA
2
2
(HL)<-XA
*1
A, mem
2
2
A<-(mem)
*3
XA, mem
2
2
XA<-(mem)
*3
mem, A
2
2
(mem)<-A
*3
mem, XA
2
2
(mem)<-XA
*3
A, reg
2
2
A<-reg
XA, rp’
2
2
XA<-rp’
reg1, A
2
2
reg1<-A
rp’1, XA
2
2
rp’1<-XA
A, @HL
1
1
A<->(HL)
*1
A, @HL+
1
2+S
A<->(HL), then L<-L+1
*1
L=0
A, @HL–
1
2+S
A<->(HL), then L<-L–1
*1
L=FH
A, @rpa1
1
1
A<->(rpa1)
*2
XA, @HL
2
2
XA<->(HL)
*1
A, mem
2
2
A<->(mem)
*3
XA, mem
2
2
XA<->(mem)
*3
A, reg1
1
1
A<->reg1
XA, rp’
2
2
XA<->rp’
XA, @PCDE
1
3
XA<-(PC13-8+DE)ROM
XA, @PCXA
1
3
XA<-(PC13-8+XA)ROM
Note
1
3
XA<-(BCDE)ROM
*6
Note
1
3
XA<-(BCXA)ROM
*6
XA, @BCDE
XA, @BCXA
Note Only the lower 3 bits in the B register are valid.
21
µPD75P3116
Instruction
group
Bit transfer
Arithmetic
Mnemonic
MOV1
ADDS
ADDC
SUBS
SUBC
AND
OR
XOR
Operand
No. of Machine
bytes cycle
Operation
Addressing
area
Skip
condition
CY, fmem.bit
2
2
CY<-(fmem.bit)
*4
CY, [email protected]
2
2
CY<-(pmem7-2+L3-2.bit(L1-0))
*5
CY, @H+mem.bit
2
2
CY<-(H+mem3-0.bit)
*1
fmem.bit, CY
2
2
(fmem.bit)<-CY
*4
[email protected], CY
2
2
(pmem7-2+L3-2.bit(L1-0))<-CY
*5
@H+mem.bit, CY
2
2
(H+mem3-0.bit)<-CY
*1
A, #n4
1
1+S
A<-A+n4
carry
XA, #n8
2
2+S
XA<-XA+n8
carry
A, @HL
1
1+S
A<-A+(HL)
XA, rp’
2
2+S
XA<-XA+rp’
carry
rp’1, XA
2
2+S
rp’1<-rp’1+XA
carry
A, @HL
1
1
A, CY<-A+(HL)+CY
XA, rp’
2
2
XA, CY<-XA+rp’+CY
rp’1, XA
2
2
rp’1, CY<-rp’1+XA+CY
A, @HL
1
1+S
A<-A–(HL)
XA, rp’
2
2+S
XA<-XA–rp’
borrow
rp’1, XA
2
2+S
rp’1<-rp’1–XA
borrow
A, @HL
1
1
A, CY<-A–(HL)–CY
XA, rp’
2
2
XA, CY<-XA–rp’–CY
rp’1, XA
2
2
rp’1, CY<-rp’1–XA–CY
A, #n4
2
2
A<-A ^ n4
A, @HL
1
1
A<-A ^ (HL)
XA, rp’
2
2
XA<-XA ^ rp’
rp’1, XA
2
2
rp’1<-rp’1 ^ XA
A, #n4
2
2
A<-A v n4
A, @HL
1
1
A<-A v (HL)
XA, rp’
2
2
XA<-XA v rp’
rp’1, XA
2
2
rp’1<-rp’1 v XA
A, #n4
2
2
A<-A v n4
A, @HL
1
1
A<-A v (HL)
XA, rp’
2
2
XA<-XA v rp’
rp’1, XA
2
2
rp’1<-rp’1 v XA
*1
carry
*1
*1
borrow
*1
*1
*1
*1
Accumulator
RORC
A
1
1
CY<-A0, A3<-CY, An-1<-An
manipulation
NOT
A
2
2
A<-A
Increment/
INCS
reg
1
1+S
reg<-reg+1
reg=0
rp1
1
1+S
rp1<-rp1+1
rp1=00H
@HL
2
2+S
(HL)<-(HL)+1
*1
(HL)=0
mem
2
2+S
(mem)<-(mem)+1
*3
(mem)=0
reg
1
1+S
reg<-reg–1
reg=FH
rp’
2
2+S
rp’<-rp’–1
rp’=FFH
decrement
DECS
22
µPD75P3116
Instruction
group
Comparison
Mnemonic
SKE
Operand
No. of Machine
bytes cycle
Operation
Addressing
area
Skip
condition
reg, #n4
2
2+S
Skip if reg=n4
reg=n4
@HL, #n4
2
2+S
Skip if (HL)=n4
*1
(HL)=n4
A, @HL
1
1+S
Skip if A=(HL)
*1
A=(HL)
XA, @HL
2
2+S
Skip if XA=(HL)
*1
XA=(HL)
A, reg
2
2+S
Skip if A=reg
A=reg
XA, rp’
2
2+S
Skip if XA=rp’
XA=rp’
Carry flag
SET1
CY
1
1
CY<-1
manipulation
CLR1
CY
1
1
CY<-0
SKT
CY
1
1+S
NOT1
CY
1
1
CY<-CY
SET1
mem.bit
2
2
(mem.bit)<-1
*3
fmem.bit
2
2
(fmem.bit)<-1
*4
[email protected]
2
2
(pmem7-2+L3-2.bit(L1-0))<-1
*5
@H+mem.bit
2
2
(H+mem3-0.bit)<-1
*1
mem.bit
2
2
(mem.bit)<-0
*3
fmem.bit
2
2
(fmem.bit)<-0
*4
[email protected]
2
2
(pmem7-2+L3-2.bit(L1-0))<-0
*5
@H+mem.bit
2
2
(H+mem3-0.bit)<-0
*1
mem.bit
2
2+S
Skip if(mem.bit)=1
*3
(mem.bit)=1
fmem.bit
2
2+S
Skip if(fmem.bit)=1
*4
(fmem.bit)=1
[email protected]
2
2+S
Skip if(pmem7-2+L3-2.bit(L1-0))=1
*5
([email protected])=1
Memory bit
manipulation
CLR1
SKT
SKF
SKTCLR
AND1
OR1
XOR1
Skip if CY=1
CY=1
@H+mem.bit
2
2+S
Skip if(H+mem3-0.bit)=1
*1
(@H+mem.bit)=1
mem.bit
2
2+S
Skip if(mem.bit)=0
*3
(mem.bit)=0
fmem.bit
2
2+S
Skip if(fmem.bit)=0
*4
(fmem.bit)=0
[email protected]
2
2+S
Skip if(pmem7-2+L3-2.bit(L1-0))=0
*5
([email protected])=0
@H+mem.bit
2
2+S
Skip if(H+mem3-0.bit)=0
*1
(@H+mem.bit)=0
fmem.bit
2
2+S
Skip if(fmem.bit)=1 and clear
*4
(fmem.bit)=1
[email protected]
2
2+S
Skip if(pmem7-2+L3-2.bit(L1-0))=1 and clear
*5
([email protected])=1
@H+mem.bit
2
2+S
Skip if(H+mem3-0.bit)=1 and clear
*1
(@H+mem.bit)=1
CY, fmem.bit
2
2
CY<-CY ^ (fmem.bit)
*4
CY, [email protected]
2
2
CY<-CY ^ (pmem7-2+L3-2.bit(L1-0))
*5
CY, @H+mem.bit
2
2
CY<-CY ^ (H+mem3-0.bit)
*1
CY, fmem.bit
2
2
CY<-CY v (fmem.bit)
*4
CY, [email protected]
2
2
CY<-CY v (pmem7-2+L3-2.bit(L1-0))
*5
CY, @H+mem.bit
2
2
CY<-CY v (H+mem3-0.bit)
*1
CY, fmem.bit
2
2
CY<-CY v (fmem.bit)
*4
CY, [email protected]
2
2
CY<- CY v (pmem7-2+L3-2.bit(L1-0))
*5
CY, @H+mem.bit
2
2
CY<-CY v (H+mem3-0.bit)
*1
23
µPD75P3116
Instruction
group
Branch
Mnemonic
BRNote 1
Operand
addr
No. of Machine
bytes cycle
Operation
Addressing
area
—
—
PC13-0<-addr
Use the assembler to select the
most appropriate instruction
among the following.
• BR !addr
• BRCB !caddr
• BR $addr
*6
—
—
PC13-0<-addr1
Use the assembler to select
the most appropriate instruction
among the following.
• BRA !addr1
• BR !addr
• BRCB !caddr
• BR $addr1
*11
!addr
3
3
PC13-0<-addr
*6
$addr
1
2
PC13-0<-addr
*7
1
2
PC13-0<-addr1
PCDE
2
3
PC13-0<-PC13-8+DE
PCXA
2
3
PC13-0<-PC13-8+XA
BCDE
2
3
PC13-0<-BCDENote 2
*6
Note 2
*6
addr1
$addr1
BCXA
2
3
PC13-0<-BCXA
BRA
!addr1
3
3
PC13-0<-addr1
*11
BRCB
!caddr
2
2
PC13-0<-PC13, 12+caddr11-0
*8
Note 1
Skip
condition
Notes 1. The portion in a double box can be supported only in the Mk II mode. The others can be supported only in the
MK I mode.
2. The B register is valid only for the lower two bits.
24
µPD75P3116
Instruction
group
Subroutine
Mnemonic
Operand
CALLANote !addr1
No. of Machine
bytes cycle
3
3
Operation
(SP–6)(SP–3)(SP–4)<-PC11-0
Addressing
area
Skip
condition
*11
(SP–5)<-0, 0, PC13, 12
stack control
(SP–2)<-X, X, MBE, RBE
PC13-0<-addr1, SP<-SP–6
CALL
Note
!addr
3
3
(SP–4)(SP–1)(SP–2)<-PC11-0
*6
(SP–3)<-MBE, RBE, PC13, 12
PC13-0<-addr, SP<-SP–4
4
(SP–6)(SP–3)(SP–4)<-PC11-0
(SP–5)<-0, 0, PC13, 12
(SP–2)<-X, X, MBE, RBE
PC13-0<-addr, SP<-SP–6
CALLFNote
!faddr
2
2
(SP–4)(SP–1)(SP–2)<-PC11-0
*9
(SP–3)<-MBE, RBE, PC13, 12
PC13-0<-000+faddr, SP<-SP–4
3
(SP–6)(SP–3)(SP–4)<-PC11-0
(SP–5)<-0, 0, PC13, 12
(SP–2)<-X, X, MBE, RBE
PC13-0<-000+faddr, SP<-SP–6
RET
Note
1
3
MBE, RBE, PC13, 12<-(SP+1)
PC11-0<-(SP)(SP+3)(SP+2)
SP<-SP+4
X, X, MBE, RBE<-(SP+4)
PC11-0<-(SP)(SP+3)(SP+2)
0, 0, PC13, 12<-(SP+1)
SP<-SP+6
RETS
Note
1
3+S
MBE, RBE, PC13, 12<-(SP+1)
Unconditional
PC11-0<-(SP)(SP+3)(SP+2)
SP<-SP+4
then skip unconditionally
X, X, MBE, RBE<-(SP+4)
PC11-0<-(SP)(SP+3)(SP+2)
0, 0, PC13, 12<-(SP+1)
SP<-SP+6
then skip unconditionally
RETI Note
1
3
MBE, RBE, PC13, 12<-(SP+1)
PC11-0<-(SP)(SP+3)(SP+2)
PSW<-(SP+4)(SP+5)
SP<-SP+6
0, 0, PC13, 12<-(SP+1)
PC11-0<-(SP)(SP+3)(SP+2)
PSW<-(SP+4)(SP+5), SP<-SP+6
Note The portion in a double box can be supported only in the Mk II mode. Other portions can be supported only in the Mk I mode.
25
µPD75P3116
Instruction
group
Subroutine
Mnemonic
PUSH
stack control
POP
Interrupt
Operand
1
1
(SP–1)(SP–2)<-rp, SP<-SP–2
BS
2
2
(SP–1)<-MBS, (SP–2)<-RBS, SP<-SP–2
rp
1
1
rp<-(SP+1)(SP), SP<-SP+2
BS
2
2
MBS<-(SP+1), RBS<-(SP), SP<-SP+2
2
2
IME(IPS.3)<-1
2
2
IEXXX<-1
2
2
IME(IPS.3)<-0
IEXXX
2
2
IEXXX<-0
A, PORTn
2
2
A<-PORTn (n=0 to 3, 5, 6, 8, 9)
IEXXX
DI
I/O
IN
Note 1
XA, PORTn
2
2
XA<-PORTn+1, PORTn (n=8)
PORTn, A
2
2
PORTn<-A (n=2 to 3, 5, 6, 8, 9)
PORTn, XA
2
2
PORTn+1, PORTn<-XA (n=8)
HALT
2
2
Set HALT Mode(PCC.2<-1)
STOP
2
2
Set STOP Mode(PCC.3<-1)
NOP
1
1
No Operation
RBn
2
2
RBS<-n (n=0 to 3)
MBn
2
2
MBS<-n (n=0, 1, 15)
taddr
1
3
• When using TBR instruction
OUT Note 1
CPU control
Special
Operation
rp
EI
control
No. of Machine
bytes cycle
SEL
GETI
Note 2, 3
Addressing
area
Skip
condition
*10
PC13-0<-(taddr)5-0+(taddr+1)
---------------------------
------------
• When using TCALL instruction
(SP–4)(SP–1)(SP–2)<-PC11-0
(SP–3)<-MBE, RBE, PC13, 12
PC13-0<-(taddr)5-0+(taddr+1)
SP<-SP–4
------------
--------------------------• When using instruction other than
TBR or TCALL
Execute (taddr)(taddr+1) instructions
1
3
• When using TBR instruction
PC13-0<-(taddr)5-0+(taddr+1)
-------------------------------4
Determined by
referenced
instruction
*10
------------
• When using TCALL instruction
(SP–6)(SP–3)(SP–4)<-PC11-0
(SP–5)<-0, 0, PC13, 12
(SP–2)<-X, X, MBE, RBE
PC13-0<-(taddr)5-0+(taddr+1)
SP<-SP–6
-------------------------------3
• When using instruction other than
TBR or TCALL
Execute (taddr)(taddr+1) instructions
-----------Determined by
referenced
instruction
Notes 1. Setting MBE=0 or MBE=1, MBS=15 is required during the execution of IN or OUT instruction.
2. TBR and TCALL instructions are assembler pseudo-instructions for the GETI instruction table definitions.
3. The portion in a double box can be supported only in the Mk II mode. Other portions can be supported only
in the Mk I mode.
26
µPD75P3116
8. ONE-TIME PROM (PROGRAM MEMORY) WRITE AND VERIFY
The program memory contained in the µPD75P3116 is a 16384 x 8-bit one-time PROM that can be electrically written one
time only. The pins listed in the table below are used for this PROM’s write/verify operations. Clock input from the X1
pin is used instead of address input as a method for updating addresses.
Pin
Function
VPP
Pin where program voltage is applied during program memory
write/verify (usually VDD potential)
X1, X2
Clock input pins for address updating during program memory
write/verify. Input the X1 pin’s inverted signal to the X2 pin.
MD0 to MD3
Operation mode selection pin for program memory write/verify
D0/P60 to D3/P63
(lower 4 bits)
D4/P50 to D7/P53
(upper 4 bits)
8-bit data I/O pins for program memory write/verify
VDD
Pin where power supply voltage is applied. Applies 1.8 to 5.5
V in normal operation mode and +6 V for program memory
write/verify.
Caution Pins not used for program memory write/verify should be connected to Vss.
8.1 Operation Modes for Program Memory Write/Verify
When +6 V is applied to the VDD pin and +12.5 V to the VPP pin, the µPD75P3116 enters the program memory write/verify
mode. The following operation modes can be specified by setting pins MD0 to MD3 as shown below.
Operation mode specification
Operation mode
VPP
VDD
MD0
MD1
MD2
MD3
+12.5 V
+6 V
H
L
H
L
Zero-clear program memory address
L
H
H
H
Write mode
L
L
H
H
Verify mode
H
X
H
H
Program inhibit mode
X: L or H
27
µPD75P3116
8.2 Program Memory Write Procedure
Program memory can be written at high speed using the following procedure.
(1) Pull down unused pins to Vss through resistors. Set the X1 pin low.
(2) Supply 5 V to the VDD and VPP pins.
(3) Wait 10 µs.
(4) Select the program memory address zero-clear mode.
(5) Supply 6 V to VDD and 12.5 V to VPP pins.
(6) Write data in the 1-ms write mode.
(7) Select the verify mode. If the data is written, go to (8) and if not, repeat (6) and (7).
(8) Additional write. (X: number of write operations from (6) and (7)) x 1 ms
(9) Apply four pulses to the X1 pin to increment the program memory address by one.
(10) Repeat (6) to (9) until the end address is reached.
(11) Select the program memory address zero-clear mode.
(12) Return the VDD- and VPP-pin voltages to 5 V.
(13) Turn off the power.
The following figure shows steps (2) to (9).
X repetitions
Write
Verify
Additional
write
VPP
VPP
VDD
VDD + 1
VDD
VDD
X1
D0/P60 to D3/P63
D4/P50 to D7/P53
MD0/P30
MD1/P31
MD2/P32
MD3/P33
28
Data input
Data
output
Data input
Address
increment
µPD75P3116
8.3 Program Memory Read Procedure
The µPD75P3116 can read program memory contents using the following procedure.
(1) Pull down unused pins to VSS through resistors. Set the X1 pin low.
(2) Supply 5 V to the VDD and VPP pins.
(3) Wait 10 µs.
(4) Select the program memory address zero-clear mode.
(5) Supply 6 V to the VDD and 12.5 to the VPP pins.
(6) Select the verify mode. Apply four pulses to the X1 pin. Every four clock pulses will output the data stored in one
address.
(7) Select the program memory address zero-clear mode.
(8) Return the VDD- and VPP-pin voltages to 5V.
(9) Turn off the power.
The following figure shows steps (2) to (7).
VPP
VPP
VDD
VDD + 1
VDD
VDD
X1
D0/P60 to D3/P63
D4/P50 to D7/P53
Data output
Data output
MD0/P30
MD1/P31
“L”
MD2/P32
MD3/P33
29
µPD75P3116
8.4 One-time PROM Screening
Due to its structure, the one-time PROM cannot be fully tested before shipment by NEC. Therefore, NEC recommends
that after the required data is written and the PROM is stored under the temperature and time conditions shown below,
the PROM should be verified via a screening.
Storage temperature
Storage time
125˚C
24 hours
NEC offers QTOP microcontrollers for which one-time PROM writing, marking, screening, and verification are provided
at additional cost. For more detailed information, contact an NEC sales representative.
30
µ PD75P3116
9. ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS (T A = 25˚C)
Parameter
Symbol
Test Conditions
Rating
Unit
Power supply voltage
VDD
–0.3 to +7.0
V
PROM power supply
voltage
VPP
–0.3 to +13.5
V
Input voltage
VI1
Except port 5
–0.3 to V DD +0.3
V
VI2
Port 5 (N-ch open drain)
–0.3 to +14
V
–0.3 to VDD +0.3
V
Per pin
–10
mA
Total of all pins
–30
mA
Per pin
30
mA
Total of all pins
220
Output voltage
VO
Output current high
I OH
Output current low
I OL
Operating ambient
temperature
TA
–40 to +85
Storage temperature
Tstg
mA
Note
˚C
–65 to +150
˚C
Note When LCD is driven in normal mode: TA = –10 to +85˚C
Caution If any of the parameters exceeds the absolute maximum ratings, even momentarily, the reliability
of the product may be impaired. The absolute maximum ratings are values that may physically
damage the products. Be sure to use the products within the ratings.
CAPACITANCE (T A = 25˚C, VDD = 0 V)
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
Input capacitance
CIN
f = 1 MHz
15
pF
Output capacitance
COUT
Unmeasured pins returned to 0 V.
15
pF
I/O capacitance
CIO
15
pF
31
µ PD75P3116
MAIN SYSTEM CLOCK OSCILLATOR CHARACTERISTICS (TA = –40 to +85 °C, VDD = 1.8 to 5.5 V)
Resonator
Recommended constant
Ceramic
resonator
frequency (fx)
C1
C2
VDD
Crystal
resonator
C1
C2
External
stabilization time Note 3
lation voltage range MIN.
1.0
X2
Oscillation
frequency (fx)
VDD = 4.5 to 5.5 V
Unit
6.0 Note 2
MHz
4
ms
6.0 Note 2
MHz
10
ms
30
1.0
6.0 Note 2
MHz
83.3
500
ns
Note 1
X1 input
high-/low-level width
(t XH, t XL)
Notes 1.
MAX.
Note 1
X1 input
X1
clock
After VDD reaches oscil-
stabilization time Note 3
VDD
TYP.
Note 1
Oscillation
frequency (fx)
MIN.
1.0
Oscillation
X2
X1
Test conditions
Oscillation
X2
X1
Parameter
The oscillation frequency and X1 input frequency indicate characteristics of the oscillator only. For
the instruction execution time, refer to AC Characteristics.
2.
When the power supply voltage is 1.8 V ≤ V DD < 2.7 V and the oscillation frequency is 4.19 MHz < fx
≤ 6.0 MHz, setting the processor clock control register (PCC) to 0011 results in 1 machine cycle being
less than the required 0.95 µs. Therefore, set PCC to a value other than 0011.
3.
The oscillation stabilization time is necessary for oscillation to stabilize after applying V DD or releasing
the STOP mode.
Caution When using the main system clock oscillator, wiring in the area enclosed with the dotted line should
be carried out as follows to avoid an adverse effect from wiring capacitance.
• Wiring should be as short as possible.
• Wiring should not cross other signal lines.
• Wiring should not be placed close to a varying high current.
• The potential of the oscillator capacitor ground should be the same as VDD.
• Do not ground to a ground pattern in which a high current flows.
• Do not fetch a signal from the oscillator.
32
µ PD75P3116
SUBSYSTEM CLOCK OSCILLATOR CHARACTERISTICS (T A = –40 to +85˚C, VDD = 1.8 to 5.5 V)
Resonator
Recommended constant
Crystal
XT1
C3
Test conditions
Oscillation
XT2
resonator
Parameter
R
frequency (fXT )
C4
Oscillation
External
MAX.
Unit
32
32.768
35
kHz
1.0
2
s
Note 1
VDD = 4.5 to 5.5 V
XT1 input frequency
clock
TYP.
stabilization time Note 2
VDD
XT1
MIN.
XT2
(f XT)
10
32
100
kHz
5
15
µs
Note 1
XT1 input high-/low-level
width (t XTH, tXTL)
Notes 1.
2.
Caution
Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
The oscillation stabilization time is necessary for oscillation to stabilize after applying V DD.
When using the subsystem clock oscillator, wiring in the area enclosed with the dotted line should
be carried out as follows to avoid an adverse effect from wiring capacitance.
• Wiring should be as short as possible.
• Wiring should not cross other signal lines.
• Wiring should not be placed close to a varying high current.
• The potential of the oscillator capacitor ground should be the same as VDD.
• Do not ground to a ground pattern in which a high current flows.
• Do not fetch a signal from the oscillator.
The subsystem clock oscillator is designed as a low amplification circuit to provide low consumption
current, and is more liable to misoperation by noise than the main system clock oscillation circuit.
Special care should therefore be taken regarding the wiring method when the subsystem clock is
used.
33
µ PD75P3116
DC CHARACTERISTICS (TA = –40 to +85˚C, V DD = 1.8 to 5.5 V)
Parameter
Output current low
Input voltage high
Symbol
I OL
VIH1
VIH2
VIH3
Input voltage low
Test conditions
MAX.
Unit
Per pin
15
mA
Total of all pins
150
mA
TYP.
2.7 ≤ VDD ≤ 5.5 V
0.7V DD
V DD
V
1.8 ≤ VDD < 2.7 V
0.9V DD
V DD
V
2.7 ≤ VDD ≤ 5.5 V
0.8V DD
V DD
V
1.8 ≤ VDD < 2.7 V
0.9V DD
V DD
V
Port 5
2.7 ≤ VDD ≤ 5.5 V
0.7V DD
13
V
(N-ch open-drain)
1.8 ≤ VDD < 2.7 V
0.9V DD
13
V
VDD – 0.1
V DD
V
2.7 ≤ VDD ≤ 5.5 V
0
0.3VDD
V
1.8 ≤ VDD < 2.7 V
0
0.1VDD
V
2.7 ≤ VDD ≤ 5.5 V
0
0.2VDD
V
1.8 ≤ VDD < 2.7 V
0
0.1VDD
V
0
0.1
V
Ports 2, 3, 8, and 9
Ports 0, 1, 6, RESET
VIH4
X1, XT1
VIL1
Ports 2, 3, 5, 8, and 9
VIL2
MIN.
Ports 0, 1, 6, RESET
VIL3
X1, XT1
Output voltage high
VOH
SCK, SO, Ports 2, 3, 6, 8, and 9
Output voltage low
VOL1
SCK, SO, Ports 2, 3, 5, 6, 8, and 9
I OH = –1.0 mA
VDD – 0.5
I OL = 15 mA,
V
0.2
2.0
V
0.4
V
0.2VDD
V
3
µA
X1, XT1
20
µA
VDD = 4.5 to 5.5 V
I OL = 1.6 mA
VOL2
SB0, SB1
When N-ch open-drain
pull-up resistor ≥ 1 kΩ
Input leakage
I LIH1
VIN = VDD
Pins other than X1, XT1
current high
I LIH2
I LIH3
VIN = 13 V
Port 5 (N-ch open-drain)
20
µA
Input leakage
I LIL1
VIN = 0 V
Pins other than X1, XT1, and Port 5
–3
µA
current low
I LIL2
X1, XT1
–20
µA
I LIL3
Port 5 (N-ch open-drain)
When another instruction than input
instruction is executed
–3
µA
Port 5 (N-ch open-drain)
–30
µA
When input instruction
VDD = 5.0 V
–10
–27
µA
is executed
VDD = 3.0 V
–3
–8
µA
3
µA
20
µA
–3
µA
200
kΩ
Output leakage
I LOH1
VOUT = VDD
SCK, SO/SB0, SB1, Ports 2, 3, 6, 8, and 9
current high
I LOH2
VOUT = 13 V
Port 5 (N-ch open-drain)
Output leakage
current low
I LOL
VOUT = 0 V
On-chip pull-up resistor
RL
VIN = 0 V
34
Ports 0, 1, 2, 3, 6, 8, and 9
(Excluding P00 pin)
50
100
µ PD75P3116
DC CHARACTERISTICS (TA = –40 to +85˚C, V DD = 1.8 to 5.5 V)
Parameter
LCD drive voltage
Symbol
VLCD
VAC0 = 0
Test conditions
MIN.
TA = –40 to +85°C
TA = –10 to +85°C
VAC0 = 1
TYP.
MAX.
Unit
2.7
V DD
V
2.2
V DD
V
1.8
V DD
V
4
µA
I VAC
VAC0 = 1, V DD = 2.0 V ± 10%
VODC
lo = ±1.0 µ A
VLCD0 = VLCD
VLCD1 = VLCD x 2/3
0
±0.2
V
LCD output voltage
VODS
deviation Note 2 (segment)
lo = ±0.5 µ A
VLCD2 = VLCD x 1/3
1.8 V ≤ V LCD ≤ VDD
0
±0.2
V
Supply current Note 3
6.00 MHz Note 4
VDD = 5.0 V ± 10%
Note 5
3.2
9.5
mA
Crystal oscillation
VDD = 3.0 V ± 10%
Note 6
0.55
1.6
mA
C1 = C2 = 22 pF
HALT mode
VDD = 5.0 V ± 10%
0.7
2.0
mA
VDD = 3.0 V ± 10%
0.25
0.8
mA
VAC current
Note 1
LCD output voltage
deviation Note 2 (common)
I DD1
I DD2
I DD1
I DD2
I DD3
4.19 MHz Note 4
VDD = 5.0 V ± 10% Note 5
2.5
7.5
mA
Crystal oscillation
VDD = 3.0 V ± 10% Note 6
0.45
1.35
mA
C1 = C2 = 22 pF
HALT mode
VDD = 5.0 V ± 10%
0.65
1.8
mA
VDD = 3.0 V ± 10%
0.22
0.7
mA
VDD = 3.0 V ± 10%
45
130
µA
VDD = 2.0 V ± 10%
20
55
µA
VDD = 3.0 V, TA = 25˚C
45
90
µA
Low power
consumption
mode Note 9
VDD = 3.0 V ± 10%
42
120
µA
VDD = 3.0 V, TA = 25˚C
42
85
µA
HALT mode
VDD = 3.0 V ± 10%
Lowvoltage VDD = 2.0 V ± 10%
mode
VDD = 3.0 V, TA = 25˚C
Note 8
5.5
18
µA
2.2
7
µA
5.5
12
µA
Low
VDD = 3.0 V ± 10%
power
consump- VDD = 3.0 V,
tion mode TA = 25˚C
Note 9
4.0
12
µA
4.0
8
µA
32.768 kHz Note 7
Low-voltage
Crystal oscillation
mode
I DD4
I DD5
2.
3.
4.
5.
6.
7.
Note 8
XT1 = 0 V Note 10
VDD = 5.0 V ± 10%
0.05
10
µA
STOP mode
VDD = 3.0 V
0.02
5
µA
0.02
3
µA
± 10%
Notes 1.
1
T A = 25˚C
Set to VAC0 = 0 when the low power consumption mode and the stop mode are used. If VAC0 = 1
is set, the current increases for approx. 1 µ A.
The voltage deviation is the difference from the output voltage corresponding to the ideal value of the
segment and common outputs (VLCDn; n = 0, 1, 2).
Not including currents flowing in on-chip pull-up resistors.
Including oscillation of the subsystem clock.
When the processor clock control register (PCC) is set to 0011 and the device is operated in the highspeed mode.
When PCC is set to 0000 and the device is operated in the low-speed mode.
When the system clock control register (SCC) is set to 1001 and the device is operated on the
subsystem clock, with main system clock oscillation stopped.
8.
When the sub-oscillation circuit control register (SOS) is set to 0000.
9.
When SOS is set to 0010.
10. When SOS is set to 00×1 and the feedback resistor of the sub-oscillation circuit is not used.
35
µ PD75P3116
AC CHARACTERISTICS (TA = –40 to +85˚C, V DD = 1.8 to 5.5 V)
Parameter
Symbol
CPU clock cycle
time
Test conditions
MAX.
Unit
0.67
64
µs
main system clock
0.95
64
µs
Operating on subsystem clock
114
125
µs
0
1.0
MHz
0
275
kHz
Operating on
t CY
Note 1
(Min. instruction execution
MIN.
VDD = 2.7 to 5.5 V
TYP.
122
time = 1 machine cycle)
TI0, TI1, TI2 input
f TI
VDD = 2.7 to 5.5 V
frequency
t TIH, tTIL
TI0, TI1, TI2 input
0.48
µs
1.8
µs
IM02 = 0
Note 2
µs
IM02 = 1
10
µs
INT1, 2, 4
10
µs
KR0 to KR7
10
µs
10
µs
VDD = 2.7 to 5.5 V
high-/low-level width
Interrupt input high-/
tINTH , tINTL INT0
low-level width
RESET low-level width
Notes 1.
t RSL
The cycle time (minimum instruction
tCY vs VDD
(At main system clock operation)
execution time) of the CPU clock
(Φ) is determined by the oscillation
64
60
frequency of the connected
resonator (and external clock), the
6
system clock control register (SCC)
5
register (PCC). The figure at the
right indicates the cycle time tCY
versus
supply
voltage
V DD
characteristic with the main system
clock operating.
2.
Cycle Time tCY [µs]
and the processor clock control
Guaranteed Operation
Range
4
3
2
2tCY or 128/fx is set by setting the
interrupt mode register (IM0).
1
0.5
0
1
2
3
4
5
Supply Voltage VDD [V]
36
6
µ PD75P3116
SERIAL TRANSFER OPERATION
2-Wire and 3-Wire Serial I/O Mode (SCK...Internal clock output): (TA = –40 to +85˚C, V DD = 1.8 to 5.5 V)
Parameter
SCK cycle time
Symbol
t KCY1
SCK high-/low-level
t KL1, t KH1
Test conditions
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
width
SI
Note 1
setup time
t SIK1
VDD = 2.7 to 5.5 V
(to SCK↑)
SI
Note 1
hold time
t KSI1
VDD = 2.7 to 5.5 V
(from SCK↑)
SCK↓→SO
Note 1
output
t KSO1
delay time
Notes 1.
2.
RL = 1 kΩ,
CL = 100 pF
VDD = 2.7 to 5.5 V
Note 2
MIN.
TYP.
MAX.
Unit
1300
ns
3800
ns
tKCY1 /2–50
ns
t KCY1/2–150
ns
150
ns
500
ns
400
ns
600
ns
0
250
ns
0
1000
ns
In 2-wire serial I/O mode, read this parameter as SB0 or SB1 instead.
RL and C L are the load resistance and load capacitance of the SO output lines, respectively.
2-Wire and 3-Wire Serial I/O Mode (SCK...External clock input): (TA = –40 to +85˚C, V DD = 1.8 to 5.5 V)
Parameter
SCK cycle time
Symbol
t KCY2
SCK high-/low-level
t KL2, tKH2
Test conditions
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
width
SI
Note 1
setup time
t SIK2
VDD = 2.7 to 5.5 V
(to SCK↑)
SI
Note 1
hold time
t KSI2
VDD = 2.7 to 5.5 V
(from SCK↑)
SCK↓→SO
delay time
Notes 1.
2.
Note 1
output
t KSO2
RL = 1 kΩ,
CL = 100 pF
VDD = 2.7 to 5.5 V
Note 2
MIN.
TYP.
MAX.
Unit
800
ns
3200
ns
400
ns
1600
ns
100
ns
150
ns
400
ns
600
ns
0
300
ns
0
1000
ns
In 2-wire serial I/O mode, read this parameter as SB0 or SB1 instead.
RL and C L are the load resistance and load capacitance of the SO output lines, respectively.
37
µ PD75P3116
SBI Mode (SCK...Internal clock output (master)): (TA = –40 to +85˚C, V DD = 1.8 to 5.5 V)
Parameter
SCK cycle time
SCK high-/low-level
Symbol
t KCY3
t KL3, tKH3
Test conditions
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
width
SB0, 1 setup time
t SIK3
VDD = 2.7 to 5.5 V
(to SCK↑)
SB0, 1 hold time (from SCK↑)
t KSI3
SCK↓→ SB0, 1
t KSO3
output delay time
RL = 1 kΩ,
CL = 100 pF
VDD = 2.7 to 5.5 V
Note
MIN.
TYP.
MAX.
Unit
1300
ns
3800
ns
t KCY3/2–50
ns
t KCY3/2–150
ns
150
ns
500
ns
t KCY3/2
ns
0
250
ns
0
1000
ns
SCK↑→ SB0, 1↓
t KSB
t KCY3
ns
SB0, 1 ↓→SCK↓
t SBK
t KCY3
ns
SB0, 1 low-level width
t SBL
t KCY3
ns
SB0, 1 high-level width
tSBH
t KCY3
ns
Note
RL and C L are the load resistance and load capacitance of the SB0 and SB1 output lines, respectively.
SBI Mode (SCK...External clock input (slave)): (TA = –40 to +85˚C, V DD = 1.8 to 5.5 V)
Parameter
SCK cycle time
SCK high-/low-level
Symbol
t KCY4
t KL4, tKH4
Test conditions
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
width
SB0, 1 setup time
t SIK4
VDD = 2.7 to 5.5 V
(to SCK↑)
SB0, 1 hold time (from SCK↑)
t KSI4
SCK↓→SB0, 1 output
t KSO4
RL = 1 kΩ,
CL = 100 pF
delay time
VDD = 2.7 to 5.5 V
Note
MIN.
TYP.
MAX.
Unit
800
ns
3200
ns
400
ns
1600
ns
100
ns
150
ns
t KCY4/2
ns
0
300
ns
0
1000
ns
SCK↑→ SB0, 1↓
t KSB
t KCY4
ns
SB0, 1↓→ SCK↓
t SBK
t KCY4
ns
SB0, 1 low-level width
t SBL
t KCY4
ns
SB0, 1 high-level width
tSBH
t KCY4
ns
Note
38
RL and C L are the load resistance and load capacitance of the SB0 and SB1 output lines, respectively.
µ PD75P3116
AC Timing Test Point (Excluding X1, XT1 Input)
VIH (MIN.)
VIL (MAX.)
VIH (MIN.)
VIL (MAX.)
VOH (MIN.)
VOL (MAX.)
VOH (MIN.)
VOL (MAX.)
Clock Timing
1/fX
tXL
tXH
VDD–0.1 V
0.1 V
X1 Input
1/fXT
tXTL
tXTH
VDD–0.1 V
0.1 V
XT1 Input
TI0, TI1, TI2 Timing
1/fTI
tTIL
tTIH
TI0, TI1, TI2
39
µ PD75P3116
Serial Transfer Timing
3-wire serial I/O mode
tKCY1, 2
tKL1, 2
tKH1, 2
SCK
tSIK1, 2
SI
tKSI1, 2
Input Data
tKSO1, 2
SO
Output Data
2-wire serial I/O mode
tKCY1, 2
tKL1, 2
tKH1, 2
SCK
tSIK1, 2
SB0, 1
tKSO1, 2
40
tKSI1, 2
µ PD75P3116
Serial Transfer Timing
Bus release signal transfer
tKCY3, 4
tKL3, 4
tKH3, 4
SCK
tKSB
tSBL
tSBH
tSIK3, 4
tSBK
tKSI3, 4
SB0, 1
tKSO3, 4
Command signal transfer
tKCY3, 4
tKL3, 4
tKH3, 4
SCK
tKSB
tSIK3, 4
tSBK
tKSI3, 4
SB0, 1
tKSO3, 4
Interrupt input timing
tINTL
tINTH
INT0, 1, 2, 4
KR0 to 7
RESET input timing
tRSL
RESET
41
µ PD75P3116
DATA MEMORY STOP MODE LOW SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS
(TA = –40 to +85˚C)
Parameter
Symbol
Release signal set time
t SREL
Oscillation stabilization
t WAIT
MIN.
TYP.
MAX.
Release by RESET
Release by interrupt request
215 /fX
ms
Note 2
ms
The oscillation stabilization wait time is the time during which the CPU operation is stopped to prevent
unstable operation at the oscillation start.
2.
Depends on the basic interval timer mode register (BTM) settings (See the table below).
BTM3
—
—
—
—
42
Unit
µs
0
wait time Note 1
Notes 1.
Test conditions
BTM2
0
0
1
1
BTM1
0
1
0
1
BTM0
0
1
1
1
Wait time
220/fx
217/fx
215/fx
213/fx
fx = at 4.19 MHz
(approx. 250 ms)
(approx. 31.3 ms)
(approx. 7.81 ms)
(approx. 1.95 ms)
220/fx
217/fx
215/fx
213/fx
fx = at 6.0 MHz
(approx. 175 ms)
(approx. 21.8 ms)
(approx. 5.46 ms)
(approx. 1.37 ms)
µ PD75P3116
Data Retention Timing (STOP Mode Release by RESET)
Internal Reset Operation
HALT mode
Operating Mode
STOP Mode
Data Retention Mode
VDD
tSREL
STOP Instruction Execution
RESET
tWAIT
Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal)
HALT mode
Operating Mode
STOP Mode
Data Retention Mode
VDD
tSREL
STOP Instruction Execution
Standby Release Signal
(Interrupt Request)
tWAIT
43
µ PD75P3116
DC PROGRAMMING CHARACTERISTICS (TA = 25 ± 5˚C, V DD = 6.0 ± 0.25 V, V PP = 12.5 ± 0.3 V, VSS = 0 V)
Parameter
Symbol
Input voltage high
Input voltage low
Test conditions
VIH1
Except X1 and X2 pins
VIH2
X1, X2
VIL1
V
V DD
V
Except X1 and X2 pins
0
0.3VDD
V
0
0.4
V
10
µA
X1, X2
V IN = VIL or VIH
Output voltage high
VOH
I OH = –1 mA
I OL = 1.6 mA
VOL
VPP power supply current
I PP
Unit
V DD
I LI
I DD
MAX.
0.7V DD
VIL2
Output voltage low
TYP.
VDD–0.5
Input leakage current
VDD power supply current
MIN.
VDD–1.0
V
MD0 = V IL, MD1 = V IH
0.4
V
30
mA
30
mA
Cautions 1. Avoid exceeding +13.5 V for VPP including the overshoot.
2. VDD must be applied before VPP , and cut after VPP .
AC PROGRAMMING CHARACTERISTICS (TA = 25 ±5˚C, V DD = 6.0 ±0.25 V, V PP = 12.5 ±0.3 V, VSS = 0 V)
Parameter
Symbol
Note 1
t AS
t AS
2
µs
MD1 setup time (to MD0↓)
t M1S
t OES
2
µs
Data setup time (to MD0↓)
t DS
t DS
2
µs
t AH
t AH
2
µs
t DH
t DH
2
µs
Address setup time
Address hold time
Note 2
Note 2
(to MD0↓)
(from MD0↑)
Data hold time (from MD0↑)
Test conditions
MIN.
TYP.
MAX.
130
Unit
MD0↑→data output float delay time
tDF
t DF
0
VPP setup time (to MD3↑)
t VPS
t VPS
2
µs
VDD setup time (to MD3↑)
t VDS
t VCS
2
µs
Initial program pulse width
tPW
t PW
0.95
Additional program pulse width
tOPW
t OPW
0.95
MD0 setup time (to MD1↑)
t M0S
t CES
2
MD0↓→data output delay time
t DV
t DV
MD0 = MD1 = VIL
MD1 hold time (from MD0↑)
t M1H
t OEH
tM1H+t M1R ≥ 50 µs
2
µs
MD1 recovery time (from MD0↓)
t M1R
t OR
2
µs
Program counter reset time
t PCR
–
10
µs
X1 input high-/low-level width
tXH, t XL
–
0.125
µs
X1 input frequency
fX
–
Initial mode set time
tI
–
2
µs
MD3 setup time (to MD1↑)
t M3S
–
2
µs
MD3 hold time (from MD1↓)
t M3H
–
2
µs
MD3 setup time (to MD0↓)
t M3SR
–
During program memory read
2
µs
1.0
1.05
ms
21.0
ms
µs
1
4.19
Address
Note 2
→data output delay time
t DAD
t ACC
During program memory read
Address
Note 2
→data output hold time
t HAD
t OH
During program memory read
0
MD3 hold time (from MD0↑)
t M3HR
–
During program memory read
2
MD3↓→data output float delay time
tDFR
–
During program memory read
ns
µs
MHz
2
µs
130
ns
µs
2
µs
Notes 1. Corresponding symbol of µPD27C256A
2. The internal address signal is incremented by 1 at the rising edge of the fourth X1 input and is not
connected to a pin.
44
µ PD75P3116
Program Memory Write Timing
tVPS
VPP
VPP
VDD
VDD
VDD+1
VDD
tVDS
tXH
X1
D0/P60 to D3/P60
D4/P50 to D7/P53
Data input
Data output
tDS
tI
tDS
tDH
tDV
tXL
Data input
Data input
tDH
tDF
tAH
tAS
MD0/P30
tPW
tM1R
tM0S
tOPW
MD1/P31
tPCR
tM1S
tM1H
MD2/P32
tM3S
tM3H
MD3/P33
Program Memory Read Timing
tVPS
VPP
VPP
VDD
VDD
VDD+1
VDD
tVDS
tXH
X1
tXL
D0/P60 to D3/P60
D4/P50 to D7/P53
tDAD
tHAD
Data output
Data output
tDV
tI
tDFR
tM3HR
MD0/P30
MD1/P31
tPCR
MD2/P32
tM3SR
MD3/P33
45
µ PD75P3116
10. CHARACTERISTIC CURVES (REFERENCE VALUES)
IDD vs VDD (Main System Clock: 6.0-MHz Crystal Resonator)
(TA = 25°C)
10
5.0
PCC = 0011
PCC = 0010
PCC = 0001
PCC = 0000
1.0
Main system clock
HALT mode + 32-kHz oscillation
Supply Current IDD (mA)
0.5
0.1
Subsystem clock operation
mode (SOS.1 = 0)
Main system clock STOP
mode + 32-kHz oscillation
(SOS.1 = 0) and
subsystem clock HALT mode
(SOS.1 = 0)
Main system clock STOP
mode + 32-kHz oscillation
(SOS.1 = 1) and subsystem
clock HALT mode (SOS.1 = 1)
0.05
0.01
0.005
X1
22 pF
0.001
0
1
2
3
4
Supply Voltage VDD (V)
46
5
X2 XT1
XT2
Crystal resonator
6.0 MHz
Crystal resonator
32.768 kHz
330 kΩ
22 pF
22 pF
22 pF
VDD
VDD
6
7
8
µ PD75P3116
IDD vs VDD (Main System Clock: 4.19-MHz Crystal Resonator)
(TA = 25°C)
10
5.0
PCC = 0011
PCC = 0010
PCC = 0001
1.0
PCC = 0000
Main system clock
HALT mode + 32-kHz oscillation
Supply Current IDD (mA)
0.5
0.1
Subsystem clock operation
mode (SOS.1 = 0)
Subsystem clock HALT mode
(SOS.1 = 0) and
main system clock STOP mode
+ 32-kHz oscillation (SOS.1 = 0)
0.05
Main system clock STOP
mode + 32-kHz oscillation
(SOS.1 = 1)
and subsystem clock HALT
mode (SOS.1 = 1)
0.01
0.005
X1
X2 XT1
Crystal resonator
32.768 kHz 330 kΩ
4.19 MHz
22 pF
0.001
0
1
2
3
4
5
XT2
Crystal resonator
22 pF
22 pF
VDD
VDD
6
22 pF
7
8
Supply Voltage VDD (V)
47
µ PD75P3116
11. PACKAGE DRAWINGS
64 PIN PLASTIC QFP (
14)
A
B
48
49
33
32
F
Q
5°±5°
S
D
C
detail of lead end
64
1
G
17
16
H
I M
J
M
P
K
N
L
P64GC-80-AB8-3
NOTE
Each lead centerline is located within 0.15
mm (0.006 inch) of its true position (T.P.) at
maximum material condition.
48
ITEM
MILLIMETERS
INCHES
A
17.6 ± 0.4
0.693 ± 0.016
B
14.0 ± 0.2
0.551 +0.009
–0.008
C
14.0 ± 0.2
0.551+0.009
–0.008
D
17.6 ± 0.4
0.693 ± 0.016
F
1.0
0.039
G
1.0
0.039
H
0.35 ± 0.10
0.014 +0.004
–0.005
I
0.15
0.006
J
0.8 (T.P.)
0.031 (T.P.)
K
1.8 ± 0.2
0.071 ± 0.008
L
0.8 ± 0.2
0.031+0.009
–0.008
M
0.15+0.10
–0.05
0.006 +0.004
–0.003
N
0.10
0.004
P
2.55
0.100
Q
0.1 ± 0.1
0.004 ± 0.004
S
2.85 MAX.
0.112 MAX.
µ PD75P3116
64 PIN PLASTIC LQFP (
12)
A
B
48
49
33
32
Q
R
D
C
S
detail of lead end
F
64
17
16
1
H
I
M
J
K
M
P
G
N
L
NOTE
Each lead centerline is located within 0.13 mm (0.005 inch) of
its true position (T.P.) at maximum material condition.
ITEM MILLIMETERS
INCHES
A
14.8±0.4
0.583±0.016
B
12.0±0.2
0.472 +0.009
–0.008
C
12.0±0.2
0.472 +0.009
–0.008
D
14.8±0.4
0.583±0.016
F
1.125
0.044
G
1.125
0.044
H
0.30±0.10
0.012 +0.004
–0.005
I
0.13
0.005
J
0.65 (T.P.)
0.026 (T.P.)
K
1.4±0.2
0.055±0.008
L
0.6±0.2
0.024 +0.008
–0.009
M
0.15 +0.10
–0.05
0.006 +0.004
–0.003
N
0.10
P
Q
1.4
0.055
R
0.125±0.075
5°±5°
0.005±0.003
5°±5°
S
1.7 MAX.
0.004
0.067 MAX.
P64GK-65-8A8-1
49
µ PD75P3116
12. RECOMMENDED SOLDERING CONDITIONS
The µPD75P3116 should be soldered and mounted under the conditions recommended in the table below.
For details of recommended soldering conditions, refer to the information document Semiconductor Device
Mounting Technology Manual (C10535E).
For soldering methods and conditions other than those recommended below, contact an NEC Sales representative.
Table 12-1. Surface Mounting Type Soldering Conditions
(1) µ PD75P3116GC-AB8: 64-pin plastic QFP (14 x 14 mm, 0.8-mm pitch)
Soldering
Method
Soldering Conditions
Symbol
Infrared
reflow
Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C min.),
Number of times: Three times max.
IR35-00-3
VPS
Package peak temperature: 215°C, Time: 40 seconds max. (at 200°C min.),
Number of times: Three times max.
VP15-00-3
Wave soldering
Solder temperature: 260°C max., Flow time: 10 seconds max., Number of
times: Once, Preheating temperature: 120°C max. (Package surface temperature)
WS60-00-1
Partial heating
Pin temperature: 300°C max., Time : 3 seconds max. (per device)
Caution
—
Use of more than one soldering method should be avoided (except for partial heating).
(2) µ PD75P3116GK-8A8: 64-pin plastic QFP (12 x 12 mm, 0.65-mm pitch)
Soldering
Method
Soldering Conditions
Recommended
Conditions
Reference Code
Infrared reflow
Package peak temperature: 235°C,
Time: 30 seconds max. (at 210˚C min.),
Number of times: Twice max., Number of days: 7Note (after that, prebaking is
necessary at 125°C for 10 hours)
<Precaution>
Products other than those supplied in thermal-resistant tray (magazine, taping,
and non-thermal-resistant tray) cannot be baked in their packs.
IR35-107-2
VPS
Package peak temperature: 215°C,
Time: 40 seconds max. (at 200°C min.),
Number of times: Twice max., Number of days: 7Note (after that, prebaking is
necessary at 125°C for 10 hours)
<Precaution>
Products other than those supplied in thermal-resistant tray (magazine, taping,
and non-thermal-resistant tray) cannot be baked in their packs.
VP15-107-2
Wave soldering
Soldering bath temperature: 260°C max., Time: 10 seconds max.,
Number of times: Once
Preheating temperature: 120°C max. (package surface temperature)
Number of days: 7Note (after that, prebaking is necessary at 125°C for
10 hours)
WS 60-107-1
Partial heating
Pin temperature: 300°C max., Time: 3 seconds max. (per pin row)
—
Note Number of days after unpacking the dry pack. Storage conditions are 25°C and 65%RH max.
Caution
Do not use different soldering methods together (however, partial heating can be performed with
other soldering methods.)
50
µ PD75P3116
APPENDIX A. FUNCTION LIST OF µPD75308B, 753108 AND 75P3116
µPD75308B
Parameter
Program memory
Mask ROM
0000H to 1F7FH
(8064 x 8 bits)
Data memory
Stack
Instruction
One-time PROM
0000H to 3FFFH
(16384 x 8 bits)
75X Standard
75XL CPU
When main system
clock is selected
0.95, 1.91, 15.3 µs
(during 4.19-MHz operation)
• 0.95, 1.91, 3.81, 15.3 µs (during 4.19-MHz operation)
• 0.67, 1.33, 2.67, 10.7 µs (during 6.0-MHz operation)
When subsystem
clock is selected
122 µs (during 32.768-kHz operation)
SBS register
None
SBS.3 = 1: Mk I mode selection
SBS.3 = 0: Mk II mode selection
Stack area
000H to 0FFH
000H to 1FFH
Subroutine call instruction stack operation
2-byte stack
When Mk I mode : 2-byte stack
When Mk II mode : 3-byte stack
BRA !addr1
CALLA !addr1
Unavailable
When Mk I mode : unavailable
When Mk II mode : available
MOVT XA, @BCDE
MOVT XA, @BCXA
BR BCDE
BR BCXA
I/O port
Mask ROM
0000H to 1FFFH
(8192 x 8 bits)
µPD75P3116
000H to 1FFH
(512 x 4 bits)
CPU
Instruction
execution
time
µ PD753108
Available
CALL !addr
3 machine cycles
Mk I mode : 3 machine cycles
Mk II mode : 4 machine cycles
CALLF !faddr
2 machine cycles
Mk I mode : 2 machine cycles
Mk II mode : 3 machine cycles
CMOS input
8
8
CMOS input/output
16
20
Bit port output
8
0
N-ch open-drain
input/output
8
4
Total
40
32
LCD controller/driver
Segment selection: 24/28/32 Segment selection: 16/20/24 segments
(can be changed to CMOS (can be changed to CMOS input/output port in
input/output port in 4-unit;
4-unit; max. 8)
max. 8)
Display mode selection: static, 1/2 duty (1/2 bias), 1/3 duty (1/2 bias), 1/3 duty
(1/3 bias), 1/4 duty (1/3 bias)
On-chip split resistor for LCD driver can be specified by
using mask option.
Timer
3 channels
• Basic interval timer:
1 channel
• 8-bit timer/event counter:
1 channel
• Watch timer: 1 channel
No on-chip split resistor
for LCD driver
5 channels
• Basic interval timer/watchdog timer: 1 channel
• 8-bit timer/event counter: 3 channels
(can be used as 16-bit timer/event counter)
• Watch timer: 1 channel
51
µ PD75P3116
µPD75308B
Parameter
µ PD753108
µPD75P3116
Clock output (PCL)
• Φ, 524, 262, 65.5 kHz
(Main system clock:
during 4.19-MHz
operation)
BUZ output (BUZ)
2 kHz
• 2, 4, 32 kHz
(Main system clock:
(Main system clock: during 4.19-MHz operation or
during 4.19-MHz operation)
subsystem clock: during 32.768-kHz operation)
• 2.93, 5.86, 46.9 kHz
(Main system clock: 6.0-MHz operation)
Serial interface
3 modes are available
• 3-wire serial I/O mode ··· MSB/LSB can be selected for transfer first bit
• 2-wire serial I/O mode
• SBI mode
SOS register
• Φ, 524, 262, 65.5 kHz
(Main system clock: during 4.19-MHz operation)
• Φ, 750, 375, 93.8 kHz
(Main system clock: during 6.0-MHz operation)
Feedback resistor
cut flag (SOS.0)
None
Contained
Sub-oscillation circuit
current cut flag (SOS.1)
None
Contained
Register bank selection register (RBS)
None
Yes
Standby release by INT0
No
Yes
Vectored interrupt
External: 3, Internal: 3
External: 3, Internal: 5
Supply voltage
VDD = 2.0 to 6.0 V
VDD = 1.8 to 5.5 V
Operating ambient temperature
TA = –40 to +85°C
Package
• 80-pin plastic QFP
(14 x 20 mm)
• 80-pin plastic QFP
(14 x 14 mm)
• 80-pin plastic TQFP
(Fine pitch) (12 x 12 mm)
52
• 84-pin plastic QFP (14 x 14 mm, 0.8-mm pitch)
• 64-pin plastic QFP (12 x 12 mm, 0.65-mm pitch)
µ PD75P3116
APPENDIX B. DEVELOPMENT TOOLS
The following development tools have been provided for system development using the µPD75P3116.
In the 75XL series, a common relocatable assembler is used in combination with a device file dedicated to each model.
RA75X relocatable assembler
Host machine
Part No. (name)
OS
PC-9800 Series
MS-DOS
Supply medium
TM
Ver.3.30 to
Ver.6.2 Note
Device file
3.5" 2HD
µS5A13RA75X
5" 2HD
µS5A10RA75X
IBM PC/ATTM
Refer to OS for
3.5" 2HC
µS7B13RA75X
or compatibles
IBM PCs
5" 2HC
µS7B10RA75X
Host machine
PC-9800 Series
Part No. (name)
OS
Supply medium
MS-DOS
3.5" 2HD
µS5A13DF753108
5" 2HD
µS5A10DF753108
Ver.3.30 to
Ver.6.2 Note
IBM PC/AT
Refer to OS for
3.5" 2HC
µS7B13DF753108
or compatibles
IBM PCs
5" 2HC
µS7B10DF753108
Note Ver. 5.00 and later include a task swapping function, but this function cannot be used in this software.
Remark
Operation of the assembler and device file is guaranteed only when using the host machine and OS described
above.
53
µ PD75P3116
PROM Write Tools
Hardware
Software
PG-1500
This is a PROM writer that can program single-chip microcontroller with PROM in stand-alone
mode or under control of host machine when connected with supplied accessory board and
optional programmer adapter.
It can also program typical PROMs in capacities ranging from 256 K to 4 M bits.
PA-75P3116BGC
This is a PROM programmer adapter for the µPD75P3116GC.
It can be used when connected to a PG-1500.
PA-75P3116BGK
This is a PROM programmer adapter for the µPD75P3116GK.
It can be used when connected to a PG-1500.
PG-1500 controller
Connects PG-1500 to host machine with serial and parallel interface and controls PG-1500 on
host machine.
Host machine
PC-9800 Series
Part No. (name)
OS
Supply medium
MS-DOS
3.5" 2HD
µ S5A13PG1500
5" 2HD
µ S5A10PG1500
Ver.3.30 to
Ver.6.2 Note
IBM PC/AT
Refer to OS for
3.5" 2HD
µ S7B13PG1500
or compatible
IBM PCs
5" 2HC
µ S7B10PG1500
Note Ver. 5.00 and later include a task swapping function, but this function cannot be used in this software.
Remark
54
Operation of the PG-1500 controller is guaranteed only when using the host machine and OS described above.
µ PD75P3116
Debugging Tools
In-circuit emulators (IE-75000-R and IE-75001-R) are provided as program debugging tools for the µPD75P3116.
Various system configurations using these in-circuit emulators are listed below.
Hardware
IE-75000-RNote 1
The IE-75000-R is an in-circuit emulator to be used for hardware and software debugging during
development of application systems using the 75X or 75XL Series products.
For development of the µPD753108 Subseries, the IE-75000-R is used with optional emulation
board (IE-75300-R-EM) and emulation probe (EP-753108GC-R or EP-753108GK-R).
Highly efficient debugging can be performed when connected to host machine and PROM
programmer.
The IE-75000-R includes a connected emulation board (IE-75000-R-EM).
IE-75001-R
The IE-75001-R is an in-circuit emulator to be used for hardware and software debugging during
development of application systems using the 75X or 75XL Series products.
The IE-75001-R is used in combination with optional emulation board (IE-75300-R-EM) and
emulation probe (EP-753108GC-R or EP-753108GK-R).
Highly efficient debugging can be performed when connected to host machine and PROM
programmer.
IE-75300-R-EM
This is an emulation board for evaluating application systems using the µPD75P3116.
It is used in combination with the IE-75000-R or IE-75001-R.
EP-753108GC-R
This is an emulation probe for the µPD75P3116GC.
When being used, it is connected with the IE-75000-R or IE-75001-R and the IE-75300-R-EM.
EV-9200GC-64
EP-753108GK-R
TGK-064SBW
Note 2
Software
IE control program
It includes a 64-pin conversion socket (EV-9200GC-64) to facilitate connections
with target system.
This is an emulation probe for the µPD75P3116GK.
When being used, it is connected with the IE-75000-R or IE-75001-R and the IE-75300-R-EM.
It includes a 64-pin conversion adapter (TGK-064SBW) to facilitate connections with target
system.
This program can control the IE-75000-R or IE-75001-R on a host machine when connected to
the IE-75000-R or IE-75001-R via an RS-232C or Centronics interface.
Host machine
PC-9800 Series
Part No. (name)
OS
Supply medium
MS-DOS
3.5" 2HD
µ S5A13IE75X
5" 2HD
µ S5A10IE75X
Ver.3.30 to
Ver.6.2 Note 3
Notes 1.
2.
IBM PC/AT
Refer to OS for
3.5" 2HC
µ S7B13IE75X
or compatible
IBM PCs
5" 2HC
µ S7B10IE75X
This is a maintenance product.
Made by TOKYO ELETECH Corporation (Tokyo, 03-5295-1661).
Contact to an NEC sales representative for detailed information.
3.
Ver. 5.00 and later include a task swapping function, but this function cannot be used in this software.
Remarks 1.
Operation of the IE control program is guaranteed only when using the host machine and OS
described above.
2.
The µ PD753104, 753106, 753108, and 75P3116 are generically called the µ PD753108 Subseries.
55
µ PD75P3116
OS for IBM PCs
The following operating systems for the IBM PC are supported.
OS
PC DOS
TM
MS-DOS
Version
Ver.3.1 to 6.3, J6.1/V Note to J6.3/V Note
Ver.5.0 to 6.2
5.0/V Note to 6.2/V Note
IBM DOSTM
J5.02/V Note
Note Only English mode is supported.
Caution
56
Ver. 5.0 and later include a task swapping function, but this function cannot be used in this software.
µ PD75P3116
APPENDIX C. RELATED DOCUMENTS
The related documents indicated in this publication may include preliminary versions. However, preliminary
versions are not marked as such.
Device Related Documents
Document No.
Document Name
English
Japanese
µPD753104, 753106, and 753108 Data Sheet
U10086E
U10086J
µPD75P3116 Data Sheet
U11369E (This document)
U11369J
µPD753108 User’s Manual
U10890E
U10890J
µPD753108 Instruction Table
–
75XL Series Selection Guide
U10453E
IEM-5600
U10453J
Development Tool Related Documents
Document No.
Document Name
English
Hardware
Software
Japanese
IE-75000-R/IE-75001-R User’s Manual
EEU-1416
EEU-846
IE-75300-R-EM User’s Manual
U11354E
U11354J
EP-753108GC/GK-R User’s Manual
EEU-1495
EEU-968
PG-1500 User’s Manual
EEU-1335
U11940J
RA75X Assembler Package
Operation
EEU-1346
EEU-731
User’s Manual
Language
EEU-1363
EEU-730
PG-1500 Controller User’s Manual
PC-9800 series
(MS-DOS) base
EEU-1291
EEU-704
IBM PC series
(PC DOS) base
U10540E
EEU-5008
Other Related Documents
Document No.
Document Name
English
Japanese
IC Package Manual
C10943X
Semiconductor Device Mounting Technology Manual
C10535E
C10535J
Quality Grades on NEC Semiconductor Devices
C11531E
C11531J
NEC Semiconductor Device Reliability/Quality Control System
C10983E
C10983J
Electrostatic Discharge (ESD) Test
–
Guide to Quality Assurance for Semiconductor Devices
Microcontroller-related Product Guide
Caution
Third Party’s Product
MEM-539
MEI-1202
C11893J
–
U11416J
The above related documents are subject to change without notice. For design purposes, etc.,
be sure to use the latest versions.
57
µ PD75P3116
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction of
the gate oxide and ultimately degrade the device operation. Steps must be taken
to stop generation of static electricity as much as possible, and quickly dissipate
it once, when it has occurred. Environmental control must be adequate. When
it is dry, humidifier should be used. It is recommended to avoid using insulators
that easily build static electricity. Semiconductor devices must be stored and
transported in an anti-static container, static shielding bag or conductive
material. All test and measurement tools including work bench and floor should
be grounded. The operator should be grounded using wrist strap. Semiconductor
devices must not be touched with bare hands. Similar precautions need to be
taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input level
may be generated due to noise, etc., hence causing malfunction. CMOS devices
behave differently than Bipolar or NMOS devices. Input levels of CMOS devices
must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have
a possibility of being an output pin. All handling related to the unused pins must
be judged device by device and related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production
process of MOS does not define the initial operation status of the device.
Immediately after the power source is turned ON, the devices with reset function
have not yet been initialized. Hence, power-on does not guarantee out-pin
levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after
power-on for devices having reset function.
58
µ PD75P3116
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, please contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
• Device availability
• Ordering information
• Product release schedule
• Availability of related technical literature
• Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
• Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
NEC Electronics (Germany) GmbH
NEC Electronics Hong Kong Ltd.
Santa Clara, California
Tel: 800-366-9782
Fax: 800-729-9288
Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 040-2444580
Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 0211-65 03 490
NEC Electronics Hong Kong Ltd.
NEC Electronics (France) S.A.
Velizy-Villacoublay, France
Tel: 01-30-67 58 00
Fax: 01-30-67 58 99
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics (France) S.A.
NEC Electronics Singapore Pte. Ltd.
Spain Office
Madrid, Spain
Tel: 01-504-2787
Fax: 01-504-2860
United Square, Singapore 1130
Tel: 253-8311
Fax: 250-3583
NEC Electronics (UK) Ltd.
Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290
NEC Electronics Italiana s.r.1.
Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99
NEC Electronics Taiwan Ltd.
NEC Electronics (Germany) GmbH
Scandinavia Office
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388
Taipei, Taiwan
Tel: 02-719-2377
Fax: 02-719-5951
NEC do Brasil S.A.
Sao Paulo-SP, Brasil
Tel: 011-889-1680
Fax: 011-889-1689
J96. 8
59
µ PD75P3116
QTOP is a trademark of NEC Corporation.
MS-DOS is a trademark of Microsoft Corporation.
IBM DOS, PC/AT, and PC DOS are trademarks of International Business Machines Corporation.
The export of this product from Japan is regulated by the Japanese government. To export this product may be
prohibited without governmental license, the need for which must be judged by the customer. The export or reexport of this product from a country other than Japan may also be prohibited without a license from that country.
Please call an NEC sales representative.
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.
M4 96.5
60