NJW4302 Preliminary THREE-PHASE DC BRUSHLESS MOTOR CONTROL IC ■ GENERAL DESCRIPTION The NJW4302 is a three-phase DC brushless motor pre-driver IC for precision applications. The NJW4302 consists of PWM driver, motor velocity control, FG(Frequency Generator) output, and voltage velocity integration circuit. The NJW4302 realizes stabilized velocity and it is suitable for printer, FAX, and other DC motor control systems. ■ PACKEGE OUTLINE NJW4302FA1 ■ FEATURES Speed discriminator and PLL speed control circuit Direct PWM driver CR oscillator Lock protection output Break circuit (short circuit braking) Start/stop switch Start/Stop Switch Circuit Current limit circuit Thermal shut down/Under voltage lockout circuit FG output amplifier/Integrating circuit Shunt regulator output : 5V Bi-CMOS technology PACKAGE OUTLINE QFP44 ■ PIN CONFIGRATION • • • • • • • • • • • • WL VH VL UH UL RF H3 H3 H2 H2 H1 H1+ WH PVCC FGIN+ VCC FGIN- VREG FGOUT DGND FGSOUT AGND PGND NJW4302 QFP44 AGND VSH CR N2 CROCK N1 R SS C CLK FILO FILI TOC INT IN POUT LD DOUT INTOUT INTREF BR FR ■BLOCK DIAGRAM D o ut FGSO FGO LD O C R OC K IN TR EF IN TIN IN TOU TS/S LD FGINFGIN+ - + + BR F/R BR F/R V+ F R OC K OSC IN TEGR ATION AMP FG SPEED D I SC RIMI N ATOR H AL L H YS AMP S/S Vreg H2+ H2 H3+ VR EF SPEE D PL L Pou t H1+ H1 - L OGIC H3 - VR EG 1 VSH VC OO U T PR OTEC TION CLK ALTER N ATIVE PLL C OU N TER P WM B LOC K C OU N TER C IR C U IT TS D / L VD S C IR CU IT P R I- D R IVER FILI FILO R C N1 N2 GN D C R R F TOC U L VL WL U H VH WH -1- NJW4302 Preliminary ■PIN DESCRIPTION SYMBOL PIN No. H1+,H1- 33, 34 Hall input pins DESCRIPTION H2+,H2- 35, 36 Positive input terminal is defined as IN+,Negative input terminal as IN- respectably. H3+,H3- 37, 38 Positive input is defined as IN+> IN- as Negative. UH 41 VH 43 WH 1 UL 40 Output pins(open collector sink outputs). VL 42 Duty control implement with PWM signal. Output pins(for fixed current source ) WL 44 VPCC 2 Power-supply voltage pin VCC 3 Connect a noise decoupling capacitor between these pins and the ground. VREG 4 Shunt regulator output pin PGND.DGND 5,6 AGND 27,28 VSH 7 Ground pins These pins are all connected internally to the ground(GND). Shunt regulator ON/OFF output pin “H” or open:ON “L”:OFF CR 8 PWM oscillator frequency setting pin Three blocks use the oscillator: motor constraint detection circuit, clock disconnection protection circuit and others CROCK 9 Reference clock signal oscillator pin Connect a capacitor between this pin to the ground.This oscillator provides clock signal when motor is locked. R 10 VCO oscillation frequency setting pin Connect a resistor between this pin and the ground. C 11 VCO oscillation frequency setting pin Connect a resister between this pin and ground. Set the value of the capacitor so that the oscillator frequency does not exceed 1MHz. FILI 13 VCO filter amplifier input pin This pin is connected to VCO PLL output with 10KΩ resistor internally in the IC. FILO 12 VCO filter amplifier output pin This pin is connected to VCO circuit internally in the IC. D OUT 18 Speed discriminator output pin Output“L”level for over speed. P OUT 19 PLL output pin Output the phase comparison result for 1/2fCLK and1/2fFG. LD 20 Lock detection output pin Open collector becomes“L”within the speed lock range(±6.25). INT REF 14 Integrating amplifier forward rotation input(a potential of 1/2V+) INT IN 17 Negative input for Integration amplifier INT OUT 16 Output for Integration amplifier TOC 15 Torque command input pin This pin is normally connected to the INT OUT pin. When the TOC voltage level falls,the UL,VL and Wl PWM duties are changed to increase. FG IN+ 32 Input pin for FG amplifier forward rotation (a potential of 1/2V+) Connect a noise decoupling capacitor between V+ terminal and the ground. -2- NJW4302 Preliminary FG IN- 31 FG amplifier reverse rotation input. FGOUT 30 FG amplifier output. FGSOUT 29 FG amplifier output(after the schmitt) Open collector output. RF 39 Output current detection Connect a resistor between this pin and GND pin.The output limitation maximum current(IOUT)is set to be 0.5/Rf. SS 24 Start⋅Stop control “L”:Start “H”or Open:Stop FR 22 Forward/reverse rotation control “L”:Forward “H”or Open:reverse BR 21 Brake control (short braking operation) “L”:Start “H”or Open:Brake CLK 23 External clock signal input 10kHz max. N1 25 N2 26 Speed discriminator count switching -3- NJW4302 Preliminary ■ FUNCTIONAL DESCRIPTION 1. VCO circuit The variable range of PLL circuit is determined by two factors: VCO frequency determined by RC value connected to Pin 15 and Pin 16 and VCO loop filter constants. VCO frequency range must be within 160kHZ to 1.0MHZ. The typical external value is as follows: R=20kΩ,C=100pF. The filter constants are C=0.47µF,R=27kΩ. 2. Output drive circuit The PWM control is made by upper side of external transistor. 3. Speed lock range The speed lock range is ±6.25% of fixed speed. When the motor speed is within the lock range, the LD pin (an open collector output)goes “L”. If the motor speed goes out of the lock range, the LD pin goes “H”. Please be noted that the LD signal may go on during startup. 4. PWM frequency The PWM frequency is determined by resistor and capacitor value connected to the CR pin. The PWM frequency is given by expressed as: fPWM=1/(0.48CR) When C=1500pF,R=75KΩ,the PWM frequency goes about 19KHz. 5. Lock detection circuit(CLOCK) Lock detection circuit protects the driver IC and the motor from fatal over current failure when the motor is locked during startup. If the LD output remains “H” (motor lock state) for a certain period (Hold time),all phase of upper side transistors are to be turned off. The hold time can be programmed by capacitor value attached to the CLOCK pin by the following: Set time(sec) =66×C(µF) With C=0.068µF,the hold time can be programmed for approximately 4.5 sec. Once Lock detection circuit is activated, the state remains unchanged unless it is turned off, or stopped. This function can be disabled when the CLOCK pin is connected to the ground. 6. Forward / Reverse(F/R)Switching The direction control can be made with the state of the F/R pin. The direction can be changed even during the motor in motion. -4- NJW4302 Preliminary 7. Brake Switch NJW4302 uses a short brake method that turns on all phase of upper side transistors for braking. During the time, all lower side transistors are turned off. 8. VREG pin/VSH pin NJW4302 includes a regulator to generate for +5V regulated IC supply when the motor drive circuit is designed with a single power supply. The VREG pin and V+ pin compose a shunt regulator for 5V±5% output with a external resistor and a transistor. To use the regulator, the VSH pin must be either “H”, or Open. Otherwise, the VSH pin must be “L” and the VREG pin is to be opened. 9. Frequency Generator (FG) Amplifier The internal FG amplifier with few passive components composes a filter amplifier shown in the application. Circuit for noise rejection. The output voltage of the amplifier must be at least 250mA p-p since it feature Schmitt comparator. The capacitor connected between the FGIN+ pin and the ground is necessary for bias voltage stabilization and initial reset pulse generation for the internal logic. The reset pulse is generated when the FGIN+ pin goes from 0 to approximately 1.25V. 10. Integration Amplifier The integration amplifier integrates the D-out and P-out and converts them to speed command voltage. During the time, it also sets the control loop gain and frequency characteristics using external components. 11. Speed Control Circuit NJW4302 features two speed control method; speed discriminator circuit with PLL circuit and phase comparison circuit. The FG pulse frequency is controlled to be the same frequency with a clock frequency input to the CLK pin. Therefore, the motor speed can be controlled by changing the clock frequency. The motor speed (N) can be expressed as: N=CLK (Hz)×(60/FGP)[RPM] ( FGP: Number of FG pulse per one rotation) Given that the oscillation frequency range is 160kHz~1.0MHZ and the number of counts is 1024,the range of clock frequency is 156HZ~960HZ , and therefore the motor speed can be changed from 260rpm to 1600rpm. -5- NJW4302 Preliminary ■ABSOLUTE MAXIMUM RATING PARAMETER SYMBOL Ma ximum supply voltage V+ Ma ximum input current Ireg Output current Io Operating temperature TEST CONDITION RATINGS UNIT 7 V Vreg pin(5.6V) 10 mA UL,VL,WL 30 mA Topr -40∼85 °C Storage temperature Tstg -55 ∼ 150 °C Power dissipation Pd 700 mW RATINGS UNIT 1.0~5.0 mA ■ALLOWABLE MAXIMUM RANGES/Ta=25°°C PARAMETER Input current range SYMBOL IREG CONDITION VREG pin=5.6V FG Schmitt output applied voltage VFGSO 0~8 V FG Schmitt output current IFGSO 0~5 mA ILD 0~20 mA 4.5~5.5 V Lock detection output current Supply voltage -6- + V NJW4302 Preliminary ■ELECTRICAL CHARACTERISTICS / Ta=25°°C,V+=5.0V PARAMETER SYMBOL MIN. TYP. MAX. UNIT - 38 55 mA in stop mode - 8 18 mA VO (sat) UL,VL and WL terminal Io=20mA - 0.2 0.7 V IO UH,VH and WHterminal Vout=1.4V -20 -16 -12 mA Supply current 1 ICC1 Supply current 2 ICC2 Output saturation voltage Output current CONDITION Output leakage current IO(leak) UL,VL,WL output - - 100 µA Output off voltage VO(off) UH,VH,WH output - - 0.5 V MIN. TYP. MAX. UNIT IHB(HA) -4 -1 - µA VICM 1.5 - VCC-1.5 V Hall input sensitivity ∆VIN(HA) - 60 - mVP-P Hysteresis ∆VIN(HA) 17 32 60 mV Input voltage Low → High VSLH 8 16 30 mV Input voltage High →Low VSHL -30 -16 -8 mV •HALL AMPLIFIER PARAMETER SYMBOL Input bias current Common mode input voltage range •CR OSCILLATOR PARAMETER SYMBOL Output high level voltage TEST CONDITION MIN. TYP. MAX. UNIT VOH(CR) 2.4 2.7 3.0 V Output low level voltage VOL(CR) 1.3 1.6 1.9 V RC oscillation frequency f(CR) - 19 - kHz RC oscillation voltage V(CR) 0.9 1.1 1.3 VP-P •CLOCK OSCILLATOR PARAMETER TEST CONDITION R=75kΩ,C=1500pF SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT Output high level voltage VOH(RK) 2.7 3.0 3.3 V Output low level voltage VOL(RK) 0.1 0.4 0.7 V External capacitor charge current ICHG1 - -10 - µA External capacitor discharge current ICHG2 - 10 - µA Clock oscillation frequency f(RK) - 35 - Hz RC oscillation voltage V(RK) 2.4 2.6 2.8 VP-P •VCO OSCILLATOR (PLL COUNTER) PARAMETER SYMBOL C=0.068µF TEST CONDITION MIN. TYP. MAX. UNIT C-terminal high-level output voltage VOH(C) 1.15 1.25 1.35 V C-terminal low-level output voltage VOL(C) 0.9 1.0 1.1 V VCO oscillation frequency f(C) - - 1.0 MHz Amplitude V(C) 0.15 0.25 0.6 VP-P -7- NJW4302 •CURRENT LIMITING OPERATION PARAMETER SYMBOL Limiter •FG AMPLIFIER PARAMETER Input offset voltage Input bias current Output low-level voltage Output high-level voltage FG input sensitivity Schmitt amplifier for next stage Operating frequency range Open loop gain Preliminary TEST CONDITION VRF SYMBOL VIO(FG) IB(FG) VOH(FG) VOL(FG) ∆VIN(FG) ∆VSH(FG) ∆FG AV(FG) •FGSO OUTPUT PARAMETER SYMBOL Output saturation voltage VO(FGSO) Output leak current IL(FGSO) MIN. TYP. MAX. UNIT 0.47 0.52 0.57 V TEST CONDITION MIN. -10 -1 + V -1.5 100 - GAIN =40dB f(FG)=2kHz TEST CONDITION TYP. 0 0 + V -1.0 1 3 180 16 51 MAX. 10 1 1.5 250 - UNIT mV µA V V mV mV kHz dB MIN. TYP. MAX. UNIT IO(FGS)=2mA - 0.1 0.5 V VO=V+ - - 10 µA •SPEED DISCRIMINATOR OUTPUT (Dout) PARAMETER SYMBOL TEST CONDITION MIN. + TYP. MAX. UNIT + Output high-level voltage VOH(D) V -1.0 V -0.7 - V Output low-level voltage VOL(D) - 0.4 - V MIN. TYP. MAX. UNIT •SPEED CONTROL PLL OUTPUT (Pout) PARAMETER SYMBOL TEST CONDITION Output high-level voltage VOH(P) 3.35 3.65 3.95 V Output low-level voltage VOL(P) 1.35 1.65 1.95 V MIN. TYP. MAX. UNIT - 0.1 0.5 V - - 10 µA -6.25 - +6.25 % •LOCK DETECTION (LD) PARAMETER Output saturation voltage Output leak current Lock range -8- SYMBOL VOL(LD) IL(LD) ∆LOCK TEST CONDITION ILD=10mA + VO=V Design target spec NJW4302 •INTEGRATER AMPLIFIER PARAMETER SYMBOL Input offset voltage Input bias current Output high-level voltage Output low-level voltage Open loop gain Gain-band width product Reference voltage TEST CONDITION VIO(INT) IB(INT) VOH(INT) VOL(INT) AV(INT) GBW(INT) VB(INT) •FILTER AMPLIFIER (PLL COUNTER) PARAMETER SYMBOL Input bias current Preliminary TEST CONDITION MIN. TYP. MAX. UNIT -10 -0.4 + V -0.12 2.375 + V -0.8 0.8 60 1.6 2.5 10 0.4 1.2 2.625 mV µA V V dB MHz V MIN. TYP. MAX. UNIT 0.4 - µA + IB(FIL) + Output high-level voltage VOH(FIL) V -1.2 V -0.8 - V Output low-level voltage VOL(FIL) - 0.8 1.2 V Hysteresis VB(FIL) 2.375 2.5 2.625 V MIN. TYP. MAX. UNIT •S/S AMPLIFIER PARAMETER SYMBOL TEST CONDITION Input high-level voltage VIH(S/S) 3.5 4.2 V+ V Input low-level voltage VIL(S/S) 0 0.8 1.0 V ∆VIN(S/S) 1.0 1.3 1.6 V RU(S/S) 60 80 100 kΩ MIN. TYP. MAX. UNIT Hysteresis Pull-Up resistance •F/R AMPLIFIER PARAMETER SYMBOL TEST CONDITION + Input high-level voltage VIH(F/R) 3.5 4.2 V V Input low-level voltage VIL(F/R) 0 0.8 1.0 V ∆VIN(F/R) 1.0 1.3 1.6 V RU(F/R) 60 80 100 kΩ MIN. TPY. MAX. UNIT Hysteresis Pull-Up resistance •BR AMPLIFIER PARAMETER SYMBOL TEST CONDITION + Input high-level voltage VIH(BR) 3.5 4.2 V V Input low-level voltage VIL(BR) 0 0.8 1.0 V ∆VIN(BR) 1.0 1.3 1.6 V RU(BR) 60 80 100 kΩ Hysteresis Pull-Up resistance -9- NJW4302 Preliminary •CLK AMPLIFIER PARAMETER SYMBOL Input high-level voltage MIN. TPY. MAX. UNIT VIH(CLK) 3.5 4.2 V+ V Input low-level voltage VIL(CLK) 0 0.8 1.0 V Hysteresis ∆VIN(CLK) 1.0 1.3 1.6 V Pull-Up resistance RU(CLK) 60 80 100 kΩ f(CLK) - 16 - kHz MIN. TYP. MAX. UNIT Input frequency •N1 AMPLIFIER PARAMETER SYMBOL TEST CONDITION TEST CONDITION + Input high-level voltage VIH(N1) 3.5 4.2 V V Input low-level voltage VIL(N1) 0 0.8 1.0 V ∆VIN(N1) 1.0 1.3 1.6 V RU(N1) 60 80 100 kΩ MIN. TYP. MAX. UNIT Hysteresis Pull-Up resistance •N2 AMPLIFIER PARAMETER SYMBOL TEST CONDITION Input high-level voltage VIH(N2) 3.5 4.2 V+ V Input low-level voltage VIL(N2) 0 0.8 1.0 V ∆VIN(N2) 1.0 1.3 1.6 V RU(N2) 60 80 100 kΩ MIN. TYP. MAX. UNIT Hysteresis Pull-Up resistance •UNDER VOLTAGE LOCKOUT PARAMETER SYMBOL TEST CONDITION Operating voltage VSDL - 3.75 - V Release voltage VSDH - 4.0 - V Hysteresis ∆VSD 0.15 0.25 0.35 V MIN. TYP. MAX. UNIT 4.75 5.0 5.25 V MIN. TYP. MAX. UNIT •SHUNT REGULATOR PARAKMETER SYMBOL Output voltage VO(VSH) •VSH AMPLIFIER PARAMETER SYMBOL Input high-level voltage VIH(VSH) 3.5 4.2 V+ V Input low-level voltage VIL(VSH) 0 0.8 1.0 V ∆VIN(VSH) 1.0 1.3 1.6 V RU(VSH) 60 80 100 kΩ Hysteresis Pull-Up resistance - 10 - TEST CONDITION TEST CONDITION NJW4302 Preliminary ■ SPEED DISCRIMINATOR COUNT TABLE N1 N2 NUMBER OF COUNTS High or Open High or Open 128 High or Open Low 512 Low High or Open 256 Low Low 1024 ■ THREE PHASE LOGIC TRUTH TABLE F/R=L F/R=H OUTPUTS H1 H2 H3 H1 H2 H3 Source Sink 1 H L H L H L VH UL 2 H L L L H H WH UL 3 H H L L L H WH VL 4 L H L H L H UH VL 5 L H H H L L UH WL 6 L L H H H L VH WL ■ S/S TERMINAL High or Open Stop Low Start ■ BRAKE TERMINAL High or Open Brake Low Release - 11 - NJW4302 Preliminary ■ TYPICAL APPLICATION VM QVR R12 R13 R14 R10 VCC DGND AGND CROCK N1 0.47u 220p C5 0.1u C6 0.22u C7 R5 R6 R418k 2.4M 150k FR BR C 2k 0.47u R8 C9 FGS SS CLK LD R R3 27k C4 - 12 - H1- N2 POUT 100p CR DOUT C3 20k C8 1000p AGND INT IN R2 0.047u VSH INT OUT C2 1500p 0.1u PGND NJW4302 QFP44 INT REF C1 75k FILI VSH FILO R1 R11 C10 FGOUT 100k R7 FGSOUT VREG 47u H1+ FGIN+ FGIN- TOC CVR H2+ H2- H3+ H3- RF UL UH WH PVCC VL VH WL R9 C NJW4302 Preliminary ■ TYPICAL CHARACTERISTICS - 13 - NJW4302 Preliminary ■ TYPICAL CHARACTERISTICS (Ta=25degC,With standard device) - 14 - NJW4302 Preliminary ■ APPLICATION NOTE •FG Amplifier FG Amplifier consists of input differential amplifier and output Schmitt-trigger comparator. Input amplifier is constructed as low-pass filter with external resistors and capacitors to reduce noise. The amplifier output level should be over 250mVp-p to adjust gain by external resistors, due to hysteresis of Schmitt-trigger comparator. FG+ input is biased internally to the half level of Vcc. This DC bias voltage is also used to RESET the internal logic circuit. For stable RESET operation, It a capacitor, requires a 0.1 uF capacitor connected to FG+ terminal. RESET is enable a during 0V to 1.25V of the voltage at the FG+. FG Sensor Amplifier Application Circuit 1000p 100k FGO 0.47u 2k FGS FGFG+ 0.1u for Internal logic NJW4302 - 15 - NJW4302 Preliminary • FG interfac for logic output device The circuit below is a FG interface for logic output device (i.e. Hall IC and optical encoder). Two external resistors are required to adjust the input voltage within the common mode input voltage range,0 to Vcc-1.5V. FG interface for logic level input 5V FGO logic FG 1.5k FG FG + 3.5k for Internal logic 0.1u NJW4302 • Power supply generating from Vref To supply for NJM4302, Hall sensor and Power stage, QR1 should have 100mA current capacity. It needs 47 microfarad capacitor on V+ of NJW4302 for ripple filtering. • Hall sensor biasing Hall biasing is determined by Hall signal amplitude. Hall signal amplitude must be larger than input sensitivity of NJW4302. • FG Input Internal FG Amplifier is a differential amplifier which inputs and output are pin-outed. The DC gain of this amplifier, AFG, is: AFG = R7 R8 C8 is for noise reduction, C9 is for DC cut. Typical value of C10 is 0.1 microfarad. The inductor symbol connected FGIN is FG sensing copper pattern on PC board. • Power supply generating from Vref To supply for NJM4302, Hall sensor and Power stage, QR1 should have 100mA current capacity. It needs 47 microfarad capacitor on V+ of NJW4302 for ripple filtering. • Hall sensor biasing Hall biasing is determined by Hall signal amplitude. Hall signal amplitude must be larger than input sensitivity of NJW4302. - 16 - NJW4302 Preliminary • FG Input Internal FG Amplifier is a differential amplifier and both inputs and output are connected to the pin. The DC gain of this amplifier, AFG, is: AFG = R7 R8 C8 is for compensation or noise reduction, C9 is for DC cut. Typical value of C10 is 0.1 microfarad. inductor symbol connected FGIN is FG sensing copper pattern on PC board. • PWM Frequency PWM clock generates by CR oscillator. The frequency is: f PWM = The 1 0.48 ⋅ R1 ⋅ C1 In fig.x*, fPWM is about 19kHz. If fPWM is about 20kHz, it could reduce audible noise. • Variable range of VCO frequency VCO frequency in typical value is recommend 160kHz to 1MHz. External constants is: R2 = 20k ohm, C3 = 100pF, R3 = 27k ohm, C4 = 0.47 uF If it can not be settled into this range, change the division of speed discriminator. • Detecting time of rock protection Detecting time is settled by C2 as follow: t ROCK = 66 ⋅ C 2 In fig.x*, trock is about 3.1 sec. • Integration Amplifier Both speed discriminator output and PLL output should be mixed via two resistors before input to INTIN of Integration Amplifier. Mixing resistor, Timing resistors and capacitors are necessary for good system operation. C6 is need for non-polar type capacitor for good stability. • Upper power transistor To reduce ripple of power line, Upper output transistor is connect NJM4302 via common-base NPN transistors. Minimum output current is 12mA, it is able to drive 1A class transistor. If more current is needed, change the output transistor to Darlington type. Re-circulating diodes is needed on between collector and emitter of output transistor. • Lower power transistor Lower output could drive external power transistor directly to about 1.5A. If more current is needed, change the output transistor to Darlington type. The resistor connected between base and emitter of power transistor is necessary on PWM operation for sharp cut-off of power transistor. When your system have any noise, attach a capacitor in parallel the resistor. Re-circulating diodes is needed on between collector and emitter of output transistor. R11 is a current sensing resistor and settled by following: R11 = VRE IO When VRF is sensing voltage, Io is sensing current. Take care of power dissipation of R11, also. - 17 - NJW4302 Preliminary • Recirculation Diodes Recirculation diodes are recommend to use Shottkey-burrier type. Forward voltage “VF” and reverse returning time “trr” are contributed for power dissipation. [CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights. - 18 -