NPC SM5865CM

ΣDECO SM5865CM
D/A Converter for Digital Audio
NIPPON PRECISION CIRCUITS INC.
OVERVIEW
PINOUT
The SM5865CM is a 24-bit input D/A converter LSI
for high-quality digital audio equipment. It comprises newly developed DEM (dynamic element
matching) circuits, 3rd-order Σ∆ noise shaper and
31-level quantizer to realize super low total harmonic distortion and wide dynamic range. Also, the
device is widely reduced residual quantization noise
up to high-frequency bandwidth in the audio band so
the order of the required final-stage analog lowpass
filter can be reduced, making it ideal for application
with high-frequency sampling format. The output
stage employs differential current outputs for highaccuracy analog signals, with appropriate lowpass
filtering of the output signal. This device can be used
in combination with an 8-times oversampling digital
filter of SM5847AF and others like that for the compatibility with 192kHz sampling format.
(Top view)
DVSS
24
1
AVSSA
DI
RA
IOUTA
WCKI
VBA
IWSL
N.C.
S M 5 8 6 5 CM
BCKI
RSTN
TSTN
TO
DVDD
CKI
AVDDA
AVDDB
RB
IOUTB
VBB
N.C.
CKDVN
CVSS
FEATURES
■
■
■
■
■
Mono-channel D/A converter LSI
High performance
• 0.00030 % (–110.5dB) typ. THD + N
• 117 dB typ. Dynamic range
• 120 dB typ. S/N
Input interface
• 20 or 24-bit word length
• MSB first, right-justified format
• 8 or 4 times oversampling at fs = 16/32/44.1/48/
88.2/96/176.4/192 kHz
System clock frequency
• 192/256/384/512/768/1024 fs
Single 5 V operating supply voltage
24-pin SSOP package
Molybdenum-gate CMOS process
13
AVSSB
PACKAGE DIMENSIONS
(Unit: mm)
Weight: 0.23g
24-pin SSOP
5.40 0.20
7.80 0.30
■
■
12
ORDERING INFORMATION
24-pin SSOP
1.80
SM5865CM
0.8
0.36 0.10
0.10
0.12 M
+0.20
1.90−0.10
Package
0.10 0.10
Device
+ 0.10
0.15 − 0.05
10.05 0.20
10.20 0.30
0.50 0.20
0 10
NIPPON PRECISION CIRCUITS—1
SM5865CM
BLOCK DIAGRAM
TO
8
TSTN
RSTN
7
IWSL
6
WCKI
5
BCKI
4
3
DI
2
Input interface
9
DVDD
CKI
CKDVN
CVSS
10
Timing
control
Divider
Interpolation
11
1
12
Noise shaper
AVSSB
Noise shaper
13
24
31 Level
DEM DAC
15
31 Level
DEM DAC
16
DVSS
17
18
19
31 Level
DEM DAC
31 Level
DEM DAC
21
22
AVSSA
23
RA
IOUTA
VBA
AVDDA
AVDDB
RB
IOUTB
VBB
NIPPON PRECISION CIRCUITS—2
SM5865CM
PIN DESCRIPTION
Number
Name
I/O
Description
1
DVSS
–
Digital ground
2
DI
I
Data input
3
BCKI
I
Bit clock input
4
WCKI
I
Word clock input
5
IWSL
Ip
Input data word length select. 24-bit when HIGH, and 20-bit when LOW.
6
RSTN
Ip
System reset. Reset when LOW.
7
TSTN
Ip
Test pin. Tie HIGH or leave open for normal operation.
8
TO
O
Test output
9
DVDD
–
Digital supply
10
CKI
I
System clock input
11
CKDVN
Ip
System clock frequency divider ratio select. 1 when HIGH (no division), and 2 when LOW (half of the
input frequency).
12
CVSS
–
System clock ground
13
AVSSB
–
Analog ground B
14
N. C.
–
Leave open for no connection or connect with ground
15
VBB
O
1/2 supply output B
16
IOUTB
O
Inverse-phase analog output B
17
RB
I
Built-in resistor connection B
18
AVDDB
–
Analog supply B
19
AVDDA
–
Analog supply A
20
N. C.
–
Leave open for no connection or connect with ground
21
VBA
O
1/2 supply output A
22
IOUTA
O
In-phase analog output A
23
RA
I
Built-in resistor connection A
24
AVSSA
–
Analog ground A
IP : Pull-up input
NIPPON PRECISION CIRCUITS—3
SM5865CM
SPECIFICATIONS
Absolute Maximum Ratings
DVSS = AVSSA = AVSSB = CVSS = 0 V, DVDD = AVDDA = AVDDB
Parameter
Symbol
Rating
Unit
Supply voltage range
DVDD, AVDDA, AVDDB
−0.3 to 7.0
V
Input voltage range1
VIN
DVSS − 0.3 to DVDD + 0.3
V
Storage temperature range
Tstg
−55 to 125
°C
Power dissipation
PD
250
mW
Symbol
Rating
Unit
DVDD, AVDDA, AVDDB
4.5 to 5.5
V
DVDD − AVDDA,
DVDD − AVDDB,
AVDDA − AVDDB,
DVSS − AVSSA,
DVSS − AVSSB,
AVSSA − AVSSB,
DVSS − CVSS,
AVSSA − CVSS,
AVSSB − CVSS
±0.1
V
Topr
−40 to 85
°C
1. Pins DI, BCKI, WCKI, CKDVN, IWSL, RSTN, TSTN.
Also applicable during supply switching.
Recommended Operating Conditions
DVSS = AVSSA = AVSSB = CVSS = 0 V, DVDD = AVDDA = AVDDB
Parameter
Supply voltage range
Supply voltage variation
Operating temperature range
NIPPON PRECISION CIRCUITS—4
SM5865CM
DC Electrical Characteristics
Recommended operating conditions, unless otherwise specified.
Rating
Parameter
DVDD, AVDDA, AVDDB
supply current1
Symbol
IDD
Condition
Unit
min
typ
max
fCKI = 11.2896 MHz
–
7
11
mA
fCKI = 16.9344 MHz
–
10
14
mA
fCKI = 24.576 MHz
–
15
19
mA
fCKI = 36.864 MHz
–
21
26
mA
CKI HIGH-level input voltage
VIHC
0.7 × DVDD
–
–
V
CKI LOW-level input voltage
VILC
–
–
0.3 × DVDD
V
CKI input voltage
VINAC
1.0
–
–
Vp-p
AC coupling
HIGH-level input voltage2
VIH
2.4
–
–
V
LOW-level input voltage2
VIL
–
–
0.5
V
HIGH-level output voltage3
VOH
IOH = −1 mA
DVDD − 0.4
–
–
V
LOW-level output voltage3
VOL
IOL = 1 mA
–
–
0.4
V
CKI HIGH-level input current
IIHC
VIN = DVDD
30
60
120
µA
CKI LOW-level input current
IILC
VIN = 0 V
30
60
120
µA
LOW-level input current4
IIL2
VIN = 0 V
–
5
15
µA
HIGH-level input leakage current5
IIH1
VIN = DVDD
–
–
1.0
µA
LOW-level input leakage current5
IIL1
VIN = 0 V
–
–
1.0
µA
HIGH-level input leakage current4
IIH2
VIN = DVDD
–
–
1.0
µA
1.
2.
3.
4.
5.
No output load, NPC-standard input data pattern.
Pins DI, BCKI, WCKI, CKDVN, IWSL, RSTN, TSTN.
Pin TO.
Pins CKDVN, IWSL, RSTN, TSTN.
Pins DI, BCKI, WCKI.
NIPPON PRECISION CIRCUITS—5
SM5865CM
AC Electrical Characteristics
System clock Input (CKI)
Rating
Parameter
Symbol
Unit
min
typ
max
CKI clock frequency
fCKI
5
–
60
MHz
HIGH-level clock pulsewidth
tCWH
5
–
–
ns
LOW-level clock pulsewidth
tCWL
5
–
–
ns
1/f CKI
VIHC
0.5∗DVDD
VILC
CKI
t CWL
t CWH
Internal System Clock
Rating
Parameter
Internal system clock frequency
Symbol
Condition
fSYS
Unit
min
typ
max
5
–
46
MHz
Internal system clock frequency is the same as the CKI clock frequency when CKDVN = HIGH.
Internal system clock frequency is half the CKI clock frequency when CKDVN = LOW.
Reset Input (RSTN)
Rating
Parameter
Symbol
Condition
At power ON
RSTN LOW-level pulsewidth
tRSTN
After power ON
Unit
min
typ
max
1
–
–
µs
100
–
–
ns
NIPPON PRECISION CIRCUITS—6
SM5865CM
Serial input (BCKI, DI, WCKI)
Rating
Parameter
Symbol
Unit
min
typ
max
BCKI HIGH-level pulsewidth
tBCWH
10
–
–
ns
BCKI LOW-level pulsewidth
tBCWL
10
–
–
ns
BCKI pulse cycle
tBCY
22
–
–
ns
DI setup time
tDS
5
–
–
ns
DI hold time
tDH
5
–
–
ns
WCKI edge to first BCKI rising edge
tWB
10
–
–
ns
Last BCKI rising edge to WCKI edge
tBW
10
–
–
ns
BCKI
1.5V
t BCWH
t BCWL
t BCY
DI
1.5V
t DS
t DH
WCKI
1.5V
t WB
t BW
Group Delay
Rating
Parameter
Group delay1
Symbol
Tgd
Condition
Unit
min
typ
max
–
–
2/fsi
s
1. fsi is the input sampling rate of SM5865CM.
For example, fsi is 384kHz when this LSI is used in combination with an 8-times oversampling digital filter of which input sampling rate is 48kHz.
NIPPON PRECISION CIRCUITS—7
SM5865CM
AC Analog Characteristics
Measurement Conditions
External 8fs digital filter
: NPC SM5847AF
External operational amplifier
: JRC NJM5534D
Supply voltage
SM5865CM : DVDD = AVDDA = AVDDB = 5V,
DVSS = AVSSA = AVSSB = CVSS = 0V
SM5847AF
: + 3.3V
NJM5534D
: ± 15V
Ambient temperature
: 25 °C
Input data of SM5847AF
: 48kHz sampling (fs), 24-bit data
System clock
: 24.576MHz (= 512fs), (64fs noise shaper operation)
Audio analyzer
: Audio Precision System Two (RMS mode)
Measurement filter condition
: THD + N
22HzHPF, 20kHzLPF (FLP-A20K)
: D.R
22HzHPF, 22kHzLPF, A-weight (FIL-AWT)
: S/N
22HzHPF, 22kHzLPF, A-weight (FIL-AWT)
Measurement circuits diagram : See next page.
Analog Characteristics
Rating
Parameter
Output level1
Total harmonic distortion
Symbol
Condition
Unit
min
typ
max
Vout
1 kHz, 0 dB
1.28
1.33
1.38
Vrms
THD + N
1 kHz, 0 dB
–
0.00030
(− 110.5dB)
0.00060
(− 104.4dB)
%
Dynamic range
D.R
1 kHz, −60 dB
111
117
–
dB
Signal-to-noise ratio
S/N
1 kHz, 0/−∞ dB
117
120
–
dB
Gain drift
G.D
–
10
–
ppm/°C
1. Vout is the output level of the first I–V conversion stage.
NIPPON PRECISION CIRCUITS—8
+
GND
C8
0.1µ
GND
12
11
10
9
8
7
6
5
4
3
2
AVSSB
N.C.
VBB
IOUTB
RB
AVDDB
AVDDA
N.C.
VBA
IOUTA
RA
AVSSA
IC1
SM5865CM
CVSS
CKDVN
CKI
DVDD
TO
TSTN
RSTN
IWSL
WCKI
BCKI
DI
DVSS
13
14
15
16
17
18
19
20
21
22
23
24
GND
GND
C6
0.1µ
GND
GND
R7
4.7k
R6
4.7k
VDD
C1
330p
C7
470µ
VDD
+
CKI
VDD
C9
100µ
WCKI
BCKI
DI
GND
1
3
2
6
R1
820
VCC
VEE
VEE
U2
4 1 8 NJM5534D
6
R2
820
U1
4 1 8 NJM5534D
C2
330p 7 5
3
2
7 5
VCC
3
2
6
C5
4.7µ
R4
620
C4
220p
VEE
GND
U3
4 1 8 NJM5534D
7 5
VCC
R3
620
C3
220p
R5
470
GND
J1
OUT 2Vrms
SM5865CM
Measurement circuit
NIPPON PRECISION CIRCUITS—9
SM5865CM
Dynamics Characteristics (under Measurement Conditions in page 8)
+0
+0
-10
-10
-20
-20
-30
-30
-40
-40
-50
-50
-60
-60
d
B
r
-70
-80
d
B
r
A
-90
A
-70
-80
-90
-100
-100
-110
-110
-120
-120
-130
-130
-140
-140
-150
-150
-160
-160
2k
4k
6k
8k
10k
12k
14k
16k
18k
20k
10k
20k
30k
40k
Hz
70k
80k
90k
100k
Figure 2. 0dB input FFT (2)
(1kHz notchfilter 32768point 8average)
-80
+0
-82
-10
-84
-20
-86
-30
-88
-40
-90
-92
-50
-94
-60
-96
-70
-98
d
B
-80
-100
-102
-90
A
60k
Hz
Figure 1. 0dB input FFT (1)
(1kHz notchfilter 32768point 8average)
d
B
r
50k
-104
-100
-106
-110
-108
-120
-110
-112
-130
-114
-140
-116
-150
-118
-120
-160
2k
4k
6k
8k
10k
12k
14k
16k
18k
20k
10
20
50
100
200
Hz
500
1k
2k
5k
10k
20k
Hz
Figure 3. –60dB input FFT (32768point 8average)
Figure 4. THD + N vs. Frequency
1
-70
0.5
-72.5
0.2
-77.5
-75
-80
0.1
-82.5
-85
0.05
-87.5
-90
0.02
%
0.01
d -92.5
B
-95
r
0.005
A -97.5
-100
-102.5
0.002
-105
-107.5
0.001
-110
-112.5
0.0005
-115
-117.5
0.0002
0.0001
-60
-120
-120
-55
-50
-45
-40
-35
-30
dBFS
-25
-20
-15
-10
-5
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBFS
+0
Figure 5. THD + N(%) vs. Amplitude
Figure 6. THD + N (dB) vs. Amplitude
+0
+1
-10
+0.9
+0.8
-20
+0.7
-30
+0.6
+0.5
-40
+0.4
-50
d
B
r
A
+0.3
+0.2
d +0.1
B
+0
r
-60
-70
A
-80
-0.1
-0.2
-0.3
-90
-0.4
-100
-0.5
-0.6
-110
-0.7
-120
-0.8
-0.9
-130
-140
-140
-1
10
-130
-120
-110
-100
-90
-80
-70
dBFS
-60
-50
Figure 7. Linearity
-40
-30
-20
-10
+0
20
50
100
200
500
Hz
1k
2k
5k
10k
20k
Figure 8. Evaluation Board Frequency Response
NIPPON PRECISION CIRCUITS—10
SM5865CM
FUNCTIONAL DESCRIPTION
Analog Outputs
IOUTA, IOUTB
The SM5865CM input data in-phase signal is processed by noise shaper A and 31-level DEM-DAC with current output on differential output A, and input data reverse-phase signal is processed by noise shaper B and 31level DEM-DAC with current output on differential output B. Differential outputs A and B also have separate
in-phase and reverse-phase outputs: A in-phase output and B reverse-phase output are connected internally and
output on IOUTA, and B in-phase output and A reverse-phase output are connected internally and output on
IOUTB.
The IOUTA and IOUTB current outputs are I/V converted by external circuit and then input to a differential
input op-amp to obtain the final analog signal.
RA, RB
Internal resistors are connected between IOUTA and RA pins and between IOUTB and RB pins, which serve
as the op-amp feedback resistors. The feedback resistors have a resistance of 4.7kΩ.
The I/V converter output gain can be adjusted by connecting external resistors in parallel or serial with the
internal resistors. Note, however, that the internal resistance can vary from device to device by ±10%, and if
external resistors are used, the output level changes depending on the difference between each resistor ratio. If
the I/V converter gain is increased, a dynamic range higher even than that given in “Analog Characteristics
(page 8)” can be obtained.
In-phase
output A
Data input
Noise shaper A
RA
IOUTA
31 Level
DEM DAC
Inverse-phase
output A
In-phase
output B
Noise shaper B
RB
IOUTB
31 Level
DEM DAC
Inverse-phase
output B
Figure 9. Analog outputs
NIPPON PRECISION CIRCUITS—11
SM5865CM
VBA, VBB
A 0.5VDD signal is output from VBA, VBB using a resistor divider network. Using these pins allows the use
of the SM5865CM to replace the pin-compatible SM5865BM product.
RA
31 Level
DEM DAC
IOUTA
31 Level
DEM DAC
VBA
SM5865CM
RB
31 Level
DEM DAC
IOUTB
31 Level
DEM DAC
VBB
Figure 10. VBA, VBB
Audio Data Input (DI, BCKI, WCKI, IWSL)
■
Input data format
The audio data is input in MSB-first, 2s-complement, 24-bit/20-bit serial format. The input word bit length is
selected by IWSL, 24-bit when HIGH, and 20-bit when LOW.
■
Jitter-free function
The SM5865CM serial input data from DI synchronize with the word clock (WCKI) and are read into the first
register stage, and those also synchronize with the clock derived from divided system clock and are read into
the next register stage. This word clock and the system clock are always phase compared. When a phase shift
was detected, the comparison result is used to perform input timing adjustment in the system clock. Therefore
this process enable internal calculations not to be affected by generated large jitter on the word clock or changing the sampling rate during inputting data.
System Clock Divider (CKDVN)
The SM5865CM has a built-in clock frequency divider. The divider enables the internal system clock to operate at half the input frequency, for example when the external system clock input frequency is high.
System Reset (RSTN)
The device should be reset in the following cases.
■
■
At power ON
When the system clock CKI stops, or other abnormalities occur.
The device is reset by applying a LOW-level pulse on RSTN.
NIPPON PRECISION CIRCUITS—12
SM5865CM
Theoretical Quantization Noise Reduction
The SM5865CM employs a 3rd-order 31-level quantized noise shaper to widely reduce quantization noise in
the audio band to the high frequency bandwidth. The theoretical quantization noise level at 16fs to 96fs operation is shown in figure 11.
0
10
0 dB sine wave equivalent white noise level
20
30
16fs
40
Quantization noise (dB)
24fs
16-bit, fs quantization noise level
50
32fs
60
48fs
64fs
70
80
96fs
90
100
110
120
130
20-bit, fs quantization noise level
140
150
24-bit, fs quantization noise level
160
170
180
0
0.5
1
1.5
2
2.5
3
3.5
4
Frequency (fs)
Figure 11. Theoretical quantization noise level
NIPPON PRECISION CIRCUITS—13
SM5865CM
Internal Oversampling Operation
The SM5865CM accepts data output from an 8-times or 4-times oversampling digital filter, and oversampled
internally again up to the noise shaper operating rate. The internal oversampling factor is determined automatically from the system clock input frequency and the input sampling frequency. This internal oversampling factor (n) must be an integer satisfying the conditions shown in table 1.
Table 1. Operating conditions
Parameter
fWCKI and fCKI compulsory conditions1
Noise shaper operating frequency
CKDVN = HIGH
CKDVN = LOW
f CKI = f WCKI × 8 × n
f CKI = f WCKI × 16 × n
where n = 1, 2, 3, ...
where n = 1, 2, 3, ...
f CKI
f ns = f WCKI × n = ---------8
f CKI
f ns = f WCKI × n = ---------16
1. fWCKI = word clock frequency, fCKI = input system clock frequency, n = internal oversampling factor
Word clock input
SM5865CM
WCKI
System clock input
CKI
System clock divider select
CKDVN
Figure 12. Clock-related inputs
NIPPON PRECISION CIRCUITS—14
SM5865CM
System Clock Frequencies
Table 2 shows some possible combinations for the circuit configuration shown in figure 13.
fs
fWCKI
Interpolating filter
SM5865CM
(8-times/4-times)
fCKI
CKDVN
Figure 13. Circuit configuration
Table 2. System clock frequencies (CKDVN = HIGH)
fs
System clock frequency1
fCKI
Noise shaper operating
rate
Internal factor
(8fs input)
Internal factor
(4fs input)
16 kHz
6.144 MHz (384fs)
48fs
6
12
16 kHz
8.192 MHz (512fs)
64fs
8
16
16 kHz
12.288 MHz (768fs)
96fs
12
24
32 kHz
6.144 MHz (192fs)
24fs
3
6
32 kHz
8.192 MHz (256fs)
32fs
4
8
32 kHz
12.288 MHz (384fs)
48fs
6
12
32 kHz
16.384 MHz (512fs)
64fs
8
16
32 kHz
24.576 MHz (768fs)
96fs
12
24
44.1 kHz
8.4672 MHz (192fs)
24fs
3
6
44.1 kHz
11.2896 MHz (256fs)
32fs
4
8
44.1 kHz
16.9344 MHz (384fs)
48fs
6
12
44.1 kHz
22.5792 MHz (512fs)
64fs
8
16
44.1 kHz
33.8688 MHz (768fs)
96fs
12
24
48 kHz
9.216 MHz (192fs)
24fs
3
6
48 kHz
12.288 MHz (256fs)
32fs
4
8
48 kHz
18.432 MHz (384fs)
48fs
6
12
48 kHz
24.576 MHz (512fs)
64fs
8
16
48 kHz
36.864 MHz (768fs)
96fs
12
24
88.2 kHz
16.9344 MHz (192fs)
24fs
3
6
88.2 kHz
22.5792 MHz (256fs)
32fs
4
8
88.2 kHz
33.8688 MHz (384fs)
48fs
6
12
88.2 kHz
45.1584 MHz (512fs)
64fs
8
16
96 kHz
18.432 MHz (192fs)
24fs
3
6
96 kHz
24.576 MHz (256fs)
32fs
4
8
96 kHz
36.864 MHz (384fs)
48fs
6
12
176.4 kHz
33.8688 MHz (192fs)
24fs
3
6
176.4 kHz
45.1584 MHz (256fs)
32fs
4
8
192 kHz
36.864 MHz (192fs)
24fs
3
6
1. When CKDVN = LOW, the system clock frequency fCKI is halved, so the values shown are half the input frequency required for the same sampling rate
and internal factors.
NIPPON PRECISION CIRCUITS—15
SM5865CM
TIMING DIAGRAMS
192fs System Clock Input Timing
1 / 8fs
WCKI
CKI
BCKI
(1)20bit *
LSB
MSB
DI
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
BCKI
(2)20bit
LSB
MSB
DI
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
BCKI
(3)24bit
LSB
MSB
DI
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
384fs System Clock Input Timing
1 / 8fs
WCKI
CKI
BCKI
(1)20bit *
LSB
MSB
DI
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
BCKI
(2)20bit
MSB
DI
LSB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
BCKI
(3)24bit
MSB
DI
LSB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
*: Data can be input at any period within the word clock cycle.
NIPPON PRECISION CIRCUITS—16
SM5865CM
256fs System Clock Input Timing
1 / 8fs
WCKI
CKI
BCKI
(1)20bit *
LSB
MSB
DI
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
BCKI
(2)20bit
LSB
MSB
DI
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
BCKI
(3)24bit *
LSB
MSB
DI
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
BCKI
(4)24bit
LSB
MSB
DI
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
512fs System Clock Input Timing
1 / 8fs
WCKI
CKI
BCKI
(1)20bit *
LSB
MSB
DI
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
BCKI
(2)20bit
LSB
MSB
DI
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
BCKI
(3)24bit *
LSB
MSB
DI
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
BCKI
(4)24bit
MSB
DI
LSB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
*: Data can be input at any period within the word clock cycle.
NIPPON PRECISION CIRCUITS—17
SM5865CM
TYPICAL APPLICATIONS
Input Interface Circuit
XTI
DOL
DOR
SM5847AF WCKO
BCKO
CKI
DI
WCKI
BCKI
SM5865CM
CKI
DI
WCKI
BCKI
SM5865CM
NIPPON PRECISION CIRCUITS—18
SM5865CM
Analog Output Circuits
Analog Output Circuit 1
RA
31 Level
DEM DAC
IOUTA
31 Level
DEM DAC
SM5865CM
RB
31 Level
DEM DAC
IOUTB
31 Level
DEM DAC
Analog Output Circuit 2
RA
31 Level
DEM DAC
IOUTA
31 Level
DEM DAC
SM5865CM
RB
31 Level
DEM DAC
IOUTB
31 Level
DEM DAC
Note that the output analog characteristics and other specifications are not guaranteed for particular formats or application circuits.
Note that NPC has no responsibility for patents related to application circuits in these datasheets.
NIPPON PRECISION CIRCUITS—19
SM5865CM
NIPPON PRECISION CIRCUITS INC. reserves the right to make changes to the products described in this data sheet in order to
improve the design or performance and to supply the best possible products. Nippon Precision Circuits Inc. assumes no responsibility for
the use of any circuits shown in this data sheet, conveys no license under any patent or other rights, and makes no claim that the circuits
are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Nippon Precision
Circuits Inc. makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification.
The products described in this data sheet are not intended to use for the apparatus which influence human lives due to the failure or
malfunction of the products. Customers are requested to comply with applicable laws and regulations in effect now and hereinafter,
including compliance with export controls on the distribution or dissemination of the products. Customers shall not export, directly or
indirectly, any products without first obtaining required licenses and approvals from appropriate government agencies.
NIPPON PRECISION CIRCUITS INC.
NIPPON PRECISION CIRCUITS INC.
4-3, Fukuzumi 2-chome
Koto-ku, Tokyo 135-8430, Japan
Telephone: +81-3-3642-6661
Facsimile: +81-3-3642-6698
http://www.npc.co.jp/
Email: [email protected]
NC0019AE 2000.12
NIPPON PRECISION CIRCUITS—20