NPC SM5847AF

SM5847AF
NIPPON PRECISION CIRCUITS INC.
High-fidelity Digital Audio, Multi-function Digital Filter
OVERVIEW
The SM5847AF is a 4/8-times oversampling (interpolation), 2-channel, linear-phase FIR, multi-function digital filter for digital audio reproduction
equipment. It features independent left and rightchannel digital deemphasis filters and soft muting
function.
The internal system clock operates at either 192fs or
256fs selectable speed (where fs is the audio sampling frequency). Plus, the divide-by 1, 2, or 4
counter settings means that external clocks of 768fs/
384fs/192fs (192fs input) and 1024fs/512fs/256fs
(256fs input) are supported.
The input/output interface supports input data in
16/18/20/24-bit words, and output data in
18/20/22/24-bit words in either 4-times or 8-times
oversampling selectable output mode.
The SM5847AF operates from a single 3 to 5 V supply, and is available in 44-pin QFP packages.
FEATURES
■
■
■
■
■
■
■
Left/right-channel (2-channel processing)
4-times/8-times oversampling (interpolation)
• 8-times interpolation filter
- 3-stage linear-phase FIR configuration
1st stage (fs to 2fs): 169-tap
2nd stage (2fs to 4fs): 29-tap
3rd stage (4fs to 8fs): 17-tap
- ≤ ±0.00002 dB passband ripple (0 to
0.4535fs)
- ≥ 117 dB stopband attenuation (0.5465fs to
7.4535fs)
• 4-times interpolation filter
- 2-stage linear-phase FIR configuration
1st stage (fs to 2fs): 169-tap
2nd stage (2fs to 4fs): 29-tap
- ≤ ±0.00002 dB passband ripple (0 to
0.4535fs)
- ≥ 116 dB stopband attenuation (0.5465fs to
3.4535fs)
Digital deemphasis
• IIR filter configuration
• fs = 32kHz, 44.1kHz, 48kHz
• 2-channel independent ON/OFF control
26 × 24-bit parallel multiplier/32-bit accumulator
Overflow limiter
Soft muting
• 2-channel independent ON/OFF control
Input data format
■
■
■
■
■
■
■
■
■
• 2s complement, MSB first
• 3 selectable formats
- LR alternating, 16/18/20/24-bit serial, rightjustified data
- LR alternating, 24-bit serial, left-justified
data
- LR simultaneous, 24-bit serial, left-justified
data
Output data format
• 2s complement, MSB first, LR simultaneous
• 18/20/22/24-bit serial
• BCKO burst (NPC format)
Dither round-off processing
• Dither round-off ON/OFF selectable
25-bit internal data word length
Internal system clock
• 192fs/256fs selectable
• Maximum operating frequency
192fs mode: 37 MHz max (5 V)
20.7 MHz max (3 V)
256fs mode: 27.6 MHz max (5 V)
25 MHz max (3 V)
Jitter-free function
• Jitter-free/Sync mode selectable
Crystal oscillator circuit built-in
3 to 5 V supply
44-pin plastic QFP
CMOS process
ORDERING INFORMATION
D e vice
P ackag e
SM5847AF
44-pin QFP
NIPPON PRECISION CIRCUITS—1
SM5847AF
PINOUT
OMD
1
DOR
2
DOL
3
WCKO
4
BCKO
5
VSS
6
VSSAC
7
VDDAC
8
VDD
9
DG
NC
DEMPR
CKDV2
CKDV1
35
34
DEMPL
37
36
VSS
VDD
38
FSEL1
40
39
MUTEL
FSEL2
41
MUTER
43
42
DITHN
44
(Top View)
RSTN
32
SYNCN
31
OW2N
30
OW1N
29
VDD
28
VSS
27
IW2N/DIR
26
IW1N/DIL
25
INF1N
10
24
CKSLN
11
23
NC
12
13
14
15
16
17
18
19
20
21
22
CKO
VSS
VDD
XTO
XTI
VSS
VDD
LRCI
DI/INF2N
BCKI
NC
SM 5 8 4 7 A F
33
PACKAGE DIMENSIONS
(Unit: mm)
44-pin plastic QFP
+ 0.30
12.80 −
+ 0.30
10.00 −
+ 0.05
0.17 −
0 to 10
10.00 +
− 0.30
4
−
C
+ 0.20
0.60 −
0.
7
0.20 M
0.15
+ 0.20
1.50 − 0.10
0.80
+ 0.05
0.15 −
(1.40)
+ 0.10
0.35 −
+ 0.05
0.17 −
12.80 +
− 0.30
(1.40)
NIPPON PRECISION CIRCUITS—2
SM5847AF
DI/INF2N
LRCI
BCKI
BLOCK DIAGRAM
XTI
IW1N/DIL
XTO
CKO
CKSLN
Input Data
Interface
System
Clock
CKDV1
CKDV2
SYNCN
RSTN
Timing
Controller
Filter and
Attenuation
Arithmetic
Block
OMD
OW1N
OW2N
DG
DOR
Mute
Controller
Output Data
Interface
Block
DOL
MUTER
VSS
VSSAC
Deemphasis
Controller
WCKO
MUTEL
VDD
VDDAC
BCKO
FSEL1
FSEL2
INF1N
DITHN
DEMPL
DEMPR
IW2N/DIR
NIPPON PRECISION CIRCUITS—3
SM5847AF
PIN DESCRIPTION
Number
Name
I/O
1
OMD
Ip 1
Description
2
DOR
O2
Right-channel data output
3
DOL
O2
Left-channel data output
4
W C KO
O2
W ord clock output
5
B C KO
O2
Bit clock output
Output data rate (4fs/8fs) select pin
6
VSS
–
Ground
7
VSSAC
–
Ground
8
V D DAC
–
Supply voltage
9
VDD
–
Supply voltage
10
DG
O2
11
NC
–
12
C KO
O2
13
VSS
–
14
VDD
–
Supply voltage
15
X TO
O
Oscillator output
Deglitched signal output
No internal connection (must be open)
Master clock output
Ground
16
XTI
I
Oscillator input/master clock input
17
VSS
–
Ground
18
VDD
–
Supply voltage
19
LRCI
I1
Input data sample rate (fs) clock input
20
DI/INF2N
I1
Data input/input format select pin 2
21
BCKI
I1
Bit clock input
22
NC
–
No internal connection (must be open)
23
NC
–
No internal connection (must be open)
24
CKSLN
Ip 2
Master clock frequency (192fs/256fs) select pin
25
INF1N
Ip 2
Input format select pin 1
26
IW1N/DIL
Ip 1
Input data word length select pin 1/left-channel data input
27
IW2N/DIR
Ip 1
Input data word length select pin 2/right-channel data input
28
VSS
–
Ground
29
VDD
–
Supply voltage
30
OW1N
Ip 2
Output data word length select pin 1
31
OW2N
Ip 2
Output data word length select pin 2
32
SYNCN
Ip 2
Sync mode select pin
33
RSTN
Ip 1
Reset input
34
C K DV 1
Ip 1
Internal system clock frequency divider set pin 1
35
C K DV 2
Ip 1
Internal system clock frequency divider set pin 2
36
DEMPR
Ip 1
Right-channel deemphasis ON/OFF pin
37
DEMPL
Ip 1
Left-channel deemphasis ON/OFF pin
38
VDD
–
Supply voltage
39
VSS
–
Ground
40
FSEL1
Ip 1
Deemphasis filter sample rate (fs) select pin 1
41
FSEL2
Ip 1
Deemphasis filter sample rate (fs) select pin 2
42
MUTEL
Ip 1
Left-channel mute ON/OFF pin
43
MUTER
Ip 1
Right-channel mute ON/OFF pin
DITHN
Ip 1
Output data dither ON/OFF pin
44
1. Schmitt input, TTL level
2. TTL level
Ip = Pull-up input
NIPPON PRECISION CIRCUITS—4
SM5847AF
SPECIFICATIONS
Absolute Maximum Ratings
VSS = VSSAC = 0 V, VDD = VDDAC
P arameter
Symbol
range 1
Rating
Unit
V D D, V D D A C
−0.3 to 6.5
V
VI
V S S − 0.3 to V D D + 0.3
V
Storage temperature range
T stg
−55 to 125
°C
Pow er dissipation
PD
Supply voltage
Input voltage range
Condition
≤ 70 °C
900
≤ 85 °C
700
mW
1. Supply lines for VDD and V D D A C , and ground lines for VSS and V S S A C , should be connected on the printed circuit board to prevent device breakdown due to potential difference when the pow er is applied.
Recommended Operating Conditions
VSS = VSSAC = 0 V, VDD = VDDAC
P arameter
Supply voltage range 1
Symbol
Rating
Unit
V D D, V D D A C
3.00 to 5.25
V
Ta
−40 to 85
°C
Operating temperature range
1. The minimum required operating voltage and consequent operating temperature vary with the maximum operating frequency and sampling mode
selected, as shown in the following table.
VSS = VSSAC = 0 V, VDD = VDDAC
Internal system clock
Sampling frequency
fs (kHz)
M i n i mu m s u p p ly voltag e
V D D , V D D A C (V)
Operating temperature
T a (°C)
37
4.75 (5.0 − 5%)
−40 to 70
256fs
Not guaranteed
Not guaranteed
Not guaranteed
192fs
20.7
3.00 (3.3 − 10%)
256fs
27.6
4.50 (5.0 − 10%)
192fs
18.5
3.00 (3.3 − 10%)
256fs
25
3.00 (3.3 − 10%)
192fs
10.6
3.00 (3.3 − 10%)
256fs
14.2
3.00 (3.3 − 10%)
Mode1
M a x i m um operating
frequency (MHz)
192fs
192
108 2
96
55.2 3
−40 to 85
1. Mode with internal frequency divider ratio set to 1 (CKDV 1 = C K DV2 = LOW).
2. 96 kHz + 12.5% variable pitch
3. 48 kHz + 15% variable pitch
NIPPON PRECISION CIRCUITS—5
SM5847AF
DC Electrical Characteristics
VDD = VDDAC = 3.00 to 5.25 V, VSS = VSSAC = 0 V, Ta = −40 to 85 °C
Rating
P arameter
HIGH-level input voltage 1
HIGH-level input
voltage 2 ,4
HIGH-level input voltage 3
L O W -level input voltage 1
L O W -level input voltage 2,4
L O W -level input voltage 3
Input leakage current 1,2
Symbol
Condition
Unit
min
typ
max
V IH1
0.7V D D
–
–
V
V IH2
2.0
–
–
V
V D D = V D D A C = 4.75 to 5.25 V
2.4
–
–
V D D = V D D A C = 3.00 to 4.75 V
2.0
–
–
V D D = V D D A C = 4.75 to 5.25 V
–
–
0.3V D D
V D D = V D D A C = 3.00 to 4.75 V
–
–
0.2V D D
V D D = V D D A C = 4.75 to 5.25 V
–
–
0.8
V D D = V D D A C = 3.00 to 4.75 V
–
–
0.2V D D
V D D = V D D A C = 4.75 to 5.25 V
–
–
0.8
V D D = V D D A C = 3.00 to 4.75 V
–
–
0.2V D D
V IH3
V IL1
V IL2
V IL3
V
V
V
V
IIL1
V IN = 0 to 5.25 V
−10
–
10
µA
IIL2
V IN = 0 V
−10
−50
−120
µA
HIGH-level output
voltage 5
VOH
IO H = −4 m A
2.4
–
–
V
L O W -level output
voltage 5
VOL
IO L = 4 mA
–
–
0.4
V
Input
1.
2.
3.
4.
5.
current 3,4
Pin XTI
Pins LRCI, DI/INF2N, BCKI
Pins IW1N/DIL, IW2N/DIR
P i n s O M D, CKSLN, INF1N, OW 1 N , OW 2 N , S Y N C N , R S T N , C K DV1, CKDV2, DEMPR, DEMPL, FSEL1, FSEL2, MUTEL, MUTER, DITHN
Pins DOR, DOL, W C K O , BCKO , DG, CKO
VDD = VDDAC = 4.75 to 5.25 V, VSS = VSSAC = 0 V, Ta = −40 to 85 °C, XTI = external input, no output load
Rating
P arameter
Current consumption
Symbol
Condition
Unit
min
typ
max
ID D 1
192fs, XTI = 27 ns (37 MHz),
fs = 192 kHz,Ta = −40 to 70 °C
–
–
166
mA
ID D 2
256fs, XTI = 40 ns (25 MHz),
fs = 96 k H z
–
–
115
mA
ID D 3
384fs, XTI = 27 ns (37 MHz),
fs = 96 kHz, estimated value
–
–
105
mA
ID D 4
192fs, XTI = 54 ns (18.5 MHz),
fs = 96 kHz, estimated value
–
–
95
mA
ID D 5
384fs, XTI = 54 ns (18.5 MHz),
fs = 48 kHz, estimated value
–
–
65
mA
VDD = VDDAC = 3.00 to 3.60 V, VSS = VSSAC = 0 V, Ta = −40 to 85 °C, XTI = external input, no output load
Rating
P arameter
Symbol
Condition
Unit
min
typ
max
ID D 6
256fs, XTI = 81 ns (12.3 MHz),
fs = 48 kHz, estimated value
–
–
27
mA
ID D 7
384fs, XTI = 54 ns (18.5 MHz),
fs = 48 kHz, estimated value
–
–
28
mA
Current consumption
NIPPON PRECISION CIRCUITS—6
SM5847AF
AC Electrical Characteristics
Crystal oscillator (XTI, XTO)
VDD = VDDAC = 3.00 to 5.25 V, VSS = VSSAC = 0 V, Ta = −40 to 85 °C
Rating
P arameter
Oscillator frequency 1
Symbol
Condition
Unit
min
typ
max
–
–
50
fO S C
MHz
1. External circuit components should be matched for the crystal oscillator element used.
External clock input (XTI)
VDD = VDDAC = 3.00 to 5.25 V, VSS = VSSAC = 0 V, Ta = −40 to 85 °C
Rating
P arameter
Master clock frequency
Symbol
Condition
fXTI
Master clock duty
1/2V D D thresholds
Unit
min
typ
max
–
–
60
MHz
40
–
60
%
Internal system clock
The crystal oscillator frequency or external clock input master clock frequency ratings are described in the preceding tables, but it is the internal system clock frequency rating, set by the internal frequency divider
(CKDV1, CKDV2), that must be satisfied. The master clock frequency is a multiple of the sampling frequency
fs.
CKDV1 = CKDV2 = LOW (internal system clock frequency = XTI input frequency),
VSS = VSSAC = 0 V, Ta = −40 to 85 °C
Rating
P arameter
Symbol
Condition
Unit
min
typ
max
V D D = V D D A C = 4.50 to 5.25 V
0.256
–
27.6
V D D = V D D A C = 3.00 to 5.25 V
0.256
–
25
V D D = V D D A C = 4.75 to 5.25 V,
T a = −40 to 70 °C
0.384
–
37
V D D = V D D A C = 3.00 to 5.25 V
0.384
–
20.7
256fs (CKSLN = LOW , CKDV1 = LOW , CKDV2 = LOW )
System clock frequency
fS Y S 1
MHz
192fs (CKSLN = HIGH, CKDV1 = LOW , CKDV2 = LOW )
System clock frequency
fS Y S 2
MHz
NIPPON PRECISION CIRCUITS—7
SM5847AF
Serial input timing (BCKI, LRCI, DI/INF2N, IW1N/DIL, IW2N/DIR)
VSS = VSSAC = 0 V, Ta = −40 to 85 °C
Rating
P arameter
BCKI pulse cycle
Condition
tI B C Y
BCKI HIGH-level pulsewidth
B C K I L OW -level pulsewidth
DI, DIL, DIR setup time
DI, DIL, DIR hold time
Last BCKI rising edge to LRCI edge
LRCI edge to first BCKI rising edge
1. CKSLN = HIGH
2. C K S L N = L OW
CKSLN = HIGH
3. C K S L N = L OW
Symbol
tB C W H
tB C W L
tD S
tD H
tB L
tL B
Unit
min
typ
max
Note 1
55
–
–
Note 2
80
–
–
Note 3
100
–
–
Note 1
25
–
–
Note 2
35
–
–
Note 3
45
–
–
Note 1
25
–
–
Note 2
35
–
–
Note 3
45
–
–
Note 1
10
–
–
Note 2
20
–
–
Note 3
30
–
–
Note 1
10
–
–
Note 2
20
–
–
Note 3
30
–
–
Note 1
10
–
–
Note 2
20
–
–
Note 3
30
–
–
Note 1
10
–
–
Note 2
20
–
–
Note 3
30
–
–
ns
ns
ns
ns
ns
ns
ns
(192fs), V D D = V D D A C = 4.75 to 5.25 V, T a = −40 to 70 °C
(256fs), V D D = V D D A C = 4.50 to 5.25 V
(192fs), V D D = V D D A C = 3.00 to 4.75 V
(256fs), V D D = V D D A C = 3.00 to 4.50 V
tIBCY
1.5V
BCKI
tBCWH
tBCWL
DI
DIL
DIR
1.5V
tDS
tDH
tBL
LRCI
tLB
1.5V
NIPPON PRECISION CIRCUITS—8
SM5847AF
Reset timing (RSTN)
VDD = VDDAC = 3.00 to 5.25 V, VSS = VSSAC = 0 V, Ta = −40 to 85 °C
Rating
P arameter
R S T N L OW -level reset pulsewidth
Symbol
Condition
tR S T
Unit
min1
typ
max
2t M C K
–
–
ns
1. tM C K is equal to 1/f XTI or 1/f O S C . For example, tR S T = 54 ns when f XTI = 37 MHz.
1.5V
RSTN
tRST
Output timing (CKO, BCKO, WCKO, DOL, DOR, DG)
VDD = VDDAC = 4.75 to 5.25 V, VSS = VSSAC = 0 V, Ta = −40 to 70 °C, CL = 50 pF
Rating
P arameter
XTI falling edge to CKO falling edge delay
Symbol
tX TO
B C K O falling edge to W C K O , DOL, DOR,
DG delay
tB D O
B C K O rising edge to W C K O falling edge
tW O H
W C K O falling edge to BCKO rising edge
tW O S
B C K O period
tO B C Y
B C K O HIGH-level pulsewidth
tO B C H
B C K O L OW -level pulsewidth
tO B C L
DOL, DOR setup time
tO D S
DOL, DOR hold time
tO D H
B C K O rising edge to W C K O falling edge
tW O H
W C K O falling edge to BCKO rising edge
tW O S
B C K O period
tO B C Y
B C K O HIGH-level pulsewidth
tO B C H
B C K O L OW -level pulsewidth
tO B C L
DOL, DOR setup time
tO D S
DOL, DOR hold time
tO D H
Condition
V D D = V D D A C = 3.00 to 5.25 V,
T a = −40 to 85 °C
Output mode: 8fs
OMD = HIGH (fs = 192 kHz)
External clock input:
XTI = 27 ns (37 MHz),
C K S L N = HIGH (192fs)
Divider ratio: 1
C K DV 1 = C K DV2 = LOW
Output data length: 24 bits
O W 1 N = OW 2 N = L OW
Output mode: 4fs
O M D = L OW (fs = 192 kHz)
External clock input:
XTI = 27 ns (37 MHz),
C K S L N = HIGH (192fs)
Divider ratio: 1
C K DV 1 = C K DV2 = LOW
Output data length: 24 bits
O W 1 N = OW 2 N = L OW
Unit
min
typ
max
4
–
9
ns
4
–
11
ns
−4
–
2
ns
8
–
–
ns
8
–
–
ns
27
–
–
ns
7
–
–
ns
7
–
–
ns
7
–
–
ns
7
–
–
ns
17
–
–
ns
17
–
–
ns
54
–
–
ns
18
–
–
ns
18
–
–
ns
18
–
–
ns
18
–
–
ns
NIPPON PRECISION CIRCUITS—9
SM5847AF
VDD = VDDAC = 4.50 to 5.25 V, VSS = VSSAC = 0 V, Ta = −40 to 85 °C, CL = 50 pF
Rating
P arameter
Symbol
B C K O HIGH-level pulsewidth
tO B C H
B C K O L OW -level pulsewidth
tO B C L
DOL, DOR setup time
tO D S
DOL, DOR hold time
tO D H
B C K O HIGH-level pulsewidth
tO B C H
B C K O L OW -level pulsewidth
tO B C L
DOL, DOR setup time
tO D S
DOL, DOR hold time
tO D H
Condition
Unit
min
typ
max
External clock input: XTI = 36 ns
(27.6 MHz), CKSLN = L O W
(256fs), fs = 108 k H z
Divider ratio: 1
C K DV 1 = C K DV2 = LOW
Output mode: 8fs, OMD = H I G H
10
–
–
ns
10
–
–
ns
11
–
–
ns
11
–
–
ns
External clock input: XTI = 36 ns
(27.6 MHz), CKSLN = L O W
(256fs), fs = 108 k H z
Divider ratio: 1
C K DV 1 = C K DV2 = LOW
Output mode: 4fs, OMD = L O W
26
–
–
ns
26
–
–
ns
27
–
–
ns
27
–
–
ns
1.5V
XTI
CKO
1.5V
tXTO
BCKO
1.5V
WCKO
DOL
DOR
DG
1.5V
tBDO
WCKO
1.5V
tWOH
BCKO
tWOS
1.5V
tOBCL
tOBCH
tOBCY
DOL
DOR
1.5V
tODS
tODH
NIPPON PRECISION CIRCUITS—10
SM5847AF
Filter Characteristics
8-times interpolation filter
P arameter
Rating
P assband
0 to 0.4535fs
Stopband
0.5465fs to 7.4535fs
≤ ±0.00002 dB
P assband ripple
Stopband attenuation
≥ 117 dB
Group delay
Constant
8fs filter response with deemphasis OFF
Attenuation (dB)
0
20
40
60
80
100
120
140
0.0
1.0
2.0
4.0
3.0
5.0
6.0
7.0
8.0
Frequency (× fs)
Attenuation (dB)
8fs filter band transition response with deemphasis OFF
-0.00008
-0.00004
0.00000
0.00004
0.00008
0.000
0.125
0.250
0.375
0.500
Frequency (× fs)
8fs filter passband response with deemphasis OFF
0
Attenuation (dB)
20
40
60
80
100
120
140
0.440
0.465
0.490
0.515
0.540
0.565
0.590
0.615
0.640
Frequency (× fs)
NIPPON PRECISION CIRCUITS—11
SM5847AF
4-times interpolation filter
P arameter
Rating
P assband
0 to 0.4535fs
Stopband
0.5465fs to 3.4535fs
≤ ±0.00002 dB
P assband ripple
Stopband attenuation
≥ 116 dB
Group delay
Constant
4fs filter response with deemphasis OFF
Attenuation (dB)
0
20
40
60
80
100
120
140
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
Frequency (× fs)
Attenuation (dB)
4fs filter band transition response with deemphasis OFF
-0.00008
-0.00004
0.00000
0.00004
0.00008
0.000
0.125
0.250
0.375
0.500
Frequency (× fs)
4fs filter passband response with deemphasis OFF
0
Attenuation (dB)
20
40
60
80
100
120
140
0.440
0.465
0.490
0.515
0.540
0.565
0.590
0.615
0.640
Frequency (× fs)
NIPPON PRECISION CIRCUITS—12
SM5847AF
Deemphasis filter
Sampling frequency (fs)
P arameter
P assband bandwidth (kHz)
32 kHz
44.1 kHz
48 kHz
0 to 14.5
0 to 20.0
0 to 21.7
≤ ±0.01 dB
Attenuation
D e viation from ideal characteristic
P h a s e, θ
0 to 1.5°
0
0
32kHz
Attenuation (dB)
2
Phase
-20
44.1kHz
48kHz
4
Attenuation
6
-40
-60
Phase (degrees)
Passband response with deemphasis ON
8
32kHz
44.1kHz
48kHz
10
10
20
50
100
200
500
1k
2k
5k
10k
20k
[Hz]
Frequency (Hz)
NIPPON PRECISION CIRCUITS—13
SM5847AF
FUNCTIONAL DESCRIPTION
Oversampling (Interpolation)
The interpolation arithmetic block is comprised of 3
cascaded, 2-times FIR interpolation filters, as shown
in figure 1. The input signal is sampled at rate fs, and
then either 4-times or 8-times oversampling data is
output. Sampling noise in the 0.5465fs to 3.4535fs
(4fs output) or 0.5465fs to 7.4535fs (8fs output)
region is removed.
Input
fs
2-times interpolator
1st FIR
169-tap
2fs
2-times interpolator
2nd FIR 29-tap
4fs
Deemphasis IIR filter
Deemphasis OFF
Deemphasis ON
4fs
Soft mute
4fs
2 -times interpolator
3rd FIR 17-tap
8fs
4fs
Output
Figure 1. Arithmetic operating block
NIPPON PRECISION CIRCUITS—14
SM5847AF
Digital Deemphasis (DEMPL, DEMPR, FSEL1, FSEL2)
Most deemphasis filters are constructed using analog
circuit techniques. Here, an IIR filter is employed to
faithfully reproduce the gain and phase characteristics of standard analog deemphasis filters, corresponding
to
analog
50µs/15µs
frequency
characteristics. Three sets of filter coefficients for the
three fs = 32/44.1/48 kHz sampling frequencies are
supported. Deemphasis for other values of fs are not
supported.
Deemphasis ON/OFF (DEMPL, DEMPR)
Filter coefficient select (FSEL1, FSEL2)
Table 2. Deemphasis filter coefficient select
FSEL1
FSEL2
Sampling frequency (fs)
LOW
LOW
44.1 kHz
LOW
HIGH
48 kHz
HIGH
LOW
Prohibited mode
HIGH
HIGH
32 kHz
Deemphasis for the left and right-channel can be
controlled independently.
Table 1. Deemphasis control
DEMPL
DEMPR
Deemphasis
LOW
×
Left-channel OFF
HIGH
×
Left-channel ON
×
LOW
Right-channel OFF
×
HIGH
Right-channel ON
Soft Muting (MUTEL, MUTER)
The muting function controls the muting of left and
right-channel independently. Input data continues to
be accepted even when mute is operating.
Mute ON/OFF
When MUTEL (MUTER) goes HIGH, the attenuation changes smoothly from 0 to −∞ dB. Similarly,
when MUTEL (MUTER) goes LOW, muting is
released and the attenuation changes smoothly from
−∞ to 0 dB. This operation is termed soft muting.
Mute operation at reset
When RSTN goes LOW, the DOL and DOR outputs
are immediately muted to −∞ dB. When RSTN goes
HIGH, reset is released and the outputs are immediately set to 0 dB attenuation.
Note that even when either MUTEL or MUTER or
both are HIGH, the reset operation takes precedence.
Soft muting takes an interval of approximately
512/fs, or about 11.6 ms when fs = 44.1 kHz.
Table 3. Mute control
MUTEL
MUTER
Soft muting
LOW
×
Left-channel OFF
HIGH
×
Left-channel ON
×
LOW
Right-channel OFF
×
HIGH
Right-channel ON
NIPPON PRECISION CIRCUITS—15
SM5847AF
Analog Output Click Noise
Under the following conditions, a click noise may be
output from the DAC (digital-to-analog converter)
connected to the SM5847AF.
■
■
■
When a system reset on RSTN occurs
When the internal system clock mode, set by
CKSLN, CKDV1, and CKDV2, is switched
When the deemphasis mode, set by DEMPL,
DEMPR, FSEL1, and FSEL2, is switched
DI/INF2N,
IW1N/DIL, IW2N/DIR
MUTEL/MUTER
■
■
When the audio data input mode, set by INF1N,
DI/INF2N, IW1N/DIL, and IW2N/DIR, is
switched
When the SYNCN jitter-free mode switch timing
exceeds the internal timing delay limit
An external muting circuit connected to the analog
output may be required to eliminate this noise.
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
Normal operation
H
L
H
soft mute
RSTN
512/fs
L
soft mute
H
512/fs
L
H
reset
L
reset
0dB
Gain
−∞
+FS
External DAC
analog output
(full scale signal)
zero
-FS
click noise
FS: full scale
Figure 2. Soft muting/reset operation
NIPPON PRECISION CIRCUITS—16
SM5847AF
Internal System Clock (XTI, XTO, CKO, CKSLN, CKDV1, CKDV2)
The SM5847AF supports two system clock frequencies selected by CKSLN, 192fs and 256fs, where fs
is the sampling frequency.
The master clock can be provided either by a crystal
oscillator connected between XTI and XTO, or by an
external master clock input on XTI. Note that the
feedback resistor required by the oscillator option is
not built-in. External components should be selected
to match the crystal oscillator element. Note also that
XTO must be left open (floating) for the external
master clock input option.
Note that even though it is necessary that the master
clock and LRCI clock (sampling frequency fs) be in
sync, it is not necessary that they be exactly in-phase
(see jitter-free mode description).
Table 4. Internal system clock select
CKSLN
System clock
LOW
256fs
HIGH
192fs
Table 5. System clock frequency divider ratio select
C K DV1
C K DV2
Divider
ratio
Master clock
LOW
LOW
1
192fs, 256fs
LOW
HIGH
–
Prohibited mode
HIGH
LOW
4
768fs, 1024fs
HIGH
HIGH
2
384fs,512fs
The SM5847AF features independent divide-by 1, 2,
or 4counter, selected by CKDV1 and CKDV2. This
provides the 192fs or 256fs system clock with the
necessary divider ratios to support master clocks
with frequencies of 768fs, 384fs, 192fs, 1024fs,
512fs or 256fs.
Normal sampling frequencies 32 kHz, 44.1 kHz,
48 kHz, 88.2 kHz, 96 kHz, 176.4 kHz and 192 kHz
are supported. However, some combinations of sampling frequency and master clock frequency are not
supported, as follows.
■
■
■
768fs and 1024fs at 88.2 and 96 kHz
768fs, 384fs, 1024fs, 512fs, and 256fs at
176.4 kHz
768fs, 384fs, 1024fs, 512fs and 256fs at 192 kHz
Divider
16
15
12
XTI
R1 XTO CKO
XTAL
C1
SM5847AF
Master Clock
Buffer output
C2
Figure 3. Crystal oscillator connection
Note also that the internal crystal oscillator circuit
cannot operate at frequencies ≥ 50 MHz. The master
clock input on XTI is output on CKO.
Divider
Master clock stop operation
The master clock is input after power is applied.
But if, after the XTI and LRCI clocks are input and
power-ON reset occurs with all-zero input audio
data, the master clock input on XTI is held either
HIGH or LOW level, operation effectively stops.
Note also that a reset signal is not accepted when the
master clock and LRCI clock stop.
16
XTI
External Clock
15
XTO
XTO : open
12
SM5847AF
CKO
Master Clock
Buffer output
Figure 4. External clock connection
NIPPON PRECISION CIRCUITS—17
SM5847AF
Table 6. Master clock frequency example
XTI system clock frequency (MHz)
CKSLN = HIGH (192fs)
Sampling
frequency
fs (kHz)
C K S L N = L OW (256fs)
C K D V1
C K D V2
C K D V1
C K D V2
C K D V1
C K D V2
C K D V1
C K D V2
C K D V1
C K D V2
C K D V1
C K D V2
L OW
L OW
HIGH
HIGH
HIGH
L OW
L OW
L OW
HIGH
HIGH
HIGH
L OW
192fs
384fs
768fs
256fs
512fs
1024fs
32
6.144
12.288
24.576
8.192
16.384
32.768
44.1
8.4627
16.9344
33.8688
11.2896
22.5792
45.1584
48
9.216
18.432
36.864
12.288
24.576
49.152
guaranteed 1
22.5792
45.1584
Not guaranteed
88.2
16.9344
33.8688
Not
96
18.432
36.864
Not guaranteed
24.576
49.152
Not guaranteed
176.4
33.8688
Not guaranteed
Not guaranteed
Not guaranteed
Not guaranteed
Not guaranteed
192
36.864
Not guaranteed
Not guaranteed 1
Not guaranteed
Not guaranteed
Not guaranteed
1. Refer to the AC characteristics system clock ratings.
System Reset (RSTN)
During normal device operation, reset signals are not
required. However, the SM5847AF must be reset
under the following conditions.
When RSTN is LOW, the DOL and DOR outputs are
tied LOW, muting the output signal to an attenuation
level of −∞.
At power-ON
When the LRCI clock and internal operation timing need to be resynchronized in jitter-free mode.
After the LRCI or XTI clocks, or both, stop and
are subsequently started.
After system reset, when RSTN goes HIGH, the
arithmetic and output timing counters are reset on
the first LRCI start edge, assuming that the XTI and
LRCI input clocks have already stabilized. The LRCI
start edge is determined by the state of INF1N and
INF2N. When INF1N is LOW or when both INF1N
and INF2N are HIGH, the start edge is the rising
edge. When INF1N is HIGH and INF2N is LOW, the
start edge is the falling edge.
■
■
■
The system is reset by applying a LOW-level pulse
on RSTN.
RSTN
RSTN=L
LRCI
Internal reset
OMD=H
8fs
WCKO
OMD=L
4fs
DOL/DOR
zero
Figure 5. System reset timing and output muting (INF1N = LOW or INF1N = INF2N = HIGH)
NIPPON PRECISION CIRCUITS—18
SM5847AF
Audio Data Input (INF1N, DI/INF2N, IW1N/DIL, IW2N/DIR, BCKI, LRCI)
The input data format and input pin functions are
selected by the state of INF1N and INF2N. When
INF1N is LOW, the inputs are left and right-channel
data inputs, and when INF1N is HIGH, the
DI/INF2N input is an input format select pin, and
DIL and DIR are the audio data inputs.
Input data format select
Table 7. Input settings and functions
Pin function selection
INF1N
DI/INF2N
Input format
LOW
−
LOW
−
HIGH
LOW
LR alternating, left-justified data
HIGH
HIGH
LR simultaneous 2 , left-justified data
DI/INF2N
IW1N/DIL
IW2N/DIR
DI
IW1N
IW2N
INF2N
DIL
DIR
LR alternating 1 , right-justified data
1. Alternating left-channel and right-channel data input on a single input DI.
2. S i multaneous left-channel and right-channel data input on two inputs, DIL and DIR, respectively.
Input data word length
The input data word length is selected by the state of
IW1N and IW2N when INF1N is LOW. 20-bit is
selected when INF1N is HIGH.
Table 8. Input data word length select
INF1N
IW1N/DIL
IW2N/DIR
Input word length
LOW
LOW
24 bits
HIGH
LOW
20 bits
LOW
HIGH
18 bits
HIGH
HIGH
16 bits
–
–
24 bits
LOW
HIGH
Jitter-free Function (SYNCN)
The arithmetic circuit and output control timing is
derived from the system clock, and is therefore independent of the input LRCI and BCKI clocks.
Accordingly, any jitter in the data input clock (LRCI
and BCKI) does not cause jitter in the output.
Generally, the internal timing is synchronized to the
LRCI input timing after a system reset release, when
RSTN goes from LOW to HIGH, on the first LRCI
clock start edge. If the input timing and LRCI start
edge timing subsequently drift, the input timing is
automatically resynchronized when the timing error
exceeds a certain value. There are 2 timing error values at which resynchronization occurs, selected by
the state of SYNCN.
resynchronized and all functions continue to operate
normally.
Sync mode (SYNCN = LOW)
When SYNCN is LOW, the timing error value is ±1
× (XTI master clock period), which is a much
smaller timing error tolerance than in jitter-free
mode. In this mode, the internal timing is guaranteed
to follow the LRCI clock timing within this tolerance, making this mode useful for systems constructed from a multiple number of SM5847AF
devices.
Jitter-free mode (SYNCN = HIGH)
When SYNCN is HIGH, the timing error value is
±3/8 × (LRCI clock period). When the difference
between the input timing and LRCI start edge position do not exceed this value, internal timing is not
NIPPON PRECISION CIRCUITS—19
SM5847AF
Audio Data Output (DOL, DOR, BCKO, WCKO, DG, OW1N, OW2N, OMD, DITHN)
Output data format
Output timing
The output data is in serial, simultaneous left and
right-channel, 2s complement, MSB first, BCKO
burst (NPC format) format. Left-channel data is output on DOL, and right-channel data is output on
DOR.
The output timing is dependent on the CKSLN level
and output data word length.
Output data word length
The output data word length is selected by the state
of OW1N and OW2N.
When CKSLN is LOW, the output timing does not
change with the output data word length. However,
when CKSLN is HIGH, the DOL and DOR output
timing for 24-bit output data length (OW1N =
OW2N = LOW) start 1 clock cycle earlier than for
18, 20, or 22-bit output data length.
Table 9. Output data word length select
OW1N
OW2N
Output word length
LOW
LOW
24 bits
HIGH
LOW
22 bits
LOW
HIGH
20 bits
HIGH
HIGH
18 bits
Table 10. Output timing
P arameter
Symbol
Bit clock rate
TB
Data word length
TDW
CKSLN
OMD = HIGH
O M D = L OW
HIGH
1/192fs
1/96fs
LOW
1/256fs
1/128fs
HIGH
24t S Y S
48t S Y S
LOW
32t S Y S
64t S Y S
Output mode
Output dither processing
The output mode, either 4fs oversampling or 8fs
oversampling, is selected by the level on OMD,
where fs is the input sampling rate.
OMD
Output mode
LOW
4fs
The output data word length is set by OW1N and
OW2N, whereas the SM5847AF performs all internal calculations in 25-bit words. As a consequence,
dither processing is provided to round-off errors. The
SM5847AF uses triangular dither processing (triangular probability density function or TPDF) and can
be turned ON or OFF. Simple round-off processing
occurs when dither is OFF (DITHN = HIGH).
HIGH
8fs
Table 12. Dither select
Table 11. Output mode select
DITHN
Dither
LOW
ON
HIGH
OFF
NIPPON PRECISION CIRCUITS—20
SM5847AF
Group Delay
The data input to data output group delay is the delay
which occurs due to the digital filter calculations. It
is the time between the serial input data is completely read in (at rate fs) until the serial data is output (at rate 8fs or 4fs, depending on the mode
selected).
tINPUT represents the LRCI clock rising edge after
the serial input data has been read in at rate fs.
tOUTPUT represents the WCKO clock falling edge at
the start of serial data output at rate 8fs or 4fs.
Table 13. Group delay
Mode
CKSLN
G roup delay
t O U T P U T − tI N P U T
SYNCN
LOW
After reset, or sync mode
HIGH
Jitter-free mode
LOW
After reset, or sync mode
HIGH
Jitter-free mode
Unit
48.625/fs
L O W (256fs)
48.25/fs − 49.0/fs
sec
48.75/fs
HIGH (192fs)
48.375/fs − 49.125/fs
1/fs
LRCI
serial data input (DI/INF2N,
IW1N/DIL, IW2N/DIR)
48/fs
t INPUT
LRCI
1/fs
WCKO
8fs
OMD=H
t OUTPUT
CKSLN=L
(256fs)
serial data output (DOL,DOR)
WCKO
4fs
OMD=L
t OUTPUT
serial data output (DOL,DOR)
WCKO
8fs
OMD=H
CKSLN=H
(192fs)
t OUTPUT
serial data output (DOL,DOR)
WCKO
4fs
OMD=L
t OUTPUT
serial data output (DOL,DOR)
Figure 6. Group delay timing (SYNCN = LOW)
NIPPON PRECISION CIRCUITS—21
SM5847AF
TIMING DIAGRAMS
Input Timing Examples
1 / fs
Lch
LRCI
*1
Rch
1
16
MSB
LSB
1
16
MSB
LSB
BCKI
16bit
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Don't care
Don't care
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
DI/
INF2N
IW1N/DIL = H, IW2N/DIR = H
1
18
MSB
LSB
1
18
MSB
LSB
BCKI
18bit
Don't care
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Don't care
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
DI/
INF2N
IW1N/DIL = L, IW2N/DIR = H
1
20
MSB
LSB
1
20
MSB
LSB
BCKI
20bit
Don't care
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Don't care
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
DI/
INF2N
1
24
MSB
LSB
IW1N/DIL = H, IW2N/DIR = L
1
24
MSB
LSB
BCKI
24bit
Don't care
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Don't care
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
DI/
INF2N
IW1N/DIL = L, IW2N/DIR = L
*1: Optional BCKI clock cycles
Figure 7. LR alternating, right-justified data, 2s complement, MSB first, INF1N = L
NIPPON PRECISION CIRCUITS—22
SM5847AF
1 / fs
Lch
LRCI
Rch
24
1
*1
24
1
BCKI
MSB
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
IW1N/DIL
LSB
Don't care
Don't care
MSB
IW2N/DIR
LSB
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Don't care
Don't care
*1: There must be a minimum of 24 BCKI clock cycles. Data input after the LSB is ignored.
Figure 8. LR alternating, left-justified data, 2s complement, MSB first, INF1N = H, DI/INF2N = L, 24-bit
1 / fs
LRCI
1
24
*1
BCKI
MSB
MSB
Don't care
LSB
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
IW2N/DIR
LSB
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
IW1N/DIL
Don't care
*1: There must be a minimum of 24 BCKI clock cycles. Data input after the LSB is ignored.
Figure 9. LR simultaneous, left-justified data, 2s complement, MSB first, INF1N = H, DI/INF2N = H, 24-bit
NIPPON PRECISION CIRCUITS—23
SM5847AF
Output Timing Examples
1 / 8fs
WCKO
1
18
MSB
LSB
BCKO
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
18bit
OW1N = H
OW2N = H
DOL
MSB
LSB
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
DOR
1
20
BCKO
LSB
MSB
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
20bit
OW1N = L
OW2N = H
DOL
LSB
MSB
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
DOR
1
22
MSB
LSB
BCKO
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
22bit
OW1N = H
OW2N = L
DOL
MSB
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
DOR
LSB
1
24
BCKO
MSB
DOL
LSB
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
24bit
OW1N = L
OW2N = L
MSB
LSB
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
DOR
DG
192fs
internal
system clock
1
10
22
12
24
TB
TDW
Figure 10. 2s complement, MSB first, CKSLN = H, OMD = H
NIPPON PRECISION CIRCUITS—24
SM5847AF
1 / 4fs
WCKO
1
18
MSB
LSB
BCKO
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
18bit
OW1N = H
OW2N = H
DOL
MSB
LSB
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
DOR
1
20
BCKO
LSB
MSB
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
20bit
OW1N = L
OW2N = H
DOL
LSB
MSB
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
DOR
1
22
MSB
LSB
BCKO
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
22bit
OW1N = H
OW2N = L
DOL
MSB
LSB
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
DOR
1
24
BCKO
MSB
DOL
LSB
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
24bit
OW1N = L
OW2N = L
MSB
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
DOR
LSB
DG
192fs
internal
system clock
20
2
24
44
48
TB
TDW
Figure 11. 2s complement, MSB first, CKSLN = H, OMD = L
NIPPON PRECISION CIRCUITS—25
SM5847AF
1 / 8fs
WCKO
1
18
MSB
LSB
BCKO
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
18bit
OW1N = H
OW2N = H
DOL
MSB
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
DOR
LSB
1
20
BCKO
LSB
MSB
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
20bit
OW1N = L
OW2N = H
DOL
LSB
MSB
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
DOR
1
22
MSB
LSB
BCKO
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
22bit
OW1N = H
OW2N = L
DOL
MSB
LSB
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
DOR
1
24
MSB
LSB
BCKO
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
24bit
OW1N = L
OW2N = L
DOL
MSB
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
DOR
LSB
DG
256fs
internal
system clock
1
14
16
25
30
32
TB
TDW
Figure 12. 2s complement, MSB first, CKSLN = L, OMD = H
NIPPON PRECISION CIRCUITS—26
SM5847AF
1 / 4fs
WCKO
1
18
MSB
LSB
BCKO
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
18bit
OW1N = H
OW2N = H
DOL
MSB
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
DOR
LSB
1
20
BCKO
LSB
MSB
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
20bit
OW1N = L
OW2N = H
DOL
LSB
MSB
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
DOR
1
22
MSB
LSB
BCKO
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
22bit
OW1N = H
OW2N = L
DOL
MSB
LSB
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
DOR
1
24
MSB
LSB
BCKO
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
24bit
OW1N = L
OW2N = L
DOL
MSB
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
DOR
LSB
DG
256fs
internal
system clock
2
28
32
50
60
64
TB
TDW
Figure 13. 2s complement, MSB first, CKSLN = L, OMD = L
NIPPON PRECISION CIRCUITS—27
SM5847AF
TYPICAL APPLICATION (1)
This circuit shows a basic connection to a 24-bit
input DAC (SM5865BM).
(Note that certain circuit details required for good
DAC analog output characteristics have been omitted.)
36.864 MHz external clock, 48/96/192 kHz sampling rate fs, 24-bit data, 8fs oversampling operation
+5V
36.864MHz
SM5865BM
fs
+5V
24-bit Data
17
BCKI
LRCI
VDD
VSS
16
15
14
13
VSS
18
VDD
19
XTI
20
XTO
21
DI/INF2N
Bit Clock
12
1
DVSS
2
DI
3
BCKI
AVSSA
24
RAP
23
IOUTA
22
4
WCKI IOUTAN
21
5
IWSL
RAN
20
11
6
RSTN
AVDDA
19
10
7
TSTN
AVDDB
18
VDD
9
8
TO
26 IW1N/DIL
VDDAC
8
9
DVDD
27 IW2N/DIR
VSSAC
7
10 CKI
22
23
24 CKSLN
25 INF1N
SM5847AF
28 VSS
RBP 17
30 OW1N
WCKO
4
31 OW2N
DOL
3
1
DVSS
32
DOR
2
2
DI
OMD
1
3
BCKI
34
35
36
37
VSS
12 CVSS
VDD
11 CKDVN
5
CKDV2
6
BCKO
CKDV1
VSS
29 VDD
33
38
39
40
41
42
43
44
CKDV1
CKDV2
I/V Converter
IOUTB
16
IOUTBN
15
RBN
14
I/V Converter
AVSSB 13
AVSSA
24
RAP
23
IOUTA
22
4
WCKI IOUTAN
21
5
IWSL
RAN
20
6
RSTN
AVDDA
19
7
TSTN
AVDDB
18
8
TO
9
DVDD
I/V Converter
RBP 17
OMD
10 CKI
RSTN
11 CKDVN
12 CVSS
IOUTB
16
IOUTBN
15
RBN
14
I/V Converter
AVSSB 13
SM5865BM
Figure 14. SM5847AF and SM5865BM connection
Table 14. Operating mode select
Internal system clock frequency divider ratio select
Sampling
frequency
fs (kHz)
Output mode select
CKSLN = HIGH (192fs)
Mode
C K DV1
C K DV2
Divider
OMD
Output mode
48
768fs
HIGH
LOW
4
HIGH
8fs
96
384fs
HIGH
HIGH
2
HIGH
8fs
192
192fs
LOW
LOW
1
HIGH
8fs
External
clock XTI
(MHz)
36.864
NIPPON PRECISION CIRCUITS—28
SM5847AF
TYPICAL APPLICATION (2)
This circuit shows a basic connection to a 24-bit
input DAC (Burr-Brown PCM1704U).
36.864 MHz external clock, 48/96/192 kHz sampling rate fs, 24-bit data, 8fs or 4fs oversampling
operation (Note that certain circuit details required
for good DAC analog output characteristics have
been omitted.)
36.864MHz
fs
+5V
24-bit Data
-5V
17
LRCI
VDD
VSS
23
24 CKSLN
16
15
14
13
VSS
18
VDD
19
XTI
20
XTO
21
BCKI
22
DI/INF2N
Bit Clock
25 INF1N
12
1
DATA
-V CC 20
2
BCLK
19
PCM1704U
11
3
10
4
-V DD
18
17
VDD
9
5
DGND
AGND 16
26 IW1N/DIL
VDDAC
8
6
+V DD
AGND 15
27 IW2N/DIR
VSSAC
7
7
WCLK
8
9
28 VSS
VSS
29 VDD
BCKO
5
30 OW1N
WCKO
4
31 OW2N
DOL
3
DOR
2
1
DATA
-V CC 20
OMD
1
2
BCLK
19
35
36
37
VSS
34
VDD
CKDV1
33
CKDV2
32
SM5847AF
38
39
40
41
42
43
I/V Converter
IOUT 14
6
13
12
20BIT
10 INVERT +VCC 11
3
44
CKDV1
CKDV2
PCM1704U
18
4
17
-V DD
5
DGND
AGND 16
6
+VDD
AGND 15
7
WCLK
OMD
9
RSTN
10
I/V Converter
I OUT 14
8
13
12
20BIT
INVERT +VCC 11
+5V
Figure 15. SM5847AF and Burr-Brown PCM1704U connection
Table 15. Operating mode select
Internal system clock frequency divider ratio select
Sampling
frequency
fs (kHz)
Output mode select
CKSLN = HIGH (192fs)
Mode
C K DV1
C K DV2
Divider
OMD
Output mode
48
768fs
HIGH
LOW
4
HIGH
8fs
96
384fs
HIGH
HIGH
2
HIGH
8fs
192
192fs
LOW
LOW
1
LOW
4fs
External
clock XTI
(MHz)
36.864
NIPPON PRECISION CIRCUITS—29
SM5847AF
NIPPON PRECISION CIRCUITS INC. reserves the right to make changes to the products described in this data sheet in order to
improve the design or performance and to supply the best possible products. Nippon Precision Circuits Inc. assumes no responsibility fo r
the use of any circuits shown in this data sheet, conveys no license under any patent or other rights, and makes no claim that the circuits
are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Nippon Precision
Circuits Inc. makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification.
The products described in this data sheet are not intended to use for the apparatus which influence human lives due to the failure or
malfunction of the products. Customers are requested to comply with applicable laws and regulations in effect now and hereinafter,
including compliance with expor t controls on the distribution or dissemination of the products. Customers shall not expor t, directly or
indirectly, any products without first obtaining required licenses and approvals from appropriate government agencies.
NIPPON PRECISION CIRCUITS INC.
NIPPON PRECISION CIRCUITS INC.
4-3, Fukuzumi 2-chome
Koto-ku, Tokyo 135-8430, Japan
Telephone: 03-3642-6661
Facsimile: 03-3642-6698
NC9803DE
2000.2
NIPPON PRECISION CIRCUITS—30