NTE1690 Integrated Circuit Telephone DTMF Dialer Description: The NTE1690 is a low threshold voltage, field–implanted, metal gate CMOS integrated circuit in a 16–Lead DIP type package. This device interfaces directly to a standard telephone keypad and generates all dual tone multi–frequency pairs required in tone dialing systems. The tone synthesizers are locked to an on–chip reference oscillator using an inexpensive 3.579545MHz crystal for high tone accuracy. The crystal and an output load resistor are the only external components required for tone generation. A MUTE OUT logic signal, which changes state when any key is depressed is also provided. Features: D 3V to 10V Operation When Generating Tones D 2V Operation of Keyscan and MUTE Logic D Static Sensing of Key Closures or Logic Inputs D On–Chip 3.579545MHz Crystal–Controlled Oscillator D Output Amplitudes Proportional to Supply Voltage D High Group Pre–Emphasis D Low Harmonic Distortion D Open Emitter–Follower Low–Impedance Output D SINGLE TONE INHIBIT Pin Absolute Maximum Ratings: Supply Voltage (VDD – VSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15V Maximum Voltage at Any Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD+0.3V to VSS–0.3V Power Dissipation, PD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500mW Operating Temperature Range, Topr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –30° to +60°C Storage Temperature Range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55° to +150°C Electrical Characteristics: (–30°C < TA < +60°C, 3V < VDD < 10V unless otherwise specified) Parameter Test Conditions Minimum Supply Voltage for Keysense and MUTE Logic Functions Min Typ Max Unit – – 2 V Operating Current, Idle RL = 10kΩ – 20 – µA Operating Current, Generating Tones VO = 5V – 2 – mA Electrical Characteristics (Cont’d): (–30°C < TA < +60°C, 3V < VDD < 10V unless othewise specified) Parameter Test Conditions Min Typ Max Unit – 40 – kΩ SINGLE TONE INHIBIT (Pull–Down) – 50 – kΩ TONE DISABLE (Pull–Up) – 50 – kΩ Input Resistors COLUMN and ROW (Pull–Up) MUTE OUT Sink Current (COLUMN and ROW Active) VDD = 3V, VO = 0.5V 0.5 – – mA Output Amplitudes, Low Group RL = 240Ω, VDD = 3V – 250 – mVrms RL = 240Ω, VDD = 10V – 850 – mVrms RL = 240Ω, VDD = 3V – 315 – mVrms RL = 240Ω, VDD = 10V – 1000 – mVrms VDD = 3V – 1.2 – V VDD = 10V – 4.2 – V 2.4 2.7 3.0 dB 22 – – dB – 3 5 ms Output Amplitudes, High Group Mean Output DC Offset High Group Pre–Emphasis Dual Tone/Harmonic Distortion Ratio Start–Up Time (90% Amplitude) 1MHz Bandwidth Note 1. Crystal Specification: Parallel Resonant 3.579545MHz, RS ≤ 150Ω, L = 100mH, C0 = 5pF, C1 = 0.02pf. Pin Descriptions: VDD (Pin1): This is the positive voltage supply to the device, referenced to VSS. The collector of the TONE OUT transistor is connected to this pin. VSS (Pin6): This is the negative voltage supply. OSCILLATOR (Pin7 and Pin8): All tone generation timing is derived from the on–chip oscillator circuit. A low–cost 3.579545MHz A–cut crystal (NTSC TV color–burst) is needed between Pin7 and Pin8. Load capacitors and feedback resistor are included on–chip for good start–up and stability. The oscillator stops when column inputs are sensed with no valid input having been detected. The oscillator is also stopped when the TONE DISABLE input is pulled to logic low. Row and Column Inputs (Pins 3, 4, 5, 9, 11, 12, 13, 14): When no key is pushed, pull–up resistors are active on row and column inputs. A key closure is recognized when a single row and a single column are connected to VSS, which starts the oscillator and initiates tone generation. Negative–true logic signals simulating key closures can also be used. TONE DISABLE Input (Pin2): The TONE DISABLE input has an internal pull–up resistor. When this input is open or at logic high, the normal tone output mode will occur. When TONE DISABLE input is at logic low, the device will be in the inactive mode, TONE OUTPUT will be at an open circuit state. MUTE Output (Pin10): The MUTE output is an open–drain N–channel device that sinks current to VSS with any key input and is open when no key input is sensed. The MUTE output will switch regardless o the state of he SINGLE TONE INHIBIT input. SINGLE TONE INHIBIT Input (Pin15): The SINGLE TONE INHIBIT input is used to inhibit the generation of other than valid tone pairs due to multiple row–column closures. It has a pull–down resistor to VSS, and when left open or tied to VSS any input condition that would normally result in a single tone will now result in no tone, with all other functions operating normally. When tied to VDD, single or dual tones may be generated (See Table II). TONE OUT (Pin16): This output is the open emitter of an NPN transistor, the collector of which is connected to VDD. When an external load resistor is connected from TONE OUT to VSS, the output voltage on this pin is the sum of the high and low group sine–waves superimposed on a DC offset. When not generating tones, this output transistor is turned OFF to minimize the device idle current. Pin Descriptions (Cont’d): Adjustment of the emitter load resistor results in variation of the mean DC current during tone generation, the sine–wave signal current through the output transistor, and the output distortion. Increasing values of load resistances decreases both the signal current and distortion. Functional Description: With no key inputs to the device the oscillator is inhibited, the output transistor is pulled OFF and device current consumption is reduced to a minimum. Key closures are sensed statically to ensure no modification of the line when tones are not being generated. Any key closure activates the MUTE output, starts the oscillator and sets the high group and low group programmable counters to the appropriate divide ratio. These counters sequence two ratioed–capacitor D/A converters through a series of 28 equal duration steps per sine–wave cycle. The two tones are summed by a mixer amplifier, with pre–emphasis applied to the high group tone. The output is an NPN emitter–follower requiring the addition of an external load resistor to VSS. This resistor facilitates adjustment of the signal current flowing from VDD through the output transistors. The amplitude of the output tones is directly proportional to the device supply voltage. Table I. Output Frequency Accuracy Tone Group Low Group fL High Group fH Valid Input R1 Standard DTMF (Hz) 697 Tone Output Frequency 694.8 % Deviation from Standard –0.32 R2 770 770.1 +0.02 R3 852 852.4 +0.03 R4 941 940.0 –0.11 C1 1209 1206.0 –0.24 C2 1336 1331.7 –0.32 C3 1477 1486.5 +0.64 C4 16334 1639.0 +0.37 Table II. Functional Truth Table SINGLE TONE INHIBIT TONE DISABLE ROW COLUMN X O X X X X Tones MUTE Low High X 0V 0V 0 O/C O/C 0V 0V 0 1 One One fL fH 1 1 1 2 or More One – fH 1 1 1 One 2 or More fL – 1 1 1 2 or More 2 or More VOS VOS 1 0 1 2 or More One VOS VOS 1 0 1 One 2 or More VOS VOS 1 0 1 2 or More 2 or More VOS VOS 1 Note 2. X is don’t care state. Note 3. VOS is the output offset voltage. Pin Connection Diagram VDD 1 16 TONE OUT TONE DISABLE Input 2 15 SINGLE TONE INHIBIT COL 1 3 14 ROW 1 COL 2 4 13 ROW 2 COL 3 5 12 ROW 3 VSS 6 11 ROW 4 10 MUTE Output OSC Input 7 OSC Output 8 16 9 COL 4 9 .260 (6.6) Max 1 8 .785 (19.9) Max .300 (7.62) .200 (5.08) Max .245 (6.22) Min .100 (2.54) .700 (17.7)