NTE6664 Integrated Circuit 64K–Bit Dynamic RAM Description: The NTE6664 is a 65,536 Bit, high–speed, dynamic Random Access Memory. Organized as 65,536 one–bit words and fabricated using HMOS high–performance N–Channel silicon–gate technology, this 5V only dynamic RAM combines high performance with low cost and improved reliability. By multiplying row– and column– address inputs, the NTE6664 requires only eight address lines and permits packaging in a standard 16–Lead DIP package. Complete address decoding is done on chip with address latches incorporated. Data out is controlled by CAS allowing for greater system flexibility. All inputs and outputs, including clocks, are fully TTL compatible. The NTE6664 incorporates a one– transistor cell design and dynamic storage techniques. In addition to the RAS–only refresh mode, the refresh control function available on Pin1 provides two additional modes of refresh, automatic and self refresh. Features: D Single +5V Operation (±10%) D Maximum Access Time: 150ns D Low Power Dissipation: 302.5mW Max (Active) 22mW Max (Standby) D Three State Data Output D Early–Write Common I/O Capability D D D D D D 128 Cycle, 2ms Refresh Control on Pin1 for Automatic or Self Refresh RAS–Only Refresh Mode CAS Controlled Output Fast Page Mode Cycle Time Low Soft Error Rate: < 0.1% per 1000 Hrs Absolute Maximum Ratings: (Note 1) Voltage on VCC Supply Relative to VSS, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –2 to +7V Voltage Relative to VSS for Any Pin Except VCC, Vin, Vout . . . . . . . . . . . . . . . . . . . . . . . . . . . –1 to +7V Data Out Current (Short Circuit), Iout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA Power Dissipation, PD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W Operating Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to +70°C Storage Temperature Range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65° to +150°C Note 1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect the device reliability. Recommended Operating Conditions: (Note 2, TA = 0 to +70°C unless otherwise specified) Parameter Symbol Min Typ Max Unit VCC 4.5 5.0 5.5 V VSS 0 0 0 V Logic 1 Voltage, All Inputs VIH 2.4 – 6.5 V Logic 0 Voltage, All Inputs (Note 3) VIL –1.0 – 0.8 V Supply Voltage (Operating Voltage Range) Note 2. All voltages referenced to VSS. Note 3. The device will withstand undershoots to the –2V level with a maximum pulse width 0f 20ns at the –1.5V level. This is periodically sampled rather than 100% tested. DC Characteristics: (VCC = 5V ±10%, TA = 0 to +70°C unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit VCC Power Supply Current ICC1 tRC = 270ns, Note 4 – – 55 mA VCC Power Supply Current (Standby) ICC2 RAS = CAS = VIH – – 4 mA VCC Power Supply Current During RAS only Refresh Cycles ICC3 tRC = 270ns, Note 4 – – 45 mA Input Leakage Current Any Input Except REFRESH Ilkg(L) VSS < Vin < VCC – – 10 µA REFRESH Input Current Ilkg(F) VSS < Vin < VCC – – 20 µA Output Leakage Current Ilkg(O) CAS at Logic 1, 0 ≤ Vout ≤ 5.5V – – 10 µA Output Logic 1 Voltage VOH Iout = –4mA 2.4 – – V Output Logic 0 Voltage VOL Iout = 4mA – – 0.4 V Note 4. Current is a function of cycle rate and output loading; maximum current is measured at the fastest cycle rate with the output open. Capacitance: (VCC = 5V ±10%, f = 1MHz, TA = +25°C, Note 5, Periodically Sampled Rather Than 100% Tested) Parameter Symbol Input Capacitance A0 – A7, D RAS, CAS, WRITE, REFRESH Cin Output Capacitance Cout Q Test Conditions Min Typ Max Unit – – 3 6 5 8 pF – 5 7 pF CAS = VIH to Disable Output Note 5. Capacitance measured with a Boonton Meter or effective capacitance calculated from the equation: C = I∆t/∆V. Read, Write, and Read–Modify–Write Cycles: (VCC = 5V ±10%, TA = 0 to +70°C unless other– wise specified, Notes 6, 7, and 8) Parameter Random Read or Write Cycle Time Symbol Test Conditions Min Typ Max Unit tRC Note 9, Note 10 270 – – ns Read–Write Cycle Time tRWC Note 9, Note 10 280 – – ns Access Time from RAS tRAC Note 11, Note 13 – – 150 ns Access Time from CAS tCAC Note 12, Note 13 – – 75 ns Output Buffer and Turn–Off Delay tOFF Note 19 0 – 30 ns RAS Precharge Time tRP 100 – – ns RAS Pulse Width tRAS 150 – 10000 ns CAS Pulse Width tCAS 75 – 10000 ns Read, Write, and Read–Modify–Write Cycles (Cont’d): (VCC = 5V ±10%, TA = 0 to +70°C unless otherwise specified, Notes 6, 7, and 8) Parameter Symbol Test Conditions Typ Max Unit 25 – 75 ns RAS to CAS Delay Time tRCD Row Address Setup Time tASR 0 – – ns Row Address Hold Time tRAH 20 – – ns Column Address Setup Time tASC 0 – – ns Column Address Hold Time tCAH 35 – – ns Column Address Hold Time Referenced to RAS tAR 95 – – ns tT 3 – 50 ns Read Command Setup Time tRCS 0 – – ns Read Command Hold Time Referenced to CAS tRCH Note 15 0 – – ns Read Command Hold Time Referenced to RAS tRRH Note 15 0 – – ns Write Command Hold Time tWCH 35 – – ns Write Command Hold Time Referenced to RAS tWCR 95 – – ns Transition Time (Rise and Fall) Note 14 Min Note 18 Note 18 Write Command Pulse Width tWP 35 – – ns Write Command to RAS Lead Time tRWL 45 – – ns Write Command to CAS Lead Time tCWL 45 – – ns Data in Setup Time tDS Note 16 0 – – ns Data in Hold Time tDH Note 16 35 – – ns Data in Hold Time Referenced to RAS tDHR Note 18 95 – – ns CAS to RAS Precharge Time tCRP –10 – – ns RAS Hold Time tRSH 75 – – ns Refresh Period tRFSH – – 2 ms Write Command Setup Time tWCS Note 17 –10 – – ns CAS to Write Delay tCWD Note 17 45 – – ns RAS to Write Delay tRWD Note 17 120 – – ns CAS Hold Time tCSH 150 – – ns CAS Precharge Time (Page Mode Cycle Only) tCP 60 – – ns Page Mode Cycle Time tPC 145 – – ns RAS to REFRESH Delay tRFD –10 – – ns REFRESH Period (Battery Backup Mode) tFBP 2000 – – ns REFRESH to RAS Precharge Time (Battery Backup Mode) tFBR 320 – – ns REFRESH Cycle Time (Auto Pulse Mode) tFC 270 – – ns REFRESH Pulse Period (Auto Period Mode) tFP 60 – 2000 ns REFRESH to RAS Setup Time (Auto Pulse Mode) tFSR –30 – – ns REFRESH to RAS Delay Time (Auto Pulse Mode) tFRD 320 – – ns tFI 60 – – ns RAS to REFRESH Lead Time tFRL 370 – – ns RAS Inactive Time During REFRESH tFRI 370 – – ns REFRESH Inactive Time Note 6. VIH min and VIL max are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL. Note 7. An initial pause of 100µs is required after power–up followed by 8 RAS cycles before proper device operation is guaranteed. Note 8. The transition time specification applies for all input signals. In addition to meeting the transition rate specification, all input signals must transmit between VIH and VIL (or between VIL and VIH) in a monotonic manner. Note 9. The specification for tRC(min) and tRMW(min) are used only to indicate cycle time at which proper operation over the full temperature range (0°C ≤ TA ≤ +70°C) is assured. Note10. AC measurements tT = 5ns. Note 11. Assumes that tRCD ≤ tRCD(max). Note12. Assumes that tRCD ≥ tRCD(max). Note13. Measured with a current load equivalent to 2 TTL (–200µA, +4mA) loads and 100pF with the data output trip points set at VOH = 2V and VOL = 0.8V. Note14. Operation within the tRCD(max) limit ensures that tRAC(max) can be met, tRCD(max) is specified as a reference point only; if tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC. Note15. Either tRRH or tRCH must be satisfied for a read cycle. Note16. These parameters are referenced to CAS leading edge in random write cycles and to WRITE leading edge in delayed write or read–modify–write cycles. Note17. tWCS, tCWD, and tRWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only; if tWCS ≥ tWCS(min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if tCWD ≥ tCWD(min) and tRWD ≥ tRWD(min), the cycle is read–write cycle and the data out will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. Note19. tOFF(max) defines the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. Block Diagram VCC A2 A3 A4 A5 A6 A7 Precharge Clock Row Decoder Memory Array Memory Array Row Decoder Memory Array Memory Array Row Decoder Memory Array Memory Array Row Decoder Memory Array I/O Timing Control and Refresh Control A1 Memory Array Column Decoder A0 Address Buffer/Counters/Multiplexers Precharge Clock Column Decoder VSS RAS CAS Write, W REFRESH Data In, D Output Data, Q Pin Connection Diagram * REFRESH 1 16 VSS D 2 15 CAS W 3 14 Q RAS 4 13 A6 A0 5 12 A3 A1 6 11 A4 A2 7 10 A5 VCC 8 9 A7 * If pin is not used, it should be connected to VCC through a 10k resistor. 16 9 1 8 .260 (6.6) Max .870 (22.0) Max .200 (5.08) Max .100 (2.54) .700 (17.78) .099 (2.5) Min