¡ Semiconductor MSM5117805B ¡ Semiconductor MSM5117805B E2G0047-17-41 2,097,152-Word ¥ 8-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO DESCRIPTION The MSM5117805B is a 2,097,152-word ¥ 8-bit dynamic RAM fabricated in Oki's silicon-gate CMOS technology. The MSM5117805B achieves high integration, high-speed operation, and low-power consumption because Oki manufactures the device in a quadruple-layer polysilicon/double-layer metal CMOS process. The MSM5117805B is available in a 28-pin plastic SOJ or 28-pin plastic TSOP. FEATURES • 2,097,152-word ¥ 8-bit configuration • Single 5 V power supply, ±10% tolerance • Input : TTL compatible, low input capacitance • Output : TTL compatible, 3-state • Refresh : 2048 cycles/32 ms • Fast page mode with EDO, read modify write capability • CAS before RAS refresh, hidden refresh, RAS-only refresh capability • Multi-bit test mode capability • Package options: 28-pin 400 mil plastic SOJ (SOJ28-P-400-1.27) (Product : MSM5117805B-xxJS) 28-pin 400 mil plastic TSOP (TSOPII28-P-400-1.27-K) (Product : MSM5117805B-xxTS-K) (TSOPII28-P-400-1.27-L) (Product : MSM5117805B-xxTS-L) xx indicates speed rank. PRODUCT FAMILY Family Access Time (Max.) tRAC tAA tCAC tOEA Cycle Time Power Dissipation (Min.) Operating (Max.) Standby (Max.) MSM5117805B-50 50 ns 25 ns 13 ns 13 ns 90 ns 825 mW MSM5117805B-60 60 ns 30 ns 15 ns 15 ns 110 ns 715 mW MSM5117805B-70 70 ns 35 ns 20 ns 20 ns 130 ns 605 mW 5.5 mW 263 MSM5117805B ¡ Semiconductor PIN CONFIGURATION (TOP VIEW) VCC 1 28 VSS VCC 1 28 VSS VSS 28 1 VCC DQ1 2 27 DQ8 DQ1 2 27 DQ8 DQ8 27 2 DQ1 DQ2 3 26 DQ7 DQ2 3 26 DQ7 DQ7 26 3 DQ2 DQ3 4 25 DQ6 DQ3 4 25 DQ6 DQ6 25 4 DQ3 DQ4 5 24 DQ5 DQ4 5 24 DQ5 DQ5 24 5 DQ4 WE 6 23 CAS WE 6 23 CAS CAS 23 6 WE RAS 7 22 OE RAS 7 22 OE OE 22 7 RAS NC 8 21 A9 NC 8 21 A9 A9 21 8 NC A10R 9 20 A8 A10R 9 20 A8 A8 20 9 A10R A0 10 19 A7 A0 10 19 A7 A7 19 10 A0 A1 11 18 A6 A1 11 18 A6 A6 18 11 A1 A2 12 17 A5 A2 12 17 A5 A5 17 12 A2 A3 13 16 A4 A3 13 16 A4 A4 16 13 A3 VCC 14 15 VSS VCC 14 15 VSS VSS 15 14 VCC 28-Pin Plastic SOJ 28-Pin Plastic TSOP (K Type) Pin Name A0 - A9, A10R Note : 264 Function Address Input RAS Row Address Strobe CAS Column Address Strobe DQ1 - DQ8 Data Input/Data Output OE 28-Pin Plastic TSOP (L Type) Output Enable WE Write Enable VCC Power Supply (5 V) VSS Ground (0 V) NC No Connection The same power supply voltage must be provided to every VCC pin, and the same GND voltage level must be provided to every VSS pin. ¡ Semiconductor MSM5117805B BLOCK DIAGRAM RAS WE Timing Generator OE I/O Controller CAS 8 Output Buffers 8 Input Buffers 8 DQ1 - DQ8 10 Internal Address Counter A0 - A9 10 A10R Column Address Buffers 1 10 Refresh Control Clock Row Row Address 11 DecoBuffers ders Word Drivers Column Decoders Sense Amplifiers 8 I/O Selector 8 8 Memory Cells VCC On Chip VBB Generator On Chip IVCC Generator VSS 265 MSM5117805B ¡ Semiconductor ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Symbol Rating Unit Voltage on Any Pin Relative to VSS VIN, VOUT –0.5 to VCC + 0.5 V Voltage on VCC Supply Relative to VSS VCC –0.5 to 7 V Short Circuit Output Current IOS 50 mA Power Dissipation PD* 1 W Operating Temperature Topr 0 to 70 °C Storage Temperature Tstg –55 to 150 °C Parameter *: Ta = 25°C Recommended Operating Conditions (Ta = 0°C to 70°C) Parameter Power Supply Voltage Symbol Min. Typ. Max. Unit VCC 4.5 5.0 5.5 V VSS 0 0 0 V Input High Voltage VIH 2.4 — Input Low Voltage VIL –0.5*2 — VCC + 0.5*1 0.8 V V Notes : *1. The input voltage is VCC + 2.0 V when the pulse width is less than 20 ns (the pulse width is with respect to the point at which VCC is applied). *2. The input voltage is VSS – 2.0 V when the pulse width is less than 20 ns (the pulse width is with respect to the point at which VSS is applied). Capacitance (VCC = 5 V ±10%, Ta = 25°C, f = 1 MHz) Parameter Symbol Typ. Max. Unit Input Capacitance (A0 - A9, A10R) CIN1 — 5 pF Input Capacitance (RAS, CAS, WE, OE) CIN2 — 7 pF Output Capacitance (DQ1 - DQ8) CI/O — 7 pF 266 ¡ Semiconductor MSM5117805B DC Characteristics Parameter (VCC = 5 V ±10%, Ta = 0°C to 70°C) Symbol Condition MSM5117805 MSM5117805 MSM5117805 B-50 B-60 B-70 Unit Note Min. Max. Min. Max. Min. Max. Output High Voltage VOH IOH = –5.0 mA 2.4 VOL IOL = 4.2 mA 0 2.4 0 VCC 0.4 2.4 0 VCC 0.4 V Output Low Voltage VCC 0.4 –10 10 –10 10 –10 10 mA –10 10 –10 10 –10 10 mA — 150 — 130 — 110 mA 1, 2 — 2 — 2 — 2 mA 1 — 1 — 1 — 1 — 150 — 130 — 110 mA 1, 2 — 5 — 5 — 5 mA 1 — 150 — 130 — 110 mA 1, 2 — 150 — 130 — 110 mA 1, 3 V 0 V £ VI £ 6.5 V; Input Leakage Current ILI All other pins not under test = 0 V Output Leakage Current ILO Average Power Supply Current ICC1 (Operating) Power Supply Current (Standby) Current (Standby) (CAS before RAS Refresh) Average Power Supply Current (Fast Page Mode) tRC = Min. ≥ VCC –0.2 V ICC3 CAS = VIH, tRC = Min. RAS = VIH, ICC5 CAS = VIL, DQ = enable Average Power Supply Current RAS, CAS cycling, RAS cycling, (RAS-only Refresh) Power Supply 0 V £ VO £ 5.5 V RAS, CAS = VIH ICC2 RAS, CAS Average Power Supply Current DQ disable ICC6 RAS cycling, CAS before RAS RAS = VIL, ICC7 CAS cycling, tHPC = Min. Notes : 1. ICC Max. is specified as ICC for output open condition. 2. The address can be changed once or less while RAS = VIL. 3. The address can be changed once or less while CAS = VIH. 267 MSM5117805B ¡ Semiconductor AC Characteristics (1/2) (VCC = 5 V ±10%, Ta = 0°C to 70°C) Note 1, 2, 3, 12, 13 Parameter Random Read or Write Cycle Time Read Modify Write Cycle Time Fast Page Mode Cycle Time Fast Page Mode Read Modify Write Cycle Time Access Time from RAS Symbol MSM5117805 MSM5117805 MSM5117805 B-60 B-50 B-70 Unit Note Min. Max. Min. Max. Min. Max. tRC 84 — 104 124 — ns tRWC tHPC 110 20 — — 135 25 — — — 160 30 — — ns ns tHPRWC 58 — 68 — 78 — ns tRAC — 50 — 60 — 70 ns 4, 5, 6 Access Time from CAS tCAC Access Time from Column Address Access Time from CAS Precharge tAA tCPA — — 13 25 — — 15 30 — — 20 35 ns ns 4, 5 4, 6 — 30 — 35 — 40 ns 4 Access Time from OE Output Low Impedance Time from CAS tOEA tCLZ — 0 13 — — 0 15 — — 0 20 — ns ns 4 4 Data Output Hold After CAS Low tDOH 5 — 5 — 5 — ns CAS to Data Output Buffer Turn-off Delay Time RAS to Data Output Buffer Turn-off Delay Time tCEZ tREZ 0 0 13 13 0 0 15 15 0 0 20 20 ns ns 7, 8 7, 8 OE to Data Output Buffer Turn-off Delay Time WE to Data Output Buffer Turn-off Delay Time tOEZ tWEZ 0 0 13 13 0 0 15 15 0 0 20 20 ns ns 7 7 Transition Time Refresh Period tT tREF 1 — 50 32 1 — 50 32 1 — 50 32 ns ms 3 RAS Precharge Time tRP 30 — 40 — 50 — ns RAS Pulse Width tRAS 50 10,000 60 10,000 70 10,000 ns RAS Pulse Width (Fast Page Mode with EDO) tRASP 50 100,000 60 100,000 70 100,000 ns RAS Hold Time tRSH tROH 7 — ns — — 13 13 — 7 10 10 — RAS Hold Time referenced to OE — ns CAS Precharge Time (Fast Page Mode with EDO) tCP 7 — 10 — 10 — ns CAS Pulse Width tCAS 7 10,000 10 10,000 13 10,000 ns CAS Hold Time CAS to RAS Precharge Time tCSH tCRP 35 5 — — 40 5 — — 45 5 — — ns ns RAS Hold Time from CAS Precharge tRHCP 30 — 35 — 40 — ns OE Hold Time from CAS (DQ Disable) RAS to CAS Delay Time RAS to Column Address Delay Time tCHO tRCD tRAD 5 — 37 25 5 14 12 — 45 30 5 11 9 14 12 — 50 35 ns ns ns Row Address Set-up Time tASR 0 — 0 — 0 — ns Row Address Hold Time tRAH 7 — 10 — 10 — ns Column Address Set-up Time tASC 0 — 0 — 0 — ns Column Address Hold Time Column Address to RAS Lead Time tCAH tRAL 7 25 — — 10 30 — — 13 35 — — ns ns 268 5 6 ¡ Semiconductor MSM5117805B AC Characteristics (2/2) (VCC = 5 V ±10%, Ta = 0°C to 70°C) Note 1, 2, 3, 12, 13 Parameter Symbol MSM5117805 MSM5117805 MSM5117805 B-50 B-60 B-70 Unit Note Min. Max. Min. Max. Min. Max. Read Command Set-up Time tRCS 0 — 0 — 0 — ns Read Command Hold Time tRCH 0 — 0 — 0 — ns 9 Read Command Hold Time referenced to RAS Write Command Set-up Time tRRH tWCS 0 0 — — 0 0 — — 0 0 — — ns ns 9 10 Write Command Hold Time tWCH 7 — 10 — 13 — ns Write Command Pulse Width tWP 7 — 10 — 10 — ns WE Pulse Width (DQ Disable) tWPE 7 — 10 — 10 — ns OE Command Hold Time tOEH 7 — 10 — 13 — ns OE Precharge Time tOEP 7 — 10 — 10 — ns OE Command Hold Time Write Command to RAS Lead Time 7 — 10 7 7 — — — 10 10 10 — — 13 13 — — Write Command to CAS Lead Time tOCH tRWL tCWL — ns ns Data-in Set-up Time Data-in Hold Time OE to Data-in Delay Time CAS to WE Delay Time Column Address to WE Delay Time RAS to WE Delay Time tDS tDH tOED tCWD tAWD tRWD 0 7 13 30 42 67 — — — — — — 0 10 15 34 49 79 — — — — — — 0 13 20 44 59 94 — — — — — — ns ns ns ns ns ns 11 11 CAS Precharge WE Delay Time 10 ns tCPWD 47 — 54 — 64 — ns CAS Active Delay Time from RAS Precharge tRPC 5 — 5 — 5 — ns RAS to CAS Set-up Time (CAS before RAS) RAS to CAS Hold Time (CAS before RAS) WE to RAS Precharge Time (CAS before RAS) WE Hold Time from RAS (CAS before RAS) RAS to WE Set-up Time (Test Mode) RAS to WE Hold Time (Test Mode) tCSR tCHR tWRP tWRH tWTS tWTH 5 10 10 10 10 10 — — — — — — 5 10 10 10 10 10 — — — — — — 5 10 10 10 10 10 — — — — — — ns ns ns ns ns ns 10 10 10 269 MSM5117805B Notes: ¡ Semiconductor 1. A start-up delay of 200 µs is required after power-up, followed by a minimum of eight initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device operation is achieved. 2. The AC characteristics assume tT = 2 ns. 3. VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals. Transition times (tT) are measured between VIH and VIL. 4. This parameter is measured with a load circuit equivalent to 2 TTL loads and 100 pF. 5. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met. tRCD (Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (Max.) limit, then the access time is controlled by tCAC. 6. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met. tRAD (Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (Max.) limit, then the access time is controlled by tAA. 7. tCEZ (Max.), tREZ (Max.), tWEZ (Max.) and tOEZ (Max.) define the time at which the output achieves the open circuit condition and are not referenced to output voltage levels. 8. tCEZ and tREZ must be satisfied for open circuit condition. 9. tRCH or tRRH must be satisfied for a read cycle. 10. tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS ≥ tWCS (Min.), then the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. If tCWD ≥ tCWD (Min.) , tRWD ≥ tRWD (Min.), tAWD ≥ tAWD (Min.) and tCPWD ≥ tCPWD (Min.), then the cycle is a read modify write cycle and data out will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, then the condition of the data out (at access time) is indeterminate. 11. These parameters are referenced to the CAS leading edge in an early write cycle, and to the WE leading edge in an OE control write cycle, or a read modify write cycle. 12. The test mode is initiated by performing a WE and CAS before RAS refresh cycle. This mode is latched and remains in effect until the exit cycle is generated. The test mode specified in this data sheet is a 2-bit parallel test function. CA9 is not used. In a read cycle, if all internal bits are equal, the DQ pin will indicate a high level. If any internal bits are not equal, the DQ pin will indicate a low level. The test mode is cleared and the memory device returned to its normal operating state by performing a RAS-only refresh cycle or a CAS before RAS refresh cycle. 13. In a test mode read cycle, the value of access time parameters is delayed for 5 ns for the specified value. These parameters should be specified in test mode cycle by adding the above value to the specified value in this data sheet. See ADDENDUM M for AC Timing Waveforms 270