ETC TS8MED3260G

32MB 72-PIN EDO
SIMM With 16Mx8 3.3VOLT
TS8MED3260G
Description
Features
The TS8MED3260G is a 8M by 32-bit dynamic RAM
•
Fast Page Mode with Extended Data Out
module with 16 pcs of 4Mx4 DRAMs assembled on the
•
Single +5.0V ± 10% power supply.
printed circuit board.
•
2,048 cycles refresh.
The TS8MED3260G is optimized for application to
•
Lower power consumption.
systems which require high density and large capacity
•
CAS before RAS refresh, RAS only refresh, Hidden
refresh, Fast Page Mode with EDO, Read_Modify_Write
along with compact sizing.
capability.
•
Placement
DRAM Status : GM71C17403CJ-60
M5M417405CJ-6
NT5117405BJ-60
B
HM5117405S-6
C
TS8MED3260G
Access time from /RAS
tRAC
Access time from /CAS
tCAC
Random read/write cycle time
tRC
Hyper page mode cycle time
tHPC
A
60ns
15ns
104ns
25ns
Dimensions
D
C
B
G
H
F
E
Transcend Information Inc.
Side
Millimeters
A
107.95 ± 0.500
Inches
4.520 ± 0.020
B
6.35
0.250
C
3.38
0.133
D
2.03
0.080
E
21.60 ± 0.500
0.850 ± 0.020
F
10.16
0.400
G
6.35
0.250
H
1.27 ± 0.080
0.050 ± 0.003
32MB 72-PIN EDO
SIMM With 16Mx8 3.3VOLT
TS8MED3260G
DQ28
DQ29
DQ30
DQ31
DQ20
DQ21
DQ22
DQ23
DQ16
DQ17
DQ18
DQ19
DQ12
DQ13
DQ14
DQ15
DQ8
DQ9
DQ10
DQ11
DQ24
DQ25
DQ26
DQ27
D3
D2
D1
D0
D3
D2
D1
D0
D3
D2
D1
D0
D3
D2
D1
D0
D3
D2
D1
D0
D3
D2
D1
D0
D3
D2
D1
D0
D3
D2
D1
D0
A0-A10
/RAS0
/CAS0
/WE
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
TS8MED3260G-- Block Diagram
A0-A10
A0-A10
A0-A10
A0-A10
A0-A10
A0-A10
A0-A10
A0-A10
/RAS
/RAS
/RAS
/RAS
/RAS
/RAS
/RAS
/RAS
/CAS
/CAS
/CAS
/CAS
/CAS
/CAS
/CAS
/CAS
/WE
/WE
/WE
/WE
/WE
/WE
/WE
/WE
/CAS1
/RAS2
/CAS2
/CAS3
/RAS3
D3
D2
D1
D0
D3
D2
D1
D0
Pin
Name
Vss
DQ0
DQ16
DQ1
DQ17
DQ2
DQ18
DQ3
DQ19
Vcc
NC
A0
A1
A2
A3
A4
A5
A6
A10
DQ4
DQ20
DQ5
DQ21
DQ6
D3
D2
D1
D0
A0-A10
A0-A10
A0-A10
A0-A10
A0-A10
A0-A10
A0-A10
A0-A10
/RAS
/RAS
/RAS
/RAS
/RAS
/RAS
/RAS
/RAS
/CAS
/CAS
/CAS
/CAS
/CAS
/CAS
/CAS
/CAS
/WE
/WE
/WE
/WE
/WE
/WE
/WE
/WE
Pinouts
Pin
No
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
D3
D2
D1
D0
D3
D2
D1
D0
D3
D2
D1
D0
D3
D2
D1
D0
D3
D2
D1
D0
/RAS1
Pin Identification
Pin
No
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
Pin
Name
DQ22
DQ7
DQ23
A7
NC
Vcc
A8
A9
/RAS3
/RAS2
NC
NC
NC
NC
Vss
/CAS0
/CAS2
/CAS3
/CAS1
/RAS0
/RAS1
NC
/WE
NC
Pin
No
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
Pin
Name
DQ8
DQ24
DQ9
DQ25
DQ10
DQ26
DQ11
DQ27
DQ12
DQ28
Vcc
DQ29
DQ13
DQ30
DQ14
DQ31
DQ15
NC
PD1
PD2
PD3
PD4
NC
Vss
Symbol
Function
A0 ~ A10
Address inputs
DQ0 ~ DQ31
Common data inputs/outputs
/RAS0 ~ /RAS3
Row address strobes
/CAS0 ~ /CAS3
Column address strobes
/WE
Write enable
Vcc
+5.0 Volt power supply
Vss
Ground
NC
No connection
PD1 ~ PD4
Presence detection pin
This technical information is based on industry standard data and tests believed to be reliable. However , Transcend makes no warranties, either
expressed or implied, as to its accuracy and assumes no liability in connection with the use of this product. Transcend reserves the right to make
changes in specifications at any time without prior notice.
Transcend Information Inc.
32MB 72-PIN EDO
SIMM With 16Mx8 3.3VOLT
TS8MED3260G
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
VIN, VOUT
-1.0~+7.0
V
Vcc
-1.0~+7.0
V
TSTG
-55~+150
°C
Power dissipation
PD
16
W
Short circuit current
IOS
50
mA
Voltage on any pin relative to Vss
Voltage on Vcc supply to Vss
Storage temperature
Note:
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device
reliability.
RECOMMENDED OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to Vss , TA = 0 to 70)
Parameter
Symbol
Min
Typ
Max
Unit
Supply voltage
Vcc
4.5
5.0
5.5
V
Ground
Vss
0
0
0
Input high voltage
VIH
2.4
Input low voltage
VIL
-1.0*
2
V
1
-
Vcc+1*
V
-
0.8
V
Note: 1. Vcc +2.0V/20ns, Pulse width is, measured at Vcc .
2. -2.0V/20ns, Pulse width is measured at Vcc.
DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted)
Symbol
Min
Max
Unit
ICC1
-
816
mA
ICC2
-
32
mA
ICC3
-
816
mA
ICC4
-
816
mA
ICC5
-
16
mA
ICC6
-
816
mA
II(L)
-80
80
uA
IO(L)
-10
10
uA
VOH
2.4
-
V
0.4
V
VOL
ICC1: Operating Current* (/RAS, /CAS, Address cycling @tRC=min)
ICC2: Standby Current (/RAS=/CAS=/W=VIH)
Transcend Information Inc.
32MB 72-PIN EDO
SIMM With 16Mx8 3.3VOLT
TS8MED3260G
ICC3: /RAS only Refresh Current* (/CAS=VIH, /RAS cycling @tRC=min)
ICC4: Fast Page Mode Current* (/RAS=VIL, /CAS Address cycling: tPC=min)
ICC5: Standby Current (/RAS=/CAS=/W=VCC-0.2V)
ICC6: /CAS-Before-/RAS Refresh Current* (/RAS and /CAS cycling @tRC=min)
LI(L): Input Leakage Current (Any input 0VINVCC+0.5V, all other pins not under test=0V)
IO(L): Output Leakage Current (Data Out is disabled, 0VVOUTVCC)
VOH: Output High Voltage Level (IOH= -5mA)
VOL: Output Low Voltage Level (IOL=4.2mA)
Note: ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are
obtained with the output open. ICC is specified as an average current. In ICC1 and ICC3, address can be
changed maximum once while /RAS=VIL. In ICC4, address can be changed maximum once within one
mode cycle, tPC.
CAPACITANCE (TA = 25°C, Vcc = 5V, f = 1MHz)
Item
Symbol
Min
Max
Unit
Input capacitance (A0~A10)
CIN1
-
100
pF
Input capacitance (/WE)
CIN2
-
130
pF
Input capacitance (/RAS0, /RAS2)
CIN3
-
35
pF
Input capacitance (/CAS0~/CSA3)
CIN4
-
30
pF
Data input/output capacitance (DQ0~DQ31)
CDQ
-
20
pF
AC CHARACTERISTICS (0TA70, Vcc=5.0V%, See notes 1, 2)
Test condition: VIH/VIL=2.4V/0.8V, VOH/VOL=2.4V/0.4V, Output loading CL=100pF
Parameter
Symbol
Min
Random read or write cycle time
tRC
110
Access time from /RAS
tRAC
60
ns
3,4
Access time from /CAS
tCAC
15
ns
3,4,5
Access time from column address
tCLZ
30
ns
3,10
/CAS to output in Low-Z
tRC
0
ns
3
Output buffer turn-off delay
tOFF
0
15
ns
6
tT
3
50
ns
2
/RAS precharge time
tRP
40
/RAS pulse width
tRAS
60
/RAS hold time
tRSH
15
ns
/CAS hold time
tCSH
60
ns
/CAS pulse width
tCAS
10
10K
ns
/RAS to /CAS delay time
tRCD
20
45
ns
Transition time (rise and fall)
Transcend Information Inc.
Max
Unit
Note
ns
ns
10K
ns
4
32MB 72-PIN EDO
SIMM With 16Mx8 3.3VOLT
TS8MED3260G
/RAS to column address delay time
tRAD
15
/CAS to /RAS precharge time
tCRP
5
ns
Row address set-up time
tASR
0
ns
Row address hold time
tRAH
10
ns
Column address set-up time
tASC
0
ns
Column address hold time
tCAH
10
Column address to /RAS lead time
tRAL
30
Read command set-up time
tRCS
0
ns
Read command hold referenced to /CAS
tRCH
0
ns
8
Read command hold referenced to /RAS
tRRH
0
ns
8
Write command hold time
tWCH
10
ns
Write command pulse width
tWP
10
ns
Write command to /RAS lead time
tRWL
15
ns
Write command to /CAS lead time
tCWL
10
ns
Date-in set-up time
tDS
0
ns
9
Date-in hold time
tDH
10
ns
9
Refresh period
tREF
Write command set-up time
tWCS
0
ns
/CAS setup time (/CAS-before-/RAS referesh)
tCSR
5
ns
/CAS hold time (/CAS-before-/RAS referesh)
tCHR
10
ns
/RAS precharge to /CAS hold time
tRPC
5
ns
Access time from /CAS precharge
tCPA
Fast page mode cycle time
tPC
40
ns
/CAS precharge time (Fast page cycle)
tCP
10
ns
/RAS pulse width (Fast page cycle)
tRASP
60
/W to /RAS precharge time (C-B-R refresh)
tWRP
10
ns
/W to /RAS hold time (C-B-R refresh)
tWRH
10
ns
/CAS precharge (C-B-R counter test)
tCPT
20
ns
Hold time /CAS low to /CAS high
tCLCH
5
ns
Transcend Information Inc.
30
32
35
200K
ns
10
ns
ns
7
3
ns
11
32MB 72-PIN EDO
SIMM With 16Mx8 3.3VOLT
TS8MED3260G
Note: 1. An initial pause of 200us is required after power-up followed by any 8 /RAS-only or /CAS-before-/RAS
refresh cycles before proper device operation is achieved.
2. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Transition times are
measured between VIH(min) and VIL(max) and are assumed to be 5ns for all inputs.
3. Measured with a load equivalent to 2 TTL loads and 100pF.
4. Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a
reference point only. If tRCD is greater than the specified tRCD(max) limit, then access time is controlled
exclusively by tCAC.
5. Assumes that tRCDtRCD(max).
6. This parameter defines the time at which the output achieves the open circuit condition and is not
referenced to VOH or VOL.
7. tWCS is non-restrictive operating parameter. It included in the data sheet as electrical characteristics only.
If tWCStWCS(min), the cycle is an early write cycle and the data out pin will remain high impedance for the
duration of the cycle.
8. Either tRCH or tRRH must be satisfied for a read cycle.
9. These parameters are refernced to the /CAS leading edge in early write cycle.
10. Operation within the tRAD(max) limit insures that tRAC(max) can be me. tRAD(max) is specified as reference
point only. If tRAD is greater than the specified tRAD(max) limit, then access time is controlled by tAA.
11. In order to hold the address latched by the first /CAS going low, the parameter Tclch must be met.
Transcend Information Inc.