NTE6810 Integrated Circuit 128 x 8–Bit Static Random Access Memory (SRAM) Description: The NTE6810 is a byte–orgainzed memory in a 24–Lead DIP type package designed for use in bus– organized systems. It is fabricated with N–channel silicon–gate technology. For ease of use, this device operates from a single power supply, has compatibility with TTL and DTL, and needs no clocks or refreshing because of static operation. The memory is compatible with the 6800 Microcomputer Family, providing random storage in byte increments. Memory expansion is provided through multiple Chip Select inputs. Features: D Organized as 128 Bytes of 8–Bits D Static Operation D Bidirectional Three–State Data Input/Output D Six Chip Select Inputs (Four Active Low, Two Active High) D Single 5V Power Supply D TTL Compatible D Maximum Access Time: 450ns Absolute Maximum Ratings: Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 to +7V Input Voltage, Vin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 to +7V Operating Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0° to +70°C Storage Temperature Range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65° to +150°C Thermal Resistance, Junction to Ambient, RΘJA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +120°C/W Note 1. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage (e.g., either VSS or VCC). DC Electrical Characteristics: (VCC = 5V ±5%, VSS = 0, TA = 0° to +70°C unless otherwise specified) Parameter Symbol Test Conditions Min Max Unit VCC V Input High Voltage VIH VSS +2.0 Input Low Voltage VIL VSS –0.3 VSS +0.8 Input Current (An, R/W, CSn) Iin Vin = 0 to 5.25V V – 2.5 µA 2.4 – V Output High Voltage VOH IOH = –205µA Output Low Voltage VOL IOL = 1.6mA – 0.4 V Output Leakage Current (Three–State) ITSI CS = 0.8V or CS = 2V, Vout = 0.4V to 2.4V – 10 µA Supply Current ICC VCC = 5.25V, All other pins grounded – 80 mA Input Capacitance (An, R/W, CSn, CSn) Cin Vin = 0, TA = +25°C, f = 1MHz – 7.5 pF Output Capacitance (Dn) Cout Vout = 0, TA = +25°C, f = 1MHz, CSO = 0 – 12.5 pF Min Max Unit tcyc(R) 450 – ns Access Time tacc – 450 ns Address Setup Time tAS 20 – ns Address Hold Time tAH 0 – ns Data Delay Time (Read) tDDR – 230 ns Read to Select Delay Time tRCS 0 – ns Data Hold from Address tDHA 10 – ns tH 10 – ns Data Hold from Read tDHR 10 80 ns Read Hold from Chip Select tRH 0 – ns tcyc(W) 450 – ns Address Setup Time tAS 20 – ns Address Hold Time tAH 0 – ns Chip Select Pulse Width tCS 300 – ns Write to Chip Select Delay Time tWCS 0 – ns Data Setup Time (Write) tDSW 190 – ns tH 10 – ns tWH 0 – ns AC Operating Conditions and Characteristics: Parameter Symbol Read Cycle (VCC = 5V ±5%, VSS = 0, TA = 0° to +70° unless otherwise specified) Read Cycle Time Output Hold Time Write Cycle (VCC = 5V ±5%, VSS = 0, TA = 0° to +70° unless otherwise specified) Write Cycle Time Input Hold Time Write Hold Time from Chip Select Read Cycle Timing tcyc(R) tacc Address tAS tAH CS tDDR CS tRH tRCS R/W tDHA tDHR tH Data Valid Data In = Don’t Care Note 1. Voltage levels shown are VL ≤ 0.4V, VH ≥ 2.4V, unless otherwise specified. Note 2. Measurement pointas shown are 0.8V and 2.0V, unless otherwise specified. Note 3. CS and CS have same timing. Write Cycle Timing tcyc(W) Address tAS tCS tAH CS CS tWH tWCS R/W tDSW Data In tH Data in Stable = Don’t Care Note 1. Voltage levels shown are VL ≤ 0.4V, VH ≥ 2.4V, unless otherwise specified. Note 2. Measurement pointas shown are 0.8V and 2.0V, unless otherwise specified. Note 3. CS and CS have same timing. Pin Connection Diagram GND 1 24 VCC D0 2 23 A0 D1 3 22 A1 D2 4 21 A2 D3 5 20 A3 D4 6 19 A4 D5 7 18 A5 D6 8 17 A6 D7 9 16 R/W CS0 10 15 CS5 CS1 11 14 CS4 CS2 12 13 CS3 24 13 1 12 .520 (13.2) 1.300 (33.02) Max .225 (5.73) Max .100 (2.54) 1.100 (27.94) .126 (3.22) Min .600 (15.24)