NTE NTE861

NTE861
Integrated Circuit
Quad, Normally Open, SPST JFET
Analog Switch w/Disable
Description:
The NTE861 is a monolithic combination of bipolar and JFET technology producing a one chip quad
JFET switch. A unique circuit technique is employed to maintain a constant resistance over the analog voltage range of ±10V. The input is designed to operate from minimum TTL levels, and switch
operation also ensures a break–before–make action.
Features:
D Analog signals are not loaded
D Constant “ON” resistance for signals up to ±10V and 100kHz
D Pin compatible with CMOS switches with the advantage of blow out free handling
D Small signal analog signals to 50MHz
D Break–before–make action
D High open switch isolation at 1.0MHz
D Low leakage in “OFF” state
D TTL, DTL, RTL compatibility
D Single disable pin opens all switches in package
This device operates from a ±15V supply and swings a ±10V analog signal. The JFET switches are
designed for applications where a dc to medium frequency analog signal needs to be controlled.
Absolute Maximum Ratings:
Positive Supply–Negative Supply (VCC –VEE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36V
Reference Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VEE ≤ VR ≤ VCC
Logic Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VR –4.0V ≤ VIN ≤ VR +6.0V
Analog Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VEE ≤ VA ≤ VCC +6V; VA ≤ VEE +36V
Analog Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IA < 20mA
Power Dissipation (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500mW
Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0° to 70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65° to 150°C
Typical Thermal Resistance, Junction–to–Ambient, RthJA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85°C/W
Lead Temperature (Soldering, 10 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +300°C
Note 1 For operating at high temperature this device must be derated based on a +100°C maximum
junction temperature and a thermal resistance of +150°C/W.
Electrical Characteristics: (Note 2)
Parameter
“ON” Resistance
“ON” Resistance Matching
Analog Range
Leakage Current in “ON” Condition
Source Current in “OFF” Condition
Drain Current in “OFF” Condition
Symbol
RON
RON Match
Test Conditions
VA = 0, ID = 1mA
TA = +25°C
TA = +25°C
VA
IS(ON) +
ID(ON) +
Switch “ON”,
VS = VD = ±
±10V
TA = +25°C
IS(OFF)
Switch “OFF”,
VS = +10V, VD = –10V
TA = +25°C
ID(OFF)
TA = +25°C
Min
Typ
Max Unit
–
150
250
Ω
–
200
350
Ω
–
10
50
Ω
±10
±11
–
V
–
0.3
10
nA
–
3
30
nA
–
0.4
10
nA
–
3
30
nA
–
0.1
10
nA
–
3
30
nA
Logical “1” Input Voltage
VINH
2.0
–
–
V
Logical “0” Input Voltage
VINL
–
–
0.8
V
Logical “1” Input Current
IINH
–
3.6
40
µA
–
–
100
µA
–
–
0.1
µA
–
–
1.0
µA
Logical “0” Input Current
IINL
VIN = 5V
VIN = 0.8V
TA = +25°C
TA = +25°C
Delay Time “ON”
tON
VS = ±10V, TA = +25°C
–
500
–
ns
Delay Time “OFF”
tOFF
VS = ±10V, TA = +25°C
–
90
–
ns
Break–Before–Make
tON – tOFF
VS = ±10V, TA = +25°C
–
80
–
ns
Source Capacitance
CS(OFF)
Switch “OFF”, VS = ±10V, TA = +25°C
–
4.0
–
pF
Drain Capacitance
CD(OFF)
Switch “OFF”, VD = ±10V, TA = +25°C
–
3.0
–
pF
Active Source and Drain
Capacitance
CS(ON) +
CD(ON) +
Switch “ON”, VS = VD = ±10V,
TA = +25°C
–
5.0
–
pF
“OFF” Isolation
ISO(OFF)
TA = +25°C, Note 3
–
–50
–
dB
Crosstalk
CT
TA = +25°C, Note 3
–
–65
–
dB
Analog Slew Rate
SR
TA = +25°C, Note 4
–
50
–
V/µs
Disable Current
IDIS
Note 5
–
0.6
1.5
mA
–
0.9
2.3
mA
–
4.3
7.0
mA
–
6.0
10.5
mA
–
2.7
5.0
mA
–
3.8
7.5
mA
–
7.0
9.0
mA
–
9.8
13.5
mA
Negative Supply Current
Reference Supply Current
Positive Supply Current
IEE
IR
ICC
All Switches “OFF”,
VS = ±
±10V
TA = +25°C
TA = +25°C
TA = +25°C
TA = +25°C
Note 2. VCC = +15V, VEE = –15V, VR = 0V, and limits apply for –25°C ≤ TA ≤ +85°C unless otherwise
specified.
Note 3. These parameters are limited by the pin to pin capacitance of the package.
Note 4. This is the analog signal slew rate above which the signal is distorted as a result of finite internal
slew rates.
Note 5. All switches in the device are turned “OFF” by saturating a transistor at the disable node.
The delay times will be approximately equal to the tON or tOFF plus the delay introduced by
the external transistor.
Pin Connection Diagram
Input 1 1
16 Input 4
D1 2
15 D 4
S1 3
14 S 4
VR 4
13 Disable
(–) VEE 5
12 (+) VCC
S2 6
11 S 3
D2 7
10 D 3
Input 2 8
9 Input 3
16
9
1
8
.870 (22.0) Max
.260 (6.6)
Max
.200 (5.08)
Max
.100 (2.54)
.700 (17.78)
.099 (2.5) Min