TECHNICAL DATA ILA8138A 5.1V +12V REGULATOR WITH DISABLE AND RESET The ILA8138A is a monolithic dual positive voltage regulator designed to provide fixed precision output voltages of 5.1V and 12V at currents up to 1A. Output 2 can be disabled by TTL input. Short circuit and thermal protections are included in all the versions. • • • • • • • • TO-220AB/7 Output currents up to 1 A Fixed precision OUTPUT 1 voltages 5.1 V ± 2% Fixed precision OUTPUT 2 voltages 12 V ± 2% OUTPUT 1 with RESET facility OUTPUT 2 with DISABLE by TTL input Short circuit protection at both outputs Thermal protection Low drop output voltage HEPTAWAT (Plastic Package) ORDERING INFORMATION ILA8138A Plastic Package IZ8138A chip TJ = -0° to 130°C PIN ASSIGNMENT 7 6 5 OUTPUT 1 4 3 GROUND DISABLE 2 INPUT 2 1 INPUT 1 OUTPUT 2 N.C. BLOCK DIAGRAM INPUT 1 INPUT 2 2 1 REFERENCE OUT 1 7 OUT 1 OUT 2 6 OUT 2 PROTECTION DISABLE 3 DISABLE 4 INTEGRAL 1 ILA8138A MAXIMUM RATINGS * Symbol Parameter Min Max Unit VIN1 DC Input Voltage Pin 1 0 20 V VIN2 DC Input Voltage Pin 2 0 20 V VDIS Disable Input Voltage Pin 3 0 20 V IO1,2 Output Currents 0 1.6 A Tstg Storage Temperature -65 150 °C TJ Junction Temperature 0 150 °C Min Max Unit * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. RECOMMENDED OPERATING CONDITIONS Symbol Parameter VIN1 DC Input Voltage Pin 1 7.0 16 V VIN2 DC Input Voltage Pin 2 14 18 V VDIS Disable Input Voltage Pin 3 0 7.0 V IO1,2 Output Currents 0 1.6 A Junction Temperature 0 130 °C TJ THERMAL DATA Symbol Rth (j-c) Rth (j-a) Parameter Maximum Thermal Resistance Junction-case Maximum Thermal Resistance Junction-ambient INTEGRAL Vlalue Unit 6 o 60 o C/W C/W 2 ILA8138A ELECTRICAL CHRACTERISTICS (VIN1 = 7 V, VIN2 = 14 V, TJ = 25°C, unless otherwise specified) Symbol VO1 Parameter Guaranteed Limit Test Conditions Output Voltage Unit Min Max 5.0 5.2 V 11.76 12.24 V VIN1 = 7 V, IO1= -10 mA VO2 VIN1 = 7 V, VIN2 = 14 V, IO2= -10 mA VO1 -5 mA ≤ IO2 ≤ -750 mA, 7 V ≤ VIN1 ≤ 14 V 4.9 5.3 V VO2 -5 mA ≤ IO2 ≤ -750 mA, 14 V ≤ VIN2 ≤ 18 V, VIN1 = 7 V 11.5 12.5 V 7 V ≤ VIN2 ≤ 14 V, IO1 = -200 mA 50 mV 14 V ≤ VIN2 ≤ 18 V, IO1 = -200 mA, VIN1 = 7 V 120 VIN1 = 7 V, -5 mA ≤ IO1 ≤ -0.6 mA 100 VIN1 = 7 V, VIN2 = 14 V, -5 mA ≤ IO2 ≤ -0.6 mA 250 VIN1 = 7 V, IO1 = -750 mA 1.4 VIN1 = 7 V, IO1 = -1.0 mA 2.0 VIN1 = 7 V, VIN2 = 14 V, IO1 = -750 mA 1.4 VIN1 = 7 V, VIN2 = 14 V, IO1 = -1.0 mA 2.0 ∆ VO1 LI Line Regulation ∆ VO2 LI ∆ VO1 LO Load Regulation ∆ VO2 LO VIO1 VIO2 Dropout Voltage Dropout Voltage mV V V IQ Quiescent Current VIN1 = 7 V, VIN2 = 14 V, VDIS = 0.8 V, IO1= -10 mA 2.0 mA IO1,2 SC Short Circuit Output Current VIN1 = 7 V, VIN2 = 14 V 1.6 A VIN1 = 16 V, VIN2 = 16 V 1.0 IDIS Disable Bias Current 0 V ≤ VDIS ≤ 7 V, VIN1 = 7 V, VIN2 = 14 V -100 VDISH Disable Voltage High (out 2 active) VIN1 = 7 V, VIN2 = 14 V 2 VDISL Disable Voltage Low (out 2 disabled) VIN1 = 7 V, VIN2 = 14 V 2.0 µA V 0.8 V TYPICAL APPLICATION C1 to C4 = 10 µF NC (05) INPUT 1 (01) OUTPUT 1 (07) ILA8138A INPUT 2 (02) OUTPUT 2 (06) C3 C1 C4 C2 DISABLE (03) GROUND (04) INTEGRAL 3 ILA8138A INTEGRAL 4 ILA8138A CHIP PAD DIAGRAM Chip marking 8138 20 09 06 07 08 10 2.0 + 0.03 11 12 01 02 03 04 05 Y (0,0) 2.4 + 0.03 X Location of marking (mm): left lower corner x=0.100, y=1.854. Chip thickness: 0.35 ± 0.02 mm. PAD LOCATION Pad No Symbol 01 02 03 04 05 06 07 08 09 10 11 12 GND OUTPUT 2 OUTPUT 1 INPUT 1 INPUT 2 DISABLE - Location (left lower corner), mm X Y 0.105 0.740 0.105 0.425 0.105 0.110 0.825 0.110 2.110 0.110 2.110 1.675 0.795 1.635 0.505 1.605 0.110 1.605 0.105 1.385 0.105 1.205 0.105 1.025 Pad size, mm 0.18 x 0.18 0.18 x 0.18 0.18 x 0.18 0.18 x 0.18 0.18 x 0.18 0.18 x 0.18 0.18 x 0.18 0.18 x 0.18 0.18 x 0.18 0.10 x 0.10 0.10 x 0.10 0.10 x 0.10 Note: Pad location is given as per passivation layer INTEGRAL 5