FEDL7050LA-02 1Semiconductor ML7050LA This version: June 2001 Previous version: Sep. 2000 Bluetooth RF Transceiver IC GENERAL DESCRIPTION The Oki ML7050LA is a highly integrated BluetoothTM radio transceiver designed to operate in the global 2.4 GHz Industrial, Scientific, and Medical (ISM) band. The ML7050LA architecture incorporates vital intermediate frequency (IF) and radio frequency (RF) circuits on a low cost, integration-friendly bulk CMOS process. Bluetooth technology directly supports short range, wireless voice and data communications with 1 Mbps throughput performance in the public ISM band across many applications, employing rapid frequency hopping (1.6K hops/s) spread spectrum (FHSS) approach. The ML7050LA highly integrated CMOS Bluetooth RF transceiver LSI will establish a 2.4 to 2.5 GHz communication link compliant with Bluetooth Specification Version 1.1 and is packaged in the Oki 48-pin ball grid array (BGA) package requires only 7 mm x 7 mm of the systems critical board space. Oki’s Bluetooth LSI family includes baseband LSI (ML70511LA), System Development Kit (BT-SDK), firmware and software (BTS Pack1/2/3). Together, the RF LSI (ML7050LA) and baseband (ML70511LA) devices form a complete hardware solution optimized for low system cost, small form factor, and reduced power consumption Bluetooth applications. FEATURES • Circuit design based on the Bluetooth Specification Version 1.1. • CMOS process technology lowers system cost and simplifies future baseband integration • Fully integrated CMOS RF LSI: TX/RX switch, power amplifier, LNA, image rejection mixer, VCO, PLL, gmC IF filter, modulator, and demodulator. • Low IF circuitry eliminates off-chip SAW filter reducing bill-of-material (BOM) • Class 2 power operation compliant covering a wide range of applications • Seamless interface with Oki’s ML70511LA Bluetooth baseband controller LSI • Power supply voltage: 2.7 to 3.3 V • Package: 48-pin BGA (7 mm x 7 mm x 1.41mm) BLUETOOTH is a trademark owned by Bluetooth SIG, Inc. and licensed to Oki Electric Industry. The information contained herein can change without notice owing to the product being under development. 1/16 FEDL7050LA-02 1Oki Semiconductor ML7050LA BLOCK DIAGRAM LIM_C1 Tune_C LNA IRM LIM_C2 Limiting AMP IF BPF LPF_C DEMOD Gm-C Tuning RXD (SW Control) TX_POW RX_POW PLL_POW SW RF_Ant PLL PLL_CLK PLL_DATA PLL_LE PLL_OFF Loop Filter Vdd_PA Vdd_VCO Vdd_PLL Vdd_IF Vdd_IRM_LO Vdd_IRM GND PA PLL_LF2 Vdd_LNA Gaussian Filter VCO AMP SW GND_D PLL_LF1 MCLK TXD Vdd_D ABSOLUTE MAXIMUM RATINGS Parameter Power supply voltage Symbol Conditions Rating Unit VDD Ta = 25°C –0.3 to 4.5 V Input voltage VI –0.3 to VDD +0.3 V Allowable power dissipation PD - 0.5 W TSTG - –55 to +150 °C In-Band TBD dBm - Out-of-Band TBD dBm Storage temperature Input RF Power RECOMMENDED OPERATING CONDITIONS Symbol Conditions Min. Typ. Max. Unit Power supply voltage Parameter VDD - 2.7 3.0 3.3 V Full specification range Ta - 0 - 55 Operating temperature range Ta - –20 - +85 2/16 °C FEDL7050LA-02 1Oki Semiconductor ML7050LA ELECTRICAL CHARACTERISTICS (VDD = 3.0V, Ta = 0 to +55°C) Symbol Description Conditions Min. Typ. Max. Unit Digital Inputs Vih Digital input high 2.4 VDD+0.3 V Vil Digital input low -0.3 0.4 V 2.2 3.6 V 0 0.8 V - MHz Digital Outputs Voh Digital output high Ioh=-2mA Vol Digital output low Iol=2mA Clock MCLK Master clock frequency - 12.13, 16 Current Consumption IDDO IDDS Ta=25°C Receive Mode - 55 - mA Transmit Mode - 34 - mA PLL Mode TX and RX disabled - 22 - mA Standby Mode VDD applied and power control pins disabled - 10 - uA Receiver FRF RF Frequency RIN Reception sensitivity 2.4 Includes ANT BPF loss, 2.5 GHz –75 dBm –20 dBm Note 1 - Maximum Received Signal - Spurious level ZIN 30 MHz to 1 GHz –57 dBm 1 GHz to 12.75 GHz –47 dBm Input VSWR RF Input impedance SW in 2:1 - 50 Ω Transmitter fRF RF Frequency PO RF Output power fRF = 2.4 to 2.5 GHz, 2.4 2.5 GHz 4 dBm — Carrier frequency tolerance initial accuracy (static) -75 75 KHz fstab1 fstab2 Frequency drift(1 slot packet) -25 25 KHz Frequency drift(3 slot packet) -40 40 KHz fstab3 Frequency drift(5 slot packet) -40 0 Maximum frequency drift rate — Power stability — Modulation index — In-band spurious level over temp 0.28 2 40 KHz 400 Hz/µs TBD dBm 0.35 - ±500 kHz –20 dBm Offset = 2 MHz –20 dBm Offset > 3 MHz –40 dBm 3/16 FEDL7050LA-02 1Oki Semiconductor — — ZOUT Out-of-band spurious level ML7050LA 30 MHz to 1 GHz –36 dBm 1 GHz to 12.75 GHz –30 dBm 1.8 GHz to 1.9 GHz –47 dBm 5.15 GHz to 5.3 GHz –47 dBm Output VSWR RF Output impedance SW out 2:1 - 50 Ω @550 kHz –103 dBc/Hz @2 MHz –120 dBc/Hz PLL — Phase noise — PLL lock-up time - 4/16 - 150 µs FEDL7050LA-02 1Oki Semiconductor ML7050LA PIN LAYOUT (TOP VIEW) A1 ball corner 1 Gnd 2 Vdd_ LNA 3 Vdd_ IRM 4 5 Vdd_ IRM_LO Test3 6 7 8 Test4 PLL_ POW TXD TX_POW Test1 Test2 A RF_Ant Gnd RX_POW Gnd Gnd Gnd Gnd Lim_C1 Lim_C2 Vdd_PA Test7 Gnd Tune_C Vdd_ VCO Test8 Vdd_IF Test6 Test5 Gnd Gnd LPF_C PLL_ LF1 Gnd PLL_ CLK Gnd_D PLL_ OFF PLL_ LF2 Vdd_ PLL PLL_ DATA B C D E F MCLK GND Test9 RXD Vdd_D G PLL_LE H TOP VIEW 5/16 Vdd_IF Test10 FEDL7050LA-02 1Oki Semiconductor ML7050LA PIN DESCRIPTION Pins for RF Function No. Pin Name I/O Description B1 RF_Ant I/O D8 Tune_C I Gm-C tuning components - Connect capacitors and resister between D8 and GND C7 C8 Lim_C1 Lim_C2 I Limiting amplifier capacitors - Connect capacitors between pins and GND F8 LPF_C I Low pass filter (LPF) capacitor - Connect capacitor between F8 and GND G1 H1 PLL_LF1 PLL_LF2 — RF connection to external BPF (antenna filter) External components for loop filter tuning: PLL_LF1 - Connect to VCO PLL_LF2 - Connect to PLL Pins for TEST Interface, etc. G4 MCLK I B7 Test1 I/O B8 Test2 I/O A5 Test3 I A6 Test4 I Master clock (12MHz, 13MHz or 16MHz) - CMOS level Test pins - Connect to GND F1 Test5 O No connect - Open E8 Test6 O No connect - Open D2 E2 Test7 Test8 O Test pins - Connect to GND G6 Test9 O No connect - Open H8 Test10 I/O No connect - Open Pins for Power Supply and Ground H6 Vdd_D — Power supply (VDD)- Digital; 3.0V+/-0.3V (from regulated voltage source) G7 GND_D — Common Ground - Digital D1 Vdd_PA E1 Vdd_VCO A2 Vdd_LNA H2 Vdd_PLL A3 Vdd_IRM A4 Vdd_IRM_LO E7, H7 Vdd_IF A1/B2 B4/B5 C1/C2 D7/F2 F7/G2 G5 GND — — Power supply (VDD) - Analog; 3.0V+/-0.3V (from regulated voltage source) Common ground (GND) - Analog 6/16 FEDL7050LA-02 1Oki Semiconductor ML7050LA Pins for the Interface Between the RF LSI and the Baseband LSI No. Pin Name I/O Description A8 TXD I Transmit (TX) data - CMOS level H5 RXD O Receive (RX) data - CMOS level H3 PLL_DATA I PLL setup data: 6 Mbps <= PLL DATA <= 10 Mbps G3 PLL_CLK I PLL clock setup: 6 MHz <= PLL CLK <= 10 MHz H4 PLL_LE I G8 PLL_OFF I A7 PLL_POW I PLL load enable setup: Data latched : ‘High’ 100 nsec <= PLL LE PLL Open-loop/Closed-loop mode control: Closed loop mode (receive): ‘High’ Open loop mode (transmit) : ‘Low’ PLL power supply control switch: PLL Power ON : ‘Low’ PLL Power OFF :’ High’ B6 TX_POW I Transmitter (TX) power supply control switch: TX ON (transmit) : ‘Low ‘ TX OFF(receive) : ‘High’ B3 RX_POW I Receiver (RX) power supply control switch: RX ON (receive) : ‘Low’ RX OFF (transmit) : ‘High’ Modes of Operation By setting or transitioning control pins, the device will enter into various modes of operation including receive, transmit, and standby. Mode PLL_POW TX_POW RX_POW Receive 0 1 0 Transmit 0 0 1 PLL 0 1 1 Standby 1 1 1 7/16 FEDL7050LA-02 1Oki Semiconductor ML7050LA PIN CONNECTION DIAGRAM Tune_C Lim_C1 Lim_C2 10 nF 1 nF 3 kΩ LNA IRM 33 nF 33 nF Limiting AMP IF BPF LPF_C 0.1 µF 33 nF DEMOD RXD Gm-C Tuning BPF (for Ant) RF_Ant TX_POW RX_POW PLL_POW (SW Control) SW PLL GND PLL_CLK PLL_DATA PLL_LE PLL_OFF Loop Filter 0.1 µF for each PA Gaussian Filter VCO AMP SW TXD (for Local) Vdd_PA Vdd_VCO Vdd_PLL Vdd_LNA Vdd_IRM_LO Vdd_IRM 0.1 µF 100 pF 66kΩ 33kΩ 47pF 470pF GND Vdd_IF NM PLL_LF2 MCLK 0.1µF 12MHz, 100 pF ~ 13MHz or 16MHz PLL_LF1 Vdd_D GND_D The externally connected components shown are tentative (April 2001). * The circuit is subject to change according to the specific board design. Please contact Oki Electric Industry Co., Ltd. for detailed information. The ML7050LA provides a low bill-of-material (BOM) Bluetooth solution by minimizing external components. The design incorporates numerous internal tuning circuits using Gm-C and other leading-edge technologies to reliably control phase lock loop (PLL), VCO, amplifiers, modulator, and demodulator circuits. The TX-POW, RX_POW, PLL_POW, PLL-CLK, PLL_DATA, PLL_LE, PLL_OFF, RXD, and TXD connect directly to the complementary Bluetooth baseband (ML70511LA) device. 8/16 FEDL7050LA-02 1Oki Semiconductor ML7050LA DESCRIPTION OF INTERNAL BLOCKS • Transmit filter (Gaussian filter): The input data is converted into a frequency modulation signal by a filter with Gaussian characteristics and is sent to the VCO. • Frequency control section (VCO, PLL, Loop Filter, AMP and SW): Generates a frequency in the 2.4 GHz to 2.5 GHz band (ISM band). During transmission, the VCO oscillator frequency is modulated by the modulation signal output by the Gaussian filter. The PLL frequency is controlled by the signals PLL_DATA, PLL_CLK, and PLL_LE. The switch SW (for Local) distributes the oscillator output to the transmitter circuit and the receiver circuit depending on the control signal (TX_POW/RX_POW). • Power amplifier (PA): This is the power amplifier for the transmitter. • Transmit/Receive selection switch (SW for Ant) Depending on the control signal (TX_POW/RX_POW), this switch feeds the output of the power amplifier to the antenna during transmission. During reception, the received signal of the antenna is fed to the LNA. • Reception amplifier (LNA): This amplifies the weak RF received signal from the antenna. • Image Rejection Mixer (IRM): Converts the output signal from the LNA (2.4 to 2.5 GHz) into an intermediate frequency and also eliminates the image frequency component. • IF Band pass filter (IF BPF): Removes the signal of the nearby bands. • Limiting amplifier: Amplifies the signal converted into the intermediate frequency up to a specific amplitude. • Demodulator (DEMOD): The received signal is demodulated using the delay detector circuit. • Filter tuning (Gm-C Tuning): The reference clock is compared with the oscillator frequency inside the tuning circuit, and the frequency characteristics of the Gm-C filter is adjusted automatically. 9/16 FEDL7050LA-02 1Oki Semiconductor ML7050LA PLL METHODOLOGY Reference crystal oscillator Programmable Divider To Mixer Charge pump And Loop Filter Phase Frequency Detector Programmable Counter Data Clock LE LC Tank VCO Prescaler Swallow Counter 10/16 Buffer Switch To PA FEDL7050LA-02 1Oki Semiconductor ML7050LA PLL Computation Method Fvco MxN+A Fosc R (0 <= A<=31) (M × N + A denotes (M - A) × 32 + A × 33) R: Reference counter set value N: Programmable counter set value A: Swallow counter set value PLL Reference Counter Freq R (MHz) (Dec) R(Bin) R4 R3 R2 R1 R0 5 5 0 0 1 0 1 6 6 0 0 1 1 0 7 7 0 0 1 1 1 8 8 0 1 0 0 0 9 9 0 1 0 0 1 10 10 0 1 0 1 0 11 11 0 1 0 1 1 12 12 0 1 1 0 0 13 13 0 1 1 0 1 14 14 0 1 1 1 0 15 15 0 1 1 1 1 16 16 1 0 0 0 0 17 17 1 0 0 0 1 18 18 1 0 0 1 0 19 19 1 0 0 1 1 20 20 1 0 1 0 0 Programmable Counter and Swallow Counter F.step 1 MHz M 32 div (RX PLL Frequency) = (TX PLL Frequency) – 2MHz * In receive mode, PLL generates local frequency for IRM. Intermediate frequency is 2MHz. Freq. N (MHz) (Dec) A N(Bin) (Dec) A(Bin) N6 N5 N4 N3 N2 N1 N0 A4 A3 A2 A1 A0 2397 74 29 1 0 0 1 0 1 0 1 1 1 0 1 2398 74 30 1 0 0 1 0 1 0 1 1 1 1 0 2399 74 31 1 0 0 1 0 1 0 1 1 1 1 1 2400 75 0 1 0 0 1 0 1 1 0 0 0 0 0 2401 75 1 1 0 0 1 0 1 1 0 0 0 0 1 11/16 FEDL7050LA-02 1Oki Semiconductor 2402 ML7050LA 75 2 1 0 0 1 0 1 1 0 0 0 1 0 : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 2496 78 0 1 0 0 1 1 1 0 0 0 0 0 0 2497 78 1 1 0 0 1 1 1 0 0 0 0 0 1 2498 78 2 1 0 0 1 1 1 0 0 0 0 1 0 2499 78 3 1 0 0 1 1 1 0 0 0 0 1 1 2500 78 4 1 0 0 1 1 1 0 0 0 1 0 0 12/16 FEDL7050LA-02 1Oki Semiconductor ML7050LA PLL Set-up Time Chart 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 1 2 3 4 5 6 CTL R4 R3 R2 R1 R0 7 8 9 10 11 12 13 14 15 16 17 18 19 CTL N6 N5 N4 N3 N2 N1 N0 A4 A3 A2 A1 20 21 CLK DATA MSB A0 LSB LE Reference counter setting duration Programmable counter and swallow counter setting duration R4 to R0: Binary 5-bit reference counter (5-20) N6 to N0: Programmable counter (7 bits) See "PLL Setting method”. A4 to A0: Swallow counter (0-31) (5 bits) See "PLL Setting method”. CTL: When CTL is "H", the input data is handed over to the reference counter register. When CTL is "L", the input data is handed over to the programmable and swallow counter register. Note: Start data input from the MSB. 13/16 FEDL7050LA-02 1Oki Semiconductor ML7050LA SYSTEM OVERVIEW VDD VDD Antenna 2.4 to 2.5 GHz ~ ~ ~ ML7050LA Band-pass Filter Control Signal TXD ML70511LA USB or UART Host System USB or UART RXD GND GND OSC Together, RF (ML7050LA) and baseband (ML70511LA) devices form a complete hardware solution optimized for low system cost, small form factor, and reduced power consumption wireless applications. The ML70511LA baseband IC controls the ML7050LA frequency selection, tuning characteristics, and control functions through writing to internal registers. ML7050LA can then read-back the register information to ML70511LA insuring proper modes of operation. The communication between the devices occurs on Oki’s proprietary, low pin count serial interface. The connection between a host controller or processor and the baseband device is implemented via USB (version 1.1) or UART. Power Supply The analog power supply (VDD) voltage is connected to pins serving each analog functional blocks (Vdd_PA, Vdd_LNA, Vdd_VCO, Vdd_PLL, Vdd_IF, Vdd_IRM and Vdd_IRM_LO). A separate digital power supply voltage is required by the digital section. Each of the analog power supply voltage should be supplied from regulated voltage source and should be low-frequency de-coupled by external blocking capacitors. Ground In order to minimize electrical noise and other interference, the ground plane should be distributed with low impedance characteristics including underneath the ML7050LA. Connect all GND pins to the ground plane. 14/16 FEDL7050LA-02 1Oki Semiconductor ML7050LA PACKAGE DIMENSIONS (48-PIN BGA) (Unit: mm) 0.70 REF 0.80 NON ACUMULATIVE 7.0 Index Mark 0.50 TYP 7.0 0.70 REF 0.40 REF 15/16 1.41 TYP FEDL7050LA-02 1Oki Semiconductor ML7050LA NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party’s right which may result from the use thereof. 6. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. No part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 2001 Oki Electric Industry Co., Ltd. 16/16