Features • • • • • • • • • • • • • • • • • Single-chip 3.5GHz WiMAX Transceiver Fully Differential Design Low-IF/Zero-IF Transceiver Architecture; Requires No External Filters Self Calibration Mode for RX / TX Filters Support Channel Bandwidths of 3.5, 5.0, 7.0, 8.75MHz, and 10MHz Modulation up to 64QAM Ultra-fast Fractional-N Synthesizer Sensitivity < -74 dBm at 64-QAM, CR=¾, 7MHz BW Phase Noise Synthesizer: 0.8° (-37dBc) Low Supply Voltage: 3.0 V TX Output PRF: 0 dBm, -34 dB EVM RX/TX Operating Current: 270/315mA Typical Low Power Off Current: < 20µA Typical 56-lead QFN Package Low External Component Count Integrated Self IQ Calibration (no external components or control) HFDD Support Applications • 3.5 GHz Band Wireless Communication Devices • IEEE® 802.16-2004 Radios • Supports OFDM up to 64QAM 3.5GHz WiMAX Transceiver AT86RF535B Preliminary Description Atmel’s AT86RF535B is a fully integrated, low cost RF 3.5GHz Low-IF/Zero-IF conversion transceiver for WiMAX applications. It combines excellent RF performance, small size, and low current consumption. The AT86RF535 chip is fabricated on the advanced SiGe BiCMOS process AT46000. The transceiver combines LNA, PA driver, RX/TX mixer, RX/TX filters, VCO, Synthesizer, RX Gain control, and TX Power control, all fully digitally controlled. Only a minimum number of external components are required. 5190A–WiMAX–4/07 Figure 1. AT86RF535B Block Diagram TX Power Control RX Gain Control I LNA Q Synthesizer I Driver Q Config Register 2 CLK AT86RF535B [Preliminary] 5190A–WiMAX–4/07 AT86RF535B [Preliminary] Quick Reference Data Table 1. Quick Reference Data Symbol FRF DFRS VDD IDDRX IDDTX IDDSYN Parameter Input Center Frequency Frequency Resolution Supply Voltage Supply Current Supply Current Supply Current IDDSTB Supply Current SENS Sensitivity QPSK Sensitivity 64QAM PRF TX Output Power Integrated Phase Noise of Synthesizer Operating Ambient Temperature PN TAMB Note: Conditions Min 3.4 Typ Applied to VDD pins Receive mode Transmit mode, -5dBm, incl. Balun Synthesizer Mode Stand By Mode, CLK driver activated Clock Load 20pF BW=3.5MHz, CR=½, S/N=9.4dB BW=7MHz, CR=¾, S/N=24.4dB FRF= 3.5 GHz, 15dB back off for 64QAM, EVM=-34dB, incl. Balun Integrated over Frequency Range 50kHz … 1MHz 3.0 3.3 270 315 135 Max 3.8 19.6 3.6 2.5 -92 -74 -30 Unit GHz Hz V mA mA mA mA -88 -70 dBm 0 dBm 0.8 deg rms 27 +70 °C Max Unit 3.8 GHz All voltages are referred to GND. VDD=3.0V TAMB=27°C, unless otherwise noted. Electrical Characteristics Table 2. Receiver Characteristics (Note 1) Symbol Parameter FRF Input Center Frequency Differential Impedance at LNA Input Sensitivity QPSK 1/2 Sensitivity 64QAM 3/4 Maximum Input Power Noise Figure Single Side Band RX Chain: Gain Steps RX Chain: Gain Range Conditions Min Typ System ZIN SENS PIN,MAX NFSSB GRX,STEP GRX,RANGE tRX/TX Symbol ACR±1 ACR±2 ROUT COUT VOMAX 3.4 Includes a matching inductor and two series capacitors BW=3.5MHz, S/N=9.4dB BW=7MHz, S/N=24.4dB BW=7MHz, EVM=24.4dB high gain mode, includes balun w/o Frontend loss Ω diff. 100 -90 -69 -20 TDD Mode HFDD Mode Parameter Conditions Min System 16QAM 3/4 Adjacent Ch. Rejection 64QAM 3/4 Nonadjacent Ch. 16QAM 3/4 Rejection 64QAM 3/4 Baseband filters, DC cancellation, RSSI, IQ outputs Output load resistance Pin to GND 1 Output load capacitance Pin to GND Maximum Output Voltage Differential 1 dBm dBm 5 6 0.76 95.5 RX to TX Switching Time Typ dB dB 5 50 Max -11 -4 -30 -23 20 dB 50 µs Unit dB dB MΩ pF V 3 5190A–WiMAX–4/07 Nominal I or Q output Voltage VOUT GB,OFFSTEP GB,RANGE I, Q output buffer: Gain Offset Steps I, Q output buffer: Gain Range BW3dB 3-dB Bandwidth of Filter IMRR Image Rejection Ratio FIF Low-IF Frequency CMD Common Mode IQ Voltage Table 3. Differential at the load specified Output buffer gain offset = 0dB Backoff –15dB relative to I or Q 0.141 Vrms 0.76 dB -9 +2.25 Low-IF Center Frequency: 1.875 MHz 2.7 MHz 3.75 MHz 5.0 MHz Note2 Note 2 5.0 7.0 8.75 Note 2 2.0 4.0 dB 3.5 -42 1.2 MHz -36 dB MHz 1.25 1.35 V DC Typ Max Unit 3.8 GHz Transmitter Characteristics (Note 1) Symbol Parameter Conditions Min System FRF Output Center Frequency Differential Impedance at Driver Output TX Output Power ZOUT POUT TX to RX Switching Time tTX/RX GPA,RANGE GLSB,STEP 3-dB Bandwidth of Filter LCarr Carrier Leakage IMRR Image Rejection Ratio EVM ZIN VIN VIN,DC Error Vector Magnitude IQ Input Impedance IQ Input Voltage DC Input Voltage Ω diff 100 For 64QAM modulated signals TDD Mode HFDD Mode TX Chain Gain Control Range TX Chain Gain Control LSB Step Size BW3dB Notes: 3.4 0 50 Low-IF Center Frequency: 1.875 MHz 2.7 MHz 3.75 MHz 5.0 MHz Note2 Referred to sub carrier level of 64QAM modulated signals Note 2, 3 Referred to sub carrier level of 64QAM modulated signals Note 2, 3 64QAM ¾, 0dBm Output Power Differential Peak, Differential dBm 5 50 µs 71.9 dB 0.76 dB 3.5 5.0 7.0 8.75 MHz -20 -12 dBc -49 -45 dBr -34 dB kΩ diff Vp,diff V 10 1 1.25 1. VDD=3.0V, TAMB =27°C, FRF=3.55 GHz, specific application circuit TBD, unless otherwise noted. 2. Internally adjusted by build-in self-calibration. 3. ETSI Mask Compliant 4 AT86RF535B [Preliminary] 5190A–WiMAX–4/07 AT86RF535B [Preliminary] Functional Description The AT86RF535B is based on the IEEE 802.16-2004 standard. This product will provide transmit, receive, and frequency synthesis functions using the OFDM modulation schemes, as defined in the above specifications. The AT86RF535B consists of a frequency-agile RF transceiver intended for use in 3.5-GHz licensed bands at data rates up to 26Mbps. Configuration and control registers and a bi-directional data communications interface are available to communicate with existing baseband devices from different vendors. The AT86RF535B addresses the requirements of base station (BS) as well as subscriber stations (SS) equipment. The device will operate down to 3.0V. The AT86RF535 is fabricated in Atmel’s AT46000 advanced SiGe BiCMOS process technology and is assembled in a 8mm x 8mm 56-lead QFN package. RX Path The differential low noise amplifier (DLNA) makes use of a differential bipolar stage with resistive emitter linearization. For digital gain control operation the DLNA supports the four gain modes 0, 6, 12, and 18dB. The linearity improves as the gain is reduced. The differential inphase quadrature phase mixer (IQMIX) utilizes a differential bipolar stage with emitter degeneration for the best linearity performance. A complex driving LO source is chosen for optimal LO leakage cancellation. The IQMIX has 4, 10, 16, and 22dB of switchable gain. The receive poly phase filter (RXPPF) is designed as a frequency shifted leapfrog structure. The filter provides three different bandwidths at three different center frequencies. The bandwidth of this filter is tuned by a built-in self-test (BIST). The PPF filter cap values are automatically adjusted upon power-up. The cap tuning can be recalled via SPI. Image rejection is also calibrated upon request via SPI. There are also three digitally controlled gain amplifiers (DGA1-3) available to provide the necessary amplification for the receive signal. Each stage supports the four gain modes 0, 6, 12, and 18dB, respectively. An additional fine gain stage DGB enables gain tuning of approximately ± 6dB in 0.76 dB steps. An output buffer with gain offset matches the voltage swing of the radio to the respective Baseband input stage. The gain control is complete digital and affects LNA, MIX, and the three DGAs by using the same granularity for each stage. The BB/MAC provides the gain vector at a separated serial interface. Fast TX/RX switching is possible via TX/RX switch input pins controlled by BB/MAC. The low-IF conversion receiver does not have to amplify DC signals, but the gain setting process produces different offsets in gain stages. An offset correction takes place after each gain step in the receiver to prevent signal saturation. Every stage has an individual offset correction circuit to maintain the correct overall dynamic range. The DC feedback (DCFB) works as an output offset compensation network, which depends on actual gain setting. The internal gain control operation is optimized for fixed target amplitude. To adapt to different application requirements, the IQ Output Buffer DGB has a programmable gain offset from – 1.5dB to 6dB in increments of 0.76dB. This allows the nominal output voltage to be set between 180mVp and 650mVp. The gain is controllable via the register setting. The IQOB is able to drive 5 5190A–WiMAX–4/07 a capacitive load on all four-output ports (RXI1, RXI2, RXQ1, RXQ2). The CMD pin is available to provide the common mode voltage of the Digital Output Buffer (DGB). TX Path The transmit low pass (TXLP) filter is band limited to meet the emission regulation for OFDM signals. The data signals to the four input ports (TXI1, TXI2, TXQ1, TXQ2) driving the TXLP should be digital but with defined levels. The complex filtered BB signal is up converted with IQ low-IF up converter (IQUC). A complex driving LO source is used to minimize LO leakage. The output currents of the two mixer stages are added together. The resulting signal drives the power amplifier control block (PAC). PAC is a Gilbert cell based current domain amplifier with the gain controlled by DC voltage across the mixer core. In that way linear to logarithmic (dB) gain control is achieved. The BB/MAC provides the gain setting vector at a separated serial interface. Synthesizer The voltage controlled oscillator (VCO) operates at two times the local oscillator (LO) frequency. The VCO output feeds a specialized divide-by-two module. The divider provides the required times one LO frequency with both in-phase and quadrature components for use in the IQ Mixer (IQMIX) and the IQ upconverter (IQUC). The use of the divider at two times the LO also reduces load pull on the LO frequency each time the integrated power amplifier (PA) is enabled. The VCO core is a differential double-grounded bipolar stage with the load for the VCO tank circuit made up of inductive and capacitive components in parallel. No external tuning devices are required. A fully differential inductor is contained on-chip. The capacitive portion of the frequency determining circuitry is made up of a binary weighted capacitor array and an analog voltage controlled varactor. The radio makes use of a hybrid phase lock loop (PLL) architecture. The coarse tuning is accomplished with the combination of Digital PLL/Binary capacitance array and the fine tuning is accomplished using the more conventional analog portion of the PLL. This use of coarse and fine tuning together reduces the analog VCO gain requirement. The reduction of tuning tolerance issues and noise are a direct effect of this type of PLL. Additionally, the characteristic impedance of the loop filter can be increased to reduce the charge pump current which helps in the integration of the active loop filter on-chip. This PLL also contains both integral and proportional charge pumps whose currents may be changed via register settings. This allows the loop parameters to be optimized for tuning speed and noise reduction. The fractional-N synthesizer in this radio utilizes a unique phase interpolation divider (PID) rather than the more conventional modulus divider architecture. The PID allows for very good frequency resolution and fast tuning speed. It also has the speed and power advantages of an asynchronous divider and is fully programmable within a restricted frequency range. Because of the coarse digital tuning the analog tuning gain could be reduced so that the characteristic impedance of the loop filter increases and the charge pump current is reduced. This helps to integrated the whole active loop filter (APLL). Using of two (proportional and integral components) charge pumps and programming their currents permit changing of filter parameters. 6 AT86RF535B [Preliminary] 5190A–WiMAX–4/07 AT86RF535B [Preliminary] The phase interpolation divider (PDIV) is an alternate divider architecture to a conventional modulus divider. It has the speed and power advantages of an asynchron divider and is programmable in a restricted range. Integrated Calibration Support Calibration of the transceiver imbalances to optimize transmit LO leakage, transmit and receive image rejection ratio (IMRR) will be performed in between RX/TX operation. It is totally independent from BB/MAC processor. SPI Interface Serial peripheral interface (SPI) controls the transceiver. This 4-wire bus contains the ports SDE, SCL, SDI and SDO. The SPI has an 8-bit organization. Each transmission starts with a command byte with the following structure: MSB CMD LSB ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0 The command bit CMD is set to “1” for WRITE operation and “0” for READ operation. The transmission is continued with the data bytes. The number of data bytes depends on the register. The MSB of each data byte is send first. For an 8 bit register: MSB DATA7 LSB DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 For a 16 bit register: MSB LSB DATA15 DATA14 DATA13 DATA12 DATA11 DATA10 DATA9 DATA8 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 7 5190A–WiMAX–4/07 Figure 2. SPI transmission for multiple bytes SDE SCL SDI SDO X CMD ADR 6 ADR 5 ADR 4 ADR 3 ADR 2 ADR 1 ADR0 IN MSB IN LSB CMD ADR 6 ADR 4 ADR 3 ADR 2 ADR 1 ADR 0 OUT MSB OUT LSB X ADR 5 Pin Description and Package Drawing Table 4. Pin Description Pin Pin No. Description FSW 1 PLL Frequency Switch for HFDD Mode Digital CMOS input levels VSSDPLL 2 Ground Supply of Digital PLL Modules VDDDPLL 3 Voltage Supply of Digital PLL Modules VDDBBIF 4 Supply Voltage of Digital Base Band Interface Pads PTX 5 Power Switch Transmit Path High active, digital CMOS input levels RFRX1 6 RF Receive Input 1 Low noise amplifier input. The 50? matching is in part by the bond/package inductance and an external component (tbd). RFRX2 7 RF Receive Input 2 Complementary signal to RFRX1 VSSRFRX 8 Ground Supply of Radio Frequency Receive Circuit Modules VDDRFRX 9 Voltage Supply of Radio Frequency Receive Circuit Modules ATB 10 Analog Test Bus Analog IO Analog output/input signal for testing purposes, connection configurable over SPI VDDRFTX1 11 Voltage Supply of Radio Frequency Transmit Circuit Modules VDDRFTX1 12 Voltage Supply of Radio Frequency Transmit Circuit Module VDDRFTX2 13 Voltage Supply of Radio Frequency Transmit Circuit Modules VDDRFTX2 14 Voltage Supply of Radio Frequency Transmit Circuit Modules VDDPA 15 Voltage Supply of Power Amplifier Driving Module VDDPA 16 Voltage Supply of Power Amplifier Driving Module 8 AT86RF535B [Preliminary] 5190A–WiMAX–4/07 AT86RF535B [Preliminary] Table 4. Pin Description (Continued) Pin Pin No. Description RFTX1 17 RF Transmit Output 1 P1dB up to +15dBm @ 50? differential 3.5GHz. The 50? matching is in part by the bond/package inductance and an external component (tbd). RFTX2 18 RF Transmit Output 2 Complementary signal to RFTX1 VDDPA 19 Voltage Supply of Power Amplifier Driving Module VDDPA 20 Voltage Supply of Power Amplifier Driving Module PRX 21 Power Switch of Receive Path High active, digital CMOS input levels DTB 22 Digital Test Bus Input/Output Digital DTB input/output signal for testing purposes, connection and direction is configurable over SPI. VSSDIG 23 Ground Supply SPI Interface Pads and of Digital Circuit Modules VDDDIG 24 Voltage Supply of Digital Circuit Modules VDDBBIF 25 Voltage Supply of Digital Base Band Interface Pads NSDE 26 SPI Enable Digital Input The rising edge of SCL and a low SDE indicate the start of a data transmission to the SPI slave SCL 27 SPI Clock Digital Input At every rising edge the SDI data is latched into the internal SPI register. SDO data change also on the rising edge. SDI 28 SPI Data Digital Input Serial SPI data input stream is started with SDE and contain first an address byte. Read in is MSB first. The MSB of the address byte is the R/W control bit. After the address byte there follows a number of data bytes. The actual number of data bytes depends on the address. SDO 29 SPI Data Digital Output NRES 30 Power On Reset Low active, open drain output with internal 10k? pull up resistor BBTXIN 31 Base Band Transmit Input I Negative Complementary signal to BBTXIP BBTXIP 32 Base Band Transmit Input I Positive Base band transmit input signal In Phase BBTXQP 33 Base Band Transmit Input Q Positive Complementary signal to BBTXQN BBTXQN 34 Base Band Transmit Input Q Negative Base band transmit input signal Quad Phase VDDBBTX 35 Voltage Supply of BB TX circuit modules VCMD 36 Common Mode Voltage Bias Output RX Elements DC output voltage 1.0V, only active if PRX=High 9 5190A–WiMAX–4/07 Table 4. Pin Description (Continued) Pin Pin No. Description BBRXIN 37 Base Band Receive Output I Negative In Phase output negative. The base band-processed signal is level voltage programmable to adapt to different base band ADCs. The capacitive load should be less than 10pF asymmetric BBRXIP 38 Base Band Receive Output I Positive Complementary signal to BBRXIN BBRXQP 39 Base Band Receive Output Q Positive Quad Phase output positive. The base band-processed signal is level voltage programmable to adapt to different base band ADCs. The capacitive load should be less than 10pF asymmetric. BBRXQN 40 Base Band Receive Output Q Negative Complementary signal to BBRXQP VSSBBRX 41 Voltage Supply of BB Receive circuit modules VDDBBRX 42 Voltage Supply of BB Receive circuit modules VDDCLK 43 Ground Supply of CMOS Clock Output Driver CLK 44 40MHz CMOS Clock Digital Output Driver VSSCLK 45 Ground Supply of CMOS Clock Output Driver VSSXCL 46 Ground Supply of Crystal Clock Input Buffer XCL 47 Crystal Clock Input Buffer VDDXCL 48 Voltage Supply of Crystal Clock Input Buffer VDDCHP 49 Voltage Supply of Phase Frequency Detector and Charge Pump Modules VSSCHP 50 Ground Supply of Phase Frequency Detector and Charge Pump Modules 51 VDDAPLL 52 Voltage Supply of PLL Analog Divider Modules VSSAPLL 53 Ground Supply of PLL Analog Divider Modules CVI 54 VCO Control Voltage IO (Testpin) VSSVCO 55 Ground Supply of Synthesizer modules VCO and APLF VDDVCO 56 Voltage Supply of Synthesizer modules VCO and APLF Note: 10 Additional ground supplies are generated by down bonds to exposed paddle AT86RF535B [Preliminary] 5190A–WiMAX–4/07 AT86RF535B [Preliminary] VSSCLK PIN45 VDDCLK VSSXCL PIN46 CLK XCL PIN47 PIN43 VDDXCL PIN48 PIN44 VDDCHP PIN49 VDDAPLL PIN52 VSSCHP VSSAPLL PIN53 PIN50 CVI PIN51 VSSVCO PIN1 PIN54 PIN56 FSW PIN55 Pin Information VDDVCO Figure 3. PIN42 AT86RF535B VDDBBRX PIN41 VSSBBRX PIN3 PIN40 BBRXQN PIN4 PIN39 BBRXQP PIN5 PIN38 BBRXIP PIN37 BBRXIN PIN36 VCMD PIN35 VDDBBTX PIN34 BBTXQN PIN10 PIN33 BBTXQP PIN11 PIN32 BBTXIP VDDRFTX1 PIN12 PIN31 VDDRFTX2 PIN13 PIN30 PIN14 PIN29 VSSDPLL PIN2 VDDDPLL VDDBBIF PTX RFRX1 PIN6 RFRX2 PIN7 VSSRFRX PIN8 VDDRFRX PIN9 ATB VDDRFTX1 PIN25 PIN26 PIN27 PIN28 VDDDIG VDDBBIF NSDE SCL SDI VDDPA PIN24 PIN20 VDDPA PIN23 PIN19 RFTX2 VSSDIG DTB PIN18 RFTX1 PIN22 PIN17 VDDPA PRX PIN16 VDDPA PIN21 PIN15 VDDRFTX2 QFN56 BBTXIN NRES SDO 11 5190A–WiMAX–4/07 Revision History 12 Doc. Rev. Date Comments 5190A 4/2007 Initial document release. AT86RF535B [Preliminary] 5190A–WiMAX–4/07 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60 ASIC/ASSP/Smart Cards RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 1150 East Cheyenne Mtn. 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