E2C0023-27-Y3 ¡ Semiconductor MSC1218 ¡ Semiconductor This version: Nov. 1997 MSC1218 Previous version: Jul. 1996 63-Bit Triplex Controller/Driver with Digital Dimming Function GENERAL DESCRIPTION The MSC1218 is a Bi-CMOS driver for 1/3 duty vacuum fluorescent display tube. It contains a 64-bit shift register, a 63-bit latch, a 10-bit digital dimming circuit, and three grids. The MSC1218 has only three microcontroller interface signal lines: CS, D-IN, and CLOCK. The chip select function enables the D-IN and CLOCK lines to be shared with other peripheral circuits. FEATURES • Power supply Voltage : 8 to 18V (built-in 5V regulator for logic circuit) • Operating temperature : -40 to +85°C • 21-segment driver outputs : IOH=–6mA at VOH=VDD–0.8V • 3-grid driver outputs : IOH=–16mA at VOH=VDD–0.8V • Built-in digital dimming circuit : 10-bit resolution • Built-in RC oscillation circuit : External R and C • Built-in Power-On-Reset circuit • Package: 32-pin plastic SSOP(SSOP32-P-430-1.00-K) (Product name: MSC1218GS-K) 1/12 ¡ Semiconductor MSC1218 BLOCK DIAGRAM SEG21 SEG1 GRID3 GRID1 VDD1 VDD2 21-bit Segment Driver 5V REG. 5V POR POR 3-bit Grid Driver VDD=8 - 18V 21-bit data 21 1 63 GND 21-Segment Control 21 63 VCC=5.0V (Regurator) 21 21 43 42 CS 22 21 1 63-bit Latch Control Circuit 63-bit data 64 63 DATA-IN 59 58 49 48 64-bit Shift Register CLOCK 1 10-bit data 10-bit Latch 10-bit data OSC0 OSC1 10-bit Digital Diming OSC POR Timing Generator 64 bits=0: Digital Dimming Mode 64 bits=1: VF Data Input Mode INPUT AND OUTPUT CONFIGURATION • Schematic Diagrams of Logic Portion Input • Schematic Diagrams of Driver Output Circuit Circuit VDD (5V Reg.) VDD VDD OUTPUT INPUT GND GND GND GND 2/12 ¡ Semiconductor MSC1218 PIN CONFIGURATION (TOP VIEW) SEG 2 1 32 SEG 1 SEG 3 2 31 GRID1 SEG 4 3 30 GRID2 SEG 5 4 29 GRID3 SEG 6 5 28 VDD2 SEG 7 6 27 OSC0 SEG 8 7 26 OSC1 SEG 9 8 25 GND SEG10 9 24 DATA-IN SEG11 10 23 CLOCK SEG12 11 22 CS SEG13 12 21 VDD1 SEG14 13 20 SEG21 SEG15 14 19 SEG20 SEG16 15 18 SEG19 SEG17 16 17 SEG18 32-Pin Plastic SSOP 3/12 ¡ Semiconductor MSC1218 PIN DESCRIPTIONS Pin 32, 1 - 20 29 - 31 24 23 Symbol SEG1 - 21 Type Decription O Output pins for segment signals for driving VF display tube (anode). GRID1 - 3 D-IN CLOCK O I I 27 OSC0 I 26 OSC1 O 22 CS I Output pins for grid signals for driving VF display tube (grid). Serial data input pin (positive logic). Shift clock input pin. Serial data shifts at the rising edge of CLOCK. RC oscillator connecting pins. Oscillation frequency is 3.2MHz. Connect a resistor between the OSC1 and OSC0 pins and a capacitor between the OSC0 pin and the ground. Chip select input pin. Data transfer is inhibited when this pin is "H". 21 28 VDD1 VDD2 — Power supply pins. When using these pins, connect each of them to the power supply. 25 GND — Ground pin. 4/12 ¡ Semiconductor MSC1218 ABSOLUTE MAXIMUM RATINGS Symbol Condition Rating Unit Power Supply Voltage Parameter VDD — –0.3 to +20 V Input Voltage VIN All input pins –0.3 to +6.0 V Storage Temperature TSTG — –65 to +150 °C PD Ta = +85°C 400 mW Power Dissipation RECOMMENDED OPERATING CONDITIONS Parameter Symbol Condition Min. Typ. Max. Unit Power Supply Voltage VDD — 8 — 18 V High Level Input Voltage (1) VIH1 All inputs except OSC0 3.8 — 5.5 V High Level Input Voltage (2) VIH2 OSC0 4.5 — 5.5 V Low Level Input Voltage (1) VIL1 All inputs except OSC0 0 — 0.8 V Low Level Input Voltage (2) VIL2 OSC0 0 — 0.5 V fC — — — 250 kHz Oscillation Frequency fOSC R = 4.7kW, C = 10pF — 3.2 — MHz Frame Frequency fFR fosc = 3.2MHz — 260 — Hz Operating Temperature Top — –40 — 85 °C Clock Frequency 5/12 ¡ Semiconductor MSC1218 ELECTRICAL CHARACTERISTICS DC Characteristics (Ta = –40 to +85˚C, VDD = 8 to 18V (Unless otherwise noted) ) Parameter High Level Input Voltage (1) (All inputs except OSC0) High Level Input Voltage (2) (All inputs except OSC0) Low Level Input Voltage (1) (OSC0) Low Level Input Voltage (2) (OSC0) High Level Input Current (All inputs) Low Level Input Current (All inputs) High Level Output Voltage (SEG1-20) High Level Output Voltage (GRID1-3) Low Level Output Voltage (1) (SEG1-20, GRID1-3) Low Level Output Voltage (2) (SEG1-20, GRID1-3) Low Level Output Voltage (3) (SEG1-20, GRID1-3) Current Consumption Symbol Condition Min. Max. Unit VIH1 — 3.8 5.5 V VIH2 External input only 4.5 5.5 V VIL1 — 0.0 0.8 V VIL2 External input only 0.0 0.8 V IIH VIH1 = 5.0V –5 5 mA IIL VIL = 0.0V –5 5 mA VDD–0.8 — V VDD–0.8 — V — 2 V — 1 V — 0.3 V — 10 V VOH1 VOH2 VOL1 VOL2 VOL3 VDD VDD= 9.5V IOH1 = –6mA VDD= 9.5V IOH2 = –16mA VDD= 9.5V IOL1 = 500mA VDD= 9.5V IOL2 = 200mA VDD= 9.5V IOL3 = 2mA fOSC= 3.2MHz No load 6/12 ¡ Semiconductor MSC1218 AC Characteristics (Ta = –40 to +85˚C, VDD = 8 to 18V (Unless otherwise noted) ) Parameter Symbol Condition Min. Max. Unit Oscillation Frequency fOSC R=4.7kW, C=10pF 2 4.4 MHz External Input Frequency to OSC0 fOSCI External input only 2.7 3.7 MHz fC — — 250 kHz Clock Pulse Width tCW — 1.3 — ms Data Setup Time tDS — 1 — ms Data Hold Time tDH — 200 — ns CS Pulse Width tCSW — 8 — ms CS Off Time tCSL — 32 — ms tCSS — 2 — ms tCSH — 2 — ms tODS CI=100pF — 8 ms tR CI=100pF t=20% to 80% or 80% to 20% — 5 ms Power – CS Time at Power-on tPCS — 300 — ms Hold Time at Power-off tPOF When mounted on the unit VDD = 0.0V 5 — ms Rise Time at Power-on tPRZ When mounted on the unit — 100 ms Clock Frequency CS Setup Time (CS – Clock) CS Hold Time (Clock – CS) CS–All Output Delay Time Slew Rate (All Drivers) 7/12 ¡ Semiconductor MSC1218 TIMING DIAGRAM 1) Data Input Timing tCSS tCSW CS tCSL tCSH fC tCW CLOCK tDS DATA-IN 2) VALID VALID VALID tCSW SEG1-21, GRID1-3 tR -3.8V -0.8V tODS tR tR -80% -20% Power-on Timing tPRZ tPCS CS -3.8V -0.8V VALID Data Output Timing tODS VDD -3.8V -0.8V tCW tDH CS 3) -3.8V -0.8V tPOF -80%VDD -0.0V -3.8V -0.8V 8/12 ¡ Semiconductor MSC1218 FUNCTIONAL DESCRIPTION l Power-on Reset The built-in Power-on-Reset (POR) circuit initializes the internal circuits when power is applied. The following condition is established after POR. 1) Contents of the shift register and latches are "0". 2) Duty cycle of digital dimming is set to "0". 3) All the outputs are OFF. l Function Mode The function mode is selected according to the output of the last bit of the shift register. The function modes are as follows. M0 (Last bit) Function 0 Digital dimming data input mode 1 Display data input mode l Digital Dimming Data Input When M0="0", the digital dimming data input mode is selected and the input data length is 16 bits. The digital dimming data input is valid only when the low level is applied to the CS pin. The digital dimming data that was input to DATA-IN is input into the shift register at the rising edge of the CLOCK. Data is automatically loaded to the latches from the shift register at the rising edge of CS. The digital dimming data consists of 10 bits. The output duty varies from 0/1024 (0%) to 1016/1624 (99%) for each grid. The 10-bit digital dimming data should be input starting with the LSB. [Data Configuration] Digital dimming data input mode Input data: 16bits Digital dimming data: 10 bits Mode selector: 1 bit 16 15 14 13 12 11 M0 * * * * * 10 9 D10 D9 8 7 6 5 4 3 2 1 BIT (First In) D8 D7 D6 D5 D4 D3 D2 D1 INPUT DATA MSB LSB MODE DATA DIMMING DATA (MSB) (LSB) DUTY CYCLE INPUT DATA 0 0 0 0 0 0 0 0 0 0 0/1024 0 0 0 0 0 0 0 0 0 1 1/1024 1 1 1 1 1 1 1 0 0 0 1016/1024 1 1 1 1 1 1 1 1 1 1 1016/1024 9/12 ¡ Semiconductor MSC1218 [Input Configuration] l Dimming data BYTE B7 B6 B5 B4 B3 B2 1 D8 D7 D6 D5 D7 D3 2 M0 * * * * * B1 B0 D2 D1 D10 D9 l Display Data Input When M0="1", the display data input mode is selected and the input data length is 16 bits. The display data input is valid only when the low level is applied to the CS pin. The display data that was input to DATA-IN is input into the shift register at the rising edge of CLOCK. The data is automatically loaded to the latched from the shift register at the rising edge of CS. [Data Configuration] Display data input mode Input data: Display data: Mode selector: 64 63 62 61 64bits 63 bits 1 bit 33 M0 D63 D62 D61 32 31 30 D33 D32 D31 D30 MODE DATA 4 3 2 1 BIT (First In) D4 D3 D2 D1 INPUT DATA DISPLAY DATA [Input Configuration] Display data BYTE B7 B6 B5 B4 B3 B2 B1 B0 1 D8 D7 D6 D5 D7 D3 D2 D1 2 D16 D15 D14 D13 D12 D11 D10 D9 3 D24 D23 D22 D21 D20 D19 D18 D17 4 D32 D31 D30 D29 D28 D27 D26 D25 5 D40 D39 D38 D37 D36 D35 D34 D33 6 D48 D47 D46 D45 D44 D43 D42 D41 7 D56 D55 D54 D53 D52 D51 D50 D49 8 D64 D63 D62 D61 D60 D59 D58 D57 10/12 ¡ Semiconductor MSC1218 [Configuration of Segment output and Shift Register] Segment Output Timing GRID GRID GRID 1 2 3 SEG1 D1 D22 D43 SEG2 D2 D23 D44 SEG3 D3 D24 D45 SEG4 D4 D25 D46 SEG5 D5 D26 D47 SEG6 SEG7 Segment GRID GRID GRID 1 SEG8 2 3 Segment GRID GRID GRID 1 D15 D36 D57 SEG9 D9 D30 D51 SEG16 D16 D37 D58 SEG10 D10 D31 D52 SEG17 D17 D38 D59 SEG11 D11 D32 D53 SEG18 D18 D39 D60 SEG12 D12 D33 D54 SEG19 D19 D40 D61 D6 D27 D48 SEG13 D13 D34 D55 SEG20 D20 D41 D62 D7 D28 D49 SEG14 D14 D35 D56 SEG21 D21 D42 D63 *1bit time=4fOSC 3072bit times (1 display cycle) VDD –GND –VDD GRID2 GRID1-21 3 SEG15 GRID1 GRID3 2 D8 D29 D50 GND –VDD 3bit times 1019bit times 5bit times 1024bit times 8bit times GND VDD –GND 11/12 ¡ Semiconductor MSC1218 PACKAGE DIMENSIONS (Unit : mm) SSOP32-P-430-1.00-K Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.60 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 12/12