NJU6434 PRELIMINARY 1/4 DUTY LCD DRIVER ! GENERAL DESCRIPTION ! PACKAGE OUTLINE The NJU6434 is a 1/4 duty LCD driver for segment type LCD panel. The LCD driver consists of 4-common and 50-segment drives up to 200 segments. The NJU6434 is useful for the digital tuning system or others segment type display driver. NJU6434KS4 ! FEATURES # # # # # # # # # 50 Segment Drivers Duty Ratio 1/4 (Up to 200-Segments) Serial Data Transmission (Shift Clock 2MHz max.) Oscillation Circuit On-chip (External Resistance Required) Display Off Function (INHb Terminal) Operating Voltage 2.4 to 5.5V LCD Driving Voltage 2.4 to 6.0V Package Outline Chip, QFN 64-S4, QFP64-H2 C-MOS Technology P-Sub NJU6434C NJU6434FH2 SEG1 SEG50 COM4 COM1 ! BLOCK DIAGRAM Common Driver OSC1 OSC2 VDD VLCD Latch Circuit / Segment Driver Oscillation Divider Input Select LCD Driving Voltage Circuit Shift Register4 50-bit Input Select Shift Register3 50-bit Input Select Shift Register2 50-bit Input Select Shift Register1 50-bit VSS INHb Reset Circuit CE DATA MODE SCL Ver.2009-11-12 Input Select Circuit Decoder Shift Register Control Circuit -1- NJU6434 ! PAD LOCATION 48 33 32 49 Y Chip Center Chip Size Chip Thickness PAD Size PAD Pitch X : X=0µm, Y=0µm : X=3.00 mm, Y=3.00 mm : 400 µm : X=70.0 µm, Y=70.0 µm : 99.0 µm (Min.) 17 64 16 1 ! PAD COORDINATES PAD No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 -2- Terminal X= µm Y= µm COM1 COM2 COM3 COM4 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 -994.5 -694.5 -549.5 -445.5 -346.5 -247.5 -148.5 -49.5 49.5 148.5 247.5 346.5 445.5 549.5 694.5 994.5 1366.3 1366.3 1366.3 1366.3 1366.3 1366.3 1366.3 1366.3 -1366.3 -1366.3 -1366.3 -1366.3 -1366.3 -1366.3 -1366.3 -1366.3 -1366.3 -1366.3 -1366.3 -1366.3 -1366.3 -1366.3 -1366.3 -1366.3 -994.5 -694.5 -549.5 -445.5 -346.5 -247.5 -148.5 -49.5 PAD No. 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Chip Size 3.00 x 3.00 mm(Chip Center PAD Terminal X= µm Y= µm Terminal No. SEG21 1366.3 49.5 49 SEG45 SEG22 1366.3 148.5 50 SEG46 SEG23 1366.3 247.5 51 SEG47 SEG24 1366.3 346.5 52 SEG48 SEG25 1366.3 445.5 53 SEG49 SEG26 1366.3 549.5 54 SEG50 SEG27 1366.3 694.5 55 VLCD SEG28 1366.3 994.5 56 INHb SEG29 994.5 1366.3 57 SCL SEG30 694.5 1366.3 58 DATA SEG31 549.5 1366.3 59 CE SEG32 445.5 1366.3 60 MODE SEG33 346.5 1366.3 61 VSS SEG34 247.5 1366.3 62 OSC1 SEG35 148.5 1366.3 63 OSC2 SEG36 49.5 1366.3 64 VDD SEG37 -49.5 1366.3 SEG38 -148.5 1366.3 SEG39 -247.5 1366.3 SEG40 -346.5 1366.3 SEG41 -445.5 1366.3 SEG42 -549.5 1366.3 SEG43 -694.5 1366.3 SEG44 -994.5 1366.3 X=0µm, Y=0µm) X= µm Y= µm -1366.3 -1366.3 -1366.3 -1366.3 -1366.3 -1366.3 -1366.3 -1366.3 -1366.3 -1366.3 -1366.3 -1366.3 -1366.3 -1366.3 -1366.3 -1366.3 994.5 694.5 549.5 445.5 346.5 247.5 148.5 49.5 -49.5 -148.5 -247.5 -346.5 -445.5 -549.5 -694.5 -994.5 Ver.2009-11-12 NJU6434 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 ! PIN CONFIGURATION SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 NJU6434 COM1 COM2 COM3 COM4 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 VLCD INHb SCL DATA CE MODE VSS OSC1 OSC2 VDD ! TERMINAL DESCRIPTION No. SYMBOL 5~54 SEG1~SEG50 LCD Segment Output Terminals 1~4 COM1~COM4 62 OSC1 63 OSC2 64 VDD LCD Common Output Terminals Oscillation Terminals : External resistance is connected to these terminals. In External clock operation, the external clock input to OSC1 terminal. OSC2 terminal should be opened. Power Supply (+5V) 61 VSS Power Supply (0V) 55 VLCD 59 CE 57 SCL 58 DATA 60 MODE 56 INHb Ver.2009-11-12 FUNCTION Power Supply for LCD Driving Chip Enable Signal Input Terminal : "H" : LCD display data and mode setting data input "L" : Disable Fall Edge : LCD display data latch Serial Data Transmission Clock Input Terminal : LCD display and Mode setting data are input synchronized SCL clock signal rise edge. Serial Data Input Terminal Data input timing : SCL clock rise edge Data or Mode Select Terminal "H" : Data input mode "L" : LCD display data input mode (Refer the mode setting table for mode setting contents) Display-Off Control Terminal : When display goes to off, the display data in the shift-register is retained. "H" : Display-On "L" : Display-Off -3- NJU6434 ! FUNCTIONAL DESCRIPTION (1) Operation of each block (1-1) Oscillation Circuit The oscillation circuit operates by connecting external resistance (capacitance is incorporated). This circuit provides the clock signal to both common and segment drivers. (1-2) Divider Circuit This circuit divides the oscillating signal to generate the common and segment timing. (1-3) Shift-Register When the CE terminal is "H" (Enable mode), the display data is transferred to the shift-register synchronized by the shift clock on the SCL terminal. (1-4) Latch Circuit and Segment Driver When the CE signal falling, the display data is latched, and the data controls the segment signal of display-on/off. (1-5) Common Driver The Common driver generates driving waveform to common terminal. (1-6) Reset Circuit The Reset circuit is type of detectable voltage. It resets internal circuit when the power turns on. (1-7) LCD Driving Voltage Generator Circuit The LCD Driving voltage generator circuit generates the LCD bias voltage. (Refer to “(6) LCD Panel Drive” for details.) -4- Ver.2009-11-12 NJU6434 (2) Mode Setting The mode setting is composed of 4-bit, and selects the shift register that writes the display data by writing data in the mode setting register. (Refer to "(4) Data Input Timing" for details.) When the data (1,1,1,1) is input, “0” (All Display-off) is written in all shift registers. The mode setting register is selected by CE="H" and MODE="H". The data is latched at the rising edge of the SCL, and selected at falling edge of the CE. Mode 1 2 3 4 5 F Data (MSB) 1,0,0,0 (LSB) 0,1,0,0 1,1,0,0 0,0,1,0 1,0,1,0 1,1,1,1 Table 1. Mode Setting Table Description Shift register 1 is selected. Shift register 2 is selected. Shift register 3 is selected. Shift register 4 is selected. All Shift register (1~4) is selected, and data is written continuously. All shift register is “0”. (3) Correspondence of the transfer data and output terminal The display data is written by CE="H" and MODE="L". The data is latched at the rising edge of the SCL, and written at falling edge of the CE. The correspondence of the data and the output terminals is as follows. Output Terminal SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 COM1 COM2 COM3 COM4 Output Terminal COM1 COM2 COM3 COM4 D1 D5 D9 D13 D17 D21 D25 D29 D33 D37 D41 D45 D49 D53 D57 D61 D65 D69 D73 D77 D81 D85 D89 D93 D97 D2 D6 D10 D14 D18 D22 D26 D30 D34 D38 D42 D46 D50 D54 D58 D62 D66 D70 D74 D78 D82 D86 D90 D94 D98 D3 D7 D11 D15 D19 D23 D27 D31 D35 D39 D43 D47 D51 D55 D59 D63 D67 D71 D75 D79 D83 D87 D91 D95 D99 D4 D8 D12 D16 D20 D24 D28 D32 D36 D40 D44 D48 D52 D56 D60 D64 D68 D72 D76 D80 D84 D88 D92 D96 D100 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 D101 D105 D109 D113 D117 D121 D125 D129 D133 D137 D141 D145 D149 D153 D157 D161 D165 D169 D173 D177 D181 D185 D189 D193 D197 D102 D106 D110 D114 D118 D122 D126 D130 D134 D138 D142 D146 D150 D154 D158 D162 D166 D170 D174 D178 D182 D186 D190 D194 D198 D103 D107 D111 D115 D119 D123 D127 D131 D135 D139 D143 D147 D151 D155 D159 D163 D167 D171 D175 D179 D183 D187 D191 D195 D199 D104 D108 D112 D116 D120 D124 D128 D132 D136 D140 D144 D148 D152 D156 D160 D164 D168 D172 D176 D180 D184 D188 D192 D196 D200 Correspondence of the transfer data and Segment Status Transfer Data ”H” ”L” Ver.2009-11-12 Segment Status ON OFF -5- NJU6434 (4) Data Input Timing The format of data is as follows. The mode data is input by 4-bit of MSB first, and after the shift register is selected, the display data is written - Mode 1 : Shift Register 1 (D1~D50) CE SCL (LSB) (MSB) DATA 1 0 0 0 D1 2 Mode Data 3 4 5 6 7 8 44 45 46 47 48 49 50 Display Data x 50-bit MODE - Mode 2 : Shift Register 2 (D51~D100) CE SCL DATA 0 1 0 0 51 52 53 54 55 56 57 58 Mode Data 94 95 96 97 98 99 100 Display Data x 50-bit MODE - Mode 3 : Shift Register 3 (D101~D150) CE SCL DATA 1 1 0 0 101 102 103 104 105 106 107 108 Mode Data 144 145 146 147 148 149 150 Display Data x 50-bit MODE - Mode 4 : Shift Register 4 (D151~D200) CE SCL DATA 0 0 1 Mode Data 0 151 152 153 154 155 156 157 158 194 195 196 197 198 199 200 Display Data x 50-bit MODE -6- Ver.2009-11-12 NJU6434 - Mode 5 : Shift Register 1~4 (D1~D200) CE SCL 1 DATA 0 1 0 D1 2 3 4 5 6 7 Mode Data 8 194 195 196 197 198 199 200 Display Data x 200-bit MODE - Mode F : Shift Register 1~4 all “0” CE SCL DATA 1 1 1 1 Mode Data MODE Note 1) All of display data should be transmitted within 30ms to keep the display quality, because huge display data D1 to D200 are transmitted at 4 times totally. Note 2) Data is latched at the rising edge of the SCL. Note 3) Mode data and display data are executed at the falling edge of the CE. Note 4) In case of less than 4-bit data, the mode data remains the LSB side of the previous mode data. Note 5) In case of over 4-bit data, the mode data is valid the previous 4-bit of the falling edge of the CE. Note 6) In case of less than 50-bit data, the display data remains the last part of the previous display data. Note 7) In case of over 50-bit data, the display data is valid the previous 50-bit of the falling edge of the CE. (5) Initialization by Power On Reset The NJU6434 incorporates the reset circuit of the detectable voltage type, and when the power supply is turned on, it automatically initializes it (reset). When the VDD becomes 1V to 2.2V of the working voltage, the reset signal is generated internally. When the power supplies rise time should be over than 0.1ms. (Refer to “condition of the Power on reset” for details.) (5-1) Status of Power On Reset 1. Mode setting release (nonselective status) 2. Shift register : all “0” 3. Latch circuit : all “0” VDD=5V V VDD=3V VDD=2.2V Internal Reset wave t Ver.2009-11-12 -7- NJU6434 (6) LCD Panel Drive (6-1) LCD driving volyage generation circuit The LCD driving voltage generation circuit is consists of bleeder resistance and voltage follower. This circuit generates LCD driving bias voltages V1 and V2 from input voltage terminal (VLCD-VSS). It is generated by the bleeder resistance in IC, and after impedance is converted by the voltage follower, it is supplied to the LCD driving circuit. The VLCD terminal requires external capacitors for bias voltage stabilization for display quality as shown in below. NJU6434 internal VLCD VLCD + V1 VLCD V2 VSS -8- VSS Ver.2009-11-12 NJU6434 ! ABSOLUTE MAXIMUM RATINGS Ta=25°C PARAMETER Operating Voltage (1) Operating Voltage (2) SYMBOL CONDITIONS RATINGS UNIT -0.3~+7.0 V VDD Terminal, Ta=25°C -0.3~+7.0 V VLCD Terminal, Ta=25°C CE, SCL, DATA, MODE, Input Voltage (1) VI -0.3~+7.0 V INHb Terminals, Ta=25°C Input Voltage (2) VI OSC1, OSC2 Terminals -0.3~VDD+0.3 V Output Voltage VO OSC1, OSC2 Terminals -0.3~VDD+0.3 V Glass epoxy board (4-layer) 1600(QFN64-S4) Power Dissipation Pdmax mW 76.2mm x 114.3mm x 1.6mm 1900(QFP64-H2) Operating Temperature Topr -40~+85 °C Storage Temperature Tstg -55~+125 °C Note 1) All voltage values are specified as VSS = 0V. Note 2) If the LSI is used on condition above the absolute maximum ratings, the LSI may be destroyed. Using the LSI within electrical characteristics is strongly recommended for normal operation. Use beyond the electric characteristics conditions will cause malfunction and poor reliability. Note 3) Turn on VDD first then turn on VLCD must be required. Note 4) Decoupling capacitor should be connected between VDD and VSS , VLCD and VSS due to the stabilized operation for the LSI. Ver.2009-11-12 VDDmax VLCDmax -9- NJU6434 ! ELECTRICAL CHARACTERISTICS • (VDD=2.4~3.6V, VLCD=VDD, Ta=-40~+85°C) DC Characteristics PARAMETER CONDITIONS SYMBOL Operating Voltage (1) Operating Voltage (2) "H" Input Voltage "L” Input Voltage "H" Input Current VDD VLCD VIH VIL IIH "L" Input Current IIL "H" Output Voltage (1) "L” Output Voltage (1) 2 Middle Level Voltage /3 (1) VOH(1) VOL(1) 2 VMS /3 1 1 Middle Level Voltage /3 (1) VMS /3 "H" Output Voltage (2) "L" Output Voltage (2) 2 Middle Level Voltage /3 (2) VOH(2) VOL(2) 2 VMC /3 1 1 Middle Level Voltage /3 (2) VMC /3 Oscillating Frequency Range fosc Oscillating Frequency fosc VDD Terminal VLCD Terminal CE, SCL, DATA, MODE, INHb CE,SCL, VI=VDD DATA,MODE, VI=VSS INHb SEG1~SEG50 Io=-10uA VLCD=3V Io=+10uA SEG1~SEG50 Io=±10uA Ta=25°C, Io=±10uA VLCD=3V COM1~COM4 Io=-50uA VLCD=3V Io=+50uA COM1~COM4 Io=±50uA Ta=25°C, Io=±50uA VLCD=3V OSC1, OSC2 Terminals Ta=25°C OSC1, OSC2, R=750kΩ Ta=25°C VDD Terminal, Ta=25°C Operating Current (1) IDD Operating Current (2) ILCD VLCD Terminal, Ta=25°C CE, SCL, DATA, MODE, INHb Hysteresis Voltage VH Note 1) V1=2/3VLCD, V2=1/3VLCD V1 VLCD 2/3VLCD V2 1/3VLCD MIN TYP MAX UNIT 2.4 VDD 0.7VDD VSS 3.0 3.6 6 VDD 0.3VDD 1 V V V V uA 1 uA V V V VLCD-0.4 VSS V1-0.4 V1 VLCD 0.4 V1+0.4 V2-0.4 V2 V2+0.4 V VLCD-0.5 VSS V1-0.5 V1 VLCD 0.5 V1+0.5 V V V V2-0.5 V2 V2+0.5 V 20 kHz 15.4 18.2 kHz 15 10 30 20 uA uA V 10 12.6 0.3 NO TE 1 1 VSS - 10 - Ver.2009-11-12 NJU6434 • (VDD=4.5~5.5V, VLCD=VDD, Ta=-40~+85°C) DC Characteristics PARAMETER CONDITIONS SYMBOL Operating Voltage (1) Operating Voltage (2) "H" Input Voltage "L” Input Voltage "H" Input Current VDD VLCD VIH VIL IIH "L" Input Current IIL "H" Output Voltage (1) "L” Output Voltage (1) 2 Middle Level Voltage /3 (1) VOH(1) VOL(1) 2 VMS /3 1 1 Middle Level Voltage /3 (1) VMS /3 "H" Output Voltage (2) "L" Output Voltage (2) 2 Middle Level Voltage /3 (2) VOH(2) VOL(2) 2 VMC /3 1 1 Middle Level Voltage /3 (2) VMC /3 Oscillating Frequency Range fosc Oscillating Frequency fosc VDD Terminal VLCD Terminal CE, SCL, DATA, MODE, INHb CE,SCL, VI=VDD DATA,MODE, VI=VSS INHb SEG1~SEG50 Io=-10uA VLCD=5V Io=+10uA SEG1~SEG50 Io=±10uA Ta=25°C, Io=±10uA VLCD=5V COM1~COM4 Io=-100uA VLCD=5V Io=+100uA COM1~COM4 Io=±100uA Ta=25°C, Io=±100uA VLCD=5V OSC1, OSC2 Terminals Ta=25°C OSC1, OSC2, R=750kΩ Ta=25°C VDD Terminal, Ta=25°C Operating Current (1) IDD Operating Current (2) ILCD VLCD Terminal, Ta=25°C CE, SCL, DATA, MODE, INHb Hysteresis Voltage VH Note 1) V1=2/3VLCD, V2=1/3VLCD V1 VLCD 2/3VLCD V2 1/3VLCD MIN TYP MAX UNIT 4.5 VDD 0.7VDD VSS 5.0 5.5 6 VDD 0.3VDD 1 V V V V uA 1 uA V V V VLCD-0.4 VSS V1-0.4 V1 VLCD 0.4 V1+0.4 V2-0.4 V2 V2+0.4 V VLCD-0.5 VSS V1-0.5. V1 VLCD 0.5 V1+0.5 V V V V2-0.5 V2 V2+0.5 V 20 kHz 15.4 18.2 kHz 25 15 50 30 uA uA V 10 12.6 0.3 VSS Ver.2009-11-12 - 11 - NO TE 1 1 NJU6434 • • (VDD=2.4~5.5V, Ta=-40~+85°C) AC Characteristics PARAMETER SYMBOL "L" Clock Pulse Width "H" Clock Pulse Width DATA Set-up Time DATA Hold Time CE Set-up Time CE Hold Time (1) CE Hold Time (2) MODE Set-up Time MODE Hold Time "L" Chip Enable Pulse Width tWCLL tWCLH tDS tDH tSCE tHDCE tHCLE tSMD tHMD tWCEL CONDITIONS MIN SCL Terminal SCL Terminal SCL, DATA Terminal SCL, DATA Terminal CE, DATA Terminal CE, DATA Terminal CE, SCL Terminal MODE, CE Terminal MODE, CE Terminal CE Terminal TYP MAX 0.25 0.25 0.25 0.25 1.0 1.0 1.25 0.25 0.25 4.0 UNIT us us us us us us us us us us Input Timing Characteristics tWCEL CE tHMD tSMD MODE tWCLH tWCLL tHCLE SCL tr tf DATA D0 tSCE • tDS D1 tDH tHDCE Power on reset condition (VDD=2.4~5.5V, Ta=-40~+85°C) PARAMETER SYMBOL Power supply rise time Power supply off time trDD tOFF CONDITIONS MIN 0.1 1 VDD Terminal VDD Terminal TYP MAX UNIT us us 2.2V VDD 0.2V 0.2V trDD - 12 - 0.2V tOFF Ver.2009-11-12 NJU6434 • LCD Driving Waveform(1/4DUTY ⋅ 1/3BIAS) 1frame = fosc/192 (Hz) COM1 V0 V1 V2 VSS COM2 V0 V1 V2 VSS COM3 V0 V1 V2 VSS COM4 V0 V1 V2 VSS “OFF” Segment Output corresponds to COM1, COM2, COM3 and COM4 “ON” Segment Output corresponds to COM1 “ON” Segment Output corresponds to COM2 “ON” Segment Output corresponds to COM1 and COM2 “ON” Segment Output corresponds to COM3 “ON” Segment Output corresponds to COM1 and COM3 “ON” Segment Output corresponds to COM2 and COM3 “ON” Segment Output corresponds to COM1, COM2 and COM3 “ON” Segment Output corresponds to COM4 “ON” Segment Output corresponds to COM2 and COM4 “ON” Segment Output corresponds to COM1, COM2, COM3 and COM4 Ver.2009-11-12 V0 V1 V2 VSS V0 V1 V2 VSS V0 V1 V2 VSS V0 V1 V2 VSS V0 V1 V2 VSS V0 V1 V2 VSS V0 V1 V2 VSS V0 V1 V2 VSS V0 V1 V2 VSS V0 V1 V2 VSS V0 V1 V2 VSS - 13 - NJU6434 ! APPLICATION CIRCUIT Example) VDD=3V, VLCD=5V CE SCL DATA MODE INHb CPU NJU6434 5V 3V + VDD OSC1 VSS OSC2 VSS VLCD + COM1 COM2 COM3 COM4 COM1 COM2 COM3 COM4 SEG1 SEG2 SEG3 SEG4 SEG5 : : SEG48 SEG49 SEG50 SEG1 SEG2 SEG3 SEG4 SEG5 : : SEG48 SEG49 SEG50 LCD Panel 200 Segments 750kΩ [CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights. - 14 - Ver.2009-11-12