FEDL9222-02 ¡ Semiconductor FEDL9222-02 ¡ Semiconductor ML9222 This version: Feb. 2000 ML9222 Previous version: Nov. 1999 32-Bit Duplex/Triplex VFD Controller/Driver with Digital Dimming, ADC and Keyscan GENERAL DESCRIPTION The ML9222 is a full CMOS controller/driver for Duplex or Triplex vacuum fluorescent display tube. It conststs of 32-segment driver outputs and 3-grid pre-driver outputs, so that it can drive directly up to 96-segment VFD. ML9222 features a digital dimming function, a 8-ch ADC, a 5 ¥ 5 keyscan circuit and an encoder type switch interface. ML9222 provides an interface with a microcontroller only by four signal lines: DATA I/O, CLOCK, CS and INT. FEATURES • Supply voltage (VDD) • Duplex/Triplex selectable • Applicable VFD tube : 8 to 18.5V (Built-in 5V regulator for logic) : 2 Grids ¥ 32 Anodes VFD tube : 3 Grids ¥ 32 Anodes VFD tube • 32-segment driver outputs : IOH=–5mA at VOH=VDD–0.8V (SEG1 to 22) IOH=–10mA at VOH=VDD–0.8V (SEG23 to 32) • 3-grid pre-driver outputs : IOL=10mA at VOL=2V • Built-in digital dimming circuit (10-bit resolution) • Built-in 8-ch A/D converter • Built-in 5 ¥ 5 keyscan circuit • 3 interface circuits for an encoder type rotary switch • Built-in oscillation circuit (external R and C) • Built-in Power-On-Reset circuit • Package: 80-pin plastic QFP (QFP80-P-1420-0.80-BK) Product name: ML9222GA 1/25 FEDL9222-02 ¡ Semiconductor ML9222 BLOCK DIAGRAM SEG1 D-GND 32 Segment Driver VDD VCC (5V) VREG (5V) L-GND 5V Regulator & Power On Reset 0H POR in1-32 7H 1H Mode Select POR in1-3 CS CLOCK GRID1 GRID2 GRID3 SEG32 Control 0H POR Out1-32 Segment Latch 1 in1-32 Out1-32 96 to 32 Segment Control in1-32 in1-32 Out1-32 Segment Latch 2 in1-32 Out1-32 Segment Latch 3 in1-32 2H 0H POR Out1-3 3bit Shift Register Out1-32 32bit Shift Register POR POR DATA I/O OSCO 3 Grid pre Driver 4H POR 3H 0H POR in1-10 Dimming Latch Out1-10 10bit Digital Dimming OSC POR DIM OUT SYNC OUT1 Timing Generator DUP/TRI 8ch, 8bit A/D Converter CH1 CH8 7H 5H 6H SYNC OUT2 5 ¥ 5 Key Scan and Encoder Switch Interface COL1 COL5 ROW1 ROW5 INT A1 B1 A2 B2 A3 B3 2/25 FEDL9222-02 ¡ Semiconductor ML9222 65 SEG15 66 SEG16 67 SEG17 68 NC 69 SEG18 70 SEG19 71 SEG20 72 NC 73 SEG21 74 SEG22 75 SEG23 76 SEG24 77 NC 78 SEG25 2 64 VDD 63 SEG14 3 62 SEG13 4 61 SEG12 5 60 SEG11 6 59 SEG10 7 8 58 SEG9 57 SEG8 9 56 SEG7 10 55 SEG6 11 12 54 SEG5 53 SEG4 13 52 SEG3 14 51 SEG2 15 1 16 50 SEG1 49 CH8 17 48 CH7 18 47 CH6 19 46 CH5 20 45 CH4 44 CH3 21 23 43 CH2 42 CH1 24 41 Vreg 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 A1 25 22 B1 INT NC DUP/TRI VCC OSC0 NC L-GND DATA I/O CLOCK CS NC SYNC OUT2 SYNC OUT1 DIM OUT VDD SEG28 SEG29 SEG30 SEG31 SEG32 GRID1 GRID2 GRID3 D-GND ROW1 ROW2 ROW3 ROW4 ROW5 COL1 COL2 COL3 COL4 COL5 A3 B3 A2 B2 79 SEG26 80 SEG27 PIN CONFIGURATION (TOP VIEW) NC: No connection 80-pin Plastic QFP 3/25 FEDL9222-02 ¡ Semiconductor ML9222 PIN DESCRIPTIONS Pin Symbol Type 1, 64 VDD — 10 D-GND — Description Power supply pins. Pin1 and pin64 should be connected externally. D-GND is ground pin for the VFD driver circuit. L-GND is ground pin for the 33 L-GND — logic circuit. Pins 8 and 26 should be connected externally. 30 VCC O 5V output pin for internal logic portion and external logic circuit. 41 VREG O Reference voltage (5V) output pin for A/D converter. 50 to 63, 65 to 67, 69 to 71, 73, 74 SEG1 to 22 O These pins can be directly connected to the VFD tube. External circuit is not required. Segment (anode) signal output pins for a VFD tube. IOH£–5 mA 75, 76, 78 to 80, Segment (anode) signal output pins for a VFD tube. SEG23 to 32 O These pins can be directly connected to the VFD tube. External circuit is not required. IOH£–10 mA 2 to 6 Inverted Grid signal output pins. 7, 8, 9 GRID1 to 3 O For pre-driver, the external circuit is requiend. IOL£10 mA 36 CS I 35 CLOCK I 34 DATA I/O I/O Chip Select input pin. Data input/output operation is valid when this pin is set at a High level. Serial clock input pin. Data is input and/or output through the DATA I/O pin at the rising edge of the serial clock. Serial data input/output pin. Data is input to / comes out from the shift register at the rising edge of the serial clock. Interrupt signal output to microcontroller. When any key of key matrix is pressed 27 INT O or released, key scanning is started. After the completion of the one cycle, this pin goes to high level and keeps the high level until keyscan stop mode is selected. Duplex/Triplex operation select input pin. 29 DUP/TRI I 42 to 49 CH1 to 8 I Duplex (1/2 duty) operation is selected when this pin is set at a VCC level. Triplex (1/3 duty) operation is selected when this pin is set at a GND level. 21 to 26 A1 to A3 B1 to B3 I Analog voltage input pin for the 8-bit A/D converter. Input pin for the encoder type rotary switch. Each input has chattering absorption function of 620ns typical. Return inputs from the key matrix. 16 to 20 COL1 to 5 I These pins are active low. When key matrix are in the inactive sate, these pins are at high level through the internal pull-up resistors. All the inputs do not have the cahttering absorption function for the keyscans. Key switch scanning outputs. Normally low level is output through these pin. When any switch of key matrix 11 to 15 ROW1 to 5 O is depressed or released, key scanning is started and is continued until keyscan stop mode is selected. When keyscan stop mode is selected, all outputs of ROW1 to 5 go back to low level. 4/25 FEDL9222-02 ¡ Semiconductor ML9222 Pin Symbol Type 40 DIM OUT O 38, 39 SYNC OUT 1, 2 O Description Dimming pulse output. Connect this pin to the slave side DIM IN pin. Synchronous signal input. Connect these pins to the SYNC IN1 and SYNC IN2 pins of a slave side. RC oscillator connecting pins. 31 OSC0 I/O Connect a resistor (R2) between the VCC and OSC0 pins, C3 VCC and a capacitor (C2) between the OSC0 pin and the GND, OSC0 R2 C2 and a capacitor (C3) between the VCC and the GND. C3 is for VCC stabilization. 5/25 FEDL9222-02 ¡ Semiconductor ML9222 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Condition Supply Voltage VDD Input Voltage VIN PD TSTG Power Dissipation Storage Temperature Output Current Rating Unit — –0.3 to +20 V — –0.3 to +6.0 V Ta = 85°C 764 mW — –55 to +150 °C IO1 SEG1 to 22 –10.0 to +2.0 mA IO2 SEG23 to 32 –20.0 to +2.0 mA IO3 GRID1 to 3 –7.0 to +20.0 mA IO4 DIM OUT, SYNC OUT1, SYNC OUT2 –2.0 to +2.0 mA RECOMMENDED OPERATING CONDITIONS Parameter Symbol Condition Min. Typ. Max. Unit Driver Supply Voltage VDD — 8.0 13.0 18.5 V High Level Input Voltage VIH All inputs except OSC0 3.8 — 5.5 V Low Level Input Voltage VIL All inputs except OSC0 0.0 — 0.8 V Clock Frequency fC — — — 1.0 MHz Oscillation Frequency fOSC Frame Frequency fFR Operating Temperature TOP R2 = 10kW±5%, C2 = 27pF±5% 2.6 3.3 4.0 MHz R2 = 10kW±5% 1/3 Duty 211 269 325 Hz C2 = 27pF±5% 1/2 Duty 317 403 488 Hz –40 — +85 °C — 6/25 FEDL9222-02 ¡ Semiconductor ML9222 ELECTRICAL CHARACTERISTICS DC Characteristics (Ta=–40 to +85°C, VDD=8.0 to 18.5V) Parameter High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current High Level Output Voltage Low Level Output Voltage Symbol Applied pin VIH *1) Condition Min. Max. Unit — 3.8 5.5 V VIL *1) — 0.0 0.8 V IIH1 *2) VIH=3.8V –5.0 +5.0 mA IIH2 *3) VIH=3.8V –100 –5.0 mA IIL1 *2) VIL=0.0V –5.0 +5.0 mA VIL=0.0V IIL2 *3) VOH1 SEG1 to 22 VOH2 SEG23 to 32 VOH3 GRID1 to 3 VOH4 *4) VOL1 SEG1 to 22 VOL2 SEG23 to 32 VOL3 GRID1 to 3 VDD=9.5V VDD=9.5V –300 –70 mA IOH1=–5mA VDD–0.8 VDD V IOH2=–10mA VDD–0.8 VDD V IOH3=–5mA VDD–0.8 VDD V IOH4=–200mA 4.0 5.5 V Output Open 4.5 5.5 V IOL1=500mA — 2.0 V IOL2=500mA — 2.0 V IOL3=10mA — 2.0 V IOL4=300mA VOL4 *5) — 0.8 V Supply Current IDD VDD fOSC=3.3MHz, no load — 10 mA Supply Voltage for Logic VL VCC C3=0.01mF±10%, IO=0 to –10mA 4.5 5.5 V *1) *2) *3) *4) *5) CS, CLOCK, DATA I/O DUP/TRI, A1 to A3, B1 to B3, COL1 to 5 CS, CLOCK, DATA I/O DUP/TRI, A1 to A3, B1 to B3 COL1 to 5 DATA I/O, INT, DIM OUT, SYNC OUT1, SYNC OUT2 DATA I/O, INT, DIM OUT, SYNC OUT1, SYNC OUT2, ROW1 to 5 7/25 FEDL9222-02 ¡ Semiconductor ML9222 AC Characteristics (Ta=–40 to +85°C, VDD=8.0 to 18.5V) Symbol Condition Min. Max. Unit fC — — 1.0 MHz tCW — 400 — ns Data Setup Time tDS — 400 — ns Data Hold Time tDH — 400 — ns CS Off Time tCSL R2=10kW±5%, C2=27pF±5% 20 — ms tCSS — 400 — ns tCSH — 400 — ns tPD — — 1.0 ms tR=20% to 80% — 4.0 ms tF=80% to 20% — 4.0 ms Parameter Clock Frequency Clock Pulse Width CS Setup Time (CS-Clock) CS Hold Time (Clock-CS) DATA Output Delay Time (Clock-DATA I/O) Output Slew Rate Time tR tF CL=100pF VDD Rise Time tPRZ Mounted in a unit — 100 ms VDD Off Time tPOF Mounted in a unit, VDD=0.0V 5.0 — ms CS Wait Time tRSOFF — 400 — ms 8/25 FEDL9222-02 ¡ Semiconductor ML9222 TIMING DIAGRAM Data Input Timing CS tCSL tCSS –3.8V –0.8V 1/fC tCW tCSH tCW –3.8V CLOCK –0.8V tDS tDH –3.8V DATA I/O (INPUT) VALID VALID VALID VALID –0.8V Data Output Timing CS –3.8V tCSS –0.8V tCSH –3.8V CLOCK –0.8V tPD –3.8V DATA I/O (OUTPUT) –0.8V Reset Timing VDD tPRZ tPOF –0.8VDD –0.0V tRSOFF –3.8V CS –0.0V Driver Output Timing SEG1-32, GRID1-3 tR tF –0.8VDD –0.2VDD 9/25 FEDL9222-02 ¡ Semiconductor ML9222 A/D Converter Characteristics (Ta = –40 to +85°C, VDD = 8.0 to 18.0 V) Parameter Condition Min. Typ. Max. Unit A/D Conversion Accuracy — — — ±1 LSB Reference Voltage (VREG) — 4.5 5.0 5.5 V Output Current — — — –10 mA Input Voltage Range — GND — VREG V R2 = 10kW±5%, C2 = 27pF±5% 256 310 394 ms Conversion Time/Channel Keyscan Characteristics (Ta = –40 to +85°C, VDD = 8.0 to 18.0 V) Parameter Condition Min. Typ. Max. Unit Keyscan Cycle Time R2 = 10kW±5%, C2 = 27pF±5% 160 194 246 ms Keyscan Pulse Width R2 = 10kW±5%, C2 = 27pF±5% 32 39 49 ms Keyscan Timing Keyscan Cycle Time ROW1 Keyscan Pulse Width ROW2 ROW3 ROW4 ROW5 10/25 FEDL9222-02 ¡ Semiconductor ML9222 Output Timing (Duplex Operation) (The dimming data is 1016/1024) *1bit time=4/fOSC 2048bit times (1 display cycle) VDD GRID1 1016bit times 1016bit times 8bit times 8bit times 8bit times D-GND VDD 1016bit times GRID2 D-GND VDD GRID3 3bit times 5bit times 5bit times D-GND 5bit times VDD SEG1-32 1019bit times 1019bit times 5bit times 1019bit times 5bit times D-GND 5bit times 5V DIM OUT 1019bit times 1019bit times 5bit times 1019bit times 5bit times L-GND 5bit times 5V SYNC OUT1 1019bit times 1029bit times 5bit times SYNC OUT2 1029bit times 1019bit times 5bit times 1019bit times L-GND 5bit times 5V 1029bit times L-GND Output Timing (Triplex Operation) (The dimming data is 1016/1024) *1bit time=4/fOSC 3072bit times (1 display cycle) VDD GRID1 1016bit times 8bit times 8bit times D-GND VDD 1016bit times GRID2 D-GND 8bit times VDD 1016bit times GRID3 3bit times 5bit times 5bit times 5bit times D-GND VDD SEG1-32 1019bit times 1019bit times 5bit times 1019bit times 5bit times 5bit times D-GND 5V DIM OUT 1019bit times 1019bit times 5bit times 1019bit times 5bit times 5bit times L-GND 5V SYNC OUT1 1019bit times 1029bit times 5bit times SYNC OUT2 1029bit times 1019bit times 1019bit times 5bit times 5bit times L-GND 5V 1019bit times L-GND 11/25 FEDL9222-02 ¡ Semiconductor ML9222 Output Timing (Duplex Operation) (The dimming data is 64/1024) *1bit time=4/fOSC 2048bit times (1 display cycle) VDD GRID1 64bit times 64bit times 960bit times 960bit times 960bit times D-GND VDD 64bit times GRID2 D-GND VDD GRID3 3bit times 957bit times 957bit times 957bit times D-GND VDD SEG1-32 67bit times 67bit times 957bit times 67bit times 957bit times 957bit times D-GND 5V DIM OUT 67bit times 67bit times 957bit times 67bit times 957bit times 957bit times L-GND 5V SYNC OUT1 67bit times 1981bit times 957bit times 67bit times 957bit times 957bit times L-GND 5V SYNC OUT2 1981bit times 67bit times 1981bit times L-GND Output Timing (Triplex Operation) (The dimming data is 64/1024) *1bit time=4/fOSC 3072bit times (1 display cycle) VDD GRID1 64bit times 960bit times 960bit times D-GND VDD 64bit times GRID2 D-GND 960bit times VDD 64bit times GRID3 3bit times 957bit times 957bit times 957bit times D-GND VDD SEG1-32 67bit times 67bit times 957bit times 67bit times 957bit times 957bit times D-GND 5V DIM OUT 67bit times 67bit times 957bit times 67bit times 957bit times 957bit times L-GND 5V SYNC OUT1 67bit times 1981bit times 957bit times 67bit times 957bit times 957bit times L-GND 5V SYNC OUT2 1981bit times 67bit times 67bit times L-GND 12/25 FEDL9222-02 ¡ Semiconductor ML9222 FUNCTIONAL DESCRIPTION Power-on Reset When power is turned on, ML9222 is initialized by the internal power-on reset circuit. The status of the internal circuit after initialization is as follows: • The contents of the shift registers and latches are set to "0". • The digital dimming duty cycle is set to "0". • All segment outputs are set to Low level. • All grid outputs are set to High level. • All the ROW outputs are set to Low level. • INT output is set to Low level. Data Input and Output Data input and output through the DATA I/O pin is valid only when the CS pin is set at a High level. The input data to DATA I/O pin is shifted into the shift register at the rising edge of the serial clock. The data is automatically loaded to the latches when the CS pin is set at a Low level. 10-bit dimming data (D1 to D10) and 32-bit segment data (S1 to S32) are used for inputting of dimming data and display data. To transfer these two data, the mode data (M0 to M2) must be sent after each of these data succeddingly. The output data from the DATA I/O pin is output from the shift register at the rising edge of the serial clock. ML9222 outputs 64-bit (8ch ¥ 8bits) A/D data (A11 to A88) and 37-bit key data (S11 to S55, R1, Q11 to Q13, R2, Q21 to Q23, R3 and Q31 to Q33). To receive these data, the mode data (M0 to M2) mast be sent first and then CS must be set once to Low level and set again to High level. Then inputting serial clocks, these data are output from the DATA I/O pin. When the CS pin is set at a Low level, the DATA I/O pin returns to an input pin. To stop the keyscan, the only mode data (M0 to M2) must be sent. After the mode data transfer, the key scanning is stopped immediately. Mode Data ML9222 has the seven function modes. The function mode is selected by the mode data (M0 to M2). The relation between function mode and mode data (M0 to M2) is as follows: FUNCTION MODE OPERATING MODE FUNCTION DATA M0 M1 M2 0 Segment Data for GRID1-3 Input 0 0 0 1 Segment Data for GRID1 Input 1 0 0 2 Segment Data for GRID2 Input 0 1 0 3 Segment Data for GRID3 Input 1 1 0 4 Digital Dimming Data Input 0 0 1 5 Keyscan Stop 1 0 1 6 Switch Data Output 0 1 1 7 A/D Data Output 1 1 1 13/25 FEDL9222-02 ¡ Semiconductor ML9222 Segment Data Input [Function Mode: 0 to 3] • ML9222 receives the segment data when function mode 0 to 3 are selected. • The same segment data is transferred to the 3 segment data latch correspond to GRID 1 to 3 at the same time when the function mode 0 is selected. • The segment data is transferred to only one segment data latch that is selected by mode data, when the function mode is 1, 2 or 3 is selected. • Segment output (SEG1 to 32) becomes High level when the segment data (S1 to 32) is High level. [Data Format] Input Data : 35 bits Segment Data : 32 bits Mode Data : 3 bits Bit 1 2 3 4 29 32 33 34 35 Input Data S1 S2 S3 S4 S29 S30 S31 S32 30 31 M0 M1 M2 Segment Data (32bits) Mode Data (3bits) [Bit correspondence between segment output and segment data] SEG n 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Segment data S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 SEG n 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Segment data S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 S32 14/25 FEDL9222-02 ¡ Semiconductor ML9222 Digital Dimming Data Input [Function Mode: 4] • ML9222 receives the digital dimming data when function mode 4 is selected. • The output duty changes in the range of 0/1024 (0%) to 1016/1024 (99.2%) for each grid. • The 10-bit digital dimming data is input from LSB. [Data Format] Input Data : 13 bits Digital Dimming Data: 10 bits Mode Data : 3 bits Bit 1 2 3 4 5 6 7 8 9 Input Data D1 LSB D2 D3 D4 D5 D6 D7 D8 D9 Digital Dimming Data (10bits) (LSB) Dimming Data 10 11 12 13 D10 M0 M1 M2 MSB Mode Data (3bits) (MSB) Duty Cycle D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 0 0 0 0 0 0 0 0 0 0 0/1024 1 0 0 0 0 0 0 0 0 0 1/1024 1 1 1 0 1 1 1 1 1 1 1015/1024 0 0 0 1 1 1 1 1 1 1 1016/1024 1 0 0 1 1 1 1 1 1 1 1016/1024 1 1 1 1 1 1 1 1 1 1 1016/1024 15/25 FEDL9222-02 ¡ Semiconductor ML9222 Keyscan Stop [Function Mode: 5] • ML9222 stops a key scanning when function mode 5 are selected. • To select this mode, the only mode data (M0 to M2) is needed. • The actual time lag range between receipt of the keyscan stop command and the ceasing of scanning is 2.4ms to 3.6ms [Input Data Format] Input Data Mode Data : 3 bits : 3 bits Bit 28 29 30 Input Data M0 M1 M2 Mode Data (3bits) Switch Data Output [Function Mode: 6] • ML9222 output the switch data when function mode 6 is selected. • To select this mode, the only mode data (M0 to M2) is needed. • When ML9222 recieves this mode, the DATA I/O pin is changed to an output pin. • 37-bit switch data come out from the DATA I/O pin synchronizing with the rise edge of the clock. • When the CS pin is set at the low level, the DATA I/O pin returns to an input pin. • R1, R2, R3=0, implies Right rotation of the knob (Clockwise) • R1, R2, R3=1, implies Left rotation of the knob (Counter Clockwise) • Contact Count bits are Q11 (LSB) to Q13 (MSB), Q21 (LSB) to Q23 (MSB) and Q31 (LSB) to Q33 (MSB) [Input Data Format] Input Data Mode Data : 3 bits : 3 bits Bit 28 29 30 Input Data M0 M1 M2 Mode Data (3bits) [Output Data Format] Output Data : 37 bits 5¥5 push swithc Data : 25 bits Encoder switch Data : 12 bits Bit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Output Data S11 S12 S13 S14 S15 S21 S22 S23 S24 S25 S31 S32 S33 S34 S35 S41 S42 S43 S44 S45 S51 S52 S53 S54 S55 Bit 26 27 28 29 30 31 32 33 34 35 36 37 Output Data R1 Q11 Q12 Q13 R2 Q21 Q22 Q23 R3 Q31 Q32 Q33 Sij:i=ROW1 to 5, j=COL1 to 5 Sij=1: Switch ON Sij=0: Switch OFF 16/25 FEDL9222-02 ¡ Semiconductor ML9222 A/D Data Output [Function Mode: 7] • ML9222 output the A/D data when function mode 7 is selected. • To select this mode, the only mode data (M0 to M2) is needed. • When ML9222 recieves this mode, the DATA I/O pin is changed to an output pin. • 64-bit A/D data come out from the DATA I/O pin synchronizeing with the rise edge of the clock. • When the CS pin is set at the low level, the DATA I/O pin returns to an input pin. [Input Data Format] Input Data Mode Data : 3 bits : 3 bits Bit 28 29 30 Input Data M0 M1 M2 Mode Data (3bits) [Output Data Format] Output Data A/D Data Bit Output Data : 64 bits : 64 bits 1 Output Data Output Data A/D Bit Output Data A/D 4 5 6 7 8 9 10 11 12 13 14 15 16 (MSB)(LSB) CH1 (MSB) CH2 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 A31 A32 A33 A34 A35 A36 A37 A38 A41 A42 A43 A44 A45 A46 A47 A48 (LSB) A/D Bit 3 (LSB) A/D Bit 2 A11 A12 A13 A14 A15 A16 A17 A18 A21 A22 A23 A24 A25 A26 A27 A28 (MSB)(LSB) CH3 (MSB) CH4 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 A51 A52 A53 A54 A55 A56 A57 A58 A61 A62 A63 A64 A65 A66 A67 A68 (LSB) (MSB)(LSB) (MSB) CH5 CH6 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 A71 A72 A73 A74 A75 A76 A77 A78 A81 A82 A83 A84 A85 A86 A87 A88 (LSB) (MSB)(LSB) CH7 (MSB) CH8 17/25 FEDL9222-02 ¡ Semiconductor ML9222 The rotary encoder switch function. As figure 1 shows, the rotary encoder switch circuit is consisted of Phase detection, Interrupt generation, Up/down counter, Direction latch and Parallel-in serial-out shift register. A B Phase Detection UP DOWN Interrupt Generation UP/DOWN Counter Q3 Q2 Q1 for INT Direction Latch R1 P-in/S-out Shift Registor Output data Fig.1 The Rotary Encoder Switch Circuit 1) Phase detection 1-1) Clockwise The input A and B have a chattering absorption circuit of 620ns (typ.). When signal A and B input as fig. 2, the phase detection circuit outputs UP signal after the chattering absorption period. At this time, the output INT also goes to high level, so this signal can be used as an interrupt. The INT stays High level until the switch data-output mode is selected. A chattering absorption time B UP (internal) INT Fig.2 The Input and Output Timing in Case of Clockwise. 18/25 FEDL9222-02 ¡ Semiconductor ML9222 1-2) counter clockwise When signal A and B input as fig. 3, the phase detection circuit outputs Down signal after the chattering absorption period. At this time, the output INT also goes to High level. The INT stays High level until the switch data-output mode is selected. A chattering absorption time B DOWN (internal) INT Fig.3 The Input and Output Timing in Case of Counter Clockwise. 2) UP/DOWN COUNTER When the UP/DOWN COUNTER is input UP, it counts up and when it is input DOWN, it counts down. But if overcounte of "111" occurs the UP/DOWN COUNTER stays "111". A B Q3, Q2, Q1 001 010 011 100 101 110 111 111 Fig.4 3) Direction latch When the Direction latch is input DOWN the output R goes "1". But if the UP pulse is input and the counts value change to plus value, the output R goes to "0". A B R1 Q1, Q2, Q3 100 010 100 000 100 010 Fig.5 19/25 FEDL9222-02 ¡ Semiconductor ML9222 4) P-in/S-out shift resistor When the switch data output mode is selected and SC goes L, all the key data send to the shift resistor, and the up/down counter is reset and the INT signal goes "L". CS Data I/O C1 C2 C3 C4 C5 C1 C2 C3 C4 C5 ROW1 ROW2 C1 C2 C3 C4 C5 R1 Q11Q12Q13 R2 Q21Q22Q23 R3 Q31Q32Q33 ROW5 Rotary CLOCK INT When CS goes L, the up/downn counter is reset and the INT goes "L". Fig.6 20/25 FEDL9222-02 ¡ Semiconductor ML9222 Keyscan Keyscanning is started only when depression or release of any key is detected in order to minimize noise caused by scanning signal. Then, keyscanning is continued until the keyscan stop mode is sent from a microcomputer. The INT pin goes to the high level at the completion of 1-cycle scanning after the keyscan start, so the (high level) signal sent from the INT pin can be used as an interrupt signal. [Keyscan Timing] ROW 1 ROW 2 ROW 3 ROW 4 ROW 5 1 Cycle INT Depress/Release Keyscan stop mode is selected. Note: Keyscanning cannot be stopped by selecting the keyscan stop mode only once if: - keyscanning is started after depression or release of any key is detected, and then - a key is depressed or released again before the keyscan stop mode is selected. To stop keyscanning, it is required to select the keyscan stop mode once again. Depress INT CS Depress Keyscan MODE5 Release Keyscan MODE5 MODE5 MODE5 : Keyscan stop 21/25 DUP/TRI SEG32 GRID1 VREG GRID2 GRID3 VDISP MSM9210 (SLAVE) SEG1 DUP/TRI SEG32 GRID1 M/S GRID2 GND GRID3 S1 S2 S3 S62 S63 S64 CH1 to 8 G1 GND Microcontroller 5¥5 Key matrix GND G2 ROW1 to 5 COL1 to 5 Ef SYNC OUT 2 SYNC OUT 1 DIM OUT CS DATA I/O CLOCK VCC SYNC IN 2 SYNC IN 1 DIM IN CS DATA IN CLOCK OSC 1 OSC0 L-GND OSC 0 L-GND GND SYNC OUT 2 SYNC OUT 1 DIM OUT FEDL9222-02 ML9222 22/25 GND Duplex VFD Tube ¡ Semiconductor VDISP VDD SEG1 APPLICATION CIRCUITS VDD ML9222 1. Circuit for the duplex VFD tube with 128 segments (2 Grid ¥ 64 Anode) VCC VDISP VREG CH1 to 8 VDD VDISP MSM9210 (SLAVE) SEG1 SEG1 SEG32 GRID1 DUP/TRI SEG32 GRID1 GRID2 M/S GRID2 GRID3 GRID3 GND G1 G2 GND 5¥5 Key matrix S1 S2 S3 ROW1 to 5 COL1 to 5 S62 S63 S64 Triplex VFD Tube G3 Ef Microcontroller GND SYNC OUT 2 SYNC OUT 1 DIM OUT CS DATA I/O CLOCK VCC SYNC IN 2 SYNC IN 1 DIM IN CS DATA IN CLOCK OSC 1 OSC0 L-GND OSC 0 L-GND DUP/TRI GND FEDL9222-02 ML9222 23/25 GND SYNC OUT 2 SYNC OUT 1 DIM OUT ¡ Semiconductor VDD ML9222 2. Circuit for the triplex VFD tube with 192 segments (3 Grid ¥ 64 Anode) VCC FEDL9222-02 ¡ Semiconductor ML9222 PACKAGE DIMENSIONS (Unit : mm) QFP80-P-1420-0.80-BK Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Epoxy resin 42 alloy Solder plating 5 mm or more Package weight (g) 1.27 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 24/25 FEDL9222-02 ¡ Semiconductor ML9222 NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party’s right which may result from the use thereof. 6. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. No part of the contents contained herein may be reprinted or reproduced without our prior permission. 9. MS-DOS is a registered trademark of Microsoft Corporation. Copyright 2000 Oki Electric Industry Co., Ltd. Printed in Japan 25/25