E2C0038-39-95 ¡ Semiconductor ¡ Semiconductor MSM9210 This version: Sep. 1999 MSM9210 Previous version: Aug. 1999 32-Bit Duplex/Triplex (1/2 duty / 1/3 duty) VF Controller/Driver with Digital Dimming GENERAL DESCRIPTION The MSM9210 is a full CMOS controller/driver for Duplex or Triplex (1/2 duty or 1/3 duty) vacuum fluorescent display tube. It consists of a 32-segment driver multiplexed to drive up to 96 segments, and 10-bit digital dimming circuit. MSM9210 features a selection of a master mode and a slave mode, and therefore it can be used to expand segments for the VFD driver with keyscan and A/D converter function. MSM9210 provides an interface with a microcontroller only by three signal lines: DATA IN, CLOCK and CS. FEATURES • Logic supply voltage (VDD) : 4.5 to 5.5V : 8 to 18V • Driver supply voltage (VDISP) • Duplex/Triplex (1/2 duty / 1/3 duty) selectable DUP/TRI=1/2 duty selectable at "H" level DUP/TRI=1/3 duty selectable at "L" level • Number of display segments Max. 64-segment display (during 1/2 duty mode) Max. 96-segment display (during 1/3 duty mode) • Master/Slave selectable M/S=Master mode selectable at "H" level M/S=Slave mode selectable at "L" level • Interface with a microcontroller Three lines: CS, CLOCK, and DATA IN • 32-segment driver outputs : IOH=–5mA at VOH=VDISP–0.8V (SEG1 to 22) (can be directly connected to VFD tube : IOH=–10mA at VOH=VDISP–0.8V (SEG23 to 32) and require no external resisters) : IOL=500mA at VOL=2V (SEG1 to 32) • 3-grid pre-driver outputs : IOH=–5.0mA at VOH=VDISP–0.8V (require external drivers) IOL=10mA at VOL=2V • Logic outputs : IOH=–200mA at VOH=VDD–0.8V IOL=200mA at VOL=0.8V • Built-in digital dimming circuit (10-bit resolution) • Built-in oscillation circuit (external R and C) • Built-in Power-On-Reset circuit • Package options: 56-pin plastic QFP (QFP56-P-910-0.65-2K) Product name: MSM9210GS-2K 64-pin plastic QFP (QFP64-P-1414-0.80-BK) Product name: MSM9210GS-BK 1/19 ¡ Semiconductor MSM9210 BLOCK DIAGRAM SEG1 VDISP 32 Segment Driver D-GND Power On Reset VDD L-GND 0H in1-32 4H 1H POR in1-3 CS Control 0H POR Out1-32 Segment Latch 1 in1-32 Out1-32 96 to 32 Segment Control in1-32 in1-32 Out1-32 Segment Latch 2 in1-32 Out1-32 Segment Latch 3 in1-32 2H 0H POR Out1-3 3bit Shift Register Out1-32 32bit Shift Register POR POR DATA IN OSC0 OSC1 3 Grid pre Driver POR Mode Select CLOCK 4H POR 3H 0H POR in1-10 Dimming Latch Out1-10 10bit Digital Dimming OSC POR DIM IN DIM OUT SYNC IN1 SYNC IN2 GRID1 GRID2 GRID3 SEG32 SYNC OUT1 Timing Generator SYNC OUT2 M/S DUP/TRI 2/19 ¡ Semiconductor MSM9210 INPUT AND OUTPUT CONFIGURATION Schematic Diagram of Driver Output Circuit VDISP VDISP OUTPUT D-GND D-GND 3/19 ¡ Semiconductor MSM9210 43 VDISP 44 SEG14 45 SEG15 46 SEG16 47 SEG17 48 SEG18 49 D-GND 50 SEG19 51 SEG20 52 SEG21 53 SEG22 54 SEG23 55 SEG24 56 VDISP PIN CONFIGURATION (TOP VIEW) SEG25 1 42 SEG13 SEG26 2 41 SEG12 SEG27 3 40 SEG11 SEG28 4 39 SEG10 SEG29 5 38 SEG9 SEG30 6 37 SEG8 SEG31 7 36 SEG7 SEG32 8 35 SEG6 GRID1 9 34 SEG5 GRID2 10 33 SEG4 GRID3 11 32 SEG3 D-GND 12 31 SEG2 NC 13 30 SEG1 DIM OUT 28 29 NC SYNC OUT 1 27 M/S 25 SYNC OUT 2 26 OSC0 23 DUP/TRI 24 OSC1 22 L-GND 21 CLOCK 19 DATA IN 20 CS 18 SYNC IN 2 17 DIM IN 15 SYNC IN 1 16 VDD 14 NC: No connection 56-pin Plastic QFP 4/19 NC 1 SEG25 2 SEG26 3 SEG27 4 SEG28 5 SEG29 6 SEG30 7 SEG31 8 50 NC 49 VDISP 52 SEG15 51 SEG14 54 SEG17 53 SEG16 56 D-GND 55 SEG18 58 SEG20 57 SEG19 60 SEG22 59 SEG21 MSM9210 62 SEG24 61 SEG23 64 VDISP 63 NC ¡ Semiconductor 48 NC 47 NC 46 SEG13 45 SEG12 44 SEG11 43 SEG10 42 SEG9 41 SEG8 SEG32 40 SEG7 39 SEG6 9 GRID1 10 GRID2 11 38 SEG5 37 SEG4 GRID3 12 D-GND 13 36 SEG3 35 SEG2 NC 14 VDD 15 34 SEG1 33 NC DIM OUT 31 NC 32 SYNC OUT2 29 SYNC OUT1 30 DUP/TRI 27 M/S 28 OSC1 25 OSC0 26 DATA IN 23 L-GND 24 CS 21 CLOCK 22 SYNC IN1 19 SYNC IN2 20 NC 17 DIM IN 18 NC 16 NC: No connection 64-pin Plastic QFP 5/19 ¡ Semiconductor MSM9210 PIN DESCRIPTIONS Symbol Pin Type Description QFP56 QFP64 VDISP 43,56 49,64 — VDD 14 15 — Power supply pin for logic drive. D-GND 12, 49 13, 56 — D-GND is ground pin for the VFD driver circuit. L-GND is ground L-GND 21 24 — 30 to 42, 34 to 46, 44 to 48, 51 to 55, 50 to 53 57 to 60 1 to 8, 2 to 9, 54, 55 61, 62 Power supply pins for VFD driver circuit. 43 pin and 56 pin should be connected externally. pin for the logic circuit. 12pin, 21pin and 49pin should be SEG1 to 22 connected externally. Segment (anode) signal output pins for a VFD tube. O These pins can be directly connected to the VFD tube. External circuit is not required. IOH£–5 mA Segment (anode) signal output pins for a VFD tube. SEG23 to 32 O These pins can be directly connected to the VFD tube. External circuit is not required. IOH£–10 mA Inverted Grid signal output pins. GRID1 to 3 9, 10, 11 10, 11, 12 O For pre-driver, the external circuit is required. IOL£10 mA CS 18 21 I CLOCK 19 22 I DATA IN 20 23 I DUP/TRI M/S DIM IN 24 25 15 27 28 18 Chip select input pin. Data is not transferred when CS is set to a Low level. Shift clock input pin. Serial data shifts at the rising edge of the CLOCK. Serial data input pin (positive logic). Data is input to the shift register at the rising edge of the CLOCK signal. I Duplex/Triplex operation select input pin. Duplex (1/2 duty) operation is selected when this pin is set to VDD. Triplex (1/3 duty) operation is selected when this pin is set to L-GND. I Master/Slave mode select input pin. Master mode is selected when this pin is set to VDD. Slave mode is selected when this pin is set to L-GND. I Dimming pulse input. When the slave mode is selected, the pulse width of the all segment output are controlled by a input pulse width of DIM IN. Connect this pin to the master side DIM OUT pin at the slave mode. When the master mode is selected, the input level of this pin is ignored and the pulse width of the all grids and segment outputs are controlled by a built-in 10-bit dimming circuit. Connect this pin to VDD or L-GND at the master mode. 6/19 ¡ Semiconductor Symbol MSM9210 Pin QFP56 QFP64 Type SYNC IN 1, 2 16, 17 19, 20 I DIM OUT 28 31 O SYNC OUT 1, 2 26, 27 29, 30 O OSC0 23 26 I OSC1 22 25 O Description Synchronous signal input. When the slave mode is selected, connect these pins to the master side SYNC OUT 1, and 2 pins. When the master mode is selected, the input level of these pins are ignored. Connect these pins to VDD or L-GND at the master mode. Dimming pulse output. Connect this pin to the slave side DIM IN pin. Synchronous signal output. Connect these pins to the slave side SYNC IN 1, and 2 pins. RC oscillator connecting pins. Oscillation frequency depends on display tubes to be used. For details, refer to ELECTRICAL CHARACTERISTICS. OSC0 R C OSC1 ABSOLUTE MAXIMUM RATING Parameter Symbol Condition Driver Supply Voltage VDISP Logic Supply Voltage VDD Input Voltage Power Dissipation Storage Temperature Output Current Ratings Unit — –0.3 to +20 V — –0.3 to +6.5 V VIN — –0.3 to VDD+0.3 V PD Ta≥25°C 360 mW TSTG — –55 to +150 °C IO1 SEG1 to 22 –10.0 to +2.0 mA IO2 SEG23 to 32 –20.0 to +2.0 mA IO3 GRID1 to 3 –10.0 to +20.0 mA IO4 DIM OUT, SYNC OUT1, SYNC OUT2 –2.0 to +2.0 mA RECOMMENDED OPERATING CONDITIONS Parameter Symbol Condition Min. Typ. Max. Unit Driver Supply Voltage VDISP — 8.0 13.0 18.0 V Logic Supply Voltage VDD — 4.5 5.0 5.5 V High Level Input Voltage VIH All inputs except OSC0 0.8VDD — — V Low Level Input Voltage VIL All inputs except OSC0 — — 0.2VDD V fC — — — 1.0 MHz TOP — –40 — +85 °C Clock Frequency Operating Temperature 7/19 ¡ Semiconductor MSM9210 When a 1/2 duty VFD tube is used Symbol Condition Oscillation Frequency fOSC R=8.2KW±5%, C=22pF±5% 1.0 Frame Frequency fFR R=8.2KW±5%, C=22pF±5% 122 Parameter Min. Typ. Max. Unit 1.5 2.0 MHz 183 244 Hz When a 1/3 duty VFD tube is used Symbol Condition Min. Typ. Max. Unit Oscillation Frequency fOSC R=6.2KW±5%, C=22pF±5% 1.5 2.25 3.0 MHz Frame Frequency fFR R=6.2KW±5%, C=22pF±5% 122 183 244 Hz Parameter 8/19 ¡ Semiconductor MSM9210 ELECTRICAL CHARACTERISTICS DC Characteristics Ta=–40 to +85°C,VDISP =8.0 to 18.0V, VDD=4.5 to 5.5V Parameter Symbol Applied pin Condition Min. Max. Unit — 0.8VDD — V — — 0.2VDD V VIH=VDD –1.0 +1.0 mA High Level Input Voltage VIH *1) Low Level Input Voltage VIL *1) High Level Input Current IIH *1) VIL=GND Low Level Input Current High Level Output Voltage Low Level Output Voltage Supply Current IIL *1) VOH1 SEG1-22 VOH2 SEG23-32 VOH3 GRID1-3 IOH1=–5mA VDISP=9.5V IOH2=–10mA IOH3=–5mA –1.0 +1.0 mA VDISP–0.8 — V VDISP–0.8 — V VDISP–0.8 — V VOH4 *2) IOH4=–200mA VDD–0.8 — V VOL1 SEG1-22 IOL1=500mA — 2.0 V VOL2 SEG23-32 VDISP=9.5V IOL2=500mA — 2.0 V IOL3=10mA — 2.0 V IOL4=200mA — 0.8 V VDD=4.5V VOL3 GRID1-3 VOL4 *2) IDISP VDISP fOSC=3.0MHz, no load — 100 mA IDD VDD fOSC=3.0MHz, no load — 5.0 mA VDD=4.5V *1) CS, CLOCK, DATA IN, DIM IN, SYNC IN 1, SYNC IN 2, M/S, DUP/TRI *2) DIM OUT, SYNC OUT 1, SYNC OUT 2 9/19 ¡ Semiconductor MSM9210 AC Characteristics Ta=–40 to +85°C,VDISP =8.0 to 18.0V, VDD=4.5 to 5.5V Parameter Symbol Condition Clock Frequency Min. Max. Unit fC — — 1.0 MHz tCW — 400 — ns Data Setup Time tDS — 400 — ns Data Hold Time tDH — 400 — ns CS Off Time tCSL — 20 — ms tCSS — 400 — ns tCSH — 400 — ns tRSOFF — 400 — ms — 2.0 ms Clock Pulse Width CS Setup Time (CS-Clock) CS Hold Time (Clock-CS) CS Wait Time tR Output Slew Rate Time tR=20% to 80% CL=100pF — 2.0 ms VDD Rise Time tPRZ Mounted in a unit — 100 ms VDD Off Time tPOF Mounted in a unit, VDD=0.0V 5.0 — ms tF tF=80% to 20% TIMING DIAGRAM l Data Input Timing tCSL tCSS CS 1/fC tCW CLOCK tDS DATA IN tCSH tCW –0.2VDD –0.8VDD –0.2VDD tDH VALID –0.8VDD VALID VALID –0.8VDD VALID –0.2VDD l Reset Timing VDD tPRZ –0.8VDD tPOF –0.0V tRSOFF –0.8VDD CS –0.0V l Driver Output Timing SEG1-32, GRID1-3 tR tF tR –0.8VDISP –0.2VDISP 10/19 ¡ Semiconductor MSM9210 l Output Timing (Duplex Operation) *1bit time=4/fOSC (The dimming data is 1016/1024 at the master mode) 2048bit times (1 display cycle) GRID1 1016bit times VDISP 1016bit times 8bit times 8bit times 8bit times D-GND VDISP 1016bit times GRID2 D-GND VDISP GRID3 3bit times SEG1-32 1019bit times 5bit times 1019bit times 5bit times DIM OUT 1019bit times 1019bit times SYNC OUT2 1029bit times 5bit times VDISP D-GND 5bit times VDD 1019bit times 5bit times 1029bit times 5bit times D-GND 5bit times 1019bit times 1019bit times 5bit times SYNC OUT1 5bit times L-GND 5bit times VDD 1019bit times 5bit times 1019bit times L-GND 5bit times VDD 1029bit times L-GND l Output Timing (Triplex Operation) *1bit time=4/fOSC (The dimming data is 1016/1024 at the master mode) 3072bit times (1 display cycle) GRID1 VDISP 1016bit times 8bit times 8bit times D-GND VDISP 1016bit times GRID2 D-GND 8bit times 3bit times SEG1-32 1019bit times 5bit times 1019bit times 5bit times DIM OUT 1019bit times 1019bit times 5bit times SYNC OUT1 1019bit times 1029bit times 5bit times SYNC OUT2 VDISP 1016bit times GRID3 1029bit times 1019bit times 5bit times 5bit times VDISP 1019bit times 5bit times 5bit times 5bit times 1019bit times L-GND VDD 1019bit times 5bit times D-GND VDD 1019bit times 5bit times D-GND 5bit times L-GND VDD L-GND 11/19 ¡ Semiconductor MSM9210 FUNCTIONAL DESCRIPTION Power-on Reset When power is turned on, MSM9210 is initialized by the internal power-on reset circuit. The status of the internal circuit after initialization is as follows: • The contents of the shift registers and latches are set to "0". • The digital dimming duty cycle is set to "0". • All segment outputs are set to Low level. • All grid outputs are set to High level. Data Transfer Method Data can be transferred between the rising edge and the next falling edge of chip select input. The mode data, segment data and dimming data are written by a serial transfer method. The serial data is input to the shift register at the rising edge of a shift clock pulse. The mode data (M0 to M2) must be transferred after the segment data and dimming data succeedingly. When the chip select input falls, an internal LOAD signal is automatically generated and data is loaded to the latches. Function Mode Function mode is selected by the mode data (M0 to M2). The relation between function mode and mode data is as follows: FUNCTION MODE FUNCTION DATA OPERATING MODE M0 M1 M2 0 Segment Data for GRID1-3 Input 0 0 0 1 Segment Data for GRID1 Input 1 0 0 2 Segment Data for GRID2 Input 0 1 0 3 Segment Data for GRID3 Input 1 1 0 4 Digital Dimming Data Input 0 0 1 Segment Data Input [Function Mode: 0 to 3] • MSM9210 receives the segment data when function mode 0 to 3 are selected. • The same segment data is transferred to the 3 segment data latches corresponding to GRID 1 to 3 at the same time when the function mode 0 is selected. • The segment data is transferred to only one segment data latch corresponding to the specified GRID when the function mode is 1, 2 or 3 is selected. • Segment output (SEG1 to 32) becomes High level (lightning) when the segment data (S1 to S32) is set to "1". [Data Format] Input Data : 35 bits Segment Data : 32 bits Mode Data : 3 bits Bit 1 2 3 4 29 32 33 34 35 Input Data S1 S2 S3 S4 S29 S30 S31 S32 M0 M1 M2 Segment Data (32bits) 30 31 Mode Data (3bits) 12/19 ¡ Semiconductor MSM9210 [Bit correspondence between segment output and segment data] SEG n 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Segment data S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 SEG n Segment data S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 S32 Digital Dimming Data Input [Function Mode: 4] • MSM9210 receives the digital dimming data when function mode 4 is selected. • The output duty changes in the range of 0/1024 (0%) to 1016/1024 (99.2%) for each grid. • The 10-bit digital dimming data is input from LSB. [Data Format] Input Data : 13 bits Digital Dimming Data: 10 bits Mode Data : 3 bits Bit 1 2 3 4 5 6 7 8 9 Input Data D1 LSB D2 D3 D4 D5 D6 D7 D8 D9 Digital Dimming Data (10bits) (LSB) Dimming Data 10 11 12 13 D10 M0 M1 M2 MSB Mode Data (3bits) (MSB) Duty Cycle D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 0 0 0 0 0 0 0 0 0 0 0/1024 1 0 0 0 0 0 0 0 0 0 1/1024 1 1 1 0 1 1 1 1 1 1 1015/1024 0 0 0 1 1 1 1 1 1 1 1016/1024 1 0 0 1 1 1 1 1 1 1 1016/1024 1 1 1 1 1 1 1 1 1 1 1016/1024 Master Mode Master Mode is selected when M/S pin is set at High level. The master mode operation is as follows: • The input levels of DIM IN, SYNC IN1 and SYNC IN2 are ignored, and these pins should be connected to L-GND or VDD. • The pulse width of GRID1 to 3 and SEG1 to 32 are controlled by the internal digital dimming circuit. • The segment Latch1 to 3 corresponding to GRID1 to 3 are selected by the internal timing generator. 13/19 ¡ Semiconductor MSM9210 Slave Mode Slave Mode is selected when M/S pin is set at Low level. The slave mode operation is as follows: • The internal dimming circuit is ignored. • The pulse width of SEG1 to 32 are controlled by the pulse width of DIM IN signal. • The segment Latch1 to 3 corresponding to GRID1 to 3 are selected by SYNC IN1 and SYNC IN2 signals. • The output levels of GRID1 to 3 are set at High level. The output levels of DIM OUT, SYNC OUT1 and SYNC OUT2 are set at Low level. [Correspondence between SYNC IN1, 2 and Segment Latch1 to 3] SYNC IN 1 SYNC IN 2 Segment Latch 0 0 1 0 0 1 Latch2 GRID2 1 1 Latch3 GRID3 [Correspondence between DIM IN and SEG1 to 32] GRID DIM IN SEG1 to 32 No No 0 Low Latch1 GRID1 1 High Note: Low: Lights OFF High: Lights ON 14/19 Microcontroller GND R C GND SEG32 GRID1 M/S GRID2 SYNC IN 2 SYNC IN 1 DIM IN CS DATA IN CLOCK OSC 1 OSC 0 L-GND GRID3 SYNC OUT 2 SYNC OUT 1 DIM OUT VDD D-GND DUP/TRI SEG32 GRID1 M/S GRID2 GND R C GND SEG1 SYNC IN 2 SYNC IN 1 DIM IN CS DATA IN CLOCK OSC 1 OSC 0 L-GND GRID3 SYNC OUT 2 SYNC OUT 1 DIM OUT S1 S2 S3 S62 S63 S64 G1 G2 Duplex VF Tube Ef D-GND 15/19 MSM9210 GND DUP/TRI VDISP MSM9210 (SLAVE) ¡ Semiconductor VDD VDD SEG1 APPLICATION CIRCUITS VDD VDISP VDISP MSM9210 (MASTER) 1. Circuit for the duplex VFD tube with 128 segments (2 Grid ¥ 64 Anode) VDD Microcontroller VDD GND R C GND VDISP MSM9210 (SLAVE) SEG1 SEG1 M/S SEG32 GRID1 M/S SEG32 GRID1 DUP/TRI GRID2 DUP/TRI GRID2 SYNC IN 2 SYNC IN 1 DIM IN CS DATA IN CLOCK OSC 1 OSC 0 L-GND GRID3 SYNC OUT 2 SYNC OUT 1 DIM OUT GND R D-GND C GND SYNC IN 2 SYNC IN 1 DIM IN CS DATA IN CLOCK OSC 1 OSC 0 L-GND GRID3 SYNC OUT 2 SYNC OUT 1 DIM OUT S1 S2 S3 S62 S63 S64 G1 G2 Triplex VF Tube G3 Ef D-GND MSM9210 16/19 GND VDD ¡ Semiconductor MSM9210 (MASTER) VDD VDISP VDISP 2. Circuit for the triplex VFD tube with 192 segments (3 Grid ¥ 64 Anode) VDD ¡ Semiconductor MSM9210 NOTES ON TURNING POWER ON/OFF • Connect L-GND and D-GND externally to be an equal potential voltage. • To avoid wrong operations, turn on the driver power supply after turning on the logic power supply. Conversely, turn off the logic power supply after tuning off the driver power supply. [Voltage] VDISP VDD [Time] 17/19 ¡ Semiconductor MSM9210 PACKAGE DIMENSIONS (Unit : mm) QFP56-P-910-0.65-2K Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.43 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 18/19 ¡ Semiconductor MSM9210 (Unit : mm) QFP64-P-1414-0.80-BK Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.87 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 19/19 E2Y0002-29-62 NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party’s right which may result from the use thereof. 6. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. No part of the contents contained herein may be reprinted or reproduced without our prior permission. 9. MS-DOS is a registered trademark of Microsoft Corporation. Copyright 1999 Oki Electric Industry Co., Ltd. Printed in Japan