E2B0018-27-Y2 ¡ Semiconductor MSC5301B-02 ¡ Semiconductor This version: Nov. 1997 MSC5301B-02 Previous version: Mar. 1996 LCD COMMON/SEGMENT DRIVER WITH RAM GENERAL DESCRIPTION The MSC5301B-02 is an LCD driver LSI with a built-in RAM. The device's bit mapping method offers greater flexibility in which each bit of the display RAM controls each section on the LCD panel. It can form a graphic display system of 64 x 8 dots in one chip. In addition, the display can be expanded by using the additional LSIs. FEATURES • LCD driving voltage range : 6 to 16V • Operating power supply voltage range : 5V ±10% • Display duty : 1/8 (1/4 bias) • Common output : 8 outputs • Segment output : 64 outputs • RAM capacity : 8 x 64 = 512 bits • Serial transfer clock frequency (fSCK) : 500 kHz Max. • Multichip configuration available • Blanking available • Built-in RC oscillation circuit • Package: 100-pin plastic QFP (QFP100-P-1420-0.65-BK) (Product name: MSC5310B-02GS-BK) 1/15 ¡ Semiconductor MSC5301B-02 BLOCK DIAGRAM V4 V1 C0 C7 VDSP S63 S0 V2 V3 VDSP 8-DOT COM DRV (4-LEVEL DRV) 64-DOT SEG DRV (4-LEVEL DRV) GND VCC GND 3-8 DECODER 64-BIT LATCH 3-BIT LATCH RAM RA2 64 x 8 = 512 bits WA1 RA1 RA0 READ (3-BIT) ADDRESS COUNTER WA2 WA0 WE TIMING GENERATOR 64-BIT LATCH INPUT CTL f 64-BIT SHIFT REGISTER LATCH CHIP CTL A/D SI BLK 6-BIT LATCH CTL SCK FRAM IN/OUT POR CS0 OSC 8-BIT SHIFT REGISTER CTL CS1 OS1 OS2 f BLK POR FRAM VCC GND 2/15 ¡ Semiconductor MSC5301B-02 S34 S40 S39 S38 S37 S36 S35 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 S52 S51 S50 S49 S48 S47 S46 S45 NC S44 S43 S42 S41 PIN CONFIGURATION (TOP VIEW) S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 VCC GND VDSP V2 V3 S0 S1 S2 V4 V1 CS0 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 S33 S32 S31 S30 S29 S28 S27 S26 S25 S24 S23 S22 S21 S20 S19 S18 S17 S16 S15 S14 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 C4 NC C5 NC C6 NC C7 80 79 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 CS1 LATCH A/D SI SCK POR BLK FRM OS1 OS2 f S53 S54 S55 S56 S57 S58 S59 S60 S61 S62 S63 NC C0 NC C1 NC C2 NC C3 NC NC: No connection 100-Pin Plastic QFP 3/15 ¡ Semiconductor MSC5301B-02 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Condition Rating Unit Power Supply Voltage VCC Ta = 25°C –0.3 to +6.5 V Power Supply Voltage VDSP Ta = 25°C –0.3 to +18.0 Input Voltage VIN Ta = 25°C –0.3V £ VIN £ VCC+0.3 Input Voltage VINDP Ta = 25°C –0.3 £ VINDP £ VDSP+0.3 V PD Ta = 85°C 275 mW TSTG — –55 to +125 °C Power Dissipation Storage Temperature *1 *1 V V VDSP>V1>V2≥V3>V4>GND RECOMMENDED OPERATING CONDITIONS Symbol Condition Range Unit Power Supply Voltage Parameter VCC GND = 0V 4.5 to 5.5 V Power Supply Voltage VDSP GND = 0V 6.0 to 16.0 Operating Temperature Top — –40 to +85 Shift Frequency *1 V °C fSCK — 25 to 500 kHz Oscillation Frequency ff — 1.92 to 8.0 kHz Frame Frequency fFR — 60 to 250 Hz *1 VDSP>V1>V2≥V3>V4>GND 4/15 ¡ Semiconductor MSC5301B-02 ELECTRICAL CHARACTERISTICS DC Characteristics (VCC = 5V, Ta = –40 to +85°C) Parameter Symbol Condition Min. Typ. Max. Unit "H" Input Voltage VIH *1 3.5 — VCC V "L" Input Voltage VIL *1 0 — 1.5 V Hysteresis Voltage 1 VHS1 *2 0.3 0.8 1.4 V Hysteresis Voltage 2 VHS2 Pull-up Resistance RPU *9 0.2 0.4 0.8 V VI = 0V *2 10 35 60 kW Pull-up Voltage "H" Input Current VPH IIN < 1mA *2 4.9 — — V IIH VCC = 5.5V, VIH = 5.5V *3 — — ±10 mA VCC = 5.5V, VIL = 0V *3 — — ±10 mA VOH IO = –0.4mA *4 4.6 — — V "L" Output Voltage VOL IO = 1.6mA — — 0.4 V Common Driver VDP VDSP = 10V I = –10mA VDSP–0.4 — — V V1 *5 "L" Input Current "H" Output Voltage Output Voltage IIL *4 I = ±10mA V1–0.4 — V1+0.4 V V4 I = ±10mA V4–0.4 — V4+0.4 V VSS I = +10mA — — 0.4 V Segment Driver VDP VDSP = 10V I = –10mA VDSP–0.4 — — V Output Voltage V2 *6 I = ±10mA V2–0.4 — V2+0.4 V V3 I = ±10mA V3–0.4 — V3+0.4 V VSS I = +10mA — — 0.4 V Supply Current 1 ICC VCC = 5.0V *7 — — 6.0 mA Supply Current 2 IDSP VCC = 5.0V *8 — — 0.5 mA *1 *2 *3 *4 *5 *6 *7 *8 *9 Applicable to all input pins Applicable to LATCH, A/D, SI, SCK, BLK and POR pins Applicable to CS0, CS1, OS1 and FRAM pins Applicable to FRAM and φ pins Applicable to C0 - C7 pins Applicable to S0 - S63 pins ff = 3.2 kHz, fSCK = 200 kHz, no load, display pattern = checkers VDSP = 16V, Current flows into VCC pin. ff = 3.2 kHz, fSCK = 200 kHz, no load, display pattern = checkers VDSP = 16V, Current flows into VDSP pin. Applicable to OS1 pin 5/15 ¡ Semiconductor MSC5301B-02 AC Characteristics (VCC = 5V, Ta = –40 to +85°C) Parameter Symbol Condition Min. Typ. Max. Unit SCK Clock Period t1 — 2 — — ms SI Data Setup Time t2 — 1 — — ms SI Data Hold Time t3 — 1 — — ms SCK-LATCH Time t4 — 1 — — ms LATCH Pulse Width t5 — 15 — — ms A/D Setup Time t6 — 1 — — ms A/D Hold Time t7 — 1 — — ms A/D-SCK Time t8 — 1 — — ms POR, BLK Fall Time t9 — — — 20 ms f, FRAM Rise Time t10 CL = 50 pF — — 0.3 ms f, FRAM Fall Time t11 CL = 50 pF — — 0.3 ms Frame Frequency fFR *1 85 100 115 Hz *1 The dispersion for external resistors and capacitors is not included. RS = 1kW, RT = 15kW, CT = 0.01mF, VCC = 4.5V to 5.5V t1 SCK t2 t3 SI t4 t5 t7 LATCH t6 t8 A/D 6/15 ¡ Semiconductor MSC5301B-02 VCC 90% POR, BLK 10% GND t9 VCC 90% f, FRAM 10% GND t11 t10 VDSP V1 C0 V4 GND 1/fFR Frame A 1/fFR Frame B 7/15 ¡ Semiconductor MSC5301B-02 FUNCTIONAL DESCRIPTION Pin Functional Description • OS1 (Pin 39), OS2 (Pin 40), f (Pin 41) These are pins for the RC oscillation circuit. Connect external resistors and a capacitor as shown below. When inputting the external clock pulse, input it to OS1 pin. OS2 and f pins should be left open. OS1 f OS2 CT RS RT The relation of frame frequency fFR and internal clock frequency ff is shown by the following equation. (RC oscillation frequency = internal clock frequency) ff = 4 x 8 x fFR In addition, the relation of frame frequency fFR and frame synchronizing signal frequency fFRAM is shown by the following equation. fFRAM = fFR/2 • CS0 (Pin 30), CS1 (Pin 31) Chip select input pins. Master and slave modes are determined by CS0 and CS1 as shown in the table below. A maximum of 4 devices can be connected in this manner. Use the master mode when using a single chip. CS0 CS1 Operation mode L L Master mode H : VCC level H L Slave mode L : GND level L H Slave mode H H Slave mode 8/15 ¡ Semiconductor MSC5301B-02 • FRAM (Pin 38) This is an input and output pin for the frame synchronizing signal to be used for master/slave configuration. It becomes an output pin in master mode and an input pin in slave mode. • SI (Pin 34) This is a serial data input pin of address data (8 bits) and segment data (64 bits). A pull-up resistor (10 kW - 60 kW) and the Schmitt circuit are contained. The serial data is shifted at the rising edge of SCK. • SCK (Pin 35) This is a shift clock input pin of address data (8 bits) and segment data (64 bits). The serial data is shifted at the rising edge of SCK pulse. A pull-up resistor (10 kW - 60 kW) and the Schmitt circuit are contained. • LATCH (Pin 32) This is a latch pulse input pin of address data (8 bits) and segment data (64 bits). The latch data comes through at "H" level of LATCH and the data just before "H" level is latched at "L" level. A pull-up resistor (10 kW - 60 kW) and the Schmitt circuit are contained. • A/D (Pin 33) This is a data select signal input pin of address data (8 bits) and segment data (64 bits). "H" level is set in the case of address 8-bit input and "L" level is set in the case of segment data 64-bit input. A pull-up resistor (10 kW - 60 kW) and the Schmitt circuit are contained. • VDSP (Pin 44), V1 (Pin 29), V2 (Pin 45), V3 (Pin 46), V4 (Pin 28), VCC (Pin 42), GND (Pin 43) These are power supply pins for this LSI and bias power supply pins for LCD driving. VCC, which is a power supply pin, is from 4.5V to 5.5V; GND, which is a ground pin, is 0V; VDSP, which is an LCD driving power supply pin, is usually used in the range between 6V and 16V. V1, V2, V3 and V4 are bias power supply pins for LCD driving and are usually used by supplying bias voltage from an external source. 9/15 ¡ Semiconductor MSC5301B-02 • BLK (Pin 37) This is an input pin to control the LCD panel display. When a "H" level is input (or when this pin is open), the segment output pins S0 - S63 come to the levels V2 - V3 and the LCD panel is turned off. In addition, during this period, the data read from a display RAM is stopped but writing into the display RAM of address and segment data inputted from the SI pin is available. When this pin is changed from "H" level to "L", the frame synchronizing signal FRAM is output within the 2 cycles of an internal clock ff, and it is synchronized at multi-chip. Then, the display RAM address is set to "000". After 1/8 frame cycle from FRAM signal generation, the output is applied from the "001" data of the display RAM address to the segment driver. Because the display RAM contents are undefined at the time the power is turned on, keep this pin to "H" level (or leave open) until writing data to the RAM is completed. A pull-up resistor (10kW 60kW) and the Schmitt circuit are contained. • POR (Pin 36) This is a power-on-reset input pin. When a "H" level is input (or when this pin is open), the common and segment outputs come to the static light-out state in no relation to the BLK pin and the segment output pins S0 - S63 become V3 level and the common output pins C0 - C8 become V4 level. When this pin is changed from "H" level to "L", the frame synchronizing signal FRAM is output within the 2 cycles of an interval clock ff, and it is synchronized when multiple devices are connected and is moreover dynamic-operated from the frame B . Then, the display RAM address is set to "000". After 1/8 frame cycle from FRAM signal generation, the "001" data of the display RAM address is output to the segment driver. However, because the BLK pin is usually at "H" level when the power-on-reset is released, reading data from the display RAM is stopped and light-out segment data is forcibly transferred to the segment output. A pull-up resistor (10kW - 60kW) and the Schmitt circuit are contained. • C0 (Pin 13) - C7 (Pin 27) These are 8-output pins of the common driver which are used for LCD panel driving. The outputs of 4 levels are obtained (VDSP and GND are select levels, and V1 and V4 are nonselect levels). • S0 (Pin 47) - S63 (Pin 11) These are 64-output pins of segment driver which are used for LCD panel driving. The outputs of 4 levels are obtained (VDSP and GND are select levels, which correspond to "1" of the display RAM data, and V2 and V3 are nonselect levels, which correspond to "0" of the display RAM data). NOTES ON USE Note the following when turning power on and off: The LCD drivers of this IC require a high voltage. For this reason, if a high voltage is applied to the LCD drivers with the logic power supply floating, excess current flows. This may damage the IC. Be sure to carry out the following power-on and power-off sequences: When turning power on: First VCC ON, next VDSP, V4, V3, V2, V1 ON. Or both ON at the same time. When turning power off: First VDSP, V4, V3, V2, V1 OFF, next VCC OFF. Or both OFF at the same time. 10/15 ¡ Semiconductor MSC5301B-02 Relation Between LCD Screen Size and Display RAM This LCD driver has a built-in RAM for the display of 8 ¥ 64 = 512 bits and the address corresponds to the duty of the LCD. The data corresponds to the number of dots in the X direction. The relation between the LCD screen size and the display RAM is shown below. Address S63 S0 0 0 0 C0 0 0 1 C1 0 1 0 C2 0 1 1 C3 1 0 0 C4 1 0 1 C5 1 1 0 C6 1 1 1 C7 1/8 duty A2 A1 A0 Data Number of dots in X direction (64) Relation Between Frame Cycle and Display RAM Data The output of the display RAM data corresponds to the segment output. The relation between the frame cycle and the display RAM data is as follows: First line address Segment output (Contents of RAM) 000 001 010 011 110 111 000 001 1 frame cycle 11/15 ¡ Semiconductor MSC5301B-02 Multiple Configuration This LCD driver can form multiple configuration. It is possible to form a maximum of 4 devices (a panel of up to 256 ¥ 8 dots in size can be formed) by using chip select signals CS0 and CS1. The devices in multiple configuration must be synchronized with one another. In this configuration, one device in the master mode, where the original oscillation signal f and the synchronous signal FRAM are output, and the other devices in the slave mode, where the original oscillation signal f and the synchronous signal FRAM are input, are used in combination. Refer to items CS0 and CS1 of the pin description on the mode setting method. The original oscillation signal output pin f of the master mode devices is connected to the OS1 pin of the slave mode device and the synchronizing signal pin FRAM is also connected to the FRAM pin of the slave mode device. Connect SI, SCK, LATCH, A/D, POR and BLK of the master mode devices to SI, SCK, LATCH, A/D, POR and BLK of each of the slave mode devices and connect them to CPU for control. In addition, connect the devices so that VDSP, V1, V2, V3, V4 and GND are shared between the devices, and connect them to each voltage level divided by resistors. Address Data Configuration (MSB) (LSB) 7 6 Dummy data 2 DM2 DM1 2 bits 5 4 Upper address CS1 CS0 2 bits 3 A2 2 1 Lower address A1 3 bits A0 0 Dummy data 1 DM0 1 bit The lower address, which is the address of the display RAM, corresponds to the common sides C0 - C7 of LCD panel. Dummy data 1 must be always set to "H". The upper address corresponds to the logical state of chip select pins CS0 and CS1 and lower address is set to the chip only with which corresponded. For the chip to output the common signal (f, FRAM), set both of the upper address 2 bits to "L". The 2 bits of dummy data can be set to either "L" or "H". 12/15 ¡ Semiconductor MSC5301B-02 Serial Signal to be Input From CPU The following signals are input from an external CPU to this LCD driver: - Serial transfer clock Æ SCK - Serial transfer data Æ SI - Serial transfer latch Æ LATCH - Serial data select Æ A/D The operations are shown in the following table. Mode A/D SCK LATCH Address data input mode H Shifts at the rising edge 8-bit address data is latched at falling edge (level type) 8-bit address data Serial input from LSB side L Shifts at the rising edge 64-bit segment data is latched at falling edge (level type) 64-bit segment data The first segment data shifted into the shift register corresponds to S63. "1" : Light-on data, "0" : Light-out data Segment data input mode SI Timing for Serial Signal Transferred From CPU A/D "H" at address data setting 1 2 3 4 5 6 "L" at segment data setting 7 8 1 2 3 63 64 SCK Dummy A0 A1 A2 CS0 CS1 Dummy Dummy SI LSB S63 S62 S61 S1 S0 MSB (Always "H") Address data (8 bits) Segment data (64 bits) LATCH Address latch signal RAM write signal Notes: 1. Be sure to set the address before writing the segment data to RAM. Then, write the segment data to RAM. 2. While the POR pin is "H" (upon power-on reset), neither address data nor segment data can be entered. 13/15 RAM address Segment signal output Common signal output FRAM f (External R and C) BLK POR VCC Frame A 0-7 Dynamic light-out state Frame B 0-7 Frame A 0-0 Frame B 1-7 Frame B Frame B 0-7 0-7 Dynamic operation (normal operation) Frame A 0-7 Frame A ¡ Semiconductor MSC5301B-02 Operation upon Power ON (When Single Device Used) 14/15 ¡ Semiconductor MSC5301B-02 PACKAGE DIMENSIONS (Unit : mm) QFP100-P-1420-0.65-BK Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 1.29 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 15/15