DATA SHEET MOS INTEGRATED CIRCUIT µPD16675A 1/34, 1/36 DUTY LCD CONTROLLER/DRIVER The µPD16675A is a driver containing a RAM capable of full-dot LCD display. A single µPD16675A IC chip can operate a full-dot (up to 128-by-32 dots) LCD and two-line (upper & lower) pictograph display. This IC is ideal for Kanji character or Chinese character pagers, displaying 16-by-16 dots per character. FEATURES • LCD driver with built-in display RAM • Can operate on a single 3-V power supply • Booster circuit incorporated: Switchable between 2X & 3X • Dot display RAM: 128 × 32 bits • Pictographic display RAM (portion of two lines): 128 × 2 bits • Pictographic display RAM duty changeable: 1/34 and 2/36 duties • Output: 128 segments & 34 commons • Data input based on serial & 4-/8-bit parallel switchover • Split resistor incorporated • Oscillation circuit incorporated ORDERING INFORMATION Part Number Package µPD16675AP/W Chips/wafer (Matched COG mounting) µPD16675AN-051 2-side standard TCP (Output OLB: 0.25 mm pitch) µPD16675AN-xxx TCP (TAB) Purchasing the above products in terms of chips per wafer requires an exchange of other documents as well, including a memorandum on the product quality. Therefore, those who are interested in this regard are advised to contact an NEC sales representative for further details. The information in this document is subject to change without notice. Document No. S11195EJ1V0DS00 (1st edition) Date Published July 1998 NS CP (K) Printed in Japan © 1996 VLC5 VLC4 VLC3 VLC2 VLC1 AmpIN( ) AmpIN( ) COM32 PCOM1,PCOM2 SEG1 Common Driver OSCBRI POCOUT SYNC CLKOUT 34 Bits Register LCD Voltage Controller WS CS0 CS1 CS2 OSCIN Segment Driver 128 Bits Latch 128 Pict Data Memory (128 1 Bits) Blink Data Memory (128 DC / DC Converter LCD Timing Controller 8 Data Memory Bank 1 (128 8 Bits) 8 Data Memory Bank 2 (128 8 Bits) 8 Data Memory Bank 3 (128 8 Bits) 8 8 1 Bits) 1 Bits) 8 Read/Write Buffer 8 8 8 Address Controller Mode Reg. Command Decoder 8 8 Bits) Blink Data Memory (128 Display Mode Reg. 1 Bits) 8 Data Memory Bank 0 (128 Pict Data Memory (128 Blink Controller CPU Interface D7 / NS D6 / CAE D5 D4 D3 D2 D1 D0 / DATA SEG128 128 34 VLCD C1 C1 C2 C2 BLOCK DIAGRAM 2 COM1 DACHA VCHA VEXT Memory Data Pointer A0-A7 Clock 8 8 Clock Buffer OSCOUT STB Command / Data Controller µPD16675A E / SCK Read / Write Controller µPD16675A PIN CONFIGURATION (PAD LAYOUT) (Chip size: 12.68 × 1.81 mm ) 2 245 1 159 158 Y X 13 14 No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 PIN DUMMY DUMMY COM22 COM21 COM20 COM19 COM18 COM17 DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY SEG128 SEG127 SEG126 SEG125 SEG124 SEG123 SEG122 SEG121 SEG120 SEG119 SEG118 SEG117 SEG116 SEG115 SEG114 SEG113 SEG112 SEG111 SEG110 SEG109 SEG108 SEG107 SEG106 SEG105 SEG104 SEG103 SEG102 SEG101 SEG100 SEG99 SEG98 SEG97 SEG96 SEG95 SEG94 SEG93 SEG92 SEG91 SEG90 SEG89 SEG88 SEG87 SEG86 SEG85 SEG84 SEG83 SEG82 SEG81 X (µm) -6094.8 -6094.8 -6094.8 -6094.8 -6094.8 -6094.8 -6094.8 -6094.8 -6094.8 -6094.8 -6094.8 -6094.8 -6094.8 -5893.8 -5803.8 -5713.8 -5623.8 -5533.8 -5443.8 -5353.8 -5263.8 -5173.8 -5083.8 -4993.8 -4903.8 -4813.8 -4723.8 -4633.8 -4543.8 -4453.8 -4363.8 -4273.8 -4183.8 -4093.8 -4003.8 -3913.8 -3823.8 -3733.8 -3643.8 -3553.8 -3463.8 -3373.8 -3283.8 -3193.8 -3103.8 -3013.8 -2923.8 -2833.8 -2743.8 -2653.8 -2563.8 -2473.8 -2383.8 -2293.8 -2203.8 -2113.8 -2023.8 -1933.8 -1843.8 -1753.8 -1663.8 -1573.8 -1483.8 Y (µm) 516.6 426.6 336.6 246.6 156.6 66.6 -23.4 -113.4 -203.4 -293.4 -383.4 -473.4 -563.4 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 146 145 No. 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 PIN SEG80 SEG79 SEG78 SEG77 SEG76 SEG75 SEG74 SEG73 SEG72 SEG71 SEG70 SEG69 SEG68 SEG67 SEG66 SEG65 SEG64 SEG63 SEG62 SEG61 SEG60 SEG59 SEG58 SEG57 SEG56 SEG55 SEG54 SEG53 SEG52 SEG51 SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 X (µm) -1393.8 -1303.8 -1213.8 -1123.8 -1033.8 -943.8 -853.8 -763.8 -673.8 -583.8 -493.8 -403.8 -313.8 -223.8 -133.8 -43.8 46.2 136.2 226.2 316.2 406.2 496.2 586.2 676.2 766.2 856.2 946.2 1036.2 1126.2 1216.2 1306.2 1396.2 1486.2 1576.2 1666.2 1756.2 1846.2 1936.2 2026.2 2116.2 2206.2 2296.2 2386.2 2476.2 2566.2 2656.2 2746.2 2836.2 2926.2 3016.2 3106.2 3196.2 3286.2 3376.2 3466.2 3556.2 3646.2 3736.2 3826.2 3916.2 4006.2 4096.2 4186.2 Y (µm) -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 No. 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 PIN SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY PCOM1 COM1 COM2 COM3 COM4 COM5 DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 DUMMY VLC5 VLC4 VLC3 VLC2 VLC1 VLCD VLCD AmpIN(−) AmpIN(+) AmpOUT C1− C1− C1− C1+ C1+ X (µm) 4276.2 4366.2 4456.2 4546.2 4636.2 4726.2 4816.2 4906.2 4996.2 5086.2 5176.2 5266.2 5356.2 5446.2 5536.2 5626.2 5716.2 5806.2 5896.2 6094.8 6094.8 6094.8 6094.8 6094.8 6094.8 6094.8 6094.8 6094.8 6094.8 6094.8 6094.8 6094.8 5870.6 5780.6 5690.6 5600.6 5510.6 5420.6 5330.6 5240.6 5150.6 5060.6 4970.6 4880.6 4790.6 4700.6 4610.6 4520.6 4400.8 4224.8 4048.8 3872.8 3696.8 3520.8 3344.8 3168.8 2992.8 2816.8 2640.8 2550.8 2460.8 2284.8 2194.8 Y (µm) -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -661.6 -563.4 -473.4 -383.4 -293.4 -203.4 -113.4 -23.4 66.6 156.6 246.6 336.6 426.6 516.6 760 760 760 760 760 760 760 760 760 760 760 760 760 760 760 760 760 760 760 760 760 760 760 760 760 760 760 760 760 760 760 No. 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 PIN C1+ C2− C2− C2− C2+ C2+ C2+ VDD2 VEXT OSCBRI OSCIN OSCOUT DACHA VDD1 VDD1 VCHA VSS CS0 CS1 CS2 RESET D7/NS D6/CAE D5 D4 D3 D2 D1 D0/DATA E/SCK STB VSS VSS WS VDD1 POCOUT CLKOUT SYNC VEE VEE DUMMY PCOM2 COM32 COM31 COM30 COM29 COM28 COM27 COM26 COM25 COM24 COM23 DUMMY DUMMY DUMMY DUMMY X (µm) 2104.8 1928.8 1838.8 1748.8 1572.8 1482.8 1392.8 1232.8 1056.8 880.8 704.8 528.8 352.8 176.8 0.8 -175.2 -351.2 -527.2 -703.2 -879.2 -1055.2 -1231.2 -1407.2 -1583.2 -1759.2 -1935.2 -2111.2 -2287.2 -2463.2 -2639.2 -2815.2 -2991.2 -3167.2 -3343.2 -3519.2 -3695.2 -3871.2 -4047.2 -4223.2 -4399.2 -4520.6 -4610.6 -4700.6 -4790.6 -4880.6 -4970.6 -5060.6 -5150.6 -5240.6 -5330.6 -5420.6 -5510.6 -5600.6 -5690.6 -5780.6 -5870.6 Y (µm) 760 760 760 760 760 760 760 760 760 760 760 760 760 760 760 760 760 760 760 760 760 760 760 760 760 760 760 760 760 760 760 760 760 760 760 760 760 760 760 760 760 760 760 760 760 760 760 760 760 760 760 760 760 760 760 760 3 µPD16675A CONTENTS 1. PIN FUNCTIONS .................................................................................................................................... 6 1.1 Power System............................................................................................................................................... 6 1.2 Logic System................................................................................................................................................ 6 1.3 Driver System ............................................................................................................................................... 8 2. VOLTAGE CONTROL CIRCUIT ............................................................................................................ 8 3. LCD DISPLAY ........................................................................................................................................ 9 4. GROUP ADDRESSES.......................................................................................................................... 10 4.1 Dot Display ................................................................................................................................................. 10 4.2 Pictographic Display.................................................................................................................................. 11 4.3 Blink Data.................................................................................................................................................... 12 5. COMMAND ........................................................................................................................................... 13 5.1 Basic Form.................................................................................................................................................. 13 5.2 Chip Address Register (CAR) ................................................................................................................... 13 5.3 Command Register .................................................................................................................................... 14 5.4 5.3.1 Reset ............................................................................................................................................... 14 5.3.2 Display ON/OFF .............................................................................................................................. 14 5.3.3 Standby ........................................................................................................................................... 14 5.3.4 Duty setting...................................................................................................................................... 15 5.3.5 Master/slave setting......................................................................................................................... 15 5.3.6 Blink setting ..................................................................................................................................... 15 5.3.7 Data R/W mode ............................................................................................................................... 16 5.3.8 Test mode........................................................................................................................................ 16 5.3.9 D/A converter setting ....................................................................................................................... 16 Address Register ....................................................................................................................................... 17 6. RESETTING.......................................................................................................................................... 18 7. COMMUNICATION FORMAT .............................................................................................................. 19 7.1 7.2 Serial ........................................................................................................................................................... 19 7.1.1 Reception 1 (Command/data write: 1 byte) ..................................................................................... 19 7.1.2 Reception 2 (Command/data write: 2 bytes or more) ...................................................................... 19 7.1.3 Transmission (Command/data read) ............................................................................................... 19 Parallel ........................................................................................................................................................ 20 7.2.1 8-bit parallel interface ...................................................................................................................... 20 7.2.2 4-bit parallel interface ...................................................................................................................... 20 8. CPU ACCESS EXAMPLES .................................................................................................................. 21 8.1 Initialize and Data Write............................................................................................................................. 21 8.2 Change Display Data and Pictographic Data (All Data are Changed) ................................................... 23 8.3 Read Display Data and Pictograph Data .................................................................................................. 24 8.4 Blink Data Setting ...................................................................................................................................... 25 9. ELECTRICAL CHARACTERISTICS .................................................................................................... 26 4 µPD16675A 10. PACKAGE DRAWING ..........................................................................................................................32 5 µPD16675A 1. PIN FUNCTIONS 1.1 Power System Pin Symbol Pin No. VDD1 Logic power supply pin 203, 224 VDD2 Power supply pin for booster circuit 197 VSS Logic ground pin 206, 222 VLCD Driver power supply pin VLC1 to VLC5 204, I/O Description --- Power supply pin for logic --- Power supply pin for booster circuit. Set the pin to VDD1 ≤ VDD2. --- Ground pin for logic 180, 181 --- Driver power supply pin. Output pin of internal booster circuit. Connect with a 1-µF booster capacitor to the VDD2 pin. When not using the internal booster circuit, the driver power can be turned on directly. Driver reference power supply 179 to 175 --- Reference power supply pin for LCD drive. When the internal bias is selected, be sure to leave it open. C1+, C1−, C2+, C2− Capacitor connection pins 185 to 196 --- Capacitor connection pins for booster circuit. Connect a 1 µF capacitor. VEE Driver ground pin 228, 229 --- Ground pin for driver 1.2 221, Logic System Pin Symbol 6 Pin Name Pin Name Pin No. I/O Description WS Word length selection 223 I This pin selects the word length. At High level, it becomes an 8-bit parallel interface. At Low level, it becomes a 4-bit parallel interface if D7/NS is High; and a serial interface if D7/NS is Low. When the word length is 4 bits, data is transferred in the upperto-lower sequence by means of data buses D0 to D3. The word length cannot be changed after power-on. STB Strobe 220 I Data can be input/output at Low level either in parallel interface or serial interface mode. E/SCK Enable/shift clock 219 I In parallel interface mode, this becomes the data enable input pin. During read-in, data is fetched into the interface buffer at the rising edge. During readout, data is fetched from the interface buffer at the falling edge. In serial interface mode, this pin becomes the data shift clock. During read-in, data is fetched into the shift register at the rising edge. During read-out, data is fetched from the shift register at the falling edge. CLKOUT Clock for slave IC output 226 O This pin outputs an inverted oscillation clock. It connects to slave IC’s OSCIN directly. POCOUT Power-on reset monitor 225 O Monitor pin for internal power-on reset. At Low level, power-on reset is set internally. At Low level, power-on reset is released. The pin is for IC testing. Normally leave it open. µPD16675A 1.2 Logic System (Continued) Pin Symbol Pin Name Pin No. I/O Description D0/DATA Data bus/data 218 I/O In parallel interface mode, this pin becomes the D0 bit of the data bus. In serial interface mode, it becomes the input/output pin of the command and display data (3 states). D1 to D5 Data bus 217 to 213 I/O In parallel interface mode, these pins become the D1 to D5 bits of the data bus. In serial interface mode, leave them open. D6/CAE Data bus/chip address enable 212 I/O In 8-bit parallel interface mode, this pin becomes the D6 bit of the data bus. In 4-bit parallel interface and serial interface modes, it becomes chip address enable. Also, at High level, it becomes chip address valid; at Low level, chip address invalid. In 8-bit parallel interface, it becomes chip address valid. D7/NS Data bus/nibble select 211 I/O When the word select (WS) is High level, this bit becomes the D7 bit of the data bus. When WS is Low level, it becomes the nibble select (NS). When NS is High level, it becomes 4-bit parallel interface. When NS is Low level, it becomes serial interface. In 4-bit parallel interface mode, data cannot be read out. RESET Reset 210 I At Low level, internal initialization is performed. VCHA Boosting magnitude switching 205 I The boosting magnitude of the internal booster circuit is switched over. At High level, it is switched to 3X, while, at Low level, 2X. DACHA D/A converter switching 202 I Select whether to use the internal D/A converter for temperature correction or not. At High level, this circuit is used, at Low level, unused. VEXT Reference supply switching 198 I Selects the method for supplying the reference power circuit. At High level, the circuit is supplied externally; and, at Low level, internally. SYNC Synchronization 227 I/O Input/output pin for synchronization. Master mode: Output Slave mode: Input CS0 to CS2 Chip select 207 to 209 I When used for multiple chips, these pins are used to specify their addresses. They can be accessed only when coinciding with b2 to b4 bits of the interface control register. OSCIN Oscillation pin 200 I 201 O These pins are connected with the 1 MΩ resistor. When using external oscillation, input it into the OSCIN, leaving the OSCOUT open. 199 I _____________ OSCOUT OSCBRI External clock for blinks Input pin of the 2-Hz external clock. It internally divides this clock by 2 to generate 1 Hz and make it the synchronizing signal for blinks. 7 µPD16675A 1.3 Driver System Pin Symbol 2. Pin Name Pin No. I/O Description SEG1 to SEG128 Segment 143 to 16 O Segment output pins COM1 to COM32 Commons 3 to 8, 152 to 156, 163 to 173, 232 to 241 O Common output pins PCOM1, PCOM2 Pictographic commons 151, 231 O Common output pins for pictograph AmpIN(+), AmpIN(−) Operational amplifier input 183, 182 I These are the input pins of the operational amplifier for LCD drive voltage adjustment. Leave AmpIN(+) open when using the internal D/A converter. When not using the D/A converter, it is necessary to input the reference voltage. Connect AmpIN(–) to the LCD voltage adjustment resistor (see the diagram below). AmpOUT Operational amplifier output 184 O This is the input pin of the operational amplifier for LCD drive voltage adjustment. It is normal to connect this pin to the LCD voltage adjustment resistor (see the diagram below). It is recommended to connect approx. 0.1 to 1 µF capacitor to this pin to stabilize the internal amplifier’s output. VOLTAGE CONTROL CIRCUIT EXAMPLE DACHA D/A Converter VEXT Reference Power Circuit AmpIN( ) AmpIN( ) AmpOUT VLC1 R2 R1 8 C1 VLC2 VLC3 VLC4 VLC5 VEE µPD16675A 3. LCD DISPLAY The µPD16675A’s LCD can display 128 by 32 dots (called full-dot display) as well as 128 by 2 pictographs on a single screen. SEG 1 3 2 PCOM1 5 4 7 6 9 8 10 123 125 127 124 126 128 Pictographic display (128 pictographs) COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 PCOM2 Pictographic display (128 pictographs) 9 µPD16675A 4. GROUP ADDRESSES 4.1 Dot Display The group addresses of dot display are assigned as follows. If address increment is set, when the X address goes to 7FH, the next address is 00H. At this time, the Y address changes to the next address. Also, when the Y address goes to 03H, the next address is 00H. X addresses 00H 01H 02H 03H Y addresses 00H 01H 02H 03H 10 7EH 7FH b7 b6 b5 b4 b3 b2 b1 b0 µPD16675A 4.2 Pictographic Display The group addresses of pictograph display are assigned as follows. If address increment is set, when the X address goes to 0FH, the next address is 00H. At this time, the Y address changes to the next address. Also, when the Y address goes to 01H, the next address is 00H. X addresses 00H 01H 02H 03H Y addresses 00H (PCOM1) 0EH 0FH 01H (PCOM2) b7 b6 b5 b4 b3 b2 b1 b0 8 bits (1) PCOM1 (Y Address = 00H) X address b7 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 1 9 17 25 33 41 49 57 65 73 81 89 97 105 113 121 b6 2 10 18 26 34 42 50 58 66 74 82 90 98 106 114 122 b5 3 11 19 27 35 43 51 59 67 75 83 91 99 107 115 123 Segment output No. b4 b3 4 5 12 13 20 21 28 29 36 37 44 45 52 53 60 61 68 69 76 77 84 85 92 93 100 101 108 109 116 117 124 125 b2 6 14 22 30 38 46 54 62 70 78 86 94 102 110 118 126 b1 7 15 23 31 39 47 55 63 71 79 87 95 103 111 119 127 b0 8 16 24 32 40 48 56 64 72 80 88 96 104 112 120 128 Segment output No. b4 b3 4 5 12 13 20 21 28 29 36 37 44 45 52 53 60 61 68 69 76 77 84 85 92 93 100 101 108 109 116 117 124 125 b2 6 14 22 30 38 46 54 62 70 78 86 94 102 110 118 126 b1 7 15 23 31 39 47 55 63 71 79 87 95 103 111 119 127 b0 8 16 24 32 40 48 56 64 72 80 88 96 104 112 120 128 (2) PCOM2 (Y Address = 01H) X address b7 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 1 9 17 25 33 41 49 57 65 73 81 89 97 105 113 121 b6 2 10 18 26 34 42 50 58 66 74 82 90 98 106 114 122 b5 3 11 19 27 35 43 51 59 67 75 83 91 99 107 115 123 11 µPD16675A 4.3 Blink Data The group addresses of pictographic blink data are assigned as follows. Write “1” in the address of the pictographic to be blinked. If address increment is set, when the X address goes to 0FH, the next address is 00H. At this time, the Y address changes to the next address. Also, when the Y address goes to 01H, the next address is 00H. X addresses 00H 01H 02H 03H Y addresses 00H (PCOM1) 0EH 0FH 01H (PCOM2) b7 b6 b5 b4 b3 b2 b1 b0 8 bits (1) PCOM1 (Y Address = 00H) X address b7 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 1 9 17 25 33 41 49 57 65 73 81 89 97 105 113 121 b6 2 10 18 26 34 42 50 58 66 74 82 90 98 106 114 122 b5 3 11 19 27 35 43 51 59 67 75 83 91 99 107 115 123 Segment output No. b4 b3 4 5 12 13 20 21 28 29 36 37 44 45 52 53 60 61 68 69 76 77 84 85 92 93 100 101 108 109 116 117 124 125 b2 6 14 22 30 38 46 54 62 70 78 86 94 102 110 118 126 b1 7 15 23 31 39 47 55 63 71 79 87 95 103 111 119 127 b0 8 16 24 32 40 48 56 64 72 80 88 96 104 112 120 128 Segment output No. b4 b3 4 5 12 13 20 21 28 29 36 37 44 45 52 53 60 61 68 69 76 77 84 85 92 93 100 101 108 109 116 117 124 125 b2 6 14 22 30 38 46 54 62 70 78 86 94 102 110 118 126 b1 7 15 23 31 39 47 55 63 71 79 87 95 103 111 119 127 b0 8 16 24 32 40 48 56 64 72 80 88 96 104 112 120 128 (2) PCOM2 (Y Address = 01H) X address b7 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 12 1 9 17 25 33 41 49 57 65 73 81 89 97 105 113 121 b6 2 10 18 26 34 42 50 58 66 74 82 90 98 106 114 122 b5 3 11 19 27 35 43 51 59 67 75 83 91 99 107 115 123 µPD16675A 5. COMMAND 5.1 Basic Form Chip address register (CAR) 5.2 + Command register (CR) + Address register (AR) + X address (XAD) + Data 1 (DT1) + Data 2 (DT2) + • • Chip Address Register (CAR) MSB 0 LSB 0 0 0 0 b2 b1 b0 Chip address 000: CS2 = 0, CS1 = 0, and CSo = 0 ICs accessible 001: CS2 = 0, CS1 = 0, and CSo = 1 ICs accessible 010: CS2 = 0, CS1 = 1, and CSo = 0 ICs accessible 011: CS2 = 0, CS1 = 1, and CSo = 1 ICs accessible 100: CS2 = 1, CS1 = 0, and CSo = 0 ICs accessible 101: CS2 = 1, CS1 = 0, and CSo = 1 ICs accessible 110: CS2 = 1, CS1 = 1, and CSo = 0 ICs accessible 111: CS2 = 1, CS1 = 1, and CSo = 1 ICs accessible The register is made valid in the following states. Interface CAE High level Low level Serial Valid Invalid 4-bit parallel Valid Invalid 8-bit parallel Valid (CAE: Used as the D6 bit) It is unnecessary to transmit the register that is invalid. 13 µPD16675A 5.3 Command Register The command register’s basic configuration is as follows. MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 Choices Command type (0×H to B×H) 5.3.1 Reset All the IC’s commands are initialized. Resetting takes effect only during the internally predetermined time (one shot). MSB 0 LSB 0 5.3.2 1 0 0 1 1 1 Display ON/OFF ON/OFF of the display is controlled. MSB 0 LSB 0 0 0 1 b2 b1 b0 Choices 000: LCD OFF (SEGn, COMn, PCOMn = VEE) 001: LCD OFF (SEGn, COMn, PCOMn = nonselective waveform) 111: LCD ON 5.3.3 Standby The DC/DC converter is stopped, thus reducing the supply current. The display is placed in the OFF state (SEGn, COMn = VEE). MSB 0 LSB 0 0 1 0 b2 b1 b0 Choices 000: Normal operation 001: Standby (DC/DC converter halt, all display OFFNote ) Note SEGn, COMn, PCOMn = VEE 14 µPD16675A 5.3.4 Duty setting The duty is set. MSB 0 LSB 0 0 1 1 b2 b1 b0 Choices 000: 1/34 duty cycle 001: 1/36 duty cycleNote Note If the duty cycle is 1/36, PCOM1 and PCOM2 are respectively selected for twice the period of the duty (2/36). 5.3.5 Master/slave setting The master/slaves are set. MSB 0 LSB 0 1 1 1 b2 b1 b0 Choices 000: Master 001: Slave 5.3.6 Blink setting The blinks of the pictograph of the address whose blink data is “1” are controlled. MSB 0 LSB 1 0 0 0 b2 b1 b0 Choices 000: Blink halt 001: Blink start (Blink frequency = fOSC/32768) 010: Blink start (Blink frequency = fBRINote/2) Note This refers to the frequency of the external clock which is input from the OSCBRI pin. 15 µPD16675A 5.3.7 Data R/W mode Data Read/Write (R/W), increment, address counter resetting, etc. are set in this mode. MSB 1 LSB 0 1 1 0 b2 b1 b0 Choices 1 00: The address is incremented (+1) after being reset (X address = 00H, Y address = 00H).Note 1 01: The address is incremented starting from the current one.Note 2 10: The address is not incremented after being reset. 11: Current address retained. Choices 2 0: Data writing 1: Data readingNote 3 Notes 1. When the X address goes to the last address, the next address is 00H. 2. The data Read mode is cancelled at STB’s rising edge (switched to data Write mode). 3. In 4-bit parallel interface mode, data cannot be read out. 5.3.8 Test mode The test mode is set. The test mode is for checking IC operation, and no assurance is made for its regular use or continued operation. MSB 1 LSB 0 1 1 1 b2 b1 b0 Choices 000: Normal operation 001 to 111: Test mode 5.3.9 D/A converter setting D/A converter output is set in 32 steps from VDD2 to 2/3 VDD2. MSB 1 LSB 0 0 b4 b3 b2 b1 b0 Choices 00H (MIN.) to 1FH (MAX.) 10H is set after reset. 16 µPD16675A 5.4 Address Register Selects the address type and specifies the address. MSB 1 MSB LSB 1 b5 b4 0 0 b1 b0 + LSB 0 b6 b5 b4 b3 b2 b1 b0 X address Dot display group addresses: 00H to 03H Y address Pictograph group addresses : 00H to 01H Blink group addresses : 00H to 01H Choices 00: Dot address 01: Pictograph group address 10: Blink data group address Caution If unspecified addresses have been set, the operation is not assured. 17 µPD16675A 6. RESETTING When reset (power-ON reset, command reset, hardware (terminal) reset), the contents of each register are as follows: Register name Register contents Status b7 b6 b5 b4 b3 b2 b1 b0 Chip address register 0 0 0 0 0 0 0 0 The ICs of CS2 = 0, CS1 = 0, CS0 = 0 can be accessed. Display ON/OFF 0 0 0 0 1 0 0 0 LCD OFF (SEGn, COMn, PCOMn = VLC5) Standby 0 0 0 1 0 0 0 0 Normal operation Duty setting 0 0 0 1 1 0 0 0 1/34 duty cycle Blink setting 0 1 0 0 0 0 0 0 Blink halt D/A converter setting 1 0 0 0 0 0 0 0 LCD drive voltage: Set to 2/3 VDD2 Data R/W mode 1 0 1 1 0 0 0 0 Data write/address reset/increment (+1) Test mode 1 0 1 1 1 0 0 0 Normal operation 18 µPD16675A 7. COMMUNICATION FORMAT 7.1 Serial 7.1.1 Reception 1 (Command/data write: 1 byte) STB DATA SCK 7.1.2 b7 b6 1 2 b2 b5 3 6 b1 b0 7 8 Reception 2 (Command/data write: 2 bytes or more) STR b7 DATA SCK 1 b6 2 b5 b2 6 3 b1 7 b0 8 1 Command 1 7.1.3 b7 b6 2 b5 3 b4 4 b3 5 Command 1/data Wait time tWAIT Transmission (Command/data read) STR b7 DATA SCK 1 b6 2 b5 3 b2 6 b1 7 Data read command setting b0 8 1 Wait time tWAIT b7 b6 b5 b4 b3 2 3 4 5 6 Data read 19 µPD16675A 7.2 7.2.1 Parallel 8-bit parallel interface STB D0 to D7 E 7.2.2 4-bit parallel interface STB D0 to D7 E 20 Higher Lower Higher Lower Higher Lower µPD16675A 8. CPU ACCESS EXAMPLES Examples of access procedure are shown below. In serial or 4-bit parallel interface mode, the Chip Address Register (CAR) is not transmitted when the CAR is invalid (CAE = L, see page 13). 8.1 Initialize and Data Write Parameter STB Command/data Description b7 b6 b5 b4 b3 b2 b1 b0 Start H X X X X X X X X (Power-on reset is released 200 µs after power supply is started) Chip Address Register (CAR) L 0 0 0 0 0 0 0 0 Chip address = 000 Duty setting L 0 0 0 1 1 0 0 0 1/34 duty H X X X X X X X X CAR L 0 0 0 0 0 0 0 0 Chip address = 000 D/A converter setting L 1 0 0 1 0 0 0 0 D/A converter output = 10000H H X X X X X X X X CAR L 0 0 0 0 0 0 0 0 Chip address = 000 Address register 1 L 1 1 0 0 0 0 0 0 Dot address, Y address = 00H Address register 2 L 0 0 0 0 0 0 0 0 X address = 00H H X X X X X X X X CAR L 0 0 0 0 0 0 0 0 Chip address = 000 Data R/W mode L 1 0 1 1 0 0 0 1 Data write, the address is incremented starting from the current one. Dot display data 1 | Dot display data 128 L | L D D D D D D D D D D D D D D D D Dot display data 1 | Dot display data 128 L | L D D D D D D D D D D D D D D D D Dot display data 1 | Dot display data 128 L | L D D D D D D D D D D D D D D D D Dot display data 1 | Dot display data 128 L | L D D D D D D D D D D D D D D D D H X X X X X X X X CAR L 0 0 0 0 0 0 0 0 Chip address = 000 Address register 1 L 1 1 0 1 0 0 0 0 Pictograph group address, Y address = 00H Address register 2 L 0 0 0 0 0 0 0 0 X address = 00H H X X X X X X X X L 0 0 0 0 0 0 0 0 CAR Data of Y address = 00H (128 bytes) Data of Y address = 01H (128 bytes) Data of Y address = 02H (128 bytes) Data of Y address = 03H (128 bytes) Chip address = 000 Remark X = Don't Care, D = Data 21 µPD16675A 8.1 Initialize and Data Write (Continued) Parameter STB Command/data Description b7 b6 b5 b4 b3 b2 b1 b0 Data R/W mode L 1 0 1 1 0 0 0 1 Pict display data 1 | Pict display data 16 L | L D D D D D D D D D D D D D D D D Pict display data 1 | Pict display data 16 L | L D D D D D D D D D D D D D D D D H X X X X X X X X CAR L 0 0 0 0 0 0 0 0 Chip address = 000 Display ON/OFF L 0 0 0 0 1 1 1 1 LCD ON End H X X X X X X X X Remark X = Don't Care, D = Data 22 Data write, the address is incremented starting from the current one. Data of Y address = 00H (16 bytes) Data of Y address = 01H (16 bytes) µPD16675A 8.2 Change Display Data and Pictographic Data (All Data are Changed) Parameter STB Command/data Description b7 b6 b5 b4 b3 b2 b1 b0 Start H X X X X X X X X Chip Address Register (CAR) L 0 0 0 0 0 0 0 0 Chip address = 000 Address register 1 L 1 1 0 0 0 0 0 0 Dot address, Y address = 00H Address register 2 L 0 0 0 0 0 0 0 0 X address = 00H H X X X X X X X X CAR L 0 0 0 0 0 0 0 0 Chip address = 000 Data R/W mode L 1 0 1 1 0 0 0 1 Data write, the address is incremented starting from the current one. Dot display data 1 | Dot display data 128 L | L D D D D D D D D D D D D D D D D Dot display data 1 | Dot display data 128 L | L D D D D D D D D D D D D D D D D Dot display data 1 | Dot display data 128 L | L D D D D D D D D D D D D D D D D Dot display data 1 | Dot display data 128 L | L D D D D D D D D D D D D D D D D H X X X X X X X X CAR L 0 0 0 0 0 0 0 0 Chip address = 000 Address register 1 L 1 1 0 1 0 0 0 0 Pictograph group address, Y address = 00H Address register 2 L 0 0 0 0 0 0 0 0 X address = 00H H X X X X X X X X CAR L 0 0 0 0 0 0 0 0 Chip address = 000 Data R/W mode L 1 0 1 1 0 0 0 1 Data write, the address is incremented starting from the current one. Pict display data 1 | Pict display data 16 L | L D D D D D D D D D D D D D D D D Pict display data 1 | Pict display data 16 L | L D D D D D D D D D D D D D D D D End H X X X X X X X X Data of Y address = 00H (128 bytes) Data of Y address = 01H (128 bytes) Data of Y address = 02H (128 bytes) Data of Y address = 03H (128 bytes) Data of Y address = 00H (16 bytes) Data of Y address = 01H (16 bytes) Remark X = Don't Care, D = Data 23 µPD16675A 8.3 Read Display Data and Pictograph Data Parameter STB Command/data Description b7 b6 b5 b4 b3 b2 b1 b0 Start H X X X X X X X X Chip Address Register (CAR) L 0 0 0 0 0 0 0 0 Chip address = 000 Address register 1 L 1 1 0 0 0 0 0 0 Dot address, Y address = 00H Address register 2 L 0 0 0 0 0 0 0 0 X address = 00H H X X X X X X X X CAR L 0 0 0 0 0 0 0 0 Chip address = 000 Data R/W mode L 1 0 1 1 0 1 0 1 Data write, the address is incremented starting from the current one. Dot display data 1 | Dot display data 128 L | L D D D D D D D D D D D D D D D D Dot display data 1 | Dot display data 128 L | L D D D D D D D D D D D D D D D D Dot display data 1 | Dot display data 128 L | L D D D D D D D D D D D D D D D D Dot display data 1 | Dot display data 128 L | L D D D D D D D D D D D D D D D D H X X X X X X X X CAR L 0 0 0 0 0 0 0 0 Chip address = 000 Address register 1 L 1 1 0 1 0 0 0 0 Pictograph group address, Y address = 00H Address register 2 L 0 0 0 0 0 0 0 0 X address = 00H H X X X X X X X X CAR L 0 0 0 0 0 0 0 0 Chip address = 000 Data R/W mode L 1 0 1 1 0 1 0 1 Data write, the address is incremented starting from the current one. Pict display data 1 | Pict display data 16 L | L D D D D D D D D D D D D D D D D H X X X X X X X X Pict display data 1 | Pict display data 16 L | L D D D D D D D D D D D D D D D D End H X X X X X X X X Remark X = Don't Care, D = Data 24 Data of Y address = 00H (128 bytes) Data of Y address = 01H (128 bytes) Data of Y address = 02H (128 bytes) Data of Y address = 03H (128 bytes) Data of Y address = 00H (16 bytes) Data of Y address = 01H (16 bytes) µPD16675A 8.4 Blink Data Setting Parameter STB Command/data Description b7 b6 b5 b4 b3 b2 b1 b0 Start H X X X X X X X X Chip Address Register (CAR) L 0 0 0 0 0 0 0 0 Chip address = 000 Address register 1 L 1 1 1 0 0 0 0 0 Blink data group address, Y address = 00H Address register 2 L 0 0 0 0 0 0 0 0 X address = 00H H X X X X X X X X CAR L 0 0 0 0 0 0 0 0 Chip address = 000 Data R/W mode L 1 0 1 1 0 0 0 1 Data write, the address is incremented starting from the current one. Blink display data 1 | Blink display data 16 L | L D D D D D D D D D D D D D D D D Blink display data 1 | Blink display data 16 L | L D D D D D D D D D D D D D D D D H X X X X X X X X CAR L 0 0 0 0 0 0 0 0 Chip address = 000 Blink setting L 0 1 0 0 0 0 1 0 Start blinking, blink frequency = fBRI/2 End H X X X X X X X X Data of Y address = 00H (16 bytes) Data of Y address = 01H (16 bytes) Remark X = Don't Care, D = Data 25 µPD16675A 9. ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings (TA = +25°°C, VSS = VEE = 0 V) Parameter Symbol Rating Unit Logic supply voltage VDD1 −0.3 to +7.0 V Booster circuit supply voltage (VCHA = H) VDD2 −0.3 to +5.0, VDD1 ≤ VDD2 V Booster circuit supply voltage (VCHA = L) VDD2 −0.3 to +7.0, VDD1 ≤ VDD2 V Driver supply voltage VLCD −0.3 to +15.0, VDD2 ≤ VLCD V Driver reference supply input voltage VLC1 to VLC5 −0.3 to VLCD +0.3 V Logic system input voltage VIN1 −0.3 to VDD1 +0.3 V Logic system output voltage VOUT1 −0.3 to VDD1 +0.3 V Logic system input/output voltage VI/O1 −0.3 to VDD1 +0.3 V Driver system input voltage VIN2 −0.3 to VLCD +0.3 V Driver system output voltage VOUT2 −0.3 to +VLCD +0.3 V Operating temperature TA −40 to +85 °C Storage temperature Tstg −55 to +150 °C Caution If the absolute maximum rating of even one of the above parameters is exceeded even momentarily, the quality of the product may be degraded. Absolute maximum ratings, therefore, specify the values exceeding which the product may be physically damaged. Be sure to use the product within the range of the absolute maximum ratings. Recommended Operating Range Parameter Symbol Logic supply voltage Note 1 VDD1 2.7 Note 1 VDD2 2.7 Booster circuit supply voltage (VCHA = H) Note 1 MIN. TYP. MAX. Unit 3.3 V 3.0 3.6 V 2.7 5.0 5.5 V VDD2 10 12 V Booster circuit supply voltage (VCHA = L) VDD2 Driver supply voltage VLCD Logic system input voltage VIN 0 VDD1 V Driver system input voltage VLC1 to VLC5 0 VLCD V Note 2 Notes 1. Set this to VDD1 ≤ VDD2. 2. If use external LCD voltage as VLCD, cannot use standby. Also, maintain VDD1 = VDD2. Caution At power on and power off, keep VDD1 ≤ VDD2 ≤ VLCD. 26 µPD16675A Electrical Specifications (Unless otherwise specified, TA = −40 to +85°°C, VDD1 = 2.7 to 3.3 V, VCHA = H: VDD2 = 2.7 to 3.6 V or VCHA = L: VDD2 = 2.7 to 5.5 V) Parameter Symbol High level input voltage VIH Low level input voltage VIL High level input current IIH1 Low level input current Condition MIN. TYP. MAX. 0.8 VDD1 Unit V 0.2 VDD1 V Except D0/DATA, D1 to D7/NS, DACHA 1 µA IIL1 Except D0/DATA, D1 to D7/NS, DACHA −1 µA High level output voltage VOH IOUT = −1.5 mA, except OSCOUT Low level output voltage VOL IOUT = 4 mA, except OSCOUT 0.5 V High level leakage current ILOH D0/DATA, D1 to D7/NS VIN/OUT = VDD1 10 µA Low level leakage current ILOL D0/DATA, D1 to D7/NS VIN/OUT = VSS −10 µA Common output ON resistance RCOM VLCn→COMn, VLCD ≥ 2 VDD2 |IO| = 50 µA 2 kΩ Segment output ON resistance RSEG VLCn→SEGn, VLCD ≥ 2 VDD2 |IO| = 50 µA 4 kΩ Driver supply voltage (Booster voltage) VLCD VCHA = L, Note 1.8 VDD2 2.0 VDD2 V VCHA = H, Note 2.7 VDD2 3.0 VDD2 V fOSC = 30 kHz, no load VDD1 = VDD2 = 3.0 V, Not to access RAM 30 µA fOSC = 30 kHz, no load VDD1 = VDD2 = 3.0 V, To access RAM 60 µA fOSC = 30 kHz, All display OFF data output, VDD1 = VDD2 = 3.0 V, VCHA = H, Note 150 µA Logic system current consumption (VDD1) IDD11 Driver system current consumption (VDD2) IDD21 VDD1 −0.5 V Remark The TYP. value is a reference value when TA = 25°C. Note Measurement circuit DACHA D/A Converter VEXT Reference Power Circuit VDD1 + AmpIN(+) - AmpIN(-) AmpOUT VLC1 VLC2 VLC3 VLC4 VLC5 VEE 27 µPD16675A Switching Characteristics (Unless otherwise specified, TA = −40 to +85°°C, VDD1 = 2.7 to 3.3 V, VCHA = H: VDD2 = 2.7 to 3.6 V or VCHA = L: VDD2 = 2.7 to 5.5 V) Parameter Symbol Condition MIN. TYP. MAX. Unit 21 30 50 kHz Oscillation frequency fOSC Self-oscillation Transfer delay time tPHL SCK↓→DATA↓ 100 ns tPLH SCK↓→DATA↑ 300 ns Remark The TYP. value is a reference value when TA = 25°C. The time for one frame is obtained with the following formula. 1 frame = 1/fOSC × 8 × number of duties If fOSC = 30 kHz and 1/34 duty, then the result is: 1 frame = 33 µs × 8 × 34 = 9.1 ms Required Conditions for Timing (Unless otherwise specified, TA = −40 to +85°°C, VDD1 = 2.7 to 3.3 V, VCHA = H: VDD2 = 2.7 to 3.6 V or VCHA = L: VDD2 = 2.7 to 5.5 V) (1) Common Parameter Symbol Condition MIN. TYP. MAX. Unit 30 50 kHz Clock frequency fOSC OSCIN external clock 20 High level clock pulse width tWHC1 OSCIN external clock 10 25 µs Low level clock pulse width tWLC1 OSCIN external clock 10 25 µs High level clock pulse width tWHC2 OSCBRI external clock 400 ns Low level clock pulse width tWLC2 OSCBRI external clock 400 ns Rise/fall time t r, t f OSCBRI external clock Reset pulse width tWRE Reset pin Remark The TYP. value is a reference value when TA = 25°C. 28 100 1.0 ns µs µPD16675A (2) Serial interface Parameter Symbol Condition MIN. TYP. MAX. Unit Shift clock cycle tCYK SCK 900 ns High level shift clock pulse width tWHK SCK 400 ns Low level shift clock pulse width tWLK SCK 400 ns Shift clock hold time tHSTBK STB↓→SCK↓ 1.5 µs Data setup time tDS1 DATA→SCK↑ 100 ns Data hold time tDH1 SCK↑→DATA 400 ns STB hold time tHKSTB SCK↑→STB↑ 1 µs STB pulse width tWSTB 1 µs Wait time tWAIT 1 µs 8th CLK↑→1st CLK↓ Remark The TYP. value is a reference value when TA = 25°C. (3) Parallel interface (8-bit/4-bit) Parameter Symbol Condition MIN. TYP. MAX. Unit Enable cycle time tCYCE E↑→E↑ 900 ns High level enable pulse width tWHE E 400 ns Low level enable pulse width tWLE E 400 ns STB pulse width tWSTB 1 µs STB hold time tHKSTB 1 µs Enable hold time tHSTBK 1.5 µs Data setup time tDS2 D0 to D7→E↑ 100 ns Data hold time tDH2 D0 to D7→E↓ 300 ns Remarks 1. The TYP. value is a reference value when TA = 25°C. 2. In 4-bit parallel mode, D0 to D3 = “L”. 29 µPD16675A Switching Characteristics Waveforms AC Measurement Point VIH Input VIL VOH Output VOL AC Characteristics Waveform OSC OSCIN tWHC1 tWLC1 1/fOSC tf tr OSCBRI tWHC2 tWLC2 Serial interface (input) STB tWSTB tHSTBK tHKSTB tCYK tWLK tWHK SCK tDS1 tDH1 DATA Serial interface (output) SCK tPHL DATA 30 tPLH µPD16675A 8-bit parallel interface STB tWSTB tHSTBK tWKSTB tCYCE tWHE tWLE E tDH2 tDS2 Dn 4-bit parallel interface tHSTBK tCYCE tWAIT tWHE tWLE tDH2 tDS2 Upper bit Lower bit Upper bit STB tWSTB tWKSTB E Dn Lower bit Upper bit Lower bit Reset RESET tWRE 31 µPD16675A 63.949±0.08 27 23.2 23.2 (44.4) (Cut Line) 22.125 (Mark) 21.1±0.3 (SR) 2.575±0.01 22.125 (Mark) 21.1±0.3 (SR) P0.25±0.01⋅165 = 41.25±0.05 1.981±0.03 2.575±0.01 W0.125±0.02 (1.2) 0.1 (COATING AREA) 3 (0.6) 6.810−4.6 (8.3) (Cut Line) 8.8 2 JAPAN P0.7±0.01⋅54 = 37.8±0.055 W0.35±0.02 (40) (Cut Line) 44 25 0 17.68 −4.6 (COATING AREA) Specification Polymide UPILEX-S 75∝ m Adhesive EPOXY 12∝ m Copper ELECTROLYSIS Cu Plating Sn Solder Resist EPOXY 25∝ m MIN 0.25∝ m 25∝ m This Figure is shown by Copper side over Polyimide 5 Sprocket holes (23.75 mm) for 1 Pattern Corner radius is 0.30 mm Max. All tolerances unless otherwise specified 0.05 mm. 32 4 MAX0.9 Standard TCP Drawing (µPD16675AN-051) 10. PACKAGE DRAWING 0.2±0.2 (1.2) 4 2 A D16675AN -051 -201 5 (Cut Line) (3) 6.7 Cu (4)(Cut Line) 0.1 1.4 4.1±0.2(SR) 5 (4.2) 5.3±0.2 (SR) 6.7 (9.5) (Cut Line) 12.95 13.7 14.45 φ1 3.3±0.2(SR) 4.8 13.7 4.75±0.03 1.5 1±0.015 0.8±0.015 1.5 µPD16675A Standard TCP Drawing (µPD16675AN-051) Detail of test pad P0.25 0.35 0.35 0.35 0.30 0.20 0.30 0.20 0.30 0.20 14.45 From P.C. 0.08 Detail of “A” part 2- φ 1.3 PI Hole 2- φ 1.1 Cu Hole 2- φ 1.9 Cu Tape unwinding direction OUTPUT LEADS UNWINDING DIRECTION FACE (COPPER) 33 µPD16675A Standard TCP Drawing (µPD16675AN-051) Pin configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 34 DUMMY VLC5 DUMMY VLC4 VLC3 VLC2 DUMMY VLC1 VLCD VLCD AmpIN(-) AmpIN(+) AmpOUT C1C1C1+ C1+ C2C2C2+ C2+ VDD2 VEXT OSCBRI OSCIN OSCOUT DACHA VDD1 VDD1 VCHA VSS CS0 CS1 CS2 RESET D7/NS D6/CAE D5 D4 D3 D2 D1 D0/DATA E/SCK STB VSS VSS WS VDD1 POCOUT CLKOUT SYNC VEE VEE DUMMY DUMMY DUMMY COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 PCOM1 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG123 SEG124 SEG125 SEG126 SEG127 SEG128 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 PCOM2 DUMMY DUMMY µPD16675A NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 35 µPD16675A Reference Document Number Quality Grades on NEC’s Semiconductor Devices C11531E Semiconductor Device Mounting Technology Manual C10535E The application circuits and their parameters are for reference only and are not intended for use in actual design-ins. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product. M4 96. 5